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Use macro for pmpcfg csrs

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Jordan Carlin 2025-01-29 19:58:06 -08:00
parent 0b7b1f3c9a
commit 6d3223fafe
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1 changed files with 23 additions and 73 deletions
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testbench/common/wallyTracer.sv
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@ -207,82 +207,32 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
end end
end end
// PMP CSRs
if (P.PMP_ENTRIES > 0) begin if (P.PMP_ENTRIES > 0) begin
always_comb begin localparam inc = P.XLEN == 32 ? 4 : 8;
if(valid) begin // PMPCFG CSRs (space is 0-15 3a0 - 3af)
// PMPCFG CSRs (space is 0-15 3a0 - 3af) for (genvar pmpCfgID = 0; pmpCfgID < P.PMP_ENTRIES; pmpCfgID += inc) begin
localparam inc = P.XLEN == 32 ? 4 : 8; logic [P.XLEN-1:0] pmp;
int i, i4, csrid; localparam int i4 = pmpCfgID / 4;
logic [P.XLEN-1:0] pmp; assign pmp = {testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+7],
testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+6],
for (i=0; i<P.PMP_ENTRIES; i+=inc) begin testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+5],
i4 = i / 4; testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+4],
csrid = 12'h3A0 + i4; testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+3],
pmp = 0; testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+2],
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+0] << 0; testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+1],
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+1] << 8; testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+0]};
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+2] << 16; `CONNECT_CSR(PMPCFG``i4, 12'h3A0 + i4, pmp);
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+3] << 24;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+4] << 32;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+5] << 40;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+6] << 48;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i+7] << 56;
CSRArray[csrid] = pmp;
end
// PMPADDR CSRs (space is 0-63 3b0 - 3ef)
for (i=0; i<P.PMP_ENTRIES; i++) begin
csrid = 12'h3B0 + i;;
pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
CSRArray[csrid] = pmp;
end
end else begin // hold the old value if the pipeline is stalled.
// PMP CFG 3A0 to 3AF
int csrid;
for(csrid='h3A0; csrid<='h3AF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid];
// PMP ADDR 3B0 to 3EF
for(csrid='h3B0; csrid<='h3EF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid];
end
end end
end
// record previous csr value. // PMPADDR CSRs 3B0 to 3EF
always_ff @(posedge clk) begin for(genvar pmpAddrID = 0; pmpAddrID < P.PMP_ENTRIES; pmpAddrID++) begin
int csrid; `CONNECT_CSR(PMPADDR``pmpAddrID, 12'h3B0 + pmpAddrID, testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[pmpAddrID]);
// PMP CFG 3A0 to 3AF end
for(csrid='h3A0; csrid<='h3AF; csrid++)
CSRArrayOld[csrid] = CSRArray[csrid];
// PMP ADDR 3B0 to 3EF
for(csrid='h3B0; csrid<='h3EF; csrid++)
CSRArrayOld[csrid] = CSRArray[csrid];
end
// PMP CFG 3A0 to 3AF
genvar index;
for(index='h3A0; index<='h3AF; index++) begin
assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
assign rvvi.csr[0][0][index] = CSRArray[index];
end
// PMP ADDR 3B0 to 3EF
for(index='h3B0; index<='h3EF; index++) begin
assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
assign rvvi.csr_wb[0][0][index] = CSR_W[index];
assign rvvi.csr[0][0][index] = CSRArray[index];
end end
// Integer register file // Integer register file
assign rf[0] = 0; assign rf[0] = 0;
for(index = 1; index < NUM_REGS; index += 1) for(genvar index = 1; index < NUM_REGS; index += 1)
assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3; assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3;
@ -298,12 +248,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
if (P.F_SUPPORTED) begin if (P.F_SUPPORTED) begin
assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4; assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4;
assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4; assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
for(index = 0; index < 32; index += 1) for(genvar index = 0; index < 32; index += 1)
assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index]; assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
end else begin end else begin
assign frf_a4 = '0; assign frf_a4 = '0;
assign frf_we4 = 0; assign frf_we4 = 0;
for(index = 0; index < 32; index += 1) for(genvar index = 0; index < 32; index += 1)
assign frf[index] = '0; assign frf[index] = '0;
end end
@ -389,11 +339,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
~FlushE ? PCD : ~FlushE ? PCD :
~FlushD ? PCF : PCNextF; ~FlushD ? PCF : PCNextF;
for(index = 0; index < NUM_REGS; index += 1) begin for(genvar index = 0; index < NUM_REGS; index += 1) begin
assign rvvi.x_wdata[0][0][index] = rf[index]; assign rvvi.x_wdata[0][0][index] = rf[index];
assign rvvi.x_wb[0][0][index] = rf_wb[index]; assign rvvi.x_wb[0][0][index] = rf_wb[index];
end end
for(index = 0; index < 32; index += 1) begin for(genvar index = 0; index < 32; index += 1) begin
assign rvvi.f_wdata[0][0][index] = frf[index]; assign rvvi.f_wdata[0][0][index] = frf[index];
assign rvvi.f_wb[0][0][index] = frf_wb[index]; assign rvvi.f_wb[0][0][index] = frf_wb[index];
end end