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Oups missed files in the last commit.

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This commit is contained in:
Ross Thompson 2021-12-15 10:25:08 -06:00
parent 21b13fc237
commit 6d2a4b8354
3 changed files with 87 additions and 87 deletions
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2
fpga/generator/xlnx_ddr4.tcl
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@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {23} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {10} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

10
wally-pipelined/src/cache/icache.sv vendored
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@ -36,11 +36,11 @@ module icache
input logic ExceptionM, PendingInterruptM,
// Data read in from the ebu unit
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
(* mark_debug = "true" *) input logic [`XLEN-1:0] InstrInF,
(* mark_debug = "true" *) input logic InstrAckF,
// Read requested from the ebu unit
output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] InstrPAdrF,
(* mark_debug = "true" *) output logic InstrReadF,
// High if the instruction currently in the fetch stage is compressed
output logic CompressedF,
// High if the icache is requesting a stall
@ -52,7 +52,7 @@ module icache
// The raw (not decompressed) instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
output logic [31:0] FinalInstrRawF
(* mark_debug = "true" *) output logic [31:0] FinalInstrRawF
);
// Configuration parameters

16
wally-pipelined/src/uncore/uartPC16550D.sv
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@ -31,7 +31,7 @@
///////////////////////////////////////////
`include "wally-config.vh"
/* verilator lint_off UNOPTFLAT */
/* verilator lint_off UNOPTFLAT */
module uartPC16550D(
// Processor Interface
@ -47,7 +47,7 @@ module uartPC16550D(
// E1A Driver
input logic SIN, DSRb, DCDb, CTSb, RIb,
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
);
);
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
@ -138,24 +138,24 @@ module uartPC16550D(
LSR <= #1 8'b01100000;
MSR <= #1 4'b0;
if (`FPGA) begin
DLL <= #1 8'd25;
DLL <= #1 8'd11;
DLM <= #1 8'b0;
end else begin
DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
DLM <= #1 8'b0;
end
/* -----\/----- EXCLUDED -----\/-----
/* -----\/----- EXCLUDED -----\/-----
-----/\----- EXCLUDED -----/\----- */
SCR <= #1 8'b0; // not strictly necessary to reset
end else begin
if (~MEMWb) begin
case (A)
/* -----\/----- EXCLUDED -----\/-----
/* -----\/----- EXCLUDED -----\/-----
3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
-----/\----- EXCLUDED -----/\----- */
// *** BUG FIX ME for now for the divider to be 11. Our clock is 23 Mhz. 23Mhz /(25 * 16) = 57600 baud, which is close enough to 57600 baud
3'b000: if (DLAB) DLL <= #1 8'd25; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
@ -335,7 +335,7 @@ module uartPC16550D(
for (i=0; i<16; i++) begin:rx
assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
/* if (i > 0)
/* if (i > 0)
assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
else
assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
@ -532,4 +532,4 @@ module uartPC16550D(
endmodule
/* verilator lint_on UNOPTFLAT */
/* verilator lint_on UNOPTFLAT */