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@ -80,17 +80,7 @@ module alu #(parameter WIDTH=32) (
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assign CondMaskB = (Mask) ? MaskB : B;
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assign CondMaskB = (Mask) ? MaskB : B;
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end else assign CondMaskB = B;
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end else assign CondMaskB = B;
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/*// Sign/Zero extend mux
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if (WIDTH == 64) begin // rv64 must handle word s/z extensions
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always_comb
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case (shASelect)
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2'b00: shA = {{1'b0}, A}; // zero-extend double-word (srl)
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2'b01: shA = {A[63], A}; // sign-extend double-word (sra)
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2'b10: shA = {{33'b0}, A[31:0]}; // zero-extend word (add.uw, shadd.uw, srlw)
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2'b11: shA = {{33{A[31]}}, A[31:0]}; //sign extend-word (sraw)
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endcase
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end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions
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*/
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if (WIDTH == 64) begin
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if (WIDTH == 64) begin
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mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA);
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mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA);
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mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA);
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mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA);
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