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Added new tsm for debuggin the plic.

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This commit is contained in:
Rose Thompson 2024-12-03 15:28:39 -06:00
parent 7bc2737fbd
commit 6c9c1fc841
1 changed files with 32 additions and 0 deletions
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fpga/generator/debug/plic.tsm Normal file
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##################################################
#
# For info on creating trigger state machines:
# 1) In the main Vivado menu bar, select
# Window > Language Templates
# 2) In the Templates window, select
# Debug > Trigger State Machine
# 3) Refer to the entry 'Info' for an overview
# of the trigger state machine language.
#
# More information can be found in this document:
#
# Vivado Design Suite User Guide: Programming
# and Debugging (UG908)
#
##################################################
state state_reset:
if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h200) then
goto state_1;
else
goto state_reset;
endif
state state_1:
if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h000) then
goto state_trigger;
else
goto state_1;
endif
state state_trigger:
trigger;