From 6c212ebf0efa671199abefcd2a64863dbf495e73 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 17:39:38 -0500 Subject: [PATCH] Changes are confirmed to work on the FPGA. --- src/rvvi/rvvisynth.sv | 2 +- testbench/testbench.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index 83c865529..f42e9c1a8 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module rvvisynth import cvw::*; #(parameter cvw_t P, - parameter integer MAX_CSRS = 3, + parameter integer MAX_CSRS = 5, parameter integer TOTAL_CSRS = 36)( input logic clk, reset, input logic StallE, StallM, StallW, FlushE, FlushM, FlushW, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4885a6121..318d3d016 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -604,7 +604,7 @@ module testbench; end if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth - localparam MAX_CSRS = 3; + localparam MAX_CSRS = 5; logic valid; logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;