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Merge branch 'main' of github.com:openhwgroup/cvw

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This commit is contained in:
Jacob Pease 2024-05-30 15:48:31 -05:00
commit 6bf43ebe61
45 changed files with 3036 additions and 278 deletions
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1
.gitignore vendored
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@ -232,6 +232,7 @@ examples/verilog/fulladder/simprofile_dir/
examples/verilog/fulladder/simv.daidir/
examples/verilog/fulladder/ucli.key
examples/verilog/fulladder/verdi_config_file
examples/crypto/gfmul/gfmul
tests/functcov
tests/functcov/*
tests/functcov/*/*

1
Makefile
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@ -89,6 +89,7 @@ riscvdv_functcov:
combine_functcov:
mkdir -p ${SIM}/questa/functcov
mkdir -p ${SIM}/questa/functcov_logs
cd ${SIM}/questa/functcov && rm -rf *
run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1
run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1

56
README.md
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@ -41,19 +41,14 @@ Clone your fork of the repo and run the setup script. Change <yourgithubid> to y
$ git remote add upstream https://github.com/openhwgroup/cvw
$ source ./setup.sh
If you are installing on a new system without any tools installed please jump to the next section, Toolchain Installation then come back here.
Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
if [ -f ~/cvw/setup.sh ]; then
source ~/cvw/setup.sh
fi
Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis.
export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server
export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server
export QUESTAPATH=.. # Change this for your path to Questa
export SNPSPATH=.. # Change this for your path to Design Compiler
If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while.
@ -73,6 +68,19 @@ Ubuntu users can install the tools by running
$ sudo $WALLY/bin/wally-tool-chain-install.sh
The default installation directory is /opt/riscv defined by the environment variable RISCV. You must copy and edit ~/cvw/site-setup.sh to $RISCV/site-setup.sh.
~/cvw/setup.sh sources $RISCV/site-setup.sh.
This allows for customization of the site specific information such as commerical licenses and PATH variables.
Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis. If Questa or Design Compiler are already setup on this system then don't set these variables.
export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server
export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server
export QUESTAPATH=.. # Change this for your path to Questa
export SNPSPATH=.. # Change this for your path to Design Compiler
See wally-tool-chain-install.sh for a detailed description of each component,
or to issue the commands one at a time to install on the command line.
## Installing EDA Tools
@ -138,3 +146,37 @@ If you want to add a cronjob you can do the following:
30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
```
# Example wsim commands
wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
The general syntax is
wsim <config> <suite or elf file> [--options]
Parameters and options:
-h, --help show this help message and exit
--elf, -e Elf file
--sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator
--tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench
--gui, -g Simulate with GUI
--coverage, -c Code & Functional Coverage
--args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs
--vcd, -v Generate testbench.vcd
--lockstep, -l Run ImperasDV lock, step, and compare.
--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging.
Run basic test with questa
wsim rv64gc arch64i
Run Questa with gui
wsim rv64gc wally64priv --gui
Run lockstep against ImperasDV with a single elf file in the --gui. Lockstep requires single elf.
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --elf --lockstep --gui
Run lockstep against ImperasDV with a single elf file. Compute coverage.
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --elf --lockstep --coverage

2
bin/derivgen.pl
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@ -70,10 +70,10 @@ foreach my $line (<$fh>) {
}
&terminateDeriv();
close($fh);
system("rm -rf $ENV{WALLY}/config/deriv");
#foreach my $key (keys %derivs) {
foreach my $key (@derivnames) {
my $dir = "$ENV{WALLY}/config/deriv/$key";
system("rm -rf $dir");
system("mkdir -p $dir");
my $configunmod = "$dir/config_unmod.vh";
my $config = "$dir/config.vh";

1
bin/wally-tool-chain-install.sh
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@ -49,6 +49,7 @@ sudo apt upgrade -y
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt ssmtp
# Other python libraries used through the book.
sudo -H pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml
sudo -H pip3 install riscv_isac # to generate new tests, such as quads with fp_dataset.py
# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
if ! command -v python &> /dev/null

40
bin/wsim
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@ -18,14 +18,24 @@ import os
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite or ELF file")
parser.add_argument("--elf", "-e", help="Elf file", action="store_true")
parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
args = parser.parse_args()
print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
ElfFile=""
if(args.elf):
ElfFile = "+ElfFile=" + args.testsuite
args.testsuite = "none"
# Validate arguments
if (args.gui):
@ -50,21 +60,41 @@ for d in ["logs", "wkdir", "cov"]:
except:
pass
# Launch selected simulator
cd = "cd $WALLY/sim/" +args.sim
# ugh. can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running
# functional coverage and imply it.
if (args.sim == "questa"):
if (args.lockstep):
prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic" # OTHERFLAGS=\"+IDV_TRACE2LOG=" + str(args.locksteplog) + " +IDV_TRACE2COV=" + str(args.covlog) + "\"";
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0";
#ImperasPlusArgs = "+IDV_TRACE2LOG=" + str(args.locksteplog) + " +IDV_TRACE2COV=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
suffix = ""
else:
CovEnableStr = ""
ImperasPlusArgs = "";
suffix = "--lockstep"
else:
prefix = ""
ImperasPlusArgs = ""
suffix = ""
if (args.tb == "testbench_fp"):
args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + suffix + " " + ImperasPlusArgs
if (args.coverage):
cmd += " --coverage"
if (args.fcov):
cmd += " --fcov"
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
if(args.tb == "testbench"):
cmd = cd + "; vsim -do \"" + cmd + " +acc -GDEBUG=1\""
cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc -GDEBUG=1\""
elif(args.tb == "testbench_fp"):
cmd = cd + "; vsim -do \"" + cmd + " +acc\""
cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc\""
else: # launch Questa in batch mode
cmd = cd + "; vsim -c -do \"" + cmd + "\""
cmd = cd + "; " + prefix + " vsim -c -do \"" + cmd + "\""
print("Running Questa with command: " + cmd)
os.system(cmd)
elif (args.sim == "verilator"):

240
config/derivlist.txt
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@ -530,6 +530,246 @@ ZALRSC_SUPPORTED 0
deriv zalrsc_rv64gc rv64gc
ZAAMO_SUPPORTED 0
deriv zba_rv32gc rv32gc
ZBA_SUPPORTED 1
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbb_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 1
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbc_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 1
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbs_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 1
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbkb_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 1
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbkc_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 1
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbkx_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 1
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zknd_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 1
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zkne_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 1
ZKNH_SUPPORTED 0
deriv zknh_rv32gc rv32gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 1
deriv zba_rv64gc rv64gc
ZBA_SUPPORTED 1
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbb_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 1
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbc_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 1
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbs_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 1
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbkb_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 1
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbkc_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 1
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zbkx_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 1
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zknd_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 1
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 0
deriv zkne_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 1
ZKNH_SUPPORTED 0
deriv zknh_rv64gc rv64gc
ZBA_SUPPORTED 0
ZBB_SUPPORTED 0
ZBS_SUPPORTED 0
ZBC_SUPPORTED 0
ZBKB_SUPPORTED 0
ZBKC_SUPPORTED 0
ZBKX_SUPPORTED 0
ZKND_SUPPORTED 0
ZKNE_SUPPORTED 0
ZKNH_SUPPORTED 1
# Floating-point modes supported
deriv f_rv32gc rv32gc

16
examples/crypto/gfmul/Makefile Normal file
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@ -0,0 +1,16 @@
# Makefile
CC = gcc
CFLAGS = -O3
LIBS =
SRCS = $(wildcard *.c)
PROGS = $(patsubst %.c,%,$(SRCS))
all: $(PROGS)
%: %.c
$(CC) $(CFLAGS) $(IFLAGS) -o $@ $< $(LIBS)
clean:
rm -f $(PROGS)

72
examples/crypto/gfmul/gfmul.c Normal file
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@ -0,0 +1,72 @@
// gfmul.c - Galois Field multiplication
// James Stine and David Harris 16 May 2024
#include <stdio.h>
/* return ab mod m(x) - long multiplication in GF(2^n) with polynomial m */
int gfmul(int a, int b, int n, int m) {
int result = 0;
while (b) {
if (b & 1) result = result ^ a; /* if bit of b is set add a */
a = a << 1; /* multiply a by x */
if (a & 1 << n)
a = a ^ m; /* reduce/sub modulo AES m(x) = 100011011 */
//printf("a = %x, b = %x, result = %x\n", a, b, result);
b = b >> 1; /* get next bit of b */
}
return result;
}
void inverses(void) {
int i, j, k, num;
printf("\nTable of inverses in GF(2^8) with polynomial m(x) = 100011011\n");
for (i=0; i<16; i++) {
for (j=0; j<16; j++) {
num = i*16+j;
if (num ==0) printf ("00 ");
else for (k=1; k<256; k++) {
if (gfmul(num, k, 8, 0b100011011) == 1) {
printf("%02x ", k);
break;
}
}
}
printf("\n");
}
}
void inverses3(void) {
int k, num;
printf("\nTable of inverses in GF(2^8) with polynomial m(x) = 100011011\n");
for (num=0; num<8; num++) {
if (num == 0) printf ("0 ");
else for (k=1; k<8; k++) {
if (gfmul(num, k, 3, 0b1011) == 1) {
printf("%d ", k);
break;
}
}
}
printf("\n");
}
int main() {
int a = 0xC5;
int b = 0xA1;
printf("The GF(2^8) result is %x\n", gfmul(a,b, 8, 0b100011011));
printf("The GF(2^8) result is %x\n", gfmul(0xC1, 0x28, 8, 0b100011011));
inverses();
// tabulate inverses for GF(2^3)
inverses3();
// check worked examples
printf("The GF(2^3) result is %d\n", gfmul(0b101,0b011, 3, 0b1011));
printf("The GF(2^3) result is %d\n", gfmul(0b101,0b010, 3, 0b1011));
printf("The GF(2^3) result is %d\n", gfmul(0b101,0b100, 3, 0b1011));
printf("The GF(2^3) result is %d\n", gfmul(0b101,0b011, 3, 0b1011));
}

2
sim/questa/run-imperas-linux.sh
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@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
#export OTHERFLAGS=""
vsim -c -do "do wally.do buildroot buildroot testbench --lockstep"
vsim -do "do wally.do buildroot buildroot testbench --lockstep +acc -GDEBUG=1"

22
sim/questa/wally-imperas-cov.do
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@ -29,6 +29,14 @@ vlog +incdir+$env(WALLY)/config/$1 \
+incdir+$env(WALLY)/config/shared \
+define+USE_IMPERAS_DV \
+define+IDV_INCLUDE_TRACE2COV \
+define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
+define+COVER_RV64I \
+define+COVER_RV64M \
+define+COVER_RV64A \
+define+COVER_RV64F \
+define+COVER_RV64D \
+define+COVER_RV64ZICSR \
+define+COVER_RV64C \
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
@ -39,19 +47,11 @@ vlog +incdir+$env(WALLY)/config/$1 \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
\
+define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
+define+COVER_RV64I \
+define+COVER_RV64M \
+define+COVER_RV64A \
+define+COVER_RV64F \
+define+COVER_RV64D \
+define+COVER_RV64ZICSR \
+define+COVER_RV64C \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
\
$env(WALLY)/src/cvw.sv \
$env(WALLY)/testbench/testbench-imperas.sv \
$env(WALLY)/testbench/testbench.sv \
$env(WALLY)/testbench/common/*.sv \
$env(WALLY)/src/*/*.sv \
$env(WALLY)/src/*/*/*.sv \
@ -61,7 +61,7 @@ vlog +incdir+$env(WALLY)/config/$1 \
vopt +acc work.testbench -G DEBUG=1 -o workopt
eval vsim workopt +nowarn3829 -fatal 7 \
-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
+testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
+ElfFile=$env(TESTDIR)/ref/ref.elf $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
coverage save -onexit $env(WALLY)/sim/questa/riscv.ucdb
@ -76,4 +76,4 @@ run -all
noview $env(WALLY)/testbench/testbench-imperas.sv
view wave
quit -f
#quit -f

80
sim/questa/wally.do
View File

@ -44,6 +44,20 @@ set coverage 0
set CoverageVoptArg ""
set CoverageVsimArg ""
set FunctCoverage 0
set riscvISACOVsrc ""
set FCdefineINCLUDE_TRACE2COV ""
set FCdefineCOVER_BASE_RV64I ""
set FCdefineCOVER_LEVEL_DV_PR_EXT ""
set FCdefineCOVER_RV64I ""
set FCdefineCOVER_RV64M ""
set FCdefineCOVER_RV64A ""
set FCdefineCOVER_RV64F ""
set FCdefineCOVER_RV64D ""
set FCdefineCOVER_RV64ZICSR ""
set FCdefineCOVER_RV64C ""
set FCdefineIDV_INCLUDE_TRACE2COV ""
set lockstep 0
# ok this is annoying. vlog, vopt, and vsim are very picky about how arguments are passed.
# unforunately it won't allow these to be grouped as one argument per command so they are broken
@ -51,7 +65,7 @@ set lockstep 0
set lockstepvoptstring ""
set SVLib ""
set SVLibPath ""
set OtherFlags ""
#set OtherFlags ""
set ImperasPubInc ""
set ImperasPrivInc ""
set rvviFiles ""
@ -98,8 +112,31 @@ if {$CoverageIndex >= 0} {
set lst [lreplace $lst $CoverageIndex $CoverageIndex]
}
# if +coverage found set flag and remove from list
set FunctCoverageIndex [lsearch -exact $lst "--fcov"]
if {$FunctCoverageIndex >= 0} {
set FunctCoverage 1
set riscvISACOVsrc +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source
set FCdefineINCLUDE_TRACE2COV "+define+INCLUDE_TRACE2COV"
set FCdefineCOVER_BASE_RV64I "+define+COVER_BASE_RV64I"
set FCdefineCOVER_LEVEL_DV_PR_EXT "+define+COVER_LEVEL_DV_PR_EXT"
set FCdefineCOVER_RV64I "+define+COVER_RV64I"
set FCdefineCOVER_RV64M "+define+COVER_RV64M"
set FCdefineCOVER_RV64A "+define+COVER_RV64A"
set FCdefineCOVER_RV64F "+define+COVER_RV64F"
set FCdefineCOVER_RV64D "+define+COVER_RV64D"
set FCdefineCOVER_RV64ZICSR "+define+COVER_RV64ZICSR"
set FCdefineCOVER_RV64C "+define+COVER_RV64C"
set FCdefineIDV_INCLUDE_TRACE2COV "+define+IDV_INCLUDE_TRACE2COV"
set lst [lreplace $lst $FunctCoverageIndex $FunctCoverageIndex]
}
set LockStepIndex [lsearch -exact $lst "--lockstep"]
if {$LockStepIndex >= 0} {
# ugh. can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running
# functional coverage and imply it.
if {$LockStepIndex >= 0 || $FunctCoverageIndex >= 0} {
set lockstep 1
# ideally this would all be one or two variables, but questa is having a real hard time
@ -111,9 +148,11 @@ if {$LockStepIndex >= 0} {
set idvFiles $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/*.sv
set SVLib "-sv_lib"
set SVLibPath $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model
set OtherFlags $env(OTHERFLAGS)
#set OtherFlags $env(OTHERFLAGS)
set lst [lreplace $lst $LockStepIndex $LockStepIndex]
if {$LockStepIndex >= 0} {
set lst [lreplace $lst $LockStepIndex $LockStepIndex]
}
}
# separate the +args from the -G parameters
@ -129,23 +168,40 @@ if {$DEBUG > 0} {
echo "GUI = $GUI"
echo "coverage = $coverage"
echo "lockstep = $lockstep"
echo "remaining list = \'$lst\'"
echo "Extra +args = \'$PlusArgs\'"
echo "Extra -args = \'$ParamArgs\'"
echo "FunctCoverage = $FunctCoverage"
echo "remaining list = $lst"
echo "Extra +args = $PlusArgs"
echo "Extra -args = $ParamArgs"
}
foreach x $PlusArgs {
echo "Element is $x"
}
# need a better solution this is really ugly
# Questa really don't like passing $PlusArgs on the command line to vsim. It treats the whole things
# as one string rather than mutliple separate +args. Is there an automated way to pass these?
set temp0 [lindex $PlusArgs 0]
set temp1 [lindex $PlusArgs 1]
set temp2 [lindex $PlusArgs 2]
set temp3 [lindex $PlusArgs 3]
#quit
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} ${lockstepvoptstring} ${ImperasPubInc} ${ImperasPrivInc} +incdir+${CONFIG}/shared ${rvviFiles} ${idvFiles} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${lst} -o testbenchopt ${CoverageVoptArg}
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${ParamArgs} -o testbenchopt ${CoverageVoptArg}
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} -suppress 3829 ${CoverageVsimArg}
#vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg}
#vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} +IDV_TRACE2COV=1 +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg}
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} -suppress 3829 ${CoverageVsimArg}
# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
# power add generates the logging necessary for said generation.
@ -162,8 +218,8 @@ if { ${GUI} } {
run -all
# power off -r /dut/core/*
if {$coverage} {
set UCDB cov/${CFG}_${TESTSUITE}.ucdb
if {$coverage || $FunctCoverage} {
set UCDB ${WALLY}/sim/questa/cov/${CFG}_${TESTSUITE}.ucdb
echo "Saving coverage to ${UCDB}"
do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
coverage save -instance /testbench/dut/core ${UCDB}

12
src/fpu/fctrl.sv
View File

@ -165,19 +165,19 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.s (Zfa)
else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // froundnx.s (Zfa)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.s (Zfa)
7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0_0_0; // fcvt.d.(s/h/q)
else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.d (Zfa)
else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // froundnx.d (Zfa)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.d (Zfa)
7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0_0_0; // fcvt.h.(s/d/q)
else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.h (Zfa)
else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // froundnx.h (Zfa)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.h (Zfa)
// coverage off
// Not covered in testing because rv64gc does not support quad precision
7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11)
@ -185,7 +185,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.q (Zfa)
else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // froundnx.q (Zfa)
ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.q (Zfa)
// coverage on
7'b1101000: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.s.w w->s
@ -273,10 +273,10 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
assign FmtD = 1'b0;
else if (P.FPSIZES == 2) begin
logic [1:0] FmtTmp;
assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]&~Rs2D[2]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
assign FmtD = (P.FMT == FmtTmp);
end else if (P.FPSIZES == 3|P.FPSIZES == 4)
assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]&~Rs2D[2]) ? Rs2D[1:0] : Funct7D[1:0];
// Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
// When disabled infinity and NaN on source registers are ignored by the unpacker and thus special case logic.

4
src/fpu/fround.sv
View File

@ -79,7 +79,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
// Logic for nonnegative mask and rounding bits
assign IMask = {1'b1, {P.NF{1'b0}}} >>> E;
assign Tmasknonneg = ~(IMask >>> 1'b1);
assign Tmasknonneg = ~IMask >>> 1'b1;
assign HotE = IMask & ~(IMask << 1'b1);
assign HotEP1 = HotE >> 1'b1;
assign Lnonneg = |(Xm & HotE);
@ -139,7 +139,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
else if (Elt0) // 0 <= |X| < 1 rounds to 0 or 1
if (RoundUp) W = {Xs, P.BIAS[P.NE-1:0], {P.NF{1'b0}}}; // round to +/- 1
else W = {Xs, {(P.FLEN-1){1'b0}}}; // round to +/- 0
else begin // |X| > 1 rounds to an integer
else begin // |X| >= 1 rounds to an integer
if (RoundUp & Two) W = {Xs, Xep1, {(P.NF){1'b0}}}; // Round up to 2.0
else if (RoundUp) W = {Xs, Xe, Rnd[P.NF-1:0]}; // Round up to Rnd
else W = {Xs, Xe, Trunc[P.NF-1:0]}; // Round down to Trunc

6
src/ieu/aes/aes32d.sv
View File

@ -34,8 +34,8 @@ module aes32d(
logic [7:0] SboxOut;
logic [31:0] so, mixed;
aesinvsbox8 inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
aesinvmixcolumns32 mix(so, mixed); // Run so through the mixword AES function
aesinvsbox8 inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
aesinvmixcolumns8 mix(SboxOut, mixed); // Run so through the InvMixColumns AES function
assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
endmodule

8
src/ieu/aes/aes32e.sv
View File

@ -34,8 +34,8 @@ module aes32e(
logic [7:0] SboxOut;
logic [31:0] so, mixed;
aessbox8 sbox(SboxIn, SboxOut); // Substitute
assign so = {24'h0, SboxOut}; // Pad sbox output
aesmixcolumns32 mwd(so, mixed); // Mix Word using aesmixword component
mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
aessbox8 sbox(SboxIn, SboxOut); // Substitute
assign so = {24'h0, SboxOut}; // Pad sbox output
aesmixcolumns32 mb(so, mixed); // Mix using MixColumns component
mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip MixColumns
endmodule

16
src/ieu/aes/aes64d.sv
View File

@ -32,20 +32,20 @@ module aes64d(
output logic [63:0] result
);
logic [63:0] ShiftRowOut, SboxOut, MixcolIn, MixcolOut;
logic [63:0] ShiftRowsOut, SboxOut, MixcolsIn, MixcolsOut;
// Apply inverse shiftrows to rs2 and rs1
aesinvshiftrow64 srow({rs2, rs1}, ShiftRowOut);
aesinvshiftrows64 srow({rs2, rs1}, ShiftRowsOut);
// Apply full word inverse substitution to lower doubleord of shiftrow out
aesinvsbox64 invsbox(ShiftRowOut, SboxOut);
aesinvsbox64 invsbox(ShiftRowsOut, SboxOut);
mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolsIn);
// Apply inverse mixword to sbox outputs
aesinvmixcolumns32 invmw0(MixcolIn[31:0], MixcolOut[31:0]);
aesinvmixcolumns32 invmw1(MixcolIn[63:32], MixcolOut[63:32]);
// Apply inverse MixColumns to sbox outputs
aesinvmixcolumns32 invmw0(MixcolsIn[31:0], MixcolsOut[31:0]);
aesinvmixcolumns32 invmw1(MixcolsIn[63:32], MixcolsOut[63:32]);
// Final round skips mixcolumns.
mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
endmodule

16
src/ieu/aes/aes64e.sv
View File

@ -34,22 +34,22 @@ module aes64e(
output logic [63:0] result
);
logic [63:0] ShiftRowOut, SboxOut, MixcolOut;
logic [63:0] ShiftRowsOut, SboxOut, MixcolsOut;
// AES shiftrow unit
aesshiftrow64 srow({rs2,rs1}, ShiftRowOut);
aesshiftrows64 srow({rs2,rs1}, ShiftRowsOut);
// Apply substitution box to 2 lower words
// Use the shared sbox in zknde64.sv for the first sbox
assign SboxEIn = ShiftRowOut[31:0];
assign SboxEIn = ShiftRowsOut[31:0];
assign SboxOut[31:0] = Sbox0Out;
aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
aessbox32 sbox1(ShiftRowsOut[63:32], SboxOut[63:32]); // instantiate second sbox
// Apply mix columns operations
aesmixcolumns32 mw0(SboxOut[31:0], MixcolOut[31:0]);
aesmixcolumns32 mw1(SboxOut[63:32], MixcolOut[63:32]);
// Apply MixColumns operations
aesmixcolumns32 mw0(SboxOut[31:0], MixcolsOut[31:0]);
aesmixcolumns32 mw1(SboxOut[63:32], MixcolsOut[63:32]);
// Skip mixcolumns on last round
mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
endmodule

47
src/ieu/aes/aesinvmixcolumns8.sv Normal file
View File

@ -0,0 +1,47 @@
///////////////////////////////////////////
// aesinvmixcolumns8.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 05 March 2024
//
// Purpose: AES Inverted Mix Column Function for use with AES
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvmixcolumns8(
input logic [7:0] a,
output logic [31:0] y
);
logic [10:0] t, x0, x1, x2, x3;
// aes32d operates on shifted versions of the input
assign t = {a, 3'b0} ^ {3'b0, a};
assign x0 = {a, 3'b0} ^ {1'b0, a, 2'b0} ^ {2'b0, a, 1'b0};
assign x1 = t;
assign x2 = t ^ {1'b0, a, 2'b0};
assign x3 = t ^ {2'b0, a, 1'b0};
galoismultinverse8 gm0 (x0, y[7:0]);
galoismultinverse8 gm1 (x1, y[15:8]);
galoismultinverse8 gm2 (x2, y[23:16]);
galoismultinverse8 gm3 (x3, y[31:24]);
endmodule

6
src/ieu/aes/aesinvshiftrow64.sv → src/ieu/aes/aesinvshiftrows64.sv
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesinvshiftrow.sv
// aesinvshiftrows64.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
@ -25,9 +25,9 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvshiftrow64(
module aesinvshiftrows64(
input logic [127:0] a,
output logic [63:0] y
output logic [63:0] y
);
assign y = {a[95:88], a[119:112], a[15:8], a[39:32],

39
src/ieu/aes/aesmixcolumns8.sv Normal file
View File

@ -0,0 +1,39 @@
///////////////////////////////////////////
// aesmixcolumns8.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
// Created: 20 February 2024
//
// Purpose: Galois field operation to byte in an individual 32-bit word
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesmixcolumns8(
input logic [7:0] a,
output logic [31:0] y
);
logic [7:0] xa, xapa;
galoismultforward8 gm(a, xa); // xa
assign xapa = a ^ xa; // a ^ xa
assign y = {xapa, a, a, xa};
endmodule

4
src/ieu/aes/aesshiftrow64.sv → src/ieu/aes/aesshiftrows64.sv
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////
// aesshiftrow.sv
// aesshiftrows64.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
@ -25,7 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesshiftrow64(
module aesshiftrows64(
input logic [127:0] a,
output logic [63:0] y
);

35
src/ieu/aes/aesshiftrows64.xv Normal file
View File

@ -0,0 +1,35 @@
///////////////////////////////////////////
// aesshiftrows64.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aesshiftrow for taking in first Data line
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesshiftrows64(
input logic [127:0] a,
output logic [63:0] y
);
assign y = {a[31:24], a[119:112], a[79:72], a[39:32],
a[127:120], a[87:80], a[47:40], a[7:0]};
endmodule

29
src/ieu/alu.sv
View File

@ -61,6 +61,21 @@ module alu import cvw::*; #(parameter cvw_t P) (
assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(P.XLEN-1){1'b0}}, SubArith};
// Zicond block conditionally zeros B
if (P.ZICOND_SUPPORTED) begin: zicond
logic BZero;
assign BZero = (B == 0); // check if rs2 = 0
// Create a signal that is 0 when czero.* instruction should clear result
// If B = 0 for czero.eqz or if B != 0 for czero.nez
always_comb
case (CZero)
2'b01: ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
2'b10: ZeroCondMaskInvB = {P.XLEN{BZero}}; // czero.nez: kill if B != 0
default: ZeroCondMaskInvB = CondMaskInvB; // otherwise normal behavior
endcase
end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
// Shifts (configurable for rotation)
shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
@ -105,18 +120,4 @@ module alu import cvw::*; #(parameter cvw_t P) (
assign CondShiftA = A;
end
// Zicond block
if (P.ZICOND_SUPPORTED) begin: zicond
logic BZero;
assign BZero = (B == 0); // check if rs2 = 0
// Create a signal that is 0 when czero.* instruction should clear result
// If B = 0 for czero.eqz or if B != 0 for czero.nez
always_comb
case (CZero)
2'b01: ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
2'b10: ZeroCondMaskInvB = {P.XLEN{BZero}}; // czero.nez: kill if B != 0
default: ZeroCondMaskInvB = CondMaskInvB; // otherwise normal behavior
endcase
end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
endmodule

8
src/ieu/bmu/bitmanipalu.sv
View File

@ -103,18 +103,18 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
// ZBKB Unit
if (P.ZBKB_SUPPORTED) begin: zbkb
zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
end else assign ZBKBResult = '0;
// ZBKX Unit
if (P.ZBKX_SUPPORTED) begin: zbkx
zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[2:0]), .ZBKXResult);
zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[0]), .ZBKXResult);
end else assign ZBKXResult = '0;
// ZKND and ZKNE AES decryption and encryption
if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin: zknde
if (P.XLEN == 32) zknde32 #(P) ZKN32(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult);
else zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult);
if (P.XLEN == 32) zknde32 #(P) ZKN32(.A(ABMU), .B(BBMU), .bs(Funct7[6:5]), .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult);
else zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU), .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult);
end else assign ZKNDEResult = '0;
// ZKNH Unit

2
src/ieu/bmu/bmuctrl.sv
View File

@ -264,7 +264,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sig1h
17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sig1l
17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_1_0_0_0_0_0; // sha512sum0r
17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1101_1_0_0_1_0_0_0_0_0; // sha512sum1r
17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1110_1_0_0_1_0_0_0_0_0; // sha512sum1r
endcase
else if (P.XLEN==64)

16
src/ieu/bmu/byteop.sv
View File

@ -30,24 +30,16 @@
module byteop #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, // Operands
input logic [WIDTH-1:0] RevA, // Reversed A
input logic [1:0] ByteSelect, // LSB of Immediate
input logic ByteSelect, // LSB of Immediate
output logic [WIDTH-1:0] ByteResult); // rev8, orcb result
logic [WIDTH-1:0] OrcBResult, Rev8Result, Brev8Result;
logic [WIDTH-1:0] OrcBResult, Rev8Result;
genvar i;
for (i=0;i<WIDTH;i+=8) begin:loop
for (i=0;i<WIDTH;i+=8) begin:byteloop
assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
assign Brev8Result[i+7:i] = RevA[WIDTH-1-i:WIDTH-i-8];
end
// ByteOp Result Mux
always_comb begin
if (ByteSelect[0] == 1'b0) ByteResult = Rev8Result;
else if (ByteSelect[1] == 1'b0) ByteResult = OrcBResult;
else ByteResult = Brev8Result;
end
mux2 #(WIDTH) byteresultmux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
endmodule

2
src/ieu/bmu/zbb.sv
View File

@ -45,7 +45,7 @@ module zbb #(parameter WIDTH=32) (
mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
byteop #(WIDTH) bu(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
// ZBBSelect[2] differentiates between min(u) vs max(u) instruction

16
src/ieu/kmu/zbkb.sv
View File

@ -26,21 +26,25 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module zbkb #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B, RevA,
input logic W64,
input logic [2:0] Funct3,
input logic [WIDTH-1:0] A, B,
input logic [2:0] Funct3,
input logic [2:0] ZBKBSelect,
output logic [WIDTH-1:0] ZBKBResult
);
logic [WIDTH-1:0] ByteResult; // rev8, brev8
logic [WIDTH-1:0] Brev8Result; // rev8, brev8
logic [WIDTH-1:0] PackResult; // pack, packh, packw (RB64 only)
logic [WIDTH-1:0] ZipResult; // zip, unzip
byteop #(WIDTH) rev(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
// brev8 just uses wires
genvar i, j;
for (i=0;i<WIDTH/8;i=i+1)
for (j=0; j<8; j=j+1)
assign Brev8Result[i*8+j] = A[i*8+7-j];
packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult);
// ZBKB Result Select Mux
mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
mux3 #(WIDTH) zbkbresultmux(Brev8Result, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
endmodule

4
src/ieu/kmu/zbkx.sv
View File

@ -27,7 +27,7 @@
module zbkx #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B,
input logic [2:0] ZBKXSelect,
input logic ZBKXSelect,
output logic [WIDTH-1:0] ZBKXResult
);
@ -46,5 +46,5 @@ module zbkx #(parameter WIDTH=32) (
end
end
assign ZBKXResult = ZBKXSelect[0] ? xperm4 : xperm8;
assign ZBKXResult = ZBKXSelect ? xperm4 : xperm8;
endmodule

7
src/ieu/kmu/zknde32.sv
View File

@ -28,7 +28,7 @@
module zknde32 import cvw::*; #(parameter cvw_t P) (
input logic [31:0] A, B,
input logic [6:0] Funct7,
input logic [1:0] bs,
input logic [3:0] round,
input logic [3:0] ZKNSelect,
output logic [31:0] ZKNDEResult
@ -39,7 +39,7 @@ module zknde32 import cvw::*; #(parameter cvw_t P) (
logic [31:0] ZKNEResult, ZKNDResult, rotin, rotout;
// Initial shamt and Sbox input selection steps shared between encrypt and decrypt
assign shamt = {Funct7[6:5], 3'b0}; // shamt = bs * 8 (convert bytes to bits)
assign shamt = {bs, 3'b0}; // shamt = bs * 8 (convert bytes to bits)
assign SboxIn = B[shamt +: 8]; // select byte bs of rs2
// Handle logic specific to encrypt or decrypt
@ -55,6 +55,7 @@ module zknde32 import cvw::*; #(parameter cvw_t P) (
assign rotin = ZKNEResult;
// final rotate and XOR steps shared between encrypt and decrypt
rotate #(32) mrot(rotin, shamt, rotout); // Rotate the mixcolumns output left by shamt (bs * 8)
mux4 #(32) mrotmux(rotin, {rotin[23:0], rotin[31:24]},
{rotin[15:0], rotin[31:16]}, {rotin[7:0], rotin[31:8]}, bs, rotout); // Rotate the mixcolumns output left by shamt (bs * 8)
assign ZKNDEResult = A ^ rotout; // xor with running value (A = rs1)
endmodule

7
src/ieu/kmu/zknde64.sv
View File

@ -28,7 +28,6 @@
module zknde64 import cvw::*; #(parameter cvw_t P) (
input logic [63:0] A, B,
input logic [6:0] Funct7,
input logic [3:0] round,
input logic [3:0] ZKNSelect,
output logic [63:0] ZKNDEResult
@ -39,11 +38,13 @@ module zknde64 import cvw::*; #(parameter cvw_t P) (
if (P.ZKND_SUPPORTED) // ZKND supports aes64ds, aes64dsm, aes64im
aes64d aes64d(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .aes64im(ZKNSelect[3]), .result(aes64dRes)); // decode AES
if (P.ZKNE_SUPPORTED) // ZKNE supports aes64es, aes64esm
if (P.ZKNE_SUPPORTED) begin // ZKNE supports aes64es, aes64esm
aes64e aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
end else
assign Sbox0In = SboxKIn;
// One S Box is always needed for aes64ks1i and is also needed for aes64e if that is supported. Put it at the top level to allow sharing
mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
aessbox32 sbox(Sbox0In, Sbox0Out); // Substitute bytes of value obtained for tmp2 using Rijndael sbox
// Both ZKND and ZKNE support aes64ks1i and aes64ks2 instructions

24
src/ieu/sha/sha256.sv
View File

@ -37,24 +37,24 @@ module sha256 (
// sha256{sig0/sig1/sum0/sum1} select shifted operands for 32-bit xor3 and then sign-extend
// sha256sig0
assign x[0][0] = {A[6:0], A[31:7]};
assign x[0][1] = {A[17:0], A[31:18]};
assign x[0][2] = {3'b0, A[31:3]};
assign x[0][0] = {A[6:0], A[31:7]}; // ror 7
assign x[0][1] = {A[17:0], A[31:18]}; // ror 18
assign x[0][2] = {3'b0, A[31:3]}; // >> 3
// sha256sig1
assign x[1][0] = {A[16:0], A[31:17]};
assign x[1][1] = {A[18:0], A[31:19]};
assign x[1][2] = {10'b0, A[31:10]};
assign x[1][0] = {A[16:0], A[31:17]}; // ror 17
assign x[1][1] = {A[18:0], A[31:19]}; // ror 19
assign x[1][2] = {10'b0, A[31:10]}; // >> 10
// sha256sum0
assign x[2][0] = {A[1:0], A[31:2]};
assign x[2][1] = {A[12:0], A[31:13]};
assign x[2][2] = {A[21:0], A[31:22]};
assign x[2][0] = {A[1:0], A[31:2]}; // ror 2
assign x[2][1] = {A[12:0], A[31:13]}; // ror 13
assign x[2][2] = {A[21:0], A[31:22]}; // ror 22
// sha256sum1
assign x[3][0] = {A[5:0], A[31:6]};
assign x[3][1] ={A[10:0], A[31:11]};
assign x[3][2] = {A[24:0], A[31:25]};
assign x[3][0] = {A[5:0], A[31:6]}; // ror 6
assign x[3][1] ={ A[10:0], A[31:11]}; // ror 11
assign x[3][2] = {A[24:0], A[31:25]}; // ror 25
// 32-bit muxes to select inputs to xor3 for sha256
assign y[0] = x[ZKNHSelect[1:0]][0];

74
src/ieu/sha/sha512_32.sv
View File

@ -31,67 +31,39 @@ module sha512_32 (
output logic [31:0] result
);
logic [31:0] x[6][6];
logic [31:0] y[6];
logic [31:0] x[4][3];
logic [31:0] y[3];
// sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor6
// rotate/shift a 64-bit value contained in {B, A} and select 32 bits
// sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor
// sha512sig0h
assign x[0][0] = A >> 1;
assign x[0][1] = A >> 7;
assign x[0][2] = A >> 8;
assign x[0][3] = B << 31;
assign x[0][4] = B << 24;
assign x[0][5] = '0;
// The l flavors differ from h by using low bits of B instead of zeros in x[0/1][2]
// sha512sig0l
assign x[1][0] = A >> 1;
assign x[1][1] = A >> 7;
assign x[1][2] = A >> 8;
assign x[1][3] = B << 31;
assign x[1][4] = B << 25;
assign x[1][5] = B << 24;
// sha512sig0h/l
assign x[0][0] = {B[0], A[31:1]}; // ror 1
assign x[0][1] = {B[7:0], A[31:8]}; // ror 8
assign x[0][2] = {B[6:0] & {7{ZKNHSelect[0]}}, A[31:7]}; // ror/srl 7
// sha512sig1h
assign x[2][0] = A << 3;
assign x[2][1] = A >> 6;
assign x[2][2] = A >> 19;
assign x[2][3] = B >> 29;
assign x[2][4] = B << 13;
assign x[2][5] = '0;
// sha512sig1l
assign x[3][0] = A << 3;
assign x[3][1] = A >> 6;
assign x[3][2] = A >> 19;
assign x[3][3] = B >> 29;
assign x[3][4] = B << 26;
assign x[3][5] = B << 13;
// sha512sig1h/l
assign x[1][0] = {A[28:0], B[31:29]}; // ror 61
assign x[1][1] = {B[18:0], A[31:19]}; // ror 19
assign x[1][2] = {B[5:0] & {6{ZKNHSelect[0]}}, A[31:6]}; // ror/srl 6
// sha512sum0r
assign x[4][0] = A << 25;
assign x[4][1] = A << 30;
assign x[4][2] = A >> 28;
assign x[4][3] = B >> 7;
assign x[4][4] = B >> 2;
assign x[4][5] = B << 4;
assign x[2][0] = {A[6:0], B[31:7]}; // ror 39
assign x[2][1] = {A[1:0], B[31:2]}; // ror 34
assign x[2][2] = {B[27:0], A[31:28]}; // ror 28
// sha512sum1r
assign x[5][0] = A << 23;
assign x[5][1] = A >> 14;
assign x[5][2] = A >> 18;
assign x[5][3] = B >> 9;
assign x[5][4] = B << 18;
assign x[5][5] = B << 14;
assign x[3][0] = {A[8:0], B[31:9]}; // ror 41
assign x[3][1] = {B[13:0], A[31:14]}; // ror 14
assign x[3][2] = {B[17:0], A[31:18]}; // ror 18
// 32-bit muxes to select inputs to xor6 for sha512
assign y[0] = x[ZKNHSelect[2:0]][0];
assign y[1] = x[ZKNHSelect[2:0]][1];
assign y[2] = x[ZKNHSelect[2:0]][2];
assign y[3] = x[ZKNHSelect[2:0]][3];
assign y[4] = x[ZKNHSelect[2:0]][4];
assign y[5] = x[ZKNHSelect[2:0]][5];
assign y[0] = x[ZKNHSelect[2:1]][0];
assign y[1] = x[ZKNHSelect[2:1]][1];
assign y[2] = x[ZKNHSelect[2:1]][2];
// sha512 32-bit xor6
assign result = y[0] ^ y[1] ^ y[2] ^ y[3] ^ y[4] ^ y[5];
assign result = y[0] ^ y[1] ^ y[2];
endmodule

26
src/ieu/sha/sha512_64.sv
View File

@ -34,27 +34,27 @@ module sha512_64 (
logic [63:0] x[4][3];
logic [63:0] y[3];
// sha512{sig0/sig1/sum0/sum1} select shifted operands for 64-bit xor3
// sha512{sig0/sig1/sum0/sum1} select rotated/shifted operands for 64-bit xor3
// sha512sig0
assign x[0][0] = {A[0], A[63:1]};
assign x[0][1] = {A[7:0], A[63:8]};
assign x[0][2] = A >> 7;
assign x[0][0] = {A[0], A[63:1]}; // ror 1
assign x[0][1] = {A[7:0], A[63:8]}; // ror 8
assign x[0][2] = {7'b0, A[63:7]}; // >> 7
// sha512sig1
assign x[1][0] = {A[18:0], A[63:19]};
assign x[1][1] = {A[60:0], A[63:61]};
assign x[1][2] = A >> 6;
assign x[1][0] = {A[18:0], A[63:19]}; // ror 19
assign x[1][1] = {A[60:0], A[63:61]}; // ror 61
assign x[1][2] = {6'b0, A[63:6]}; // >> 6
// sha512sum0
assign x[2][0] = {A[27:0], A[63:28]};
assign x[2][1] = {A[33:0], A[63:34]};
assign x[2][2] = {A[38:0], A[63:39]};
assign x[2][0] = {A[27:0], A[63:28]}; // ror 28
assign x[2][1] = {A[33:0], A[63:34]}; // ror 34
assign x[2][2] = {A[38:0], A[63:39]}; // ror 39
// sha512sum1
assign x[3][0] = {A[13:0], A[63:14]};
assign x[3][1] = {A[17:0], A[63:18]};
assign x[3][2] = {A[40:0], A[63:41]};
assign x[3][0] = {A[13:0], A[63:14]}; // ror 14
assign x[3][1] = {A[17:0], A[63:18]}; // ror 18
assign x[3][2] = {A[40:0], A[63:41]}; // ror 41
// 64-bit muxes to select inputs to xor3 for sha512
assign y[0] = x[ZKNHSelect[1:0]][0];

3
testbench/testbench-imperas.sv
View File

@ -149,10 +149,11 @@ module testbench;
$display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
$fatal;
end
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org"));
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv"));
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC"));
void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 39));
void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56));
void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
if (!rvviRefInit(elffilename)) begin

157
testbench/testbench.sv
View File

@ -68,7 +68,7 @@ module testbench;
logic ResetMem;
// Variables that can be overwritten with $value$plusargs at start of simulation
string TEST;
string TEST, ElfFile;
integer INSTR_LIMIT;
// DUT signals
@ -115,6 +115,10 @@ module testbench;
// look for arguments passed to simulation, or use defaults
if (!$value$plusargs("TEST=%s", TEST))
TEST = "none";
if (!$value$plusargs("ElfFile=%s", ElfFile))
ElfFile = "none";
else begin
end
if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
INSTR_LIMIT = 0;
@ -221,8 +225,12 @@ module testbench;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
endcase
end
if (tests.size() == 0) begin
$display("TEST %s not supported in this configuration", TEST);
if (tests.size() == 0 & ElfFile == "none") begin
if (tests.size() == 0) begin
$display("TEST %s not supported in this configuration", TEST);
end else if(ElfFile == "none") begin
$display("ElfFile %s not found", ElfFile);
end
$finish;
end
`ifdef MAKEVCD
@ -257,7 +265,7 @@ module testbench;
logic ResetCntRst;
logic CopyRAM;
string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
string signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
integer begin_signature_addr, end_signature_addr, signature_size;
integer uartoutfile;
@ -356,21 +364,27 @@ module testbench;
//end // added
//always @(posedge SelectTest) // added
if(SelectTest) begin
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else if(TEST == "buildroot") begin
if (riscofTest) begin
memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
elffilename = {pathname, tests[test], "ref/ref.elf"};
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
end else if(TEST == "buildroot") begin
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
elffilename = "buildroot";
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
uartoutfilename = {"logs/", TEST, "_uart.out"};
uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
end
else memfilename = {pathname, tests[test], ".elf.memfile"};
if (riscofTest) begin
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
end else if (TEST == "buildroot") begin
ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
end else if(ElfFile != "none") begin
elffilename = ElfFile;
memfilename = {ElfFile, ".memfile"};
ProgramAddrMapFile = {ElfFile, ".objdump.addr"};
ProgramLabelMapFile = {ElfFile, ".objdump.lab"};
end else begin
elffilename = {pathname, tests[test], ".elf"};
memfilename = {pathname, tests[test], ".elf.memfile"};
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
end
@ -410,6 +424,15 @@ module testbench;
$display("Embench Benchmark: created output file: %s", outputfile);
end else if (TEST == "coverage64gc") begin
$display("Coverage tests don't get checked");
end else if (ElfFile != "none") begin
$display("Single Elf file tests are not signatured verified.");
`ifdef VERILATOR // this macro is defined when verilator is used
$finish; // Simulator Verilator needs $finish to terminate simulation.
`elsif SIM_VCS // this macro is defined when vcs is used
$finish; // Simulator VCS needs $finish to terminate simulation.
`else
$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
`endif
end else begin
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
// clear signature to prevent contamination from previous tests
@ -658,7 +681,7 @@ end
wallyTracer #(P) wallyTracer(rvvi);
trace2log idv_trace2log(rvvi);
// trace2cov idv_trace2cov(rvvi);
trace2cov idv_trace2cov(rvvi);
// enabling of comparison types
trace2api #(.CMP_PC (1),
@ -669,10 +692,17 @@ end
.CMP_CSR (1)
) idv_trace2api(rvvi);
string filename;
initial begin
// imperasDV requires the elffile be defined at the begining of the simulation.
int iter;
longint x64;
int x32[2];
longint index;
string memfilenameImperasDV, bootmemfilenameImperasDV;
#1;
IDV_MAX_ERRORS = 3;
elffilename = ElfFile;
// Initialize REF (do this before initializing the DUT)
if (!rvviVersionCheck(RVVI_API_VERSION)) begin
@ -686,9 +716,57 @@ end
void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56));
void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
if (!rvviRefInit("")) begin
$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
$fatal;
if(elffilename == "buildroot") filename = "";
else filename = elffilename;
// use the ImperasDV rvviRefInit to load the reference model with an elf file
if(elffilename != "none") begin
if (!rvviRefInit(filename)) begin
$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
$fatal;
end
end else begin // for buildroot use the binary instead to load teh reference model.
if (!rvviRefInit("")) begin // still have to call with nothing
$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
$fatal;
end
memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
$display("RVVI Loading bootmem.bin");
memFile = $fopen(bootmemfilenameImperasDV, "rb");
index = 'h1000 - 8;
while(!$feof(memFile)) begin
index+=8;
readResult = $fread(x64, memFile);
if (x64 == 0) continue;
x32[0] = x64 & 'hffffffff;
x32[1] = x64 >> 32;
rvviRefMemoryWrite(0, index+0, x32[0], 4);
rvviRefMemoryWrite(0, index+4, x32[1], 4);
//$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
end
$fclose(memFile);
$display("RVVI Loading ram.bin");
memFile = $fopen(memfilenameImperasDV, "rb");
index = 'h80000000 - 8;
while(!$feof(memFile)) begin
index+=8;
readResult = $fread(x64, memFile);
if (x64 == 0) continue;
x32[0] = x64 & 'hffffffff;
x32[1] = x64 >> 32;
rvviRefMemoryWrite(0, index+0, x32[0], 4);
rvviRefMemoryWrite(0, index+4, x32[1], 4);
//$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
end
$fclose(memFile);
$display("RVVI Loading Complete");
void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
end
// Volatile CSRs
@ -744,53 +822,6 @@ end
void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
// Load memory
// *** RT: This section can probably be moved into the same chunk of code which
// loads the memories. However I'm not sure that ImperasDV supports reloading
// the memories without relaunching the simulator.
begin
longint x64;
int x32[2];
longint index;
string memfilenameImperasDV, bootmemfilenameImperasDV;
memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
$display("RVVI Loading bootmem.bin");
memFile = $fopen(bootmemfilenameImperasDV, "rb");
index = 'h1000 - 8;
while(!$feof(memFile)) begin
index+=8;
readResult = $fread(x64, memFile);
if (x64 == 0) continue;
x32[0] = x64 & 'hffffffff;
x32[1] = x64 >> 32;
rvviRefMemoryWrite(0, index+0, x32[0], 4);
rvviRefMemoryWrite(0, index+4, x32[1], 4);
//$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
end
$fclose(memFile);
$display("RVVI Loading ram.bin");
memFile = $fopen(memfilenameImperasDV, "rb");
index = 'h80000000 - 8;
while(!$feof(memFile)) begin
index+=8;
readResult = $fread(x64, memFile);
if (x64 == 0) continue;
x32[0] = x64 & 'hffffffff;
x32[1] = x64 >> 32;
rvviRefMemoryWrite(0, index+0, x32[0], 4);
rvviRefMemoryWrite(0, index+4, x32[1], 4);
//$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
end
$fclose(memFile);
$display("RVVI Loading Complete");
void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
end
end
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));

10
testbench/tests.vh
View File

@ -2279,6 +2279,7 @@ string arch64zknh[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
"rv32i_m/F_Zfa/src/fround_b1-01.S",
"rv32i_m/F_Zfa/src/froundnx_b1-01.S",
"rv32i_m/F_Zfa/src/fleq_b1-01.S",
"rv32i_m/F_Zfa/src/fleq_b19-01.S",
"rv32i_m/F_Zfa/src/fli.s-01.S",
@ -2296,6 +2297,9 @@ string arch64zknh[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
"rv32i_m/D_Zfa/src/fround_b1-01.S",
"rv32i_m/D_Zfa/src/froundnx_b1-01.S",
"rv32i_m/D_Zfa/src/fround.d_b1-01.S",
"rv32i_m/D_Zfa/src/froundnx.d_b1-01.S",
"rv32i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
"rv32i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S",
"rv32i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",
@ -2333,6 +2337,7 @@ string arch64zknh[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
"rv64i_m/F_Zfa/src/fround_b1-01.S",
"rv64i_m/F_Zfa/src/froundnx_b1-01.S",
"rv64i_m/F_Zfa/src/fleq_b1-01.S",
"rv64i_m/F_Zfa/src/fleq_b19-01.S",
"rv64i_m/F_Zfa/src/fli.s-01.S",
@ -2347,7 +2352,10 @@ string arch64zknh[] = '{
string arch64zfad[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
"rv64i_m/D_Zfa/src/fround_b1-01.S",
"rv64i_m/D_Zfa/src/fround_b1-01.S",
"rv64i_m/D_Zfa/src/froundnx_b1-01.S",
"rv64i_m/D_Zfa/src/fround.d_b1-01.S",
"rv64i_m/D_Zfa/src/froundnx.d_b1-01.S",
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S",
"rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",

63
tests/testgen/covergen.py
View File

@ -31,6 +31,12 @@ def signedImm12(imm):
imm = imm - 0x1000
return str(imm)
def signedImm20(imm):
imm = imm % pow(2, 20)
if (imm & 0x80000):
imm = imm - 0x100000
return str(imm)
def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen):
lines = "\n# Testcase " + str(desc) + "\n"
if (rs1val < 0):
@ -48,6 +54,26 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor
elif (test in itype):
lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n"
elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n"
lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1 \n"
lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
elif (test in stypes):#["sb", "sh", "sw", "sd"]
#lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
#print("Error: %s type not implemented yet" % test)
elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"]
if (randint(1,100) > 50):
rs1val = rs2val
lines = lines + "# same values in both registers\n"
lines = lines + "nop\n"
lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value that should get changed\n"
lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value that should get changed\n"
lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n"
lines = lines + "addi x0, x1, 1\n"
lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n"
lines = lines + "addi x0, x2, 2\n"
lines = lines + "nop\nnop\nnop\nnop\nnop\n"
else:
pass
#print("Error: %s type not implemented yet" % test)
@ -130,12 +156,12 @@ def make_rd_maxvals(test, storecmd, xlen):
def make_rd_rs1_eqval(test, storecmd, xlen):
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
desc = "cmp_rdm_rs1_eqval (Test rs1 = rd = " + hex(rs1val) + ")"
writeCovVector(desc, rs1, 0, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
writeCovVector(desc, rs1, 0, rd, rdval, rs2val, immval, rdval, test, storecmd, xlen)
def make_rd_rs2_eqval(test, storecmd, xlen):
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
desc = "cmp_rd_rs2_eqval (Test rs2 = rd = " + hex(rs2val) + ")"
writeCovVector(desc, 0, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
writeCovVector(desc, 0, rs2, rd, rs1val, rdval, immval, rdval, test, storecmd, xlen)
def make_rs1_rs2_eqval(test, storecmd, xlen):
[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
@ -207,17 +233,37 @@ def write_tests(coverpoints, test, storecmd, xlen):
elif (coverpoint == "cp_rs2_sign"):
make_rs2_sign(test, storecmd, xlen)
elif (coverpoint == "cp_rd_sign"):
pass # hope already covered by rd_maxvals
pass #TODO hope already covered by rd_maxvals
elif (coverpoint == "cr_rs1_rs2"):
make_cr_rs1_rs2_sign(test, storecmd, xlen)
elif (coverpoint == "cp_rs1_toggle"):
pass # toggle not needed and seems to be covered by other things
pass #TODO toggle not needed and seems to be covered by other things
elif (coverpoint == "cp_rs2_toggle"):
pass # toggle not needed and seems to be covered by other things
pass #TODO toggle not needed and seems to be covered by other things
elif (coverpoint == "cp_rd_toggle"):
pass # toggle not needed and seems to be covered by other things
pass #TODO toggle not needed and seems to be covered by other things
elif (coverpoint == "cp_gpr_hazard"):
pass # not yet implemented
pass #TODO not yet implemented
elif (coverpoint == "cp_imm_sign"):
pass #TODO
elif (coverpoint == "cr_rs1_imm"):
pass #TODO (not if crosses are not needed)
elif (coverpoint == "cp_imm_ones_zeros"):
pass #TODO
elif (coverpoint == "cp_mem_hazard"):
pass #TODO
elif (coverpoint == "cp_imm_zero"):
pass #TODO
elif (coverpoint == "cp_mem_unaligned"):
pass #TODO
elif (coverpoint == "cp_offset"):
pass #TODO
elif (coverpoint == "cr_nord_rs1_rs2"):
pass #TODO (not if crosses are not needed)
elif (coverpoint == "cp_imm_shift"):
pass #TODO
elif (coverpoint == "cp_rd_boolean"):
pass #TODO
else:
print("Warning: " + coverpoint + " not implemented yet for " + test)
@ -238,6 +284,7 @@ def getcovergroups(coverdefdir, coverfiles):
if (m):
coverpoints[curinstr].append(m.group(1))
f.close()
print(coverpoints)
return coverpoints
##################################
@ -258,6 +305,8 @@ shiftitype = ["slli", "srli", "srai"]
itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"]
stypes = ["sb", "sh", "sw", "sd"]
btypes = ["beq", "bne", "blt", "bge", "bltu", "bgeu"]
# TODO: auipc missing, check whatelse is missing in ^these^ types
coverpoints = getcovergroups(coverdefdir, coverfiles)
author = "David_Harris@hmc.edu"

353
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/froundnx.d_b1-01.S Normal file
View File

@ -0,0 +1,353 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.12.1
// timestamp : Mon Apr 1 19:41:20 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/froundnx.d.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the froundnx.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the froundnx.d_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",froundnx.d_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f29; dest:f30; op1val:0x8000000000000000; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f30, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f29, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f27; dest:f28; op1val:0x8000000000000001; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f25; dest:f26; op1val:0x8000000000000002; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f23; dest:f24; op1val:0x800fffffffffffff; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f24; dest:f23; op1val:0x10000000000000; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f21; dest:f22; op1val:0x8010000000000000; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f22; dest:f21; op1val:0x10000000000002; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f19; dest:f20; op1val:0x8010000000000002; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f18; dest:f17; op1val:0x7ff0000000000000; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f15; dest:f16; op1val:0xfff0000000000000; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f12; dest:f11; op1val:0x7ff0000000000001; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f9; dest:f10; op1val:0xfff0000000000001; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f10; dest:f9; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f7; dest:f8; op1val:0xbf80000000000000; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f7,
/* opcode: froundnx.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rd==f6,
/* opcode: froundnx.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f6, rd==f5,
/* opcode: froundnx.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rd==f4,
/* opcode: froundnx.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f4, rd==f3,
/* opcode: froundnx.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f1, rd==f2,
/* opcode: froundnx.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f2, rd==f1,
/* opcode: froundnx.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,
/* opcode: froundnx.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// rd==f0,
/* opcode: froundnx.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(9223372036854775809,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(9223372036854775810,64,FLEN)
NAN_BOXED(4503599627370495,64,FLEN)
NAN_BOXED(9227875636482146303,64,FLEN)
NAN_BOXED(4503599627370496,64,FLEN)
NAN_BOXED(9227875636482146304,64,FLEN)
NAN_BOXED(4503599627370498,64,FLEN)
NAN_BOXED(9227875636482146306,64,FLEN)
NAN_BOXED(9218868437227405311,64,FLEN)
NAN_BOXED(18442240474082181119,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(9221120237041090560,64,FLEN)
NAN_BOXED(18444492273895866368,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

353
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/froundnx_b1-01.S Normal file
View File

@ -0,0 +1,353 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.12.1
// timestamp : Wed Mar 6 21:52:24 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/froundnx.s.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the froundnx.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the froundnx_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f30, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f29, f30, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f28, f27, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f27, f28, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f26, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f25, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f24, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f23, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f22, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f21, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f20, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f19, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f18, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f17, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f16, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f15, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f14, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f13, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f12, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f11, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f10, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f9, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f8, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f7,
/* opcode: froundnx.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f7, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rd==f6,
/* opcode: froundnx.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f6, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f6, rd==f5,
/* opcode: froundnx.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f5, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rd==f4,
/* opcode: froundnx.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f4, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f4, rd==f3,
/* opcode: froundnx.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f3, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f1, rd==f2,
/* opcode: froundnx.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f2, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f2, rd==f1,
/* opcode: froundnx.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f1, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,
/* opcode: froundnx.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f0, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rd==f0,
/* opcode: froundnx.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f0, f31, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

353
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/froundnx_b1-01.S Normal file
View File

@ -0,0 +1,353 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.12.1
// timestamp : Mon Apr 1 19:36:23 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/froundnx.s.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the froundnx.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the froundnx_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f30, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f29, f30, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f28, f27, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f27, f28, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f26, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f25, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f24, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f23, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f22, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f21, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f20, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f19, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f18, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f17, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f16, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f15, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f14, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f13, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f12, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f11, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f10, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f9, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f8, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f7,
/* opcode: froundnx.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f7, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rd==f6,
/* opcode: froundnx.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f6, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f6, rd==f5,
/* opcode: froundnx.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f5, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rd==f4,
/* opcode: froundnx.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f4, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f4, rd==f3,
/* opcode: froundnx.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f3, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f1, rd==f2,
/* opcode: froundnx.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f2, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f2, rd==f1,
/* opcode: froundnx.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f1, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,
/* opcode: froundnx.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f0, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rd==f0,
/* opcode: froundnx.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f0, f31, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

353
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx.d_b1-01.S Normal file
View File

@ -0,0 +1,353 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.12.1
// timestamp : Mon Apr 1 19:41:22 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/froundnx.d.cgf \
\
// -- xlen 64 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the froundnx.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the froundnx.d_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IFD_Zicsr_Zfa")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",froundnx.d_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f29; dest:f30; op1val:0x8000000000000000; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f30, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f29, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f27; dest:f28; op1val:0x8000000000000001; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f25; dest:f26; op1val:0x8000000000000002; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f23; dest:f24; op1val:0x800fffffffffffff; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f24; dest:f23; op1val:0x10000000000000; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f21; dest:f22; op1val:0x8010000000000000; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f22; dest:f21; op1val:0x10000000000002; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f19; dest:f20; op1val:0x8010000000000002; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f18; dest:f17; op1val:0x7ff0000000000000; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f15; dest:f16; op1val:0xfff0000000000000; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f12; dest:f11; op1val:0x7ff0000000000001; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f9; dest:f10; op1val:0xfff0000000000001; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f10; dest:f9; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.d ; op1:f7; dest:f8; op1val:0xbf80000000000000; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f7,
/* opcode: froundnx.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rd==f6,
/* opcode: froundnx.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f6, rd==f5,
/* opcode: froundnx.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rd==f4,
/* opcode: froundnx.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f4, rd==f3,
/* opcode: froundnx.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f1, rd==f2,
/* opcode: froundnx.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f2, rd==f1,
/* opcode: froundnx.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,
/* opcode: froundnx.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// rd==f0,
/* opcode: froundnx.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.d, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(9223372036854775809,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(9223372036854775810,64,FLEN)
NAN_BOXED(4503599627370495,64,FLEN)
NAN_BOXED(9227875636482146303,64,FLEN)
NAN_BOXED(4503599627370496,64,FLEN)
NAN_BOXED(9227875636482146304,64,FLEN)
NAN_BOXED(4503599627370498,64,FLEN)
NAN_BOXED(9227875636482146306,64,FLEN)
NAN_BOXED(9218868437227405311,64,FLEN)
NAN_BOXED(18442240474082181119,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(9221120237041090560,64,FLEN)
NAN_BOXED(18444492273895866368,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

353
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx_b1-01.S Normal file
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@ -0,0 +1,353 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.12.1
// timestamp : Wed Mar 6 21:52:28 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/froundnx.s.cgf \
\
// -- xlen 64 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the froundnx.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the froundnx_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f30, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f29, f30, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f28, f27, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f27, f28, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f26, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f25, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f24, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f23, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f22, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f21, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f20, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f19, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f18, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f17, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f16, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f15, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f14, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f13, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f12, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f11, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f10, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f9, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: froundnx.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f8, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f7,
/* opcode: froundnx.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f7, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rd==f6,
/* opcode: froundnx.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f6, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f6, rd==f5,
/* opcode: froundnx.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f5, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rd==f4,
/* opcode: froundnx.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f4, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f4, rd==f3,
/* opcode: froundnx.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f3, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f1, rd==f2,
/* opcode: froundnx.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f2, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f2, rd==f1,
/* opcode: froundnx.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f1, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,
/* opcode: froundnx.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f0, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rd==f0,
/* opcode: froundnx.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f0, f31, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

353
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/froundnx_b1-01.S Normal file
View File

@ -0,0 +1,353 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.12.1
// timestamp : Mon Apr 1 19:36:25 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/froundnx.s.cgf \
\
// -- xlen 64 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the froundnx.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the froundnx_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f30, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f29; dest:f29; op1val:0x80000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f30, f31, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f28, f27, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f27, f28, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f26, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f25, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f24, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f23, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f22, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f21, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f20, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f19, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f18, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f17, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f16, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f15, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f14, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f13, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f12, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f11, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f10, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f9, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
/* opcode: froundnx.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f8, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f7,
/* opcode: froundnx.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f7, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rd==f6,
/* opcode: froundnx.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f6, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f6, rd==f5,
/* opcode: froundnx.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f5, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rd==f4,
/* opcode: froundnx.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f4, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f4, rd==f3,
/* opcode: froundnx.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f3, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f1, rd==f2,
/* opcode: froundnx.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f2, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f2, rd==f1,
/* opcode: froundnx.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f1, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,
/* opcode: froundnx.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f31, f0, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rd==f0,
/* opcode: froundnx.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(froundnx.s, f0, f31, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END