mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added GUI support and removed unused wave files
This commit is contained in:
David Harris
parent
d3d39d39d0
commit
6b844a2e6e
@ -20,6 +20,10 @@ from multiprocessing import Pool, TimeoutError
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# Define lists of configurations and tests to run on each configuration
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# Define lists of configurations and tests to run on each configuration
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##################################
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##################################
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# The tests are a list with one element for each configuration
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# The element consists of the configuration name, a list of test suites to run,
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# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
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INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
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INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
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tests = [
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tests = [
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["rv32e", ["arch32e"]],
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["rv32e", ["arch32e"]],
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@ -192,43 +196,19 @@ class bcolors:
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BOLD = '\033[1m'
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BOLD = '\033[1m'
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UNDERLINE = '\033[4m'
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UNDERLINE = '\033[4m'
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#def getBuildrootTC(boot):
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# INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
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# BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot configOptions -GINSTR_LIMIT=" +str(INSTR_LIMIT) + " \n!"
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# BRgrepstr=str(INSTR_LIMIT)+" instructions"
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# MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
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# if boot:
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# name="buildrootboot"
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# BRcmd="vsim > {} -c <<!\ndo wally.do buildroot buildroot-no-trace $RISCV 0 1 0\n!"
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# BRgrepstr="WallyHostname login:"
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# else:
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# name="buildroot"
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# if (coverage):
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# print( "buildroot coverage")
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# BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
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# else:
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# print( "buildroot no coverage")
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# BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot configOptions -GINSTR_LIMIT=" +str(INSTR_LIMIT) + " \n!"
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# BRgrepstr=str(INSTR_LIMIT)+" instructions"
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# return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
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def addTests(tests, sim):
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def addTests(tests, sim):
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for test in tests:
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for test in tests:
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config = test[0];
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config = test[0];
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suites = test[1];
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suites = test[1];
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if (len(test) > 2):
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if (len(test) >= 3):
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args = " --args " + " ".join(test[2])
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args = " --args " + " ".join(test[2])
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else:
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else:
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args = ""
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args = ""
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if (len(test) > 3):
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if (len(test) >= 4):
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gs = test[3]
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gs = test[3]
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else:
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else:
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gs = "All tests ran without failures"
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gs = "All tests ran without failures"
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cmdPrefix="wsim -s " + sim + " " + config
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cmdPrefix="wsim --sim " + sim + " " + config
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for t in suites:
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for t in suites:
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tc = TestCase(
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tc = TestCase(
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name=t,
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name=t,
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@ -251,7 +231,6 @@ def run_test_case(config):
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cmd = config.cmd + " | tee " + logname
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cmd = config.cmd + " | tee " + logname
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else:
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else:
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cmd = config.cmd + " > " + logname
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cmd = config.cmd + " > " + logname
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print(cmd)
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os.chdir(regressionDir)
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os.chdir(regressionDir)
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# print(" run_test_case invoking %s" % cmd)
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# print(" run_test_case invoking %s" % cmd)
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os.system(cmd)
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os.system(cmd)
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@ -347,46 +326,17 @@ if (testfloat):
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]
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]
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for config in testfloatconfigs:
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for config in testfloatconfigs:
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# div test case
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# div test case
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divtest = TestCase(
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tests = ["div", "sqrt"]
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name="div",
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " div \n!",
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grepstr="All Tests completed with 0 errors"
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)
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configs.insert(0,divtest)
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# sqrt test case
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sqrttest = TestCase(
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name="sqrt",
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " sqrt \n!",
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grepstr="All Tests completed with 0 errors"
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)
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#configs.append(sqrttest)
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configs.insert(0,sqrttest)
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# skip if divider variant config
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if ("ieee" in config):
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if ("ieee" in config):
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# cvtint test case
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tests.append("cvtint")
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cvtinttest = TestCase(
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tests.append("cvtfp")
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name="cvtint",
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for test in tests:
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tc = TestCase(
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name=test,
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variant=config,
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtint \n!",
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cmd="wsim --tb testbench_fp --sim questa " + config + " " + test,
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grepstr="All Tests completed with 0 errors"
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grepstr="All Tests completed with 0 errors")
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)
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configs.append(tc)
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configs.append(cvtinttest)
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# cvtfp test case
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# WILL fail on F_only (refer to spec)
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cvtfptest = TestCase(
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name="cvtfp",
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variant=config,
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cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtfp \n!",
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grepstr="All Tests completed with 0 errors"
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)
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configs.append(cvtfptest)
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def main():
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def main():
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6
bin/wsim
6
bin/wsim
@ -40,6 +40,11 @@ if (args.coverage):
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# Launch selected simulator
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# Launch selected simulator
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cd = "cd $WALLY/sim/" +args.sim
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cd = "cd $WALLY/sim/" +args.sim
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if (args.sim == "questa"):
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if (args.sim == "questa"):
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if (args.tb == "testbench_fp"):
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args.args = " -GTEST=" + args.testsuite + " " + args.args
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# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + " -GTEST=" + args.testsuite + " " + args.args
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# else:
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# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
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cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
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cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
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if (args.coverage):
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if (args.coverage):
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cmd += " -coverage"
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cmd += " -coverage"
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@ -47,6 +52,7 @@ if (args.sim == "questa"):
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cmd = cd + "; vsim -do \"" + cmd + " +acc\""
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cmd = cd + "; vsim -do \"" + cmd + " +acc\""
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else: # launch Questa in batch mode
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else: # launch Questa in batch mode
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cmd = cd + "; vsim -c -do \"" + cmd + "\""
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cmd = cd + "; vsim -c -do \"" + cmd + "\""
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print("Running Questa with command: " + cmd)
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os.system(cmd)
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os.system(cmd)
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elif (args.sim == "verilator"):
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elif (args.sim == "verilator"):
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print("Running Verilator on %s %s", args.config, args.testsuite)
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print("Running Verilator on %s %s", args.config, args.testsuite)
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@ -1,357 +0,0 @@
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onerror {resume}
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quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/core/lsu/bus { &{/testbench/dut/core/lsu/LSUHTRANS[1], /testbench/dut/core/lsu/LSUHADDR }} test
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/dut/core/priv/priv/SATP_REGW
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add wave -noupdate -group Testbench /testbench/reset_ext
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add wave -noupdate -group Testbench -radix unsigned /testbench/InstrCountW
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add wave -noupdate -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
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add wave -noupdate -group Testbench -radix decimal /testbench/interruptInstrCount
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add wave -noupdate -group Testbench /testbench/interruptCauseVal
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add wave -noupdate -group Testbench /testbench/interruptEpcVal
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add wave -noupdate -group Testbench /testbench/interruptTVal
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add wave -noupdate -group Testbench /testbench/interruptDesc
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/priv/priv/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/ExceptionM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/textE
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add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
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add wave -noupdate -group {WriteBack stage} /testbench/textW
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add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/core/PCE
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add wave -noupdate -group PCS /testbench/dut/core/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
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add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
|
|
||||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
|
|
||||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
|
|
||||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
|
|
||||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
|
|
||||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
|
|
||||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
|
|
||||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
|
|
||||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
|
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
|
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
|
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
|
|
||||||
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
|
||||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
|
||||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
|
||||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
|
||||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
|
||||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
|
||||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
|
||||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
|
||||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
|
||||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
|
||||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
|
|
||||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM
|
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/PAdrM
|
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
|
|
||||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
|
||||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
|
|
||||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
|
|
||||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
|
||||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
|
||||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
|
||||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
|
||||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
|
||||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
|
||||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
|
||||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
|
||||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
|
||||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
|
||||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
|
||||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
|
|
||||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
|
||||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
|
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
|
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
|
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/SIN
|
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DSRb
|
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DCDb
|
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/CTSb
|
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/RIb
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/SOUT
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RTSb
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/DTRb
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT1b
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT2b
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/INTR
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/TXRDYb
|
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RXRDYb
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
|
|
||||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
|
|
||||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/test
|
|
||||||
add wave -noupdate {/testbench/dut/core/lsu/LSUHTRANS[1]}
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/LSUHADDR
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/LSUHTRANS
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/HRDATA
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/LSUHWDATA
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
|
||||||
add wave -noupdate /testbench/dut/core/priv/priv/PrivilegeModeW
|
|
||||||
TreeUpdate [SetDefaultTree]
|
|
||||||
WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {165196425 ns} 0} {{Cursor 4} {165662196 ns} 1} {{Cursor 5} {165196436 ns} 1}
|
|
||||||
quietly wave cursor active 3
|
|
||||||
configure wave -namecolwidth 250
|
|
||||||
configure wave -valuecolwidth 314
|
|
||||||
configure wave -justifyvalue left
|
|
||||||
configure wave -signalnamewidth 1
|
|
||||||
configure wave -snapdistance 10
|
|
||||||
configure wave -datasetprefix 0
|
|
||||||
configure wave -rowmargin 4
|
|
||||||
configure wave -childrowmargin 2
|
|
||||||
configure wave -gridoffset 0
|
|
||||||
configure wave -gridperiod 1
|
|
||||||
configure wave -griddelta 40
|
|
||||||
configure wave -timeline 0
|
|
||||||
configure wave -timelineunits ns
|
|
||||||
update
|
|
||||||
WaveRestoreZoom {165196205 ns} {165196487 ns}
|
|
||||||
@ -1,3 +1,4 @@
|
|||||||
|
# Run TestFloat simulation
|
||||||
|
|
||||||
# cvtint - test integer conversion unit (fcvtint)
|
# cvtint - test integer conversion unit (fcvtint)
|
||||||
# cvtfp - test floating-point conversion unit (fcvtfp)
|
# cvtfp - test floating-point conversion unit (fcvtfp)
|
||||||
@ -10,4 +11,7 @@
|
|||||||
# sqrt - test square root
|
# sqrt - test square root
|
||||||
# all - test everything
|
# all - test everything
|
||||||
|
|
||||||
vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
||||||
|
wsim fdqh_ieee_rv64gc $1 --tb testbench_fp
|
||||||
|
#wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui
|
||||||
|
|
||||||
|
|||||||
@ -1,55 +0,0 @@
|
|||||||
# testfloat-batch.do
|
|
||||||
#
|
|
||||||
# Modification by Oklahoma State University & Harvey Mudd College
|
|
||||||
# Use with Testbench
|
|
||||||
# James Stine, 2008; David Harris 2021; Kevin Kim 2024
|
|
||||||
# Go Cowboys!!!!!!
|
|
||||||
#
|
|
||||||
# Takes 1:10 to run RV64IC tests using gui
|
|
||||||
|
|
||||||
# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
|
|
||||||
|
|
||||||
onbreak {resume}
|
|
||||||
|
|
||||||
# create library
|
|
||||||
|
|
||||||
if [file exists wkdir/work_${1}_${2}] {
|
|
||||||
vdel -lib wkdir/work_${1}_${2} -all
|
|
||||||
}
|
|
||||||
vlib wkdir/work_${1}_${2}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
# c# compile source files
|
|
||||||
# suppress spurious warnngs about
|
|
||||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
|
||||||
# because vsim will run vopt
|
|
||||||
|
|
||||||
# start and run simulation
|
|
||||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
|
||||||
# $num = the added words after the call
|
|
||||||
|
|
||||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697,7033
|
|
||||||
|
|
||||||
|
|
||||||
# Set WAV variable to avoid having any output to wave (to limit disk space)
|
|
||||||
quietly set WAV 0;
|
|
||||||
|
|
||||||
# Determine if nowave argument is provided this removes any output to
|
|
||||||
# a wlf or wave window to reduce disk space.
|
|
||||||
if {$WAV eq 0} {
|
|
||||||
puts "No wave output is selected"
|
|
||||||
} else {
|
|
||||||
puts "wave output is selected"
|
|
||||||
view wave
|
|
||||||
add log -recursive /*
|
|
||||||
do wave-fpu.do
|
|
||||||
}
|
|
||||||
|
|
||||||
# Change TEST_SIZE to only test certain FP width
|
|
||||||
# values are QP, DP, SP, HP or all for all tests
|
|
||||||
|
|
||||||
vopt +acc wkdir/work_${1}_${2}.testbench-fp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt
|
|
||||||
vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
|
|
||||||
#-- Run the Simulation
|
|
||||||
run -all
|
|
||||||
@ -1,52 +0,0 @@
|
|||||||
# testfloat.do
|
|
||||||
#
|
|
||||||
# Modification by Oklahoma State University & Harvey Mudd College
|
|
||||||
# Use with Testbench
|
|
||||||
# James Stine, 2008; David Harris 2021
|
|
||||||
# Go Cowboys!!!!!!
|
|
||||||
#
|
|
||||||
# Takes 1:10 to run RV64IC tests using gui
|
|
||||||
|
|
||||||
# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
|
|
||||||
|
|
||||||
onbreak {resume}
|
|
||||||
|
|
||||||
# create library
|
|
||||||
if [file exists work] {
|
|
||||||
vdel -all
|
|
||||||
}
|
|
||||||
vlib work
|
|
||||||
|
|
||||||
# compile source files
|
|
||||||
# suppress spurious warnngs about
|
|
||||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
|
||||||
# because vsim will run vopt
|
|
||||||
|
|
||||||
# start and run simulation
|
|
||||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
|
||||||
# $num = the added words after the call
|
|
||||||
vlog +incdir+../../config/deriv/$1 +incdir+../../config/$1 +incdir+../../config/shared ../../src/cvw.sv ../../testbench/testbench_fp.sv ../../src/fpu/*.sv ../../src/fpu/*/*.sv ../../src/generic/*.sv ../../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
|
|
||||||
|
|
||||||
# Change TEST_SIZE to only test certain FP width
|
|
||||||
# values are QP, DP, SP, HP or all for all tests
|
|
||||||
vsim -voptargs=+acc work.testbench_fp -GTEST=$2 -GTEST_SIZE="all"
|
|
||||||
|
|
||||||
# Set WAV variable to avoid having any output to wave (to limit disk space)
|
|
||||||
quietly set WAV 1;
|
|
||||||
|
|
||||||
# Determine if nowave argument is provided this removes any output to
|
|
||||||
# a wlf or wave window to reduce disk space.
|
|
||||||
if {$WAV eq 0} {
|
|
||||||
puts "No wave output is selected"
|
|
||||||
} else {
|
|
||||||
puts "wave output is selected"
|
|
||||||
view wave
|
|
||||||
add log -recursive /*
|
|
||||||
do wave-fpu.do
|
|
||||||
}
|
|
||||||
|
|
||||||
#-- Run the Simulation
|
|
||||||
run -all
|
|
||||||
noview testbench-fp.sv
|
|
||||||
view wave
|
|
||||||
|
|
||||||
@ -45,10 +45,11 @@ set CoverageVsimArg ""
|
|||||||
# it takes on different values if vsim and the do file are called from the command line or
|
# it takes on different values if vsim and the do file are called from the command line or
|
||||||
# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
|
# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
|
||||||
# variables and compacts into a single list for passing to vopt.
|
# variables and compacts into a single list for passing to vopt.
|
||||||
set configOptions ""
|
set tbArgs ""
|
||||||
set from 4
|
set from 4
|
||||||
set step 1
|
set step 1
|
||||||
set lst {}
|
set lst {}
|
||||||
|
set GUI 0
|
||||||
for {set i 0} true {incr i} {
|
for {set i 0} true {incr i} {
|
||||||
set x [expr {$i*$step + $from}]
|
set x [expr {$i*$step + $from}]
|
||||||
if {$x > $argc} break
|
if {$x > $argc} break
|
||||||
@ -57,15 +58,20 @@ for {set i 0} true {incr i} {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if {$argc >= 3} {
|
if {$argc >= 3} {
|
||||||
set configOptions $lst
|
set tbArgs $lst
|
||||||
puts $configOptions
|
puts $tbArgs
|
||||||
|
|
||||||
|
if {[lindex $lst [expr { [llength $lst] -1 } ]] eq "+acc"} {
|
||||||
|
set GUI 1
|
||||||
|
}
|
||||||
|
|
||||||
#if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
|
#if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
|
||||||
# set coverage 1
|
# set coverage 1
|
||||||
# set CoverageVoptArg "+cover=sbecf"
|
# set CoverageVoptArg "+cover=sbecf"
|
||||||
# set CoverageVsimArg "-coverage"
|
# set CoverageVsimArg "-coverage"
|
||||||
#} elseif {$3 eq "configOptions"} {
|
#} elseif {$3 eq "tbArgs"} {
|
||||||
# set configOptions $lst
|
# set tbArgs $lst
|
||||||
# puts $configOptions
|
# puts $tbArgs
|
||||||
#}
|
#}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -78,13 +84,22 @@ vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdi
|
|||||||
|
|
||||||
# start and run simulation
|
# start and run simulation
|
||||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||||
#vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
|
vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg}
|
||||||
vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${configOptions} -o testbenchopt ${CoverageVoptArg}
|
# *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim
|
||||||
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${configOptions} -fatal 7 -suppress 3829 ${CoverageVsimArg}
|
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${tbArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg}
|
||||||
|
|
||||||
# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
|
# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
|
||||||
# power add generates the logging necessary for said generation.
|
# power add generates the logging necessary for said generation.
|
||||||
# power add -r /dut/core/*
|
# power add -r /dut/core/*
|
||||||
|
if { ${GUI} } {
|
||||||
|
add log -recursive /*
|
||||||
|
if { ${TESTBENCH} eq "testbench_fp" } {
|
||||||
|
do wave-fpu.do
|
||||||
|
} else {
|
||||||
|
do wave.do
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
run -all
|
run -all
|
||||||
# power off -r /dut/core/*
|
# power off -r /dut/core/*
|
||||||
|
|
||||||
@ -99,4 +114,9 @@ if {$coverage} {
|
|||||||
# These aren't doing anything helpful
|
# These aren't doing anything helpful
|
||||||
#profile report -calltree -file wally-calltree.rpt -cutoff 2
|
#profile report -calltree -file wally-calltree.rpt -cutoff 2
|
||||||
#power report -all -bsaif power.saif
|
#power report -all -bsaif power.saif
|
||||||
|
|
||||||
|
# terminate simulation unless we need to keep the GUI running
|
||||||
|
if { ${GUI} == 0} {
|
||||||
quit
|
quit
|
||||||
|
}
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@ -34,6 +34,7 @@
|
|||||||
`endif
|
`endif
|
||||||
|
|
||||||
import cvw::*;
|
import cvw::*;
|
||||||
|
import "DPI-C" function string getenv(input string env_name);
|
||||||
|
|
||||||
module testbench;
|
module testbench;
|
||||||
/* verilator lint_off WIDTHTRUNC */
|
/* verilator lint_off WIDTHTRUNC */
|
||||||
@ -43,7 +44,6 @@ module testbench;
|
|||||||
parameter BPRED_LOGGER=0;
|
parameter BPRED_LOGGER=0;
|
||||||
parameter I_CACHE_ADDR_LOGGER=0;
|
parameter I_CACHE_ADDR_LOGGER=0;
|
||||||
parameter D_CACHE_ADDR_LOGGER=0;
|
parameter D_CACHE_ADDR_LOGGER=0;
|
||||||
parameter RISCV_DIR = "/opt/riscv";
|
|
||||||
|
|
||||||
`ifdef USE_IMPERAS_DV
|
`ifdef USE_IMPERAS_DV
|
||||||
import idvPkg::*;
|
import idvPkg::*;
|
||||||
@ -60,6 +60,7 @@ module testbench;
|
|||||||
// Variables that can be overwritten with $value$plusargs at start of simulation
|
// Variables that can be overwritten with $value$plusargs at start of simulation
|
||||||
string TEST;
|
string TEST;
|
||||||
integer INSTR_LIMIT;
|
integer INSTR_LIMIT;
|
||||||
|
string RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
|
||||||
|
|
||||||
// DUT signals
|
// DUT signals
|
||||||
logic [P.AHBW-1:0] HRDATAEXT;
|
logic [P.AHBW-1:0] HRDATAEXT;
|
||||||
|
|||||||
@ -30,8 +30,6 @@ import cvw::*;
|
|||||||
module testbench_fp;
|
module testbench_fp;
|
||||||
// Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
|
// Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
|
||||||
// to run specific precisions (e.g., quad or all)
|
// to run specific precisions (e.g., quad or all)
|
||||||
// parameter string TEST="none";
|
|
||||||
// parameter string TEST_SIZE="none";
|
|
||||||
parameter string TEST="none";
|
parameter string TEST="none";
|
||||||
parameter string TEST_SIZE="all";
|
parameter string TEST_SIZE="all";
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user