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Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.

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This commit is contained in:
Rose Thompson 2023-11-13 16:44:02 -06:00
parent a6995af91c
commit 6b7ff50a84
2 changed files with 6 additions and 6 deletions
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2
fpga/generator/xlnx_mmcm.tcl
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@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT4_USED {false} \ CONFIG.CLKOUT4_USED {false} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {23} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
CONFIG.CLKIN1_JITTER_PS {10.0} \ CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName] ] [get_ips $ipName]

10
linux/devicetree/wally-artya7.dts
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@ -21,8 +21,8 @@
cpus { cpus {
#address-cells = <0x01>; #address-cells = <0x01>;
#size-cells = <0x00>; #size-cells = <0x00>;
clock-frequency = <0x15EF3C0>; clock-frequency = <0x1312D00>;
timebase-frequency = <0x15EF3C0>; timebase-frequency = <0x1312D00>;
cpu@0 { cpu@0 {
phandle = <0x01>; phandle = <0x01>;
@ -51,7 +51,7 @@
uart@10000000 { uart@10000000 {
interrupts = <0x0a>; interrupts = <0x0a>;
interrupt-parent = <0x03>; interrupt-parent = <0x03>;
clock-frequency = <0x15EF3C0>; clock-frequency = <0x1312D00>;
reg = <0x00 0x10000000 0x00 0x100>; reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a"; compatible = "ns16550a";
}; };
@ -74,8 +74,8 @@
fifo-depth = <256>; fifo-depth = <256>;
bus-width = <4>; bus-width = <4>;
interrupt-parent = <0x03>; interrupt-parent = <0x03>;
clock = <0x15EF3C0>; clock = <0x1312D00>;
max-frequency = <0x15EF3C0>; max-frequency = <0x1312D00>;
cap-sd-highspeed; cap-sd-highspeed;
cap-mmc-highspeed; cap-mmc-highspeed;
no-sdio; no-sdio;