Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix misa synthesis bug (for real now)

Browse Source
This commit is contained in:
Domenico Ottolia 2021-04-22 15:35:20 -04:00
parent 5df6be3ad5
commit 6b4d2e9634
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
wally-pipelined/src/privileged/csrm.sv
View File

@ -107,8 +107,10 @@ module csrm #(parameter
logic WritePMPCFG0M, WritePMPCFG2M; logic WritePMPCFG0M, WritePMPCFG2M;
logic WritePMPADDRM [0:15]; logic WritePMPADDRM [0:15];
localparam MISA_26 = (`MISA) & 32'h03ffffff;
// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally // MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, {`MISA}[25:0]}; assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]};
// Write machine Mode CSRs // Write machine Mode CSRs
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS); assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS);