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Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.

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This commit is contained in:
slmnemo 2022-07-05 18:21:17 -07:00
parent 0a774d9bf3
commit 6b2125ab0e
3 changed files with 40 additions and 35 deletions
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37
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output
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@ -1,18 +1,16 @@
00000000 # test reset to zero
00000000
00000000 # output_en
00000000 # output_val
00000000 # rise_ie
00000000 # rise_ip
00000000 # fall_ie
00000000 # fall_ip
00000000 # high_ie
00000000 # high_ip
00000000 # fall_ie
ffffffff # fall_ip
00000000 # iof_en
00000000 # iof_sel
00000000 # out_xor
00000000 # reset to zero tests: input_val
00000000 # input_en
00000000 # output_en
00000000 # output_val
00000000 # rise_ie
00000000 # fall_ie
00000000 # low_ie
00000000 # high_ie
00000000 # rise_ip
00000000 # fall_ip
00000000 # high_ip
ffffffff # low_ip
00000000 # out_xor
A5A5A5A5 # test output pins
5A5AFFFF
00000000 # test input enables
@ -32,5 +30,12 @@ A5FA0000 # high_ip
00000000 # MIP = 0
00000000 # MIP = 0
00000000 # MIP = 0
00000800 # Test interrupts can be enabled and triggered: MEIP set
00000800 # Test interrupts can be enabled and triggered: MEIP set from high_ie
00000000 # MEIP = 0
00000800 # MEIP set from low_ie
00000000 # MEIP = 0
00000800 # MEIP set from rise_ie
00000000 # MEIP = 0
00000800 # MEIP set from fall_ie
00000000 # MEIP = 0

10
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
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@ -91,13 +91,3 @@ test_cases:
.4byte 0x0, 0x00000080, readmip_test # mtip should be set
.4byte 0x0, 0x0, terminate_test # terminate tests
# =========== Experimental mtime counting test ===========
# .4byte mtimecmph, 0xFFFFFFFF, write32_test # make sure mtip isn't set until ready
# .4byte mtimeh, 0x0FFFFFFF, write32_test # write near max value to mtimeh
# .4byte mtime, 0x00000000, write32_test # write small value to mtime
# .4byte 0x0, 0x000000000, readmip_test # mtip should be zero
# .4byte mtimecmp, 0x00000001, write32_test # write slightly larger value than mtime to test mtime counting
# .4byte mtimecmph, 0x0FFFFFFF, write32_test # write same value as mtimeh to test mtime counting
# .4byte 0x0, 0x00000080, readmip_test # mtip should be set since it has been at least two cycles

28
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
View File

@ -75,15 +75,13 @@ test_cases:
.4byte output_en, 0x00000000, read32_test # output_en reset to zero
.4byte output_val, 0x00000000, read32_test # output_val reset to zero
.4byte rise_ie, 0x00000000, read32_test # rise_ie reset to zero
.4byte rise_ip, 0x00000000, read32_test # rise_ip reset to zero
.4byte fall_ie, 0x00000000, read32_test # fall_ie reset to zero
.4byte fall_ip, 0xffffffff, read32_test # fall_ip reset to ones (input_val is zero)
.4byte high_ie, 0x00000000, read32_test # high_ie reset to zero
.4byte high_ip, 0x00000000, read32_test # high_ip reset to zero
.4byte low_ie, 0x00000000, read32_test # low_ie reset to zero
.4byte low_ip, 0x00000000, read32_test # low_ip reset to zero
.4byte iof_en, 0x00000000, read32_test # iof_en reset to zero
.4byte iof_sel, 0x00000000, read32_test # iof_sel reset to zero
.4byte rise_ip, 0x00000000, read32_test # rise_ip reset to zero
.4byte fall_ip, 0x00000000, read32_test # fall_ip reset to zero
.4byte high_ip, 0x00000000, read32_test # high_ip reset to zero
.4byte low_ip, 0xffffffff, read32_test # low_ip reset to ones since all zeroes
.4byte out_xor, 0x00000000, read32_test # out_xor reset to zero
# =========== Test output and input pins ===========
@ -120,7 +118,7 @@ SETUP_PLIC
.4byte fall_ip, 0x00000000, read32_test # check pending fall interrupts
.4byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts
.4byte input_val, 0xA4AA0000, read32_test # check new output matches expected output
.4byte high_ip, 0xA5FA00000, read32_test # high interrupt pending *** (is this correct?)
.4byte high_ip, 0xA5FA0000, read32_test # high interrupt pending
.4byte low_ip, 0x5BF5FFFF, read32_test # low interrupt pending should be opposite high for enabled pins
.4byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising)
.4byte fall_ip, 0x01500000, read32_test # check for changed bits (falling)
@ -137,11 +135,23 @@ SETUP_PLIC
.4byte fall_ie, 0x00010000, write32_test # enable fall interrupt on bit 16, no pending interrupt
.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
# =========== Test interrupts can be enabled and triggered
# =========== Test interrupts can be enabled and triggered ===========
.4byte high_ie, 0x00020000, write32_test # enable high interrupt on bit 17, which is pending
.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
.4byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 17, which is pending
.4byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 17
.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
.4byte low_ie, 0x00010000, write32_test # enable low interrupt on bit 16, which is pending
.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
.4byte low_ie, 0x00000000, write32_test # disable low interrupt on bit 16
.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
.4byte rise_ie, 0x00200000, write32_test # enable rise interrupt on bit 21, which is pending
.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
.4byte rise_ie, 0x00000000, write32_test # disable rise interrupt on bit 21, which is pending
.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
.4byte fall_ie, 0x01000000, write32_test # enable high interrupt on bit 24, which is pending
.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
.4byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 24, which is pending
.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
.4byte 0x0, 0x0, terminate_test # terminate tests