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Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.

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Ross Thompson 2022-03-22 22:04:06 -05:00
parent 600a97982f
commit 6ab14d7302
1 changed files with 12 additions and 13 deletions
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17
pipelined/src/privileged/csri.sv
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@ -95,21 +95,20 @@ module csri #(parameter
// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
// restricted views of registers // restricted views of registers
always_comb begin:regs
// Add MEIP read-only signal // Add MEIP read-only signal
IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
// Machine Mode // Machine Mode
MIP_REGW = IP_REGW; assign MIP_REGW = IP_REGW;
MIE_REGW = IE_REGW; assign MIE_REGW = IE_REGW;
// Supervisor mode // Supervisor mode
if (`S_SUPPORTED) begin if (`S_SUPPORTED) begin
SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible
SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222;
end else begin end else begin
SIP_REGW = 12'b0; assign SIP_REGW = 12'b0;
SIE_REGW = 12'b0; assign SIE_REGW = 12'b0;
end
end end
endmodule endmodule