diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index e10183a9e..12ab9930e 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -426,7 +426,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(MISALIGN_SUPPORT) begin subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); - subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .IMAFWriteDataM, .LittleEndianWriteDataM); + subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .CacheableM, .IMAFWriteDataM, .LittleEndianWriteDataM); end else begin subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); diff --git a/src/lsu/subwordwritedouble.sv b/src/lsu/subwordwritedouble.sv index 728a4f4aa..599d71984 100644 --- a/src/lsu/subwordwritedouble.sv +++ b/src/lsu/subwordwritedouble.sv @@ -33,6 +33,7 @@ module subwordwritedouble #(parameter LLEN) ( input logic [2:0] PAdrM, input logic FpLoadStoreM, input logic BigEndianM, + input logic CacheableM, input logic [LLEN-1:0] IMAFWriteDataM, output logic [LLEN*2-1:0] LittleEndianWriteDataM ); @@ -43,7 +44,13 @@ module subwordwritedouble #(parameter LLEN) ( logic [4:0] LengthM; // Funct3M[2] is the unsigned bit. mask upper bits. // Funct3M[1:0] is the size of the memory access. - assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM}; + // cacheable, BigEndian + // 10: PAdrM[2:0] + // 11: BigEndianPAdr + // 00: 00000 + // 01: 00111 + mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {CacheableM, BigEndianM}, PAdrSwap); + //assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM}; /* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHTRUNC */ assign BigEndianPAdr = (LLEN/4) - PAdrM - LengthM;