From 7984194c2a53a5f81d98baddfa1031b3b827916b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 16 Jan 2023 13:35:06 -0600 Subject: [PATCH 001/294] Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. --- pipelined/testbench/common/rvvitrace.sv | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/common/rvvitrace.sv b/pipelined/testbench/common/rvvitrace.sv index cc564d382..ece265583 100644 --- a/pipelined/testbench/common/rvvitrace.sv +++ b/pipelined/testbench/common/rvvitrace.sv @@ -39,6 +39,7 @@ module rvviTrace #( logic [4:0] frf_a4; logic frf_we4; logic [`XLEN-1:0] CSRArray [logic[11:0]]; + logic [`XLEN-1:0] CSRArrayOld [logic[11:0]]; logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; @@ -202,10 +203,24 @@ module rvviTrace #( assign f_wb[0][0][index] = frf_wb[index]; end + // record previous csr value. + integer index4; + always_ff @(posedge clk) begin + for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin + if(CSRArray.exists(index4)) begin + CSRArrayOld[index4] = CSRArray[index4]; + end + end + end + + // check for csr value change. + integer index5; always_comb begin - csr_wb[0][0] <= '0; - if(CSRWriteW) - csr_wb[0][0][CSRAdrW] <= 1'b1; + for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin + if(CSRArray.exists(index5)) begin + csr_wb[0][0][index5] = CSRArrayOld[index5] != CSRArray[index5] ? 1'b1 : 1'b0; + end else csr_wb[0][0][index5] = '0; + end end integer index3; From 1680f89ef3d9b7b6bf9356199f8cc707cc401ecd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 16 Jan 2023 13:57:28 -0600 Subject: [PATCH 002/294] Found a potential issue with mstatush when XLEN = 64. --- pipelined/src/privileged/csrsr.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 82e8b5d5d..88669126b 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -66,6 +66,7 @@ module csrsr ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE, /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0}; + assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, From 2ead2cdaf4509b2f01be863df211d9dbc7647666 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Tue, 17 Jan 2023 12:47:38 +0000 Subject: [PATCH 003/294] Code refactor and addition of rvvi interface --- .../ImpPublic/source/host/rvvi/rvvi-trace.sv | 102 +++++++++++ pipelined/regression/imperas.ic | 20 +++ .../wally-pipelined-imperas-no-idv.do | 55 ++++++ .../regression/wally-pipelined-imperas.do | 22 ++- .../common/{rvvitrace.sv => wallyTracer.sv} | 170 +++++++----------- pipelined/testbench/testbench_imperas.sv | 106 +++++++++-- setup.imperas.sh | 26 +++ 7 files changed, 381 insertions(+), 120 deletions(-) create mode 100644 external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv create mode 100644 pipelined/regression/imperas.ic create mode 100644 pipelined/regression/wally-pipelined-imperas-no-idv.do rename pipelined/testbench/common/{rvvitrace.sv => wallyTracer.sv} (57%) create mode 100644 setup.imperas.sh diff --git a/external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv b/external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv new file mode 100644 index 000000000..1dfe24cd5 --- /dev/null +++ b/external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2005-2023 Imperas Software Ltd., www.imperas.com + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. + * + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +`define NUM_REGS 32 +`define NUM_CSRS 4096 + +interface rvviTrace +#( + parameter int ILEN = 32, // Instruction length in bits + parameter int XLEN = 32, // GPR length in bits + parameter int FLEN = 32, // FPR length in bits + parameter int VLEN = 256, // Vector register size in bits + parameter int NHART = 1, // Number of harts reported + parameter int RETIRE = 1 // Number of instructions that can retire during valid event +); + // + // RISCV output signals + // + wire clk; // Interface clock + + wire valid [(NHART-1):0][(RETIRE-1):0]; // Retired instruction + wire [63:0] order [(NHART-1):0][(RETIRE-1):0]; // Unique instruction order count (no gaps or reuse) + wire [(ILEN-1):0] insn [(NHART-1):0][(RETIRE-1):0]; // Instruction bit pattern + wire trap [(NHART-1):0][(RETIRE-1):0]; // Trapped instruction (External to Core, eg Memory Subsystem) + wire halt [(NHART-1):0][(RETIRE-1):0]; // Halted instruction + wire intr [(NHART-1):0][(RETIRE-1):0]; // (RVFI Legacy) Flag first instruction of trap handler + wire [1:0] mode [(NHART-1):0][(RETIRE-1):0]; // Privilege mode of operation + wire [1:0] ixl [(NHART-1):0][(RETIRE-1):0]; // XLEN mode 32/64 bit + + wire [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0]; // PC of insn + wire [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0]; // PC of next instruction + + // X Registers + wire [31:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0]; // X data value + wire [31:0] x_wb [(NHART-1):0][(RETIRE-1):0]; // X data writeback (change) flag + + // F Registers + wire [31:0][(FLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0]; // F data value + wire [31:0] f_wb [(NHART-1):0][(RETIRE-1):0]; // F data writeback (change) flag + + // V Registers + wire [31:0][(VLEN-1):0] v_wdata [(NHART-1):0][(RETIRE-1):0]; // V data value + wire [31:0] v_wb [(NHART-1):0][(RETIRE-1):0]; // V data writeback (change) flag + + // Control & State Registers + wire [4095:0][(XLEN-1):0] csr [(NHART-1):0][(RETIRE-1):0]; // Full CSR Address range + wire [4095:0] csr_wb [(NHART-1):0][(RETIRE-1):0]; // CSR writeback (change) flag + + wire lrsc_cancel[(NHART-1):0][(RETIRE-1):0]; // Implementation defined cancel + + // + // Synchronization of NETs + // + wire clkD; + assign #1 clkD = clk; + + longint vslot; + always @(posedge clk) vslot++; + + string name[$]; + int value[$]; + longint tslot[$]; + int nets[string]; + + function automatic void net_push(input string vname, input int vvalue); + name.push_front(vname); + value.push_front(vvalue); + tslot.push_front(vslot); + endfunction + + function automatic int net_pop(output string vname, output int vvalue, output longint vslot); + int ok; + string msg; + if (name.size() > 0) begin + vname = name.pop_back(); + vvalue = value.pop_back(); + vslot = tslot.pop_back(); + nets[vname] = vvalue; + ok = 1; + end else begin + ok = 0; + end + return ok; + endfunction + +endinterface diff --git a/pipelined/regression/imperas.ic b/pipelined/regression/imperas.ic new file mode 100644 index 000000000..8a925389f --- /dev/null +++ b/pipelined/regression/imperas.ic @@ -0,0 +1,20 @@ +#--showoverrides +--override cpu/unaligned=F +--override refRoot/cpu/mstatus_FS=1 +# Enable the Imperas instruction coverage +-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 +-override refRoot/cpu/cv/cover=basic +-override refRoot/cpu/cv/extensions=RV32I +# Add Imperas simulator application instruction tracing +--trace +--tracechange +--traceshowicount +--tracemode +--monitornetschange +# Turn on verbose output for Imperas simulator +--verbose +# Turn on verbose output for RISCV model +--override cpu/verbose=1 +# Store simulator output to logfile +--output imperas.log + diff --git a/pipelined/regression/wally-pipelined-imperas-no-idv.do b/pipelined/regression/wally-pipelined-imperas-no-idv.do new file mode 100644 index 000000000..213355e54 --- /dev/null +++ b/pipelined/regression/wally-pipelined-imperas-no-idv.do @@ -0,0 +1,55 @@ +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals + # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. +vlog +incdir+../config/$1 \ + +incdir+../config/shared \ + ../../external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + ../testbench/testbench_imperas.sv \ + ../testbench/common/*.sv \ + ../src/*/*.sv \ + ../src/*/*/*.sv \ + -suppress 2583 \ + -suppress 7063 +vopt +acc work.testbench -G DEBUG=1 -o workopt +vsim workopt +nowarn3829 -fatal 7 \ + +testDir=$env(TESTDIR) $env(OTHERFLAGS) +view wave +#-- display input and output signals as hexidecimal values +add log -recursive /* +do wave.do + +run -all + +noview ../testbench/testbench_imperas.sv +view wave diff --git a/pipelined/regression/wally-pipelined-imperas.do b/pipelined/regression/wally-pipelined-imperas.do index 285d013fc..21ed71420 100644 --- a/pipelined/regression/wally-pipelined-imperas.do +++ b/pipelined/regression/wally-pipelined-imperas.do @@ -32,14 +32,32 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench_imperas.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +vlog +incdir+../config/$1 \ + +incdir+../config/shared \ + +define+USE_IMPERAS_DV \ + +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ + +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + ../testbench/testbench_imperas.sv \ + ../testbench/common/*.sv \ + ../src/*/*.sv \ + ../src/*/*/*.sv \ + -suppress 2583 \ + -suppress 7063 vopt +acc work.testbench -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 -fatal 7 +vsim workopt +nowarn3829 -fatal 7 \ + -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ + +testDir=$env(TESTDIR) $env(OTHERFLAGS) view wave #-- display input and output signals as hexidecimal values add log -recursive /* do wave.do run -all + noview ../testbench/testbench_imperas.sv view wave diff --git a/pipelined/testbench/common/rvvitrace.sv b/pipelined/testbench/common/wallyTracer.sv similarity index 57% rename from pipelined/testbench/common/rvvitrace.sv rename to pipelined/testbench/common/wallyTracer.sv index ece265583..2cba8d2a4 100644 --- a/pipelined/testbench/common/rvvitrace.sv +++ b/pipelined/testbench/common/wallyTracer.sv @@ -3,18 +3,11 @@ `define NUM_REGS 32 `define NUM_CSRS 4096 -`define PRINT_PC_INSTR 1 -`define PRINT_MOST 1 +`define PRINT_PC_INSTR 0 +`define PRINT_MOST 0 `define PRINT_ALL 0 -module rvviTrace #( - parameter int ILEN = `XLEN, // Instruction length in bits - parameter int XLEN = `XLEN, // GPR length in bits - parameter int FLEN = `FLEN, // FPR length in bits - parameter int VLEN = 0, // Vector register size in bits - parameter int NHART = 1, // Number of harts reported - parameter int RETIRE = 1) // Number of instructions that can retire during valid event - (); +module wallyTracer(rvviTrace rvvi); localparam NUMREGS = `E_SUPPORTED ? 16 : 32; @@ -38,55 +31,36 @@ module rvviTrace #( logic [`NUM_REGS-1:0] frf_wb; logic [4:0] frf_a4; logic frf_we4; - logic [`XLEN-1:0] CSRArray [logic[11:0]]; + logic [`XLEN-1:0] CSRArray [logic[11:0]]; logic [`XLEN-1:0] CSRArrayOld [logic[11:0]]; + logic [`XLEN-1:0] CSR_W [logic[11:0]]; logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; - - // tracer signals - logic clk; - logic valid; - logic [63:0] order [(NHART-1):0][(RETIRE-1):0]; - logic [ILEN-1:0] insn [(NHART-1):0][(RETIRE-1):0]; - logic intr [(NHART-1):0][(RETIRE-1):0]; - logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0]; - logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0]; - logic trap [(NHART-1):0][(RETIRE-1):0]; - logic halt [(NHART-1):0][(RETIRE-1):0]; - logic [1:0] mode [(NHART-1):0][(RETIRE-1):0]; - logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0]; - logic [`NUM_REGS-1:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0]; - logic [`NUM_REGS-1:0] x_wb [(NHART-1):0][(RETIRE-1):0]; - logic [`NUM_REGS-1:0][(XLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0]; - logic [`NUM_REGS-1:0] f_wb [(NHART-1):0][(RETIRE-1):0]; - logic [4095:0][(XLEN-1):0] csr [(NHART-1):0][(RETIRE-1):0]; - logic [4095:0] csr_wb [(NHART-1):0][(RETIRE-1):0]; - logic lrsc_cancel[(NHART-1):0][(RETIRE-1):0]; assign clk = testbench.dut.clk; // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet - assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD; - assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE; - assign InstrValidM = testbench.dut.core.ieu.InstrValidM; - assign InstrRawD = testbench.dut.core.ifu.InstrRawD; - assign PCNextF = testbench.dut.core.ifu.PCNextF; - assign PCF = testbench.dut.core.ifu.PCF; - assign PCD = testbench.dut.core.ifu.PCD; - assign PCE = testbench.dut.core.ifu.PCE; - assign PCM = testbench.dut.core.ifu.PCM; - assign reset = testbench.reset; - assign StallE = testbench.dut.core.StallE; - assign StallM = testbench.dut.core.StallM; - assign StallW = testbench.dut.core.StallW; - assign FlushD = testbench.dut.core.FlushD; - assign FlushE = testbench.dut.core.FlushE; - assign FlushM = testbench.dut.core.FlushM; - assign FlushW = testbench.dut.core.FlushW; - assign TrapM = testbench.dut.core.TrapM; - assign HaltM = testbench.DCacheFlushStart; + assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD; + assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE; + assign InstrValidM = testbench.dut.core.ieu.InstrValidM; + assign InstrRawD = testbench.dut.core.ifu.InstrRawD; + assign PCNextF = testbench.dut.core.ifu.PCNextF; + assign PCF = testbench.dut.core.ifu.PCF; + assign PCD = testbench.dut.core.ifu.PCD; + assign PCE = testbench.dut.core.ifu.PCE; + assign PCM = testbench.dut.core.ifu.PCM; + assign reset = testbench.reset; + assign StallE = testbench.dut.core.StallE; + assign StallM = testbench.dut.core.StallM; + assign StallW = testbench.dut.core.StallW; + assign FlushD = testbench.dut.core.FlushD; + assign FlushE = testbench.dut.core.FlushE; + assign FlushM = testbench.dut.core.FlushM; + assign FlushW = testbench.dut.core.FlushW; + assign TrapM = testbench.dut.core.TrapM; + assign HaltM = testbench.DCacheFlushStart; assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW; - assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; - assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; + assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; + assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; always_comb begin // machine CSRs @@ -136,7 +110,7 @@ module rvviTrace #( for(index = 1; index < NUMREGS; index += 1) assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; - assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3; + assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3; assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3; always_comb begin @@ -148,7 +122,7 @@ module rvviTrace #( for(index = 0; index < NUMREGS; index += 1) assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index]; - assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4; + assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4; assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4; always_comb begin @@ -157,7 +131,7 @@ module rvviTrace #( frf_wb[frf_a4] <= 1'b1; end - assign CSRAdrM = testbench.dut.core.priv.priv.csr.CSRAdrM; + assign CSRAdrM = testbench.dut.core.priv.priv.csr.CSRAdrM; assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM; // pipeline to writeback stage @@ -175,89 +149,77 @@ module rvviTrace #( flopenrc #(1) IntrMReg (clk, reset, FlushM, ~StallM, IntrE, IntrM); flopenrc #(1) IntrWReg (clk, reset, FlushW, ~StallW, IntrM, IntrW); - flopenrc #(12) CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW); - flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); + flopenrc #(12) CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW); + flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. - assign valid = InstrValidW & ~StallW & ~FlushW; - assign order[0][0] = CSRArray[12'hB02]; - assign insn[0][0] = InstrRawW; - assign pc_rdata[0][0] = PCW; - assign trap[0][0] = TrapW; - assign halt[0][0] = HaltW; - assign intr[0][0] = IntrW; - assign mode[0][0] = PrivilegeModeW; - assign ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 : - PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL; - assign pc_wdata[0][0] = ~FlushW ? PCM : - ~FlushM ? PCE : - ~FlushE ? PCD : - ~FlushD ? PCF : PCNextF; + assign rvvi.clk = clk; + assign rvvi.valid[0][0] = InstrValidW & ~StallW & ~FlushW; + assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order + assign rvvi.insn[0][0] = InstrRawW; + assign rvvi.pc_rdata[0][0] = PCW; + assign rvvi.trap[0][0] = 0; // TODO: IMPERAS TrapW; + assign rvvi.halt[0][0] = HaltW; + assign rvvi.intr[0][0] = IntrW; + assign rvvi.mode[0][0] = PrivilegeModeW; + assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 : + PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL; + assign rvvi.pc_wdata[0][0] = ~FlushW ? PCM : + ~FlushM ? PCE : + ~FlushE ? PCD : + ~FlushD ? PCF : PCNextF; for(index = 0; index < `NUM_REGS; index += 1) begin - assign x_wdata[0][0][index] = rf[index]; - assign x_wb[0][0][index] = rf_wb[index]; - assign f_wdata[0][0][index] = frf[index]; - assign f_wb[0][0][index] = frf_wb[index]; + assign rvvi.x_wdata[0][0][index] = rf[index]; + assign rvvi.x_wb[0][0][index] = rf_wb[index]; + assign rvvi.f_wdata[0][0][index] = frf[index]; + assign rvvi.f_wb[0][0][index] = frf_wb[index]; end // record previous csr value. integer index4; always_ff @(posedge clk) begin for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin - if(CSRArray.exists(index4)) begin + CSR_W[index4] = (CSRArrayOld[index4] != CSRArray[index4]) ? 1 : 0; CSRArrayOld[index4] = CSRArray[index4]; - end end end - + // check for csr value change. - integer index5; - always_comb begin - for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin - if(CSRArray.exists(index5)) begin - csr_wb[0][0][index5] = CSRArrayOld[index5] != CSRArray[index5] ? 1'b1 : 1'b0; - end else csr_wb[0][0][index5] = '0; - end - end - - integer index3; - - always_comb begin - for(index3 = 0; index3 < `NUM_CSRS; index3 += 1) begin - if(CSRArray.exists(index3)) - csr[0][0][index3] = CSRArray[index3]; - else - csr[0][0][index3] = '0; - end + genvar index5; + for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin + assign rvvi.csr_wb[0][0][index5] = CSR_W[index5]; + assign rvvi.csr[0][0][index5] = CSRArray[index5]; end // *** implementation only cancel? so sc does not clear? - assign lrsc_cancel[0][0] = '0; + assign rvvi.lrsc_cancel[0][0] = '0; integer index2; always_ff @(posedge clk) begin - if(valid) begin + if(rvvi.valid[0][0]) begin if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST)) - $display("order = %08d, PC = %08x, insn = %08x", order[0][0], pc_rdata[0][0], insn[0][0]); + $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]); else if(`PRINT_MOST & !`PRINT_ALL) $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", - order[0][0], pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], intr[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0], rf_a3, x_wdata[0][0][rf_a3], frf_a4, f_wdata[0][0][frf_a4], CSRAdrW, csr[0][0][CSRAdrW]); + rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]); else if(`PRINT_ALL) begin $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", - order[0][0], pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], intr[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0]); + rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]); for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin - $display("x%02d = %08x", index2, x_wdata[0][0][index2]); + $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); end for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin - $display("f%02d = %08x", index2, f_wdata[0][0][index2]); + $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); end end end - if(HaltW) $stop(); + if(HaltW) $finish; +// if(HaltW) $stop; + end diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 6e84e879b..4d100e8ad 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -31,10 +31,21 @@ `include "wally-config.vh" +// This is set from the commsnd line script +// `define USE_IMPERAS_DV + +`ifdef USE_IMPERAS_DV + `include "rvvi/imperasDV.svh" +`endif module testbench; parameter DEBUG=0; - + +`ifdef USE_IMPERAS_DV + import rvviPkg::*; + import rvviApiPkg::*; +`endif + logic clk; logic reset_ext, reset; @@ -63,7 +74,7 @@ module testbench; integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; logic DCacheFlushDone, DCacheFlushStart; string testName; - string memfilename, pathname, adrstr; + string memfilename, testDir, adrstr, elffilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -91,29 +102,54 @@ module testbench; InReset = 1; testadr = 0; testadrNoBase = 0; + +`ifdef USE_IMPERAS_DV + // Enable the trace2log module + if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin + msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE)); + end - //testName = "rv64i_m/I/src/add-01.S"; - testName = "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S"; - + if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin + msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE)); + end +`endif + + if ($value$plusargs("testDir=%s", testDir)) begin + memfilename = {testDir, "/ref/ref.elf.memfile"}; + elffilename = {testDir, "/ref/ref.elf"}; + $display($sformatf("%m @ t=%0t: loading testDir %0s", $time, testDir)); + end else begin + $error("Must specify test directory using plusarg testDir"); + end - //pathname = "../../tests/riscof/work/riscv-arch-test/"; - pathname = "../../tests/riscof/work/wally-riscv-arch-test/"; - - memfilename = {pathname, testName, "/ref/ref.elf.memfile"}; if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); else $error("Imperas test bench requires BUS."); - ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"}; - ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"}; - + ProgramAddrMapFile = {testDir, "/ref/ref.elf.objdump.addr"}; + ProgramLabelMapFile = {testDir, "/ref/ref.elf.objdump.lab"}; + // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); $display("Read memfile %s", memfilename); + end - rvviTrace rvviTrace(); + rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); + wallyTracer wallyTracer(rvvi); +`ifdef USE_IMPERAS_DV + trace2log idv_trace2log(rvvi); + + // enabling of comparison types + trace2api #(.CMP_PC (1), + .CMP_INS (1), + .CMP_GPR (1), + .CMP_FPR (1), + .CMP_VR (0), + .CMP_CSR (1) + ) idv_trace2api(rvvi); +`endif flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); @@ -254,7 +290,48 @@ module testbench; end end - +`ifdef USE_IMPERAS_DV + initial begin + + MAX_ERRS = 3; + + // Initialize REF (do this before initializing the DUT) + if (!rvviVersionCheck(RVVI_API_VERSION)) begin + msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); + end + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + if (!rvviRefInit(elffilename)) begin + msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); + end + + // Volatile CSRs + void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE + void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE + void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET + void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET + void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME + + if(`XLEN==32) begin + void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH + end + +// // Temporary fix for inexact difference +// void'(rvviRefCsrSetVolatileMask(0, 32'h001, 'h1)); // fflags +// void'(rvviRefCsrSetVolatileMask(0, 32'h003, 'h1)); // fcsr + void'(rvviRefCsrSetVolatile(0, 32'h001)); // fflags + void'(rvviRefCsrSetVolatile(0, 32'h003)); // fcsr + end + + final begin + void'(rvviRefShutdown()); + end +`endif + endmodule module riscvassertions; @@ -413,6 +490,7 @@ module copyShadow end end + endmodule task automatic updateProgramAddrLabelArray; diff --git a/setup.imperas.sh b/setup.imperas.sh new file mode 100644 index 000000000..7f3d6c3d8 --- /dev/null +++ b/setup.imperas.sh @@ -0,0 +1,26 @@ +#!/bin/bash + +echo "Imperas Environment to setup Wally" + +# Path to Wally repository +WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) +export WALLY=$(cd "$WALLY" && pwd) +echo \$WALLY set to ${WALLY} + +isetup -dv +svsetup -questa + +pushd pipelined/regression + # With IDV + IMPERAS_TOOLS=$(pwd)/imperas.ic \ + OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ + TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ + vsim -c -do "do wally-pipelined-imperas.do rv64gc" + + # Without IDV + IMPERAS_TOOLS=$(pwd)/imperas.ic \ + OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ + TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ + vsim -c -do "do wally-pipelined-imperas-no-idv.do rv64gc" +popd + From cf3223df22e8c88f9a6683d8cf96a08079ca746f Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Tue, 17 Jan 2023 13:01:01 +0000 Subject: [PATCH 004/294] refactor all rvvi into single initial block --- pipelined/testbench/testbench_imperas.sv | 103 +++++++++++------------ 1 file changed, 50 insertions(+), 53 deletions(-) diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 4d100e8ad..5c8ad2ff3 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -102,17 +102,6 @@ module testbench; InReset = 1; testadr = 0; testadrNoBase = 0; - -`ifdef USE_IMPERAS_DV - // Enable the trace2log module - if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin - msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE)); - end - - if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin - msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE)); - end -`endif if ($value$plusargs("testDir=%s", testDir)) begin memfilename = {testDir, "/ref/ref.elf.memfile"}; @@ -149,6 +138,56 @@ module testbench; .CMP_VR (0), .CMP_CSR (1) ) idv_trace2api(rvvi); + + initial begin + MAX_ERRS = 3; + + // Initialize REF (do this before initializing the DUT) + if (!rvviVersionCheck(RVVI_API_VERSION)) begin + msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); + end + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + if (!rvviRefInit(elffilename)) begin + msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); + end + + // Volatile CSRs + void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE + void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE + void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET + void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET + void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME + + if(`XLEN==32) begin + void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH + end + + // // Temporary fix for inexact difference + // void'(rvviRefCsrSetVolatileMask(0, 32'h001, 'h1)); // fflags + // void'(rvviRefCsrSetVolatileMask(0, 32'h003, 'h1)); // fcsr + void'(rvviRefCsrSetVolatile(0, 32'h001)); // fflags + void'(rvviRefCsrSetVolatile(0, 32'h003)); // fcsr + + + // Enable the trace2log module + if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin + msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE)); + end + + if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin + msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE)); + end + end + + final begin + void'(rvviRefShutdown()); + end + `endif flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); @@ -290,48 +329,6 @@ module testbench; end end -`ifdef USE_IMPERAS_DV - initial begin - - MAX_ERRS = 3; - - // Initialize REF (do this before initializing the DUT) - if (!rvviVersionCheck(RVVI_API_VERSION)) begin - msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); - end - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); - if (!rvviRefInit(elffilename)) begin - msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); - end - - // Volatile CSRs - void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE - void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE - void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET - void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET - void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME - - if(`XLEN==32) begin - void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH - void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH - void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH - void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH - end - -// // Temporary fix for inexact difference -// void'(rvviRefCsrSetVolatileMask(0, 32'h001, 'h1)); // fflags -// void'(rvviRefCsrSetVolatileMask(0, 32'h003, 'h1)); // fcsr - void'(rvviRefCsrSetVolatile(0, 32'h001)); // fflags - void'(rvviRefCsrSetVolatile(0, 32'h003)); // fcsr - end - - final begin - void'(rvviRefShutdown()); - end -`endif - endmodule module riscvassertions; From 374f95ebf3d78e67cc52d6740f3187c31ac94d57 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 17 Jan 2023 18:24:46 -0600 Subject: [PATCH 005/294] Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. --- pipelined/testbench/common/wallyTracer.sv | 147 +++++++++++++++------- pipelined/testbench/testbench_imperas.sv | 4 +- 2 files changed, 103 insertions(+), 48 deletions(-) diff --git a/pipelined/testbench/common/wallyTracer.sv b/pipelined/testbench/common/wallyTracer.sv index 2cba8d2a4..c7f68e65e 100644 --- a/pipelined/testbench/common/wallyTracer.sv +++ b/pipelined/testbench/common/wallyTracer.sv @@ -6,6 +6,7 @@ `define PRINT_PC_INSTR 0 `define PRINT_MOST 0 `define PRINT_ALL 0 +`define PRINT_CSRS 0 module wallyTracer(rvviTrace rvvi); @@ -33,7 +34,7 @@ module wallyTracer(rvviTrace rvvi); logic frf_we4; logic [`XLEN-1:0] CSRArray [logic[11:0]]; logic [`XLEN-1:0] CSRArrayOld [logic[11:0]]; - logic [`XLEN-1:0] CSR_W [logic[11:0]]; + logic [`NUM_CSRS-1:0] CSR_W; logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; @@ -49,6 +50,8 @@ module wallyTracer(rvviTrace rvvi); assign PCE = testbench.dut.core.ifu.PCE; assign PCM = testbench.dut.core.ifu.PCM; assign reset = testbench.reset; + assign StallF = testbench.dut.core.StallF; + assign StallD = testbench.dut.core.StallD; assign StallE = testbench.dut.core.StallE; assign StallM = testbench.dut.core.StallM; assign StallW = testbench.dut.core.StallW; @@ -63,46 +66,90 @@ module wallyTracer(rvviTrace rvvi); assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; always_comb begin - // machine CSRs - // *** missing PMP and performance counters. - CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; - CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; - CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW; - CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW; - CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; - CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; - CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW; - CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; - CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW; - CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW; - CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW; - CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW; - CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; - CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW; - CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW; - CSRArray[12'hF11] = 0; - CSRArray[12'hF12] = 0; - CSRArray[12'hF13] = `XLEN'h100; - CSRArray[12'hF15] = 0; - CSRArray[12'h34A] = 0; - // MCYCLE and MINSTRET - CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; - CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; - // supervisor CSRs - CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.SSTATUS_REGW; - CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; - CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.STVEC_REGW; - CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.SEPC_REGW; - CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.SCOUNTEREN_REGW; - CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.SATP_REGW; - CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; - CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; - CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; - CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; - // user CSRs - CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; - CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.FRM_REGW; - CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; + // Since we are detected the CSR change by comparing the old value we need to + // ensure the CSR is detected when the pipeline's Writeback stage is not + // stalled. If it is stalled we want CSRArray to hold the old value. + if(~StallW) begin + // machine CSRs + // *** missing PMP and performance counters. + CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; + CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; + CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW; + CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW; + CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; + CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; + CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW; + CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; + CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW; + CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW; + CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW; + CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW; + CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; + CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW; + CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW; + CSRArray[12'hF11] = 0; + CSRArray[12'hF12] = 0; + CSRArray[12'hF13] = `XLEN'h100; + CSRArray[12'hF15] = 0; + CSRArray[12'h34A] = 0; + // MCYCLE and MINSTRET + CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; + CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + // supervisor CSRs + CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.SSTATUS_REGW; + CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; + CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.STVEC_REGW; + CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.SEPC_REGW; + CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.SCOUNTEREN_REGW; + CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.SATP_REGW; + CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; + CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; + CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; + CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; + // user CSRs + CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; + CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.FRM_REGW; + CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; + end else begin // hold the old value if the pipeline is stalled. + CSRArray[12'h300] = CSRArrayOld[12'h300]; + CSRArray[12'h310] = CSRArrayOld[12'h310]; + CSRArray[12'h305] = CSRArrayOld[12'h305]; + CSRArray[12'h341] = CSRArrayOld[12'h341]; + CSRArray[12'h306] = CSRArrayOld[12'h306]; + CSRArray[12'h320] = CSRArrayOld[12'h320]; + CSRArray[12'h302] = CSRArrayOld[12'h302]; + CSRArray[12'h303] = CSRArrayOld[12'h303]; + CSRArray[12'h344] = CSRArrayOld[12'h344]; + CSRArray[12'h304] = CSRArrayOld[12'h304]; + CSRArray[12'h301] = CSRArrayOld[12'h301]; + CSRArray[12'hF14] = CSRArrayOld[12'hF14]; + CSRArray[12'h340] = CSRArrayOld[12'h340]; + CSRArray[12'h342] = CSRArrayOld[12'h342]; + CSRArray[12'h343] = CSRArrayOld[12'h343]; + CSRArray[12'hF11] = CSRArrayOld[12'hF11]; + CSRArray[12'hF12] = CSRArrayOld[12'hF12]; + CSRArray[12'hF13] = CSRArrayOld[12'hF13]; + CSRArray[12'hF15] = CSRArrayOld[12'hF15]; + CSRArray[12'h34A] = CSRArrayOld[12'h34A]; + // MCYCLE and MINSTRET + CSRArray[12'hB00] = CSRArrayOld[12'hB00]; + CSRArray[12'hB02] = CSRArrayOld[12'hB02]; + // supervisor CSRs + CSRArray[12'h100] = CSRArrayOld[12'h100]; + CSRArray[12'h104] = CSRArrayOld[12'h104]; + CSRArray[12'h105] = CSRArrayOld[12'h105]; + CSRArray[12'h141] = CSRArrayOld[12'h141]; + CSRArray[12'h106] = CSRArrayOld[12'h106]; + CSRArray[12'h180] = CSRArrayOld[12'h180]; + CSRArray[12'h140] = CSRArrayOld[12'h140]; + CSRArray[12'h143] = CSRArrayOld[12'h143]; + CSRArray[12'h142] = CSRArrayOld[12'h142]; + CSRArray[12'h144] = CSRArrayOld[12'h144]; + // user CSRs + CSRArray[12'h001] = CSRArrayOld[12'h001]; + CSRArray[12'h002] = CSRArrayOld[12'h002]; + CSRArray[12'h003] = CSRArrayOld[12'h003]; + end end genvar index; @@ -155,8 +202,10 @@ module wallyTracer(rvviTrace rvvi); // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. + logic valid; + assign valid = InstrValidW & ~StallW & ~FlushW; assign rvvi.clk = clk; - assign rvvi.valid[0][0] = InstrValidW & ~StallW & ~FlushW; + assign rvvi.valid[0][0] = valid; assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order assign rvvi.insn[0][0] = InstrRawW; assign rvvi.pc_rdata[0][0] = PCW; @@ -182,14 +231,15 @@ module wallyTracer(rvviTrace rvvi); integer index4; always_ff @(posedge clk) begin for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin - CSR_W[index4] = (CSRArrayOld[index4] != CSRArray[index4]) ? 1 : 0; - CSRArrayOld[index4] = CSRArray[index4]; + CSRArrayOld[index4] = CSRArray[index4]; end end // check for csr value change. genvar index5; for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin + // CSR_W should only indicate the change when the Writeback stage is not stalled and valid. + assign CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0; assign rvvi.csr_wb[0][0][index5] = CSR_W[index5]; assign rvvi.csr[0][0][index5] = CSRArray[index5]; end @@ -216,10 +266,15 @@ module wallyTracer(rvviTrace rvvi); $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); end end + if (`PRINT_CSRS) begin + for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin + if(CSR_W[index2]) begin + $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]); + end + end + end end if(HaltW) $finish; -// if(HaltW) $stop; - end diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 5c8ad2ff3..23aff3cba 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -124,8 +124,8 @@ module testbench; end - rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); - wallyTracer wallyTracer(rvvi); + rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); + wallyTracer wallyTracer(rvvi); `ifdef USE_IMPERAS_DV trace2log idv_trace2log(rvvi); From c120717027ebba5aca3dc3f8543dd0447ad8d64a Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 18 Jan 2023 13:19:14 +0000 Subject: [PATCH 006/294] update for private copy of Imperas --- .../ImpPublic/source/host/rvvi/rvvi-trace.sv | 102 ------------------ setup.imperas.sh | 15 ++- 2 files changed, 14 insertions(+), 103 deletions(-) delete mode 100644 external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv diff --git a/external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv b/external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv deleted file mode 100644 index 1dfe24cd5..000000000 --- a/external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2005-2023 Imperas Software Ltd., www.imperas.com - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, - * either express or implied. - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -`define NUM_REGS 32 -`define NUM_CSRS 4096 - -interface rvviTrace -#( - parameter int ILEN = 32, // Instruction length in bits - parameter int XLEN = 32, // GPR length in bits - parameter int FLEN = 32, // FPR length in bits - parameter int VLEN = 256, // Vector register size in bits - parameter int NHART = 1, // Number of harts reported - parameter int RETIRE = 1 // Number of instructions that can retire during valid event -); - // - // RISCV output signals - // - wire clk; // Interface clock - - wire valid [(NHART-1):0][(RETIRE-1):0]; // Retired instruction - wire [63:0] order [(NHART-1):0][(RETIRE-1):0]; // Unique instruction order count (no gaps or reuse) - wire [(ILEN-1):0] insn [(NHART-1):0][(RETIRE-1):0]; // Instruction bit pattern - wire trap [(NHART-1):0][(RETIRE-1):0]; // Trapped instruction (External to Core, eg Memory Subsystem) - wire halt [(NHART-1):0][(RETIRE-1):0]; // Halted instruction - wire intr [(NHART-1):0][(RETIRE-1):0]; // (RVFI Legacy) Flag first instruction of trap handler - wire [1:0] mode [(NHART-1):0][(RETIRE-1):0]; // Privilege mode of operation - wire [1:0] ixl [(NHART-1):0][(RETIRE-1):0]; // XLEN mode 32/64 bit - - wire [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0]; // PC of insn - wire [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0]; // PC of next instruction - - // X Registers - wire [31:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0]; // X data value - wire [31:0] x_wb [(NHART-1):0][(RETIRE-1):0]; // X data writeback (change) flag - - // F Registers - wire [31:0][(FLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0]; // F data value - wire [31:0] f_wb [(NHART-1):0][(RETIRE-1):0]; // F data writeback (change) flag - - // V Registers - wire [31:0][(VLEN-1):0] v_wdata [(NHART-1):0][(RETIRE-1):0]; // V data value - wire [31:0] v_wb [(NHART-1):0][(RETIRE-1):0]; // V data writeback (change) flag - - // Control & State Registers - wire [4095:0][(XLEN-1):0] csr [(NHART-1):0][(RETIRE-1):0]; // Full CSR Address range - wire [4095:0] csr_wb [(NHART-1):0][(RETIRE-1):0]; // CSR writeback (change) flag - - wire lrsc_cancel[(NHART-1):0][(RETIRE-1):0]; // Implementation defined cancel - - // - // Synchronization of NETs - // - wire clkD; - assign #1 clkD = clk; - - longint vslot; - always @(posedge clk) vslot++; - - string name[$]; - int value[$]; - longint tslot[$]; - int nets[string]; - - function automatic void net_push(input string vname, input int vvalue); - name.push_front(vname); - value.push_front(vvalue); - tslot.push_front(vslot); - endfunction - - function automatic int net_pop(output string vname, output int vvalue, output longint vslot); - int ok; - string msg; - if (name.size() > 0) begin - vname = name.pop_back(); - vvalue = value.pop_back(); - vslot = tslot.pop_back(); - nets[vname] = vvalue; - ok = 1; - end else begin - ok = 0; - end - return ok; - endfunction - -endinterface diff --git a/setup.imperas.sh b/setup.imperas.sh index 7f3d6c3d8..ac7740796 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -7,7 +7,20 @@ WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) export WALLY=$(cd "$WALLY" && pwd) echo \$WALLY set to ${WALLY} -isetup -dv +# clone the Imperas repo +if [ ! -d external ]; then + mkdir -p external +fi +pushd external + if [ ! -f ImperasDV-HMC ]; then + git clone https://github.com/Imperas/ImperasDV-HMC + fi + pushd ImperasDV-HMC + git checkout 0c2f365 + popd +popd + +isetup -dv ${WALLY}/external/ImperasDV-HMC/Imperas svsetup -questa pushd pipelined/regression From 7a4472f94ec3c60ec88a57f18bf5b02597fc7aaf Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 18 Jan 2023 13:22:32 +0000 Subject: [PATCH 007/294] ignore external --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index d4e9acd58..a7f1d43be 100644 --- a/.gitignore +++ b/.gitignore @@ -126,3 +126,4 @@ tests/custom/*/*/*.map tests/custom/*/*/*.memfile tests/custom/crt0/*.a /pipelined/regression/sd_model.log +external From 68af12ece18fe96d534acc7a1e9c01eb3d70e9f6 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 18 Jan 2023 13:26:07 +0000 Subject: [PATCH 008/294] refer to correct path --- pipelined/regression/wally-pipelined-imperas-no-idv.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/wally-pipelined-imperas-no-idv.do b/pipelined/regression/wally-pipelined-imperas-no-idv.do index 213355e54..646c41c72 100644 --- a/pipelined/regression/wally-pipelined-imperas-no-idv.do +++ b/pipelined/regression/wally-pipelined-imperas-no-idv.do @@ -34,7 +34,7 @@ vlib work # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. vlog +incdir+../config/$1 \ +incdir+../config/shared \ - ../../external/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + ../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv \ ../testbench/testbench_imperas.sv \ ../testbench/common/*.sv \ ../src/*/*.sv \ From 52ebac59b8bb8d696ed4fee73425fde9e9c81c26 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 18 Jan 2023 13:33:57 +0000 Subject: [PATCH 009/294] remove volatile for FFLAGS and FCSR --- pipelined/testbench/testbench_imperas.sv | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 23aff3cba..846662310 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -168,10 +168,8 @@ module testbench; end // // Temporary fix for inexact difference - // void'(rvviRefCsrSetVolatileMask(0, 32'h001, 'h1)); // fflags - // void'(rvviRefCsrSetVolatileMask(0, 32'h003, 'h1)); // fcsr - void'(rvviRefCsrSetVolatile(0, 32'h001)); // fflags - void'(rvviRefCsrSetVolatile(0, 32'h003)); // fcsr +// void'(rvviRefCsrSetVolatile(0, 32'h001)); // fflags +// void'(rvviRefCsrSetVolatile(0, 32'h003)); // fcsr // Enable the trace2log module From 247879e7c707c9106c1fd06825f5a195074a8c42 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 18 Jan 2023 13:37:28 +0000 Subject: [PATCH 010/294] add im flags for compressed disass --- pipelined/regression/imperas.ic | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/pipelined/regression/imperas.ic b/pipelined/regression/imperas.ic index 8a925389f..164cec228 100644 --- a/pipelined/regression/imperas.ic +++ b/pipelined/regression/imperas.ic @@ -1,20 +1,26 @@ #--showoverrides +--override cpu/show_c_prefix=T --override cpu/unaligned=F ---override refRoot/cpu/mstatus_FS=1 +--override cpu/mstatus_FS=1 + # Enable the Imperas instruction coverage -extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 -override refRoot/cpu/cv/cover=basic -override refRoot/cpu/cv/extensions=RV32I + # Add Imperas simulator application instruction tracing --trace --tracechange --traceshowicount --tracemode --monitornetschange + # Turn on verbose output for Imperas simulator --verbose + # Turn on verbose output for RISCV model --override cpu/verbose=1 + # Store simulator output to logfile --output imperas.log From 0ccab9accc949d7cf167c5193f3cec65384a486c Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 18 Jan 2023 16:46:48 +0000 Subject: [PATCH 011/294] changes made with Ross --- pipelined/regression/wave.do | 78 +++++++++++++---------- pipelined/testbench/common/wallyTracer.sv | 18 ++++-- 2 files changed, 56 insertions(+), 40 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index be29ed870..edb10fc47 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -5,37 +5,37 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -86,7 +86,6 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex @@ -571,7 +570,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y @@ -603,8 +601,18 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Br add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW +add wave -noupdate {/testbench/rvvi/csr[0][0][3]} +add wave -noupdate {/testbench/rvvi/csr[0][0][1]} +add wave -noupdate {/testbench/rvvi/csr_wb[0][0][3]} +add wave -noupdate {/testbench/rvvi/csr_wb[0][0][1]} +add wave -noupdate {/testbench/rvvi/valid[0][0]} +add wave -noupdate /testbench/rvvi/clk +add wave -noupdate {/testbench/rvvi/csr[0][0][768]} +add wave -noupdate /testbench/rvvi/csr +add wave -noupdate {/testbench/rvvi/csr_wb[0][0][768]} +add wave -noupdate /testbench/wallyTracer/InstrValidW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {104199 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -620,4 +628,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {118528 ns} {128752 ns} +WaveRestoreZoom {104186 ns} {104255 ns} diff --git a/pipelined/testbench/common/wallyTracer.sv b/pipelined/testbench/common/wallyTracer.sv index c7f68e65e..b1732488e 100644 --- a/pipelined/testbench/common/wallyTracer.sv +++ b/pipelined/testbench/common/wallyTracer.sv @@ -65,11 +65,13 @@ module wallyTracer(rvviTrace rvvi); assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; + logic valid; + always_comb begin // Since we are detected the CSR change by comparing the old value we need to // ensure the CSR is detected when the pipeline's Writeback stage is not // stalled. If it is stalled we want CSRArray to hold the old value. - if(~StallW) begin + if(valid) begin // machine CSRs // *** missing PMP and performance counters. CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; @@ -202,10 +204,9 @@ module wallyTracer(rvviTrace rvvi); // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. - logic valid; assign valid = InstrValidW & ~StallW & ~FlushW; assign rvvi.clk = clk; - assign rvvi.valid[0][0] = valid; + assign #1 rvvi.valid[0][0] = valid; assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order assign rvvi.insn[0][0] = InstrRawW; assign rvvi.pc_rdata[0][0] = PCW; @@ -231,6 +232,8 @@ module wallyTracer(rvviTrace rvvi); integer index4; always_ff @(posedge clk) begin for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin +// IMPERAS + //CSR_W[index4] = (CSRArrayOld[index4] != CSRArray[index4]) ? 1 : 0; CSRArrayOld[index4] = CSRArray[index4]; end end @@ -239,11 +242,16 @@ module wallyTracer(rvviTrace rvvi); genvar index5; for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin // CSR_W should only indicate the change when the Writeback stage is not stalled and valid. - assign CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0; + assign #2 CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0; assign rvvi.csr_wb[0][0][index5] = CSR_W[index5]; assign rvvi.csr[0][0][index5] = CSRArray[index5]; end - + +// always @rvvi.clk $display("%t @rvvi.clk=%X", $time, rvvi.clk); +// always @rvvi.csr[0][0]['h300] $display("%t rvvi.csr[0][0]['h300]=%X", $time, rvvi.csr[0][0]['h300]); +// always @rvvi.csr_wb[0][0]['h300] $display("%t rvvi.csr_wb[0][0]['h300]=%X", $time, rvvi.csr_wb[0][0]['h300]); +// always @rvvi.valid[0][0] $display("%t rvvi.valid[0][0]=%X", $time, rvvi.valid[0][0]); + // *** implementation only cancel? so sc does not clear? assign rvvi.lrsc_cancel[0][0] = '0; From 8dea3491a31f1fa2b9e3077b169ae3fb7792177e Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 18 Jan 2023 17:11:39 +0000 Subject: [PATCH 012/294] Partial fix for misaligned LD/ST --- pipelined/regression/wave.do | 81 ++++++++++++----------- pipelined/testbench/common/wallyTracer.sv | 2 +- 2 files changed, 43 insertions(+), 40 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index edb10fc47..62de1867b 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -5,48 +5,48 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/core/PCF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/core/PCE -add wave -noupdate -expand -group PCS /testbench/dut/core/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/core/PCF +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/core/PCE +add wave -noupdate -group PCS /testbench/dut/core/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -611,8 +611,11 @@ add wave -noupdate {/testbench/rvvi/csr[0][0][768]} add wave -noupdate /testbench/rvvi/csr add wave -noupdate {/testbench/rvvi/csr_wb[0][0][768]} add wave -noupdate /testbench/wallyTracer/InstrValidW +add wave -noupdate -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -color Orange /testbench/dut/core/StallW +add wave -noupdate {/testbench/rvvi/insn[0][0]} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {104199 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {4687 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -628,4 +631,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {104186 ns} {104255 ns} +WaveRestoreZoom {4636 ns} {4705 ns} diff --git a/pipelined/testbench/common/wallyTracer.sv b/pipelined/testbench/common/wallyTracer.sv index b1732488e..23aaebd10 100644 --- a/pipelined/testbench/common/wallyTracer.sv +++ b/pipelined/testbench/common/wallyTracer.sv @@ -204,7 +204,7 @@ module wallyTracer(rvviTrace rvvi); // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. - assign valid = InstrValidW & ~StallW & ~FlushW; + assign valid = InstrValidW & ~StallW; assign rvvi.clk = clk; assign #1 rvvi.valid[0][0] = valid; assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order From 474f934fd13c8d661eb1ec38f926e4e4dba81795 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 18 Jan 2023 15:49:42 -0600 Subject: [PATCH 013/294] Modified to clone imperas via git rather than https. --- setup.imperas.sh | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/setup.imperas.sh b/setup.imperas.sh index ac7740796..9a9f12f94 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -13,7 +13,7 @@ if [ ! -d external ]; then fi pushd external if [ ! -f ImperasDV-HMC ]; then - git clone https://github.com/Imperas/ImperasDV-HMC + git clone git@github.com:Imperas/ImperasDV-HMC.git fi pushd ImperasDV-HMC git checkout 0c2f365 @@ -37,3 +37,19 @@ pushd pipelined/regression vsim -c -do "do wally-pipelined-imperas-no-idv.do rv64gc" popd +# notes +# run the pushd external code + +#source external/ImperasDV-HMC/Imperas/bin/setup.sh +# setupImperas /home/ross/repos/active-wally/riscv-wally/external/ImperasDV-HMC/Imperas +# env | grep IMPERAS +# export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC + +IMPERAS_TOOLS=$(pwd)/imperas.ic \ +OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ +TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ +vsim -c -do "do wally-pipelined-imperas.do rv64gc" + + +# getting library issue. +# try switching to modelsim 2022.01 From f9b14ccdc5932c8fcfb54dc418e56b96ae53d5b2 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Thu, 19 Jan 2023 10:20:55 +0000 Subject: [PATCH 014/294] customer commands --- setup.imperas.sh | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/setup.imperas.sh b/setup.imperas.sh index ac7740796..7ec1afd99 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -1,11 +1,12 @@ #!/bin/bash -echo "Imperas Environment to setup Wally" +REPO=davidharrishmc +REPO=eroom1966 +git clone https://github.com/${REPO}/riscv-wally -b imperas -# Path to Wally repository +cd riscv-wally WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) export WALLY=$(cd "$WALLY" && pwd) -echo \$WALLY set to ${WALLY} # clone the Imperas repo if [ ! -d external ]; then @@ -16,24 +17,23 @@ pushd external git clone https://github.com/Imperas/ImperasDV-HMC fi pushd ImperasDV-HMC - git checkout 0c2f365 + git checkout fac563d popd popd -isetup -dv ${WALLY}/external/ImperasDV-HMC/Imperas +# Setup Imperas +source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh +setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas +export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC + +# setup QUESTA (Imperas only command, YMMV) svsetup -questa pushd pipelined/regression # With IDV IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ - TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ + TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ vsim -c -do "do wally-pipelined-imperas.do rv64gc" - - # Without IDV - IMPERAS_TOOLS=$(pwd)/imperas.ic \ - OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ - TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ - vsim -c -do "do wally-pipelined-imperas-no-idv.do rv64gc" popd From 52124995132cd64acf419d7992e71a9463e23638 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Thu, 19 Jan 2023 10:41:11 +0000 Subject: [PATCH 015/294] correct the HASH --- setup.imperas.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/setup.imperas.sh b/setup.imperas.sh index 7ec1afd99..d1de23ab4 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -1,5 +1,7 @@ #!/bin/bash +IMP_HASH=56b1479 + REPO=davidharrishmc REPO=eroom1966 git clone https://github.com/${REPO}/riscv-wally -b imperas @@ -17,7 +19,7 @@ pushd external git clone https://github.com/Imperas/ImperasDV-HMC fi pushd ImperasDV-HMC - git checkout fac563d + git checkout $IMP_HASH popd popd From 43d5769bd9523f6d11b3e200023261c3aeed7dc4 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Thu, 19 Jan 2023 13:29:46 +0000 Subject: [PATCH 016/294] update --- .gitignore | 1 + pipelined/regression/run-imperasdv-tests.bash | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100755 pipelined/regression/run-imperasdv-tests.bash diff --git a/.gitignore b/.gitignore index a7f1d43be..c9935826d 100644 --- a/.gitignore +++ b/.gitignore @@ -127,3 +127,4 @@ tests/custom/*/*/*.memfile tests/custom/crt0/*.a /pipelined/regression/sd_model.log external +pipelined/regression/results diff --git a/pipelined/regression/run-imperasdv-tests.bash b/pipelined/regression/run-imperasdv-tests.bash new file mode 100755 index 000000000..c037c369d --- /dev/null +++ b/pipelined/regression/run-imperasdv-tests.bash @@ -0,0 +1,22 @@ +#!/bin/bash + +if [ -d results ]; then + rm -rf results +fi +mkdir -p results + +ALL=$(find ${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m -name "ref" -type d) + +export IMPERAS_TOOLS=$(pwd)/imperas.ic +export OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" + +for t in $ALL; do + export TESTDIR=$(dirname ${t}) + OUTLOG=$(echo ${TESTDIR} | sed "s|${WALLY}/external/ImperasDV-HMC/tests/riscof/work|results|").log + OUTDIR=$(dirname ${OUTLOG}) + echo "Running test ${TESTDIR} -> ${OUTDIR} :: ${OUTLOG}" + + mkdir -p ${OUTDIR} + vsim -c -do "do wally-pipelined-imperas.do rv64gc" + mv transcript ${OUTLOG} +done From 6f3b8680d5e2467a93c151cd74c203305f354e41 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 09:41:18 -0600 Subject: [PATCH 017/294] Imperas found a bug with the Fence.I instruction. If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write. Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is to ensure the cache continues to assert Stall while in WriteLine state. There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate. Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache. --- pipelined/src/cache/cachefsm.sv | 4 ++-- pipelined/src/cache/cacheway.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 4abbe59a2..a8be120b0 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -141,7 +141,7 @@ module cachefsm assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | - (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. + (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_WRITEBACK); // write enables internal to cache @@ -181,6 +181,6 @@ module cachefsm resetDelay; assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; - assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset; + assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; endmodule // cachefsm diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 10bb4cfa0..8e9d12b18 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -152,7 +152,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, if (reset) ValidBits <= #1 '0; if(CacheEn) begin ValidWay <= #1 ValidBits[CAdr]; - if(InvalidateCache & ~FlushStage) ValidBits <= #1 '0; + if(InvalidateCache) ValidBits <= #1 '0; else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CAdr] <= #1 SetValidWay; end end From 5b740fbf60d9f9370726c622a91c7cde57d93d11 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 14:35:46 -0600 Subject: [PATCH 018/294] Removed SDC from repo due to copy right issue. Modified fpga build flow to reference it outside the repo. --- .gitignore | 2 + fpga/generator/Makefile | 19 +- fpga/generator/wally.tcl | 1 + pipelined/src/uncore/sdc/SDC.sv | 362 ---------- pipelined/src/uncore/sdc/SDCcounter.sv | 43 -- pipelined/src/uncore/sdc/clkdivider.sv | 105 --- pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv | 63 -- pipelined/src/uncore/sdc/crc7_pipo.sv | 67 -- pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv | 60 -- pipelined/src/uncore/sdc/piso_generic_ce.sv | 49 -- .../src/uncore/sdc/regfile_p2r1w1_nibo.sv | 49 -- .../src/uncore/sdc/regfile_p2r1w1bwen.sv | 44 -- pipelined/src/uncore/sdc/sd_clk_fsm.sv | 93 --- pipelined/src/uncore/sdc/sd_cmd_fsm.sv | 586 ---------------- pipelined/src/uncore/sdc/sd_dat_fsm.sv | 253 ------- pipelined/src/uncore/sdc/sd_top.sv | 652 ------------------ pipelined/src/uncore/sdc/sd_top_wrapper.v | 98 --- pipelined/src/uncore/sdc/simple_timer.sv | 54 -- pipelined/src/uncore/sdc/sipo_generic_ce.sv | 51 -- pipelined/src/uncore/sdc/up_down_counter.sv | 45 -- 20 files changed, 15 insertions(+), 2681 deletions(-) delete mode 100644 pipelined/src/uncore/sdc/SDC.sv delete mode 100644 pipelined/src/uncore/sdc/SDCcounter.sv delete mode 100644 pipelined/src/uncore/sdc/clkdivider.sv delete mode 100644 pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv delete mode 100644 pipelined/src/uncore/sdc/crc7_pipo.sv delete mode 100644 pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv delete mode 100644 pipelined/src/uncore/sdc/piso_generic_ce.sv delete mode 100644 pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv delete mode 100644 pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv delete mode 100644 pipelined/src/uncore/sdc/sd_clk_fsm.sv delete mode 100644 pipelined/src/uncore/sdc/sd_cmd_fsm.sv delete mode 100644 pipelined/src/uncore/sdc/sd_dat_fsm.sv delete mode 100644 pipelined/src/uncore/sdc/sd_top.sv delete mode 100644 pipelined/src/uncore/sdc/sd_top_wrapper.v delete mode 100644 pipelined/src/uncore/sdc/simple_timer.sv delete mode 100644 pipelined/src/uncore/sdc/sipo_generic_ce.sv delete mode 100644 pipelined/src/uncore/sdc/up_down_counter.sv diff --git a/.gitignore b/.gitignore index d4e9acd58..587fc73a5 100644 --- a/.gitignore +++ b/.gitignore @@ -126,3 +126,5 @@ tests/custom/*/*/*.map tests/custom/*/*/*.memfile tests/custom/crt0/*.a /pipelined/regression/sd_model.log +fpga/src/sdc/* +fpga/src/sdc.tar.gz diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index f39a9bce9..b61c51ed5 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,18 +1,19 @@ dst := IP +sdc_src := ~/repos/sdc.tar.gz # vcu118 -export XILINX_PART := xcvu9p-flga2104-2L-e -export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -export board := vcu118 +#export XILINX_PART := xcvu9p-flga2104-2L-e +#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +#export board := vcu118 # vcu108 -#export XILINX_PART := xcvu095-ffva2104-2-e -#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 -#export board := vcu108 +export XILINX_PART := xcvu095-ffva2104-2-e +export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 +export board := vcu108 all: FPGA -FPGA: IP +FPGA: IP SDC vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log IP: $(dst)/xlnx_proc_sys_reset.log \ @@ -20,6 +21,10 @@ IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_ahblite_axi_bridge.log +SDC: + cp $(sdc_src) ../src/ + tar xzf ../src/sdc.tar.gz -C ../src + $(dst)/%.log: %.tcl mkdir -p IP cd IP;\ diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 6afa9e66f..b2597f60d 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -17,6 +17,7 @@ read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog {../src/fpgaTop.v} +read_verilog -sv [glob -type f ../src/sdc/*.sv] set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset] diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv deleted file mode 100644 index 5a10d6430..000000000 --- a/pipelined/src/uncore/sdc/SDC.sv +++ /dev/null @@ -1,362 +0,0 @@ -/////////////////////////////////////////// -// SDC.sv -// -// Written: Ross Thompson September 22, 2021 -// Modified: -// -// Purpose: SDC interface to AHBLite BUS. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -`define SDCCLKDIV -8'd3 - -module SDC ( - input logic HCLK, - input logic HRESETn, - input logic HSELSDC, - input logic [4:0] HADDR, - input logic HWRITE, - input logic HREADY, - input logic [1:0] HTRANS, - input logic [`XLEN-1:0] HWDATA, - output logic [`XLEN-1:0] HREADSDC, - output logic HRESPSDC, - output logic HREADYSDC, - - //sd card interface - // place the tristate drivers at the top. this level - // will use dedicated 1 direction ports. - output logic SDCCmdOut, - input logic SDCCmdIn, - output logic SDCCmdOE, - input logic [3:0] SDCDatIn, - output logic SDCCLK, - // interrupt to PLIC - output logic SDCIntM -); - - logic InitTrans; - logic RegRead; - logic RegWrite; - logic [4:0] HADDRDelay; - - - // Register outputs - logic signed [7:0] CLKDiv; - logic [2:0] Command; - logic [63:9] Address; - - - logic SDCDone; - - logic [2:0] ErrorCode; - logic InvalidCommand; - logic SDCBusy; - - logic StartCLKDivUpdate; - logic CLKDivUpdateEn; - logic SDCCLKEN; - logic CLKGate; - logic SDCCLKIn; - - - logic SDCDataValid; - logic [`XLEN-1:0] SDCReadData; - logic [`XLEN-1:0] SDCReadDataPreNibbleSwap; - logic [`XLEN-1:0] SDCWriteData; - logic FatalError; - - logic [4095:0] ReadData512Byte; - logic [`XLEN-1:0] ReadData512ByteWords [4096/`XLEN-1:0] ; - logic SDCInitialized; - logic SDCRestarting; - logic SDCLast; - - logic [$clog2(4096/`XLEN)-1:0] WordCount; - logic WordCountRst; - logic [5:0] Status; - logic CommandCompleted; - logic ReadDone; - - - - genvar index; - - assign HRESPSDC = 1'b0; - - // registers - //| Offset | Name | Size | Purpose | - //|--------+---------+--------+------------------------------------------------| - //| 0x0 | CLKDiv | 4 | Divide HCLK to produce SDCLK | - //| 0x4 | Status | 4 | Provide status to software | - //| 0x8 | Control | 4 | Send commands to SDC | - //| 0xC | Size | 4 | Size of data command (only 512 byte supported) | - //| 0x10 | address | 8 | address of operation | - //| 0x18 | data | XLEN/8 | Data Bus interface | - - // Status contains - // Status[0] initialized - // Status[1] Busy on read - // Status[2] invalid command - // Status[5:3] error code - - // control contains 3 bit command - // control[2:0] - // 000 nop op - // xx1 initialize - // 010 Write no implemented - // 100 Read - // 110 Atomic read/write not implemented - - // size is fixed to 512. Read only - - - // Currently using a mailbox style interface. Data is passed through the Data register (0x10) - // The card will support 3 operations - // 1. initialize - // 2. read - // 3. write - // all read and write operations will occur on 512 bytes (4096 bits) of data - // starting at the 512 byte aligned address in the address register This register - // is the byte address. - - // currently does not support writes - - assign InitTrans = HREADY & HSELSDC & HTRANS[1]; - //assign RegRead = InitTrans & ~HWRITE; - // register resolve combo loop - flopr #(1) RegReadReg(HCLK, ~HRESETn, InitTrans & ~HWRITE, RegRead); - // AHBLite Spec has write data 1 cycle after write command - flopr #(1) RegWriteReg(HCLK, ~HRESETn, InitTrans & HWRITE, RegWrite); - - flopenr #(5) HADDRReg(HCLK, ~HRESETn, InitTrans, HADDR, HADDRDelay); - - assign StartCLKDivUpdate = HADDRDelay == '0 & RegWrite; - - flopenl #(8) CLKDivReg(HCLK, ~HRESETn, CLKDivUpdateEn, HWDATA[7:0], `SDCCLKDIV, CLKDiv); - - // Control reg - flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (CommandCompleted), - CommandCompleted ? '0 : HWDATA[2:0], '0, Command); - - if (`XLEN == 64) begin - flopenr #(64-9) AddressReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite), - HWDATA[`XLEN-1:9], Address); - end else begin - flopenr #(32-9) AddressLowReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite), - HWDATA[`XLEN-1:9], Address[31:9]); - flopenr #(32) AddressHighReg(HCLK, ~HRESETn, (HADDRDelay == 'h14 & RegWrite), - HWDATA, Address[63:32]); - end - - flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite), - HWDATA, SDCWriteData); - - assign InvalidCommand = (Command[2] | Command[1]) & Command[0]; - - assign Status = {ErrorCode, InvalidCommand, SDCBusy, SDCInitialized}; - - if(`XLEN == 64) begin - always_comb - case(HADDRDelay[4:0]) - 'h0: HREADSDC = {24'b0, CLKDiv, 26'b0, Status}; - 'h4: HREADSDC = {26'b0, Status, 29'b0, Command}; - 'h8: HREADSDC = {29'b0, Command, 32'h200}; - 'hC: HREADSDC = {32'h200, Address[31:9], 9'b0}; - 'h10: HREADSDC = {Address, 9'b0}; - 'h18: HREADSDC = SDCReadData; - default: HREADSDC = {24'b0, CLKDiv, 26'b0, Status}; - endcase // case (HADDRDelay[4:0]) - end else begin - always_comb - case(HADDRDelay[4:0]) - 'h0: HREADSDC = {24'b0, CLKDiv}; - 'h4: HREADSDC = {26'b0, Status}; - 'h8: HREADSDC = {29'b0, Command}; - 'hC: HREADSDC = 'h200; - 'h10: HREADSDC = {Address[31:9], 9'b0}; - 'h14: HREADSDC = Address[63:32]; - 'h18: HREADSDC = SDCReadData[31:0]; - default: HREADSDC = {24'b0, CLKDiv}; - endcase - end - - - for(index = 0; index < 4096/`XLEN; index++) begin - assign ReadData512ByteWords[index] = ReadData512Byte[(index+1)*`XLEN-1:index*`XLEN]; - end - - assign SDCReadDataPreNibbleSwap = ReadData512ByteWords[WordCount]; - if(`XLEN == 64) begin - assign SDCReadData = {SDCReadDataPreNibbleSwap[59:56], SDCReadDataPreNibbleSwap[63:60], - SDCReadDataPreNibbleSwap[51:48], SDCReadDataPreNibbleSwap[55:52], - SDCReadDataPreNibbleSwap[43:40], SDCReadDataPreNibbleSwap[47:44], - SDCReadDataPreNibbleSwap[35:32], SDCReadDataPreNibbleSwap[39:36], - SDCReadDataPreNibbleSwap[27:24], SDCReadDataPreNibbleSwap[31:28], - SDCReadDataPreNibbleSwap[19:16], SDCReadDataPreNibbleSwap[23:20], - SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12], - SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]}; - end else begin - assign SDCReadData = {SDCReadDataPreNibbleSwap[27:24], SDCReadDataPreNibbleSwap[31:28], - SDCReadDataPreNibbleSwap[19:16], SDCReadDataPreNibbleSwap[23:20], - SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12], - SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]}; - end - - flopenr #($clog2(4096/`XLEN)) WordCountReg - (.clk(HCLK), - .reset(~HRESETn | WordCountRst), - .en(HADDRDelay[4:0] == 'h18 & ReadDone), - .d(WordCount + 1'b1), - .q(WordCount)); - - - - typedef enum {STATE_READY, - - // clock update states - STATE_CLK_DIV1, - STATE_CLK_DIV2, - STATE_CLK_DIV3, - STATE_CLK_DIV4, - - // restart SDC - STATE_RESTART, - - // SDC operation - STATE_PROCESS_CMD, - - STATE_READ - } statetype; - - - statetype CurrState, NextState; - - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) CurrState <= STATE_READY; - else CurrState <= NextState; - - always_comb begin - CLKDivUpdateEn = 1'b0; - HREADYSDC = 1'b0; - SDCCLKEN = 1'b1; - WordCountRst = 1'b0; - SDCBusy = 1'b0; - CommandCompleted = 1'b0; - ReadDone = 1'b0; - - case (CurrState) - STATE_READY : begin - if (StartCLKDivUpdate)begin - NextState = STATE_CLK_DIV1; - HREADYSDC = 1'b0; - end else if (Command[2] | Command[1]) begin - NextState = STATE_PROCESS_CMD; - HREADYSDC = 1'b0; - end else if(HADDRDelay[4:0] == 'h18 & RegRead) begin - NextState = STATE_READ; - HREADYSDC = 1'b0; - end else begin - NextState = STATE_READY; - HREADYSDC = 1'b1; - end - end - STATE_CLK_DIV1: begin - NextState = STATE_CLK_DIV2; - SDCCLKEN = 1'b0; - end - STATE_CLK_DIV2: begin - NextState = STATE_CLK_DIV3; - CLKDivUpdateEn = 1'b1; - SDCCLKEN = 1'b0; - end - STATE_CLK_DIV3: begin - NextState = STATE_CLK_DIV4; - SDCCLKEN = 1'b0; - end - STATE_CLK_DIV4: begin - NextState = STATE_READY; - end - STATE_PROCESS_CMD: begin - HREADYSDC = 1'b1; - WordCountRst = 1'b1; - SDCBusy = 1'b1; - if(SDCDataValid) begin - NextState = STATE_READY; - CommandCompleted = 1'b1; - end else begin - NextState = STATE_PROCESS_CMD; - CommandCompleted = 1'b0; - end - end - STATE_READ: begin - NextState = STATE_READY; - HREADYSDC = 1'b1; - ReadDone = 1'b1; - end - default: begin - NextState = STATE_READY; - end - endcase - end - - // clock generation divider - - clockgater clockgater(.E(SDCCLKEN), - .SE(1'b0), - .CLK(HCLK), - .ECLK(CLKGate)); - - - clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv), - .i_EN(CLKDiv <= 0), // enable if < 0 (msb is 1) - .i_CLK(CLKGate), - .i_RST(~HRESETn | CLKDivUpdateEn), - .o_CLK(SDCCLKIn)); - -// assign SDCCLKIn = CLKGate; - - - // should always be 0 for real implementation, but for simulation set to 1. - logic LimitTimers; - assign LimitTimers = '0; - - sd_top sd_top(.CLK(SDCCLKIn), - .a_RST(~HRESETn), - .i_SD_CMD(SDCCmdIn), - .o_SD_CMD(SDCCmdOut), - .o_SD_CMD_OE(SDCCmdOE), - .i_SD_DAT(SDCDatIn), - .o_SD_CLK(SDCCLK), - .i_BLOCK_ADDR(Address[32:9]), - .o_READY_FOR_READ(SDCInitialized), - .o_SD_RESTARTING(SDCRestarting), - .i_READ_REQUEST(Command[2]), - .o_DATA_TO_CORE(), - .ReadData(ReadData512Byte), - .o_DATA_VALID(SDCDataValid), - .o_LAST_NIBBLE(SDCLast), - .o_ERROR_CODE_Q(ErrorCode), - .o_FATAL_ERROR(FatalError), - .i_COUNT_IN_MAX(-8'd62), - .LIMIT_SD_TIMERS(LimitTimers)); // *** must change this to 0 for real hardware. - - -endmodule - diff --git a/pipelined/src/uncore/sdc/SDCcounter.sv b/pipelined/src/uncore/sdc/SDCcounter.sv deleted file mode 100644 index de39ba2b0..000000000 --- a/pipelined/src/uncore/sdc/SDCcounter.sv +++ /dev/null @@ -1,43 +0,0 @@ -/////////////////////////////////////////// -// counter.sv -// -// Written: Richard Davis -// Modified: Ross Thompson -// Converted to SystemVerilog. -// -// Purpose: basic up counter -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module SDCcounter #(parameter integer WIDTH=32) ( - input logic [WIDTH-1:0] CountIn, - output logic [WIDTH-1:0] CountOut, - input logic Load, - input logic Enable, - input logic clk, - input logic reset -); - - logic [WIDTH-1:0] NextCount; - - assign NextCount = Load ? CountIn : (CountOut + 1'b1); - flopenr #(WIDTH) reg1(clk, reset, Enable | Load, NextCount, CountOut); -endmodule - - diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv deleted file mode 100644 index c62258efb..000000000 --- a/pipelined/src/uncore/sdc/clkdivider.sv +++ /dev/null @@ -1,105 +0,0 @@ -/////////////////////////////////////////// -// clock divider.sv -// -// Written: Richard Davis -// Modified: Ross Thompson September 18, 2021 -// Converted to system verilog. -// -// Purpose: clock divider for sd flash -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module clkdivider #(parameter integer g_COUNT_WIDTH) ( - input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX, //((Divide by value)/2) - 1 - input logic i_EN, //Enable frequency division of i_clk - input logic i_CLK, // 1.2 GHz Base clock - input logic i_RST, // at start: clears flip flop and loads counter, - // i_RST must NOT be a_RST, it needs to be synchronized with the 50 MHz Clock to load the - // counter's initial value - output logic o_CLK // frequency divided clock -); - - - logic [g_COUNT_WIDTH-1:0] r_count_out; // wider for sign - logic w_counter_overflowed; - - logic r_fd_Q; - logic w_fd_D; - - logic w_load; - - logic resetD, resetDD, resetPulse; - logic rstdd2, rstddn; - - assign w_load = resetPulse | w_counter_overflowed; // reload when zero occurs or when set by outside - - SDCcounter #(.WIDTH(g_COUNT_WIDTH)) // wider for sign, this way the (MSB /= '1') only for zero - my_counter (.clk(i_CLK), - .Load(w_load), // reload when zero occurs or when set by outside - .CountIn(i_COUNT_IN_MAX), // negative signed integer - .CountOut(r_count_out), - .Enable(1'b1), // ALWAYS COUNT - .reset(1'b0)); // no reset, only load - - - assign w_counter_overflowed = r_count_out[g_COUNT_WIDTH-1] == '0; - - // to ensure the clock keeps running we need to make the reset last 1 cycle - // rather than until the reset is released. Alternatively we could do - // two resets. The first which resets this and the clk_fsm and the second - // which resets the rest of the design. - // Or we can make this clock divider not depend on reset. - - flop #(1) pulseReset - (.d(i_RST), - .q(resetD), - .clk(i_CLK)); - - flop #(1) pulseReset2 - (.d(resetD), - .q(resetDD), - .clk(i_CLK)); - - //assign resetPulse = i_RST & ~resetDD; - assign resetPulse = ~i_RST & resetDD; - - assign rstdd2 = i_RST | resetDD; - - flop #(1) fallingEdge - (.d(rstdd2), - .q(rstddn), - .clk(~i_CLK)); - - flopenr #(1) toggle_flip_flop - (.d(w_fd_D), - .q(r_fd_Q), - .clk(i_CLK), - .reset(resetPulse), - .en(w_counter_overflowed)); // only update when counter overflows - - assign w_fd_D = ~ r_fd_Q; - -/* -----\/----- EXCLUDED -----\/----- - if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN), .O(o_CLK)); - else assign o_CLK = i_EN ? r_fd_Q : i_CLK; - -----/\----- EXCLUDED -----/\----- */ - - if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN & ~rstddn), .O(o_CLK)); - else assign o_CLK = i_EN & ~rstddn ? r_fd_Q : i_CLK; -endmodule diff --git a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv deleted file mode 100644 index ae3ce2af9..000000000 --- a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv +++ /dev/null @@ -1,63 +0,0 @@ -/////////////////////////////////////////// -// crc16 sipo np ce -// -// Written: Richard Davis -// Modified: Ross Thompson September 18, 2021 -// Converted to system verilog. -// -// Purpose: CRC16 generator SIPO using register_ce -// w/o appending any zero-bits to the message -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module crc16_sipo_np_ce( - input logic CLK, // sequential device - input logic RST, // initial calue of CRC register must be "0000_0000_0000_0000" - input logic i_enable, // input is valid - input logic i_message_bit, - output logic [15:0] o_crc16 -); - - logic [15:0] w_crc16_d; - - flopenr #(16) crc16reg(.clk(CLK), - .reset(RST), - .en(i_enable), - .d(w_crc16_d), - .q(o_crc16)); - - assign w_crc16_d[15] = o_crc16[14]; - assign w_crc16_d[14] = o_crc16[13]; - assign w_crc16_d[13] = o_crc16[12]; - assign w_crc16_d[12] = o_crc16[11] ^ (i_message_bit ^ o_crc16[15]); - assign w_crc16_d[11] = o_crc16[10]; - assign w_crc16_d[10] = o_crc16[9]; - assign w_crc16_d[9] = o_crc16[8]; - assign w_crc16_d[8] = o_crc16[7]; - assign w_crc16_d[7] = o_crc16[6]; - assign w_crc16_d[6] = o_crc16[5]; - assign w_crc16_d[5] = o_crc16[4] ^ (i_message_bit ^ o_crc16[15]); - assign w_crc16_d[4] = o_crc16[3]; - assign w_crc16_d[3] = o_crc16[2]; - assign w_crc16_d[2] = o_crc16[1]; - assign w_crc16_d[1] = o_crc16[0]; - assign w_crc16_d[0] = i_message_bit ^ o_crc16[15]; - - -endmodule diff --git a/pipelined/src/uncore/sdc/crc7_pipo.sv b/pipelined/src/uncore/sdc/crc7_pipo.sv deleted file mode 100644 index 9144495f4..000000000 --- a/pipelined/src/uncore/sdc/crc7_pipo.sv +++ /dev/null @@ -1,67 +0,0 @@ -/////////////////////////////////////////// -// crc7 sipo np ce -// -// Written: Richard Davis -// Modified: Ross Thompson September 18, 2021 -// Converted to system verilog. -// -// Purpose: takes 40 bits of input, generates 7 bit CRC after a single -// clock cycle! -// w/o appending any zero-bits to the message -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module crc7_pipo ( - input logic [39:0] i_DATA, - input logic i_CRC_ENABLE, - input logic RST, - input logic CLK, - output logic [6:0] o_CRC -); - - logic [6:0] r_lfsr_q; - logic [6:0] w_lfsr_d; - - assign o_CRC = r_lfsr_q; - - assign w_lfsr_d[0] = r_lfsr_q[1] ^ r_lfsr_q[2] ^ r_lfsr_q[4] ^ r_lfsr_q[6] ^ i_DATA[0] ^ i_DATA[4] ^ i_DATA[7] ^ i_DATA[8] ^ i_DATA[12] ^ i_DATA[14] ^ i_DATA[15] ^ i_DATA[16] ^ i_DATA[18] ^ i_DATA[20] ^ i_DATA[21] ^ i_DATA[23] ^ i_DATA[24] ^ i_DATA[30] ^ i_DATA[31] ^ i_DATA[34] ^ i_DATA[35] ^ i_DATA[37] ^ i_DATA[39]; - - assign w_lfsr_d[1] = r_lfsr_q[2] ^ r_lfsr_q[3] ^ r_lfsr_q[5] ^ i_DATA[1] ^ i_DATA[5] ^ i_DATA[8] ^ i_DATA[9] ^ i_DATA[13] ^ i_DATA[15] ^ i_DATA[16] ^ i_DATA[17] ^ i_DATA[19] ^ i_DATA[21] ^ i_DATA[22] ^ i_DATA[24] ^ i_DATA[25] ^ i_DATA[31] ^ i_DATA[32] ^ i_DATA[35] ^ i_DATA[36] ^ i_DATA[38]; - - assign w_lfsr_d[2] = r_lfsr_q[0] ^ r_lfsr_q[3] ^ r_lfsr_q[4] ^ r_lfsr_q[6] ^ i_DATA[2] ^ i_DATA[6] ^ i_DATA[9] ^ i_DATA[10] ^ i_DATA[14] ^ i_DATA[16] ^ i_DATA[17] ^ i_DATA[18] ^ i_DATA[20] ^ i_DATA[22] ^ i_DATA[23] ^ i_DATA[25] ^ i_DATA[26] ^ i_DATA[32] ^ i_DATA[33] ^ i_DATA[36] ^ i_DATA[37] ^ i_DATA[39]; - - assign w_lfsr_d[3] = r_lfsr_q[0] ^ r_lfsr_q[2] ^ r_lfsr_q[5] ^ r_lfsr_q[6] ^ i_DATA[0] ^ i_DATA[3] ^ i_DATA[4] ^ i_DATA[8] ^ i_DATA[10] ^ i_DATA[11] ^ i_DATA[12] ^ i_DATA[14] ^ i_DATA[16] ^ i_DATA[17] ^ i_DATA[19] ^ i_DATA[20] ^ i_DATA[26] ^ i_DATA[27] ^ i_DATA[30] ^ i_DATA[31] ^ i_DATA[33] ^ i_DATA[35] ^ i_DATA[38] ^ i_DATA[39]; - - assign w_lfsr_d[4] = r_lfsr_q[1] ^ r_lfsr_q[3] ^ r_lfsr_q[6] ^ i_DATA[1] ^ i_DATA[4] ^ i_DATA[5] ^ i_DATA[9] ^ i_DATA[11] ^ i_DATA[12] ^ i_DATA[13] ^ i_DATA[15] ^ i_DATA[17] ^ i_DATA[18] ^ i_DATA[20] ^ i_DATA[21] ^ i_DATA[27] ^ i_DATA[28] ^ i_DATA[31] ^ i_DATA[32] ^ i_DATA[34] ^ i_DATA[36] ^ i_DATA[39]; - - assign w_lfsr_d[5] = r_lfsr_q[0] ^ r_lfsr_q[2] ^ r_lfsr_q[4] ^ i_DATA[2] ^ i_DATA[5] ^ i_DATA[6] ^ i_DATA[10] ^ i_DATA[12] ^ i_DATA[13] ^ i_DATA[14] ^ i_DATA[16] ^ i_DATA[18] ^ i_DATA[19] ^ i_DATA[21] ^ i_DATA[22] ^ i_DATA[28] ^ i_DATA[29] ^ i_DATA[32] ^ i_DATA[33] ^ i_DATA[35] ^ i_DATA[37]; - - assign w_lfsr_d[6] = r_lfsr_q[0] ^ r_lfsr_q[1] ^ r_lfsr_q[3] ^ r_lfsr_q[5] ^ i_DATA[3] ^ i_DATA[6] ^ i_DATA[7] ^ i_DATA[11] ^ i_DATA[13] ^ i_DATA[14] ^ i_DATA[15] ^ i_DATA[17] ^ i_DATA[19] ^ i_DATA[20] ^ i_DATA[22] ^ i_DATA[23] ^ i_DATA[29] ^ i_DATA[30] ^ i_DATA[33] ^ i_DATA[34] ^ i_DATA[36] ^ i_DATA[38]; - - - - flopenr #(7) - lfsrReg(.clk(CLK), - .reset(RST), - .en(i_CRC_ENABLE), - .d(w_lfsr_d), - .q(r_lfsr_q)); - - -endmodule diff --git a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv deleted file mode 100644 index 4ada97afa..000000000 --- a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv +++ /dev/null @@ -1,60 +0,0 @@ -/////////////////////////////////////////// -// crc16 sipo np ce -// -// Written: Richard Davis -// Modified: Ross Thompson September 18, 2021 -// -// Purpose: CRC7 generator SIPO using register_ce -// w/o appending any zero-bits othe message -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module crc7_sipo_np_ce( - input logic clk, - input logic rst,// initial CRC value must be b"000_0000" - input logic i_enable, - input logic i_message_bit, - output logic [6:0] o_crc7 -); - - - logic [6:0] w_crc7_d; - logic [6:0] r_crc7_q; - - flopenr #(7) - crc7Reg(.clk(clk), - .reset(rst), - .en(i_enable), - .d(w_crc7_d), - .q(r_crc7_q)); - - assign w_crc7_d[6] = r_crc7_q[5]; - assign w_crc7_d[5] = r_crc7_q[4]; - assign w_crc7_d[4] = r_crc7_q[3]; - assign w_crc7_d[3] = r_crc7_q[2] ^ (i_message_bit ^ r_crc7_q[6]); - assign w_crc7_d[2] = r_crc7_q[1]; - assign w_crc7_d[1] = r_crc7_q[0]; - assign w_crc7_d[0] = i_message_bit ^ r_crc7_q[6]; - - assign o_crc7 = r_crc7_q; - - -endmodule - - diff --git a/pipelined/src/uncore/sdc/piso_generic_ce.sv b/pipelined/src/uncore/sdc/piso_generic_ce.sv deleted file mode 100644 index 697dfa864..000000000 --- a/pipelined/src/uncore/sdc/piso_generic_ce.sv +++ /dev/null @@ -1,49 +0,0 @@ -/////////////////////////////////////////// -// piso generic ce -// -// Written: Richard Davis -// Modified: Ross Thompson September 18, 2021 -// -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module piso_generic_ce #(parameter integer g_BUS_WIDTH) ( - input logic clk, - input logic i_load, - input logic [g_BUS_WIDTH-1:0] i_data, - input logic i_en, - output o_data); - - - logic [g_BUS_WIDTH-1:0] w_reg_d; - logic [g_BUS_WIDTH-1:0] r_reg_q; - - flopenr #(g_BUS_WIDTH) - shiftReg(.clk(clk), - .reset(1'b0), - .en(1'b1), - .d(w_reg_d), - .q(r_reg_q)); - - assign o_data = i_en ? r_reg_q[g_BUS_WIDTH - 1] : 1'b1; - assign w_reg_d = i_load ? i_data : - i_en ? {r_reg_q[g_BUS_WIDTH - 2 : 0], 1'b1} : - r_reg_q[g_BUS_WIDTH - 1 : 0]; - -endmodule diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv deleted file mode 100644 index 9ee46b4b6..000000000 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv +++ /dev/null @@ -1,49 +0,0 @@ -/////////////////////////////////////////// -// regfile_p2r1w1_nibo -// -// Written: Ross Thompson September 18, 2021 -// Modified: 2 port register file with 1 read and 1 write -// -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WIDTH = 4) ( - input logic clk, - input logic we1, - input logic [DEPTH-1:0] ra1, - output logic [WIDTH-1:0] rd1, - output logic [(2**DEPTH)*WIDTH-1:0] Rd1All, - input logic [DEPTH-1:0] wa1, - input logic [WIDTH-1:0] wd1 -); - - logic [WIDTH-1:0] regs [2**DEPTH-1:0]; - genvar index; - - always_ff @(posedge clk) begin - if(we1) begin - regs[wa1] <= wd1; - end - end - - assign rd1 = regs[ra1]; - for(index = 0; index < 2**DEPTH; index++) - assign Rd1All[index*WIDTH+WIDTH-1:index*WIDTH] = regs[index]; - -endmodule diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv deleted file mode 100644 index cff149e60..000000000 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv +++ /dev/null @@ -1,44 +0,0 @@ -/////////////////////////////////////////// -// regfile_p2r1w1bwen -// -// Written: Ross Thompson September 18, 2021 -// Modified: 2 port register file with 1 read and 1 write -// -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)( - input logic clk, - input logic we1, - input logic [WIDTH-1:0] we1bit, - input logic [DEPTH-1:0] ra1, - output logic [WIDTH-1:0] rd1, - input logic [DEPTH-1:0] wa1, - input logic [WIDTH-1:0] wd1 -); - - logic [WIDTH-1:0] regs [2**DEPTH-1:0]; - integer i; - - always_ff @(posedge clk) - if (we1) // global write enable - regs[wa1] = wd1 & we1bit | regs[wa1] & ~we1bit; // bit write enable - - assign rd1 = regs[ra1]; -endmodule diff --git a/pipelined/src/uncore/sdc/sd_clk_fsm.sv b/pipelined/src/uncore/sdc/sd_clk_fsm.sv deleted file mode 100644 index 5c47e04f7..000000000 --- a/pipelined/src/uncore/sdc/sd_clk_fsm.sv +++ /dev/null @@ -1,93 +0,0 @@ -/////////////////////////////////////////// -// sd_clk_fsm.sv -// -// Written: Richard Davis -// Modified: Ross Thompson September 19, 2021 -// -// Purpose: Controls clock dividers. -// Replaces s_disable_sd_clocks, s_select_hs_clk, s_enable_hs_clk -// in sd_cmd_fsm.vhd. Attempts to correct issues with oversampling and -// under-sampling of control signals (for counter_cmd), that were present in my -// previous design. -// This runs on 50 MHz. -// sd_cmd_fsm will run on SD_CLK_Gated (50 MHz or 400 KHz, selected by this) -// asynchronous reset is used for both sd_cmd_fsm and for this. -// It must be synchronized with 50 MHz and held for a minimum period of a full -// 400 KHz pulse width. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module sd_clk_fsm ( - input logic CLK, - input logic i_RST, - (* mark_debug = "true" *)output logic o_DONE, - (* mark_debug = "true" *)input logic i_START, - (* mark_debug = "true" *)input logic i_FATAL_ERROR, - (* mark_debug = "true" *)output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz - (* mark_debug = "true" *)output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init) - (* mark_debug = "true" *)output logic o_G_CLK_SD_EN // Turns gated clock (G_CLK_SD) off and on -); - - - logic [3:0] w_next_state; - (* mark_debug = "true" *) logic [3:0] r_curr_state; - - - // clock selection - parameter c_sd_clk_init = 1'b1; - parameter c_sd_clk_hs = 1'b0; - - // States - localparam s_reset = 4'b0000; - localparam s_enable_init_clk = 4'b0001; // enable 400 KHz - localparam s_disable_sd_clocks = 4'b0010; - localparam s_select_hs_clk = 4'b0011; - localparam s_enable_hs_clk = 4'b0100; - localparam s_done = 4'b0101; - localparam s_disable_sd_clocks_2 = 4'b0110; // if error occurs - localparam s_select_init_clk = 4'b0111; // if error occurs - localparam s_safe_state = 4'b1111; //always provide a safe state return if all states are not used - - flopenr #(4) stateReg(.clk(CLK), - .reset(i_RST), - .en(1'b1), - .d(w_next_state), - .q(r_curr_state)); - - assign w_next_state = i_RST ? s_reset : - r_curr_state == s_reset | (r_curr_state == s_enable_init_clk & ~i_START) | (r_curr_state == s_select_init_clk) ? s_enable_init_clk : - r_curr_state == s_enable_init_clk & i_START ? s_disable_sd_clocks : - r_curr_state == s_disable_sd_clocks ? s_select_hs_clk : - r_curr_state == s_select_hs_clk ? s_enable_hs_clk : - r_curr_state == s_enable_hs_clk | (r_curr_state == s_done & ~i_FATAL_ERROR) ? s_done : - r_curr_state == s_done & i_FATAL_ERROR ? s_disable_sd_clocks_2 : - r_curr_state == s_disable_sd_clocks_2 ? s_select_init_clk : - s_safe_state; - - - assign o_HS_TO_INIT_CLK_DIVIDER_RST = r_curr_state == s_reset; - - assign o_SD_CLK_SELECTED = (r_curr_state == s_select_hs_clk) | (r_curr_state == s_enable_hs_clk) | (r_curr_state == s_done) ? c_sd_clk_hs : c_sd_clk_init; - - assign o_G_CLK_SD_EN = (r_curr_state == s_enable_init_clk) | (r_curr_state == s_enable_hs_clk) | (r_curr_state == s_done); - - assign o_DONE = r_curr_state == s_done; - -endmodule - diff --git a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv deleted file mode 100644 index 5c2296657..000000000 --- a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv +++ /dev/null @@ -1,586 +0,0 @@ -/////////////////////////////////////////// -// sd_clk_fsm.sv -// -// Written: Richard Davis -// Modified: Ross Thompson September 19, 2021 -// -// Purpose: Finite state machine for the SD CMD bus -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module sd_cmd_fsm ( - input logic CLK, // HS - //i_SLOWER_CLK : in std_logic; - input logic i_RST, // reset FSM, - // MUST COME OUT OF RESET - // SYNCHRONIZED TO THE 1.2 GHZ CLOCK! - output logic o_TIMER_LOAD, o_TIMER_EN, // Timer - output logic [18:0] o_TIMER_IN, - input logic [18:0] i_TIMER_OUT, - output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter - output logic [7:0] o_COUNTER_IN, - input logic [7:0] i_COUNTER_OUT, - output logic o_SD_CLK_EN, // Clock Gaters - input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM - output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM - output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter - input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17 - input logic [1:0] i_USES_DAT, - input logic [6:0] i_OPCODE, - input logic [2:0] i_R_TYPE, - // bit masks - input logic [31:0] i_NO_REDO_MASK, - input logic [31:0] i_NO_REDO_ANS, - input logic [31:0] i_NO_ERROR_MASK, - input logic [31:0] i_NO_ERROR_ANS, - (* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line - // TX Components - output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head - output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail - output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator - output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX - // TX Memory - output logic o_CMD_TX_IS_CMD55_RST, - output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index - // 55, so the subsequent command is to be - // viewed as ACMD by the SD card. - // RX Components - input logic i_SD_CMD_RX, // serial response input on SD_CMD - output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response - input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT - input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT - output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator - input logic [6:0] i_RX_CRC7, - // RX Memory - output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address - // Communication to sd_dat_fsm - output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete - input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed - (* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command - (* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT, - // Commnuication to core - output logic o_READY_FOR_READ, // tell core that I have completed initialization - output logic o_SD_RESTARTING, // inform core the need to restart - input logic i_READ_REQUEST, // core tells me to execute CMD17 - // Communication to Host - output logic o_DAT_ERROR_FD_RST, - output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error - output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card - input logic LIMIT_SD_TIMERS -); - - logic [4:0] w_next_state; - (* mark_debug = "true" *) logic [4:0] r_curr_state; - logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card; - - logic [31:0] w_redo_result, w_error_result; - logic w_ACMD41_init_done; - logic w_fail_cnt_en, w_fail_count_rst; - logic [10:0] r_fail_count_out; - - logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41 - logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM - logic w_ERROR_CODE_RST, w_ERROR_CODE_EN; - logic [18:0] Timer_In; - - - localparam s_reset_clear_error_reg = 5'b00000; - localparam s_idle_supply_no_clk = 5'b00001; - localparam s_idle_supply_sd_clk = 5'b00010; - localparam s_ld_head = 5'b00011; - localparam s_tx_head = 5'b00100; - localparam s_ld_tail = 5'b00101; - localparam s_tx_tail = 5'b00110; - localparam s_setup_rx = 5'b00111; - localparam s_idle_ncc = 5'b01000; - localparam s_fetch_next_cmd = 5'b01001; - localparam s_rx_48 = 5'b01010; - localparam s_rx_136 = 5'b01011; - localparam s_error_no_response = 5'b01100; - localparam s_idle_for_dat = 5'b01101; - localparam s_error_bad_card = 5'b01110; - localparam s_idle_nrc = 5'b01111; - localparam s_count_attempt = 5'b10000; - localparam s_reset_from_error = 5'b10001; - //localparam s_enable_hs_clk = 5'b10010; - localparam s_idle_for_start_bit = 5'b10011; - localparam s_fetch_prev_cmd = 5'b10100; // use to resend previous cmd55 if acmd is resent - // localparam s_setup_rx_b = 5'b10110; -// localparam s_idle_for_start_bit_b= 5'b10111; -// localparam s_rx_48_b = 5'b11000; -// localparam s_rx_136_b = 5'b11001; - localparam s_error_dat_time_out = 5'b11010; // don't advance states if the dat fsm times out - localparam s_idle_for_clock_change = 5'b11011; // replaces s_disable_sd_clocks, s_select_hs_clk, s_enable_hs_clk - localparam s_study_response = 5'b11100; // Do error checking here - localparam s_idle_for_read_request = 5'b11101; // After power up and initialization sequence is completed - localparam s_Error_TX_Failed = 5'b11110; // when fail_cnt_out exceeds c_max_attempts - - localparam c_MAX_ATTEMPTS = 1500; // Give up sending a command after 3 failed attempts - // (except ACMD41) so the processor is not locked up forever - - localparam c_response_type_R0_NONE = 0; - localparam c_response_type_R1_NORMAL = 1; - localparam c_response_type_R2_CID_CSD = 2; - localparam c_response_type_R3_OCR = 3; - localparam c_response_type_R6_RCA = 6; - localparam c_response_type_R7_CIC = 7; - - localparam c_start_bit = 1'b0; - - localparam c_DAT_none = 2'b00; - localparam c_DAT_busy = 2'b01; - localparam c_DAT_wide = 2'b10; - localparam c_DAT_block = 2'b11; - - // Instructions mnemonics based on index (opcode(5 downto 0)) - localparam logic [45:40] c_Go_Idle_State = 6'd0; //CMD0 - localparam logic [45:40] c_All_Send_CID = 6'd02; // CMD2 - localparam logic [45:40] c_SD_Send_RCA = 6'd03; // CMD3 - localparam logic [45:40] c_Switch_Function = 6'd06; // CMD6 - localparam logic [45:40] c_Set_Bus_Width = 6'd06; // ACMD6 - localparam logic [45:40] c_Select_Card = 6'd07; // CMD7 - localparam logic [45:40] c_Send_IF_State = 6'd08; // CMD8 - localparam logic [45:40] c_Read_Single_Block = 6'd17; // CMD17 - localparam logic [45:40] c_SD_Send_OCR = 6'd41; // ACMD41 - localparam logic [45:40] c_App_Command = 6'd55; // CMD55 - -// clock selection - localparam c_sd_clk_init = 1'b1; - localparam c_sd_clk_hs = 1'b0; - - //tx source selection - localparam logic [1:0] c_tx_low = 2'b00; - localparam logic [1:0] c_tx_high = 2'b01; - localparam logic [1:0] c_tx_head = 2'b10; - localparam logic [1:0] c_tx_tail = 2'b11; - - // Error Codes for Error Register - localparam logic [2:0] c_NO_ERRORS = 3'b000; // no fatal errors occurred - // (default value when register is cleared during reset) - localparam [2:0] C_ERROR_NO_CMD_RESPONSE = 3'b100; // card timed out while waiting for a response on CMD, no start bit - // of response packet was ever received - // (possible causes: illegal command, card is disconnected, - // not meeting timing (you can fix timing by inverting the clock - // sent to card)) - localparam logic [2:0] c_ERROR_NO_DAT_RESPONSE = 3'b101; // card timed out while waiting for a data block on DAT, no start bit - // of DAT packet was ever received - // (possible cause: card is disconnected) - localparam logic [2:0] C_ERROR_BAD_CARD_STATUS = 3'b110; // status bits of a response indicate a card is not supported - // or that the card is damaged internally - localparam logic [2:0] C_ERROR_EXCEED_MAX_ATTEMPTS = 3'b111; // if a command fails it may be resent, - // but after so many attempts you should just give up - - //Alias for value of SD_CMD_Output_Enable - localparam c_TX_COMMAND = 1'b1; // Enable output on SD_CMD - localparam c_RX_RESPONSE = 1'b0; // Disable Output on SD_CMD - - // load values in for timers and counters - localparam logic [7:0] c_NID_max = 8'd63; // counter_in: should be "4" - // downto 0 = 5 bits count - // but is not enough time for - // sdModel.v - localparam logic [7:0] c_NCR_max = 8'd63; // counter_in - localparam logic [7:0] c_NCC_min = 8'd7; // counter_in - localparam logic [7:0] c_NRC_min = 8'd8; // counter_in - - //localparam logic [18:0] c_1000ms = 19'd400000; // ACMD41 timeout - //*** BUG this value is too bit to fit into 19 bits. - localparam logic [18:0] c_1000ms = 19'd40000; // ACMD41 timeout - - // command instruction type (opcode(6)) - localparam c_CMD = 1'b0; - localparam c_ACMD = 1'b1; - - // counter direction for up_down - localparam c_increment = 1'b1; // count <= count + 1 - localparam c_decrement = 1'b0; // count <= count - 1 - - - logic COUNTER_OUT_GT_ZERO; - logic COUNTER_OUT_GE_ZERO; - logic COUNTER_OUT_GT_8; - logic COUNTER_OUT_EQ_8; - logic COUNTER_OUT_EQ_ZERO; - logic TIMER_OUT_GT_ZERO; - logic TIMER_OUT_EQ_ZERO; - logic fail_count_out_le_max_attempts; - logic fail_count_out_lt_max_attempts; - logic fail_count_out_gt_max_attempts; - logic IC_OUT_EQ_2; - logic IC_OUT_EQ_3; - logic IC_OUT_LT_9; - logic IC_OUT_GE_9; - - - assign Timer_In = LIMIT_SD_TIMERS ? 19'b0000000000000000011 : 19'b0011000011010100000; // 250 ms - - //Fail Counter, tracks how many failed attempts at command transmission - SDCcounter #(11) fail_counter - (.CountIn(11'b0), - .CountOut(r_fail_count_out), - .Load(1'b0), - .Enable(w_fail_cnt_en), - .clk(CLK), - .reset(w_fail_count_rst)); - - // Simple timer for ACMD41 busy - simple_timer #(19) ACMD41_busy_timer - (.VALUE(c_1000ms), - .START(w_ACMD41_busy_timer_START), - .FLAG(w_ACMD41_times_out_FLAG), - .RST(w_ACMD41_busy_timer_RST), - .CLK(CLK)); - - // State Register, instantiate register_ce. 32 state state machine - flopenr #(5) state_reg - (.d(w_next_state), - .q(r_curr_state), - .en(1'b1), - .reset(i_RST), - .clk(CLK)); - - // Error register : indicates what type of fatal error occured for interrupt - flopenr #(3) error_reg - (.d(w_ERROR_CODE_D), - .q(r_ERROR_CODE_Q), - .en(w_ERROR_CODE_EN), - .reset(w_ERROR_CODE_RST), - .clk(CLK)); - - assign o_ERROR_CODE_Q = r_ERROR_CODE_Q; - assign COUNTER_OUT_GT_ZERO = i_COUNTER_OUT > 0; - assign COUNTER_OUT_GE_ZERO = $signed(i_COUNTER_OUT) >= $signed(8'b0); - assign COUNTER_OUT_GT_8 = i_COUNTER_OUT > 8; - assign COUNTER_OUT_EQ_8 = i_COUNTER_OUT == 8; - assign COUNTER_OUT_EQ_ZERO = i_COUNTER_OUT == 0; - assign TIMER_OUT_GT_ZERO = i_TIMER_OUT > 0; - assign TIMER_OUT_EQ_ZERO = i_TIMER_OUT == 0; - assign fail_count_out_le_max_attempts = r_fail_count_out <= (c_MAX_ATTEMPTS-1); - assign fail_count_out_lt_max_attempts = r_fail_count_out < (c_MAX_ATTEMPTS-1); - assign fail_count_out_gt_max_attempts = r_fail_count_out > (c_MAX_ATTEMPTS-1); - assign IC_OUT_EQ_2 = i_IC_OUT == 2; - assign IC_OUT_EQ_3 = i_IC_OUT == 3; - assign IC_OUT_LT_9 = i_IC_OUT < 9; - assign IC_OUT_GE_9 = i_IC_OUT >= 9; - - assign w_next_state = i_RST ? s_reset_clear_error_reg : - - ((r_curr_state == s_reset_clear_error_reg) | - (r_curr_state == s_Error_TX_Failed) | - (r_curr_state == s_error_no_response) | - (r_curr_state == s_error_bad_card) | - (r_curr_state == s_error_dat_time_out)) ? s_reset_from_error : - - - ((r_curr_state == s_reset_from_error) | - ((r_curr_state == s_idle_supply_no_clk) & (TIMER_OUT_GT_ZERO))) ? s_idle_supply_no_clk : - - (((r_curr_state == s_idle_supply_no_clk) & (TIMER_OUT_EQ_ZERO)) | - ((r_curr_state == s_idle_supply_sd_clk) & (COUNTER_OUT_GT_ZERO))) ? s_idle_supply_sd_clk : - - (r_curr_state == s_ld_head) ? s_count_attempt : - - (((r_curr_state == s_count_attempt) & (fail_count_out_le_max_attempts)) | - ((r_curr_state == s_count_attempt) & - (((IC_OUT_EQ_2) & (i_OPCODE[5:0] == c_App_Command)) | - ((IC_OUT_EQ_3) & (i_OPCODE == ({c_ACMD, c_SD_Send_OCR})))) // to work CMD55, ACMD41 MUST be lines 2, 3 of instruction fetch mux of sd_top.vhd - & (w_ACMD41_times_out_FLAG) - & (fail_count_out_gt_max_attempts))) ? s_tx_head : - - ((r_curr_state == s_count_attempt) & (fail_count_out_gt_max_attempts)) ? s_Error_TX_Failed : - - ((r_curr_state == s_tx_head) | ((r_curr_state == s_ld_tail) & (COUNTER_OUT_GT_8))) ? s_ld_tail : - - (((r_curr_state == s_ld_tail) & (COUNTER_OUT_EQ_8)) | - ((r_curr_state == s_tx_tail) & (COUNTER_OUT_GT_ZERO))) ? s_tx_tail : - - (r_curr_state == s_tx_tail) & (COUNTER_OUT_EQ_ZERO) ? s_setup_rx : - - (((r_curr_state == s_setup_rx) & (i_R_TYPE == c_response_type_R0_NONE)) | - ((r_curr_state == s_idle_ncc) & (COUNTER_OUT_GT_ZERO))) ? s_idle_ncc : - - (((r_curr_state == s_setup_rx) & (i_R_TYPE != c_response_type_R0_NONE)) | - ((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX != c_start_bit) & - (COUNTER_OUT_GT_ZERO))) ? s_idle_for_start_bit : - - ((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX != c_start_bit) & - (COUNTER_OUT_EQ_ZERO)) ? s_error_no_response : - - (((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) & - /* verilator lint_off UNSIGNED */ - (COUNTER_OUT_GE_ZERO) & (i_R_TYPE == c_response_type_R2_CID_CSD)) | - /* verilator lint_on UNSIGNED */ - ((r_curr_state == s_rx_136) & (COUNTER_OUT_GT_ZERO))) ? s_rx_136 : - - (((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) & - /* verilator lint_off UNSIGNED */ - (COUNTER_OUT_GE_ZERO) & (i_R_TYPE != c_response_type_R2_CID_CSD)) | - /* verilator lint_on UNSIGNED */ - ((r_curr_state == s_rx_48) & (COUNTER_OUT_GT_ZERO))) ? s_rx_48 : - - (((r_curr_state == s_rx_136) & (COUNTER_OUT_EQ_ZERO)) | - ((r_curr_state == s_rx_48) & COUNTER_OUT_EQ_ZERO)) ? s_study_response : - - (r_curr_state == s_study_response) & w_bad_card ? s_error_bad_card : - - (((r_curr_state == s_study_response) & (~w_bad_card) & (i_USES_DAT != c_DAT_none)) | - ((r_curr_state == s_idle_for_dat) & (~i_DAT_RX_DONE))) ? s_idle_for_dat : - - ((r_curr_state == s_idle_for_dat) & (i_DAT_RX_DONE) & (i_ERROR_DAT_TIMES_OUT)) ? s_error_dat_time_out : - - (((r_curr_state == s_idle_for_dat) & (i_DAT_RX_DONE) & - (~i_ERROR_DAT_TIMES_OUT)) | - ((r_curr_state == s_study_response) & (~w_bad_card) & - (i_USES_DAT == c_DAT_none)) | - ((r_curr_state == s_idle_nrc) & (COUNTER_OUT_GT_ZERO))) ? s_idle_nrc : - - ((r_curr_state == s_idle_nrc) & (COUNTER_OUT_EQ_ZERO) & - (w_resend_last_command) & ((i_OPCODE[6] == c_ACMD) & - ((i_OPCODE[5:0]) != c_App_Command))) ? s_fetch_prev_cmd : - - ((r_curr_state == s_fetch_prev_cmd) | - ((r_curr_state == s_idle_supply_sd_clk) & (COUNTER_OUT_EQ_ZERO)) | - ((r_curr_state == s_fetch_next_cmd) & // before CMD17 - (IC_OUT_LT_9)) | // blindly load head of next command - ((r_curr_state == s_idle_for_read_request) & (i_READ_REQUEST)) | // got the request, load head - ((r_curr_state == s_idle_nrc) & (COUNTER_OUT_EQ_ZERO) & - (w_resend_last_command) & ((i_OPCODE[6] == c_CMD) | - ((i_OPCODE[5:0]) == c_App_Command)))) ? s_ld_head : - - (((r_curr_state == s_idle_nrc) & (COUNTER_OUT_EQ_ZERO) & - (~w_resend_last_command) & ((i_OPCODE) == ({c_CMD, c_Switch_Function}))) | - ((r_curr_state == s_idle_for_clock_change) & (~i_CLOCK_CHANGE_DONE))) ? s_idle_for_clock_change : - - (((r_curr_state == s_idle_ncc) & (COUNTER_OUT_EQ_ZERO)) | - ((r_curr_state == s_idle_nrc) & (COUNTER_OUT_EQ_ZERO) & - (~w_resend_last_command) & ((i_OPCODE) != ({c_CMD, c_Switch_Function}))) | - ((r_curr_state == s_idle_for_clock_change) & (i_CLOCK_CHANGE_DONE))) ? s_fetch_next_cmd : - - (((r_curr_state == s_fetch_next_cmd) & - (IC_OUT_GE_9)) | // During and after CMD17, wait for request to send CMD17 from core - // waiting for request - (r_curr_state == s_idle_for_read_request)) ? s_idle_for_read_request : - - s_reset_clear_error_reg; - - - - - - - // state outputs - assign w_ACMD41_busy_timer_START = ((r_curr_state == s_count_attempt) & (i_OPCODE == {c_ACMD, c_SD_Send_OCR}) & (r_fail_count_out == 1)); - - assign w_ACMD41_busy_timer_RST = ((r_curr_state == s_reset_from_error) | (w_ACMD41_init_done)); - - // Error Register - assign w_ERROR_CODE_RST = (r_curr_state == s_reset_clear_error_reg); - - assign w_ERROR_CODE_EN = (r_curr_state == s_error_bad_card) | (r_curr_state == s_error_no_response) | (r_curr_state == s_Error_TX_Failed) | (r_curr_state == s_error_dat_time_out); - - assign w_ERROR_CODE_D = (r_curr_state == s_Error_TX_Failed) ? C_ERROR_EXCEED_MAX_ATTEMPTS : // give up - (r_curr_state == s_error_bad_card) ? C_ERROR_BAD_CARD_STATUS : // card is damaged or unsupported - (r_curr_state == s_error_no_response) ? C_ERROR_NO_CMD_RESPONSE : // no response was received on CMD line - (r_curr_state == s_error_dat_time_out) ? c_ERROR_NO_DAT_RESPONSE : // no data packet was received on DAT bus - c_NO_ERRORS; // all is well - - // Failure counter - assign w_fail_count_rst = ((r_curr_state == s_reset_from_error) | (r_curr_state == s_fetch_next_cmd & i_OPCODE[5:0] != c_App_Command)); - - - assign w_fail_cnt_en = ((r_curr_state == s_count_attempt) & (i_OPCODE[6] != c_ACMD | i_OPCODE[5:0] == c_App_Command)); - // & (i_OPCODE != ({c_ACMD, c_SD_Send_OCR})) else // NOT ACMD41, it can take up to 1 second - - // Timer module - assign o_TIMER_EN = (r_curr_state == s_idle_supply_no_clk); - - assign o_TIMER_LOAD = (r_curr_state == s_reset_from_error); - - assign o_TIMER_IN = (r_curr_state == s_reset_from_error) ? Timer_In : '0; - - // Clock selection/gater module(s) ... - assign o_SD_CLK_EN = ~((r_curr_state == s_reset_from_error) | (r_curr_state == s_idle_supply_no_clk) | (r_curr_state == s_idle_for_clock_change)); - - assign o_START_CLOCK_CHANGE = (r_curr_state == s_idle_for_clock_change); - - // RCA register module - assign o_RCA_REGISTER_RST = (r_curr_state == s_reset_from_error); - - assign o_RCA_REGISTER_EN = ((r_curr_state == s_idle_nrc) & (i_R_TYPE == c_response_type_R6_RCA)); - - // Instruction counter module - assign o_IC_RST = (r_curr_state == s_reset_from_error); - - //assign o_IC_EN = (r_curr_state == s_fetch_next_cmd) | (r_curr_state == s_fetch_prev_cmd); - - assign o_IC_EN = (((r_curr_state == s_fetch_next_cmd) & (i_IC_OUT < 10)) | (r_curr_state == s_fetch_prev_cmd)); - - assign o_IC_UP_DOWN = (r_curr_state == s_fetch_prev_cmd) ? c_decrement : c_increment; - - // "Previous Command sent was CMD55, so the command I'm now sending is ACMD" module - assign o_CMD_TX_IS_CMD55_RST = (r_curr_state == s_reset_from_error); - - assign o_CMD_TX_IS_CMD55_EN = (r_curr_state == s_ld_head); - - // Output signals to DAT FSM - //o_CMD_TX_DONE = '0' when (r_curr_state == s_reset) else // reset - // '0' when (r_curr_state == s_idle_supply_no_clk) | (r_curr_state == s_idle_supply_sd_clk) else // power up - // '0' when ((r_curr_state == s_ld_head) - // | (r_curr_state == s_tx_head) - // | (r_curr_state == s_ld_tail) - // | (r_curr_state == s_tx_tail)) else // tx - // '1'; - assign o_CMD_TX_DONE = (r_curr_state == s_setup_rx); - - // Counter Module - assign o_COUNTER_LOAD = (r_curr_state == s_idle_supply_no_clk) | - (r_curr_state == s_ld_head) | - (r_curr_state == s_setup_rx) | - (r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) | - (r_curr_state == s_rx_48) & (i_COUNTER_OUT == 0) | - (r_curr_state == s_rx_136) & (i_COUNTER_OUT == 0); - - assign o_COUNTER_IN = (r_curr_state == s_idle_supply_no_clk) ? 8'd73 : - // | is it 73 downto 0 == 74 bits - (r_curr_state == s_ld_head) ? 8'd47 : // or is it 48 - ((r_curr_state == s_setup_rx) & (i_R_TYPE == c_response_type_R0_NONE)) ? c_NCC_min : - ((r_curr_state == s_setup_rx) - & (i_R_TYPE != c_response_type_R0_NONE) - & (((i_OPCODE) == ({c_CMD, c_All_Send_CID})) | - ((i_OPCODE) == ({c_ACMD, c_SD_Send_OCR})))) ? c_NID_max : - (r_curr_state == s_setup_rx) ? c_NCR_max : - ((r_curr_state == s_idle_for_start_bit) & (i_R_TYPE == c_response_type_R2_CID_CSD)) ? 8'd135 : // | is it 136 - (r_curr_state == s_idle_for_start_bit) ? 8'd46 : // | is it not48 - (r_curr_state == s_rx_48) | (r_curr_state == s_rx_136) ? c_NRC_min : // | is it 8 - 8'd0; - - assign o_COUNTER_EN = (r_curr_state == s_idle_supply_sd_clk) ? 1'b1 : - ((r_curr_state == s_tx_head) | (r_curr_state == s_ld_tail) | (r_curr_state == s_tx_tail)) ? 1'b1 : - (r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) ? 1'b0 : - (r_curr_state == s_idle_for_start_bit) ? 1'b1 : - (r_curr_state == s_rx_48) & (i_COUNTER_OUT == 0) ? 1'b0 : - (r_curr_state == s_rx_48) ? 1'b1 : - (r_curr_state == s_idle_nrc) ? 1'b1 : - (r_curr_state == s_rx_136) & (i_COUNTER_OUT == 0) ? 1'b0 : - (r_curr_state == s_rx_136) ? 1'b1 : - (r_curr_state == s_idle_ncc) ? 1'b1 : - 1'b0; - - // SD_CMD Tri-state Buffer Module - assign o_SD_CMD_OE = (r_curr_state == s_idle_supply_sd_clk) ? c_TX_COMMAND : - ((r_curr_state == s_tx_head) - | (r_curr_state == s_ld_tail) - | (r_curr_state == s_tx_tail)) ? c_TX_COMMAND : - c_RX_RESPONSE; - - // Shift Registers - // TX_PISO40 Transmit Command Head - assign o_TX_PISO40_LOAD = (r_curr_state == s_ld_head); - - assign o_TX_PISO40_EN = (r_curr_state == s_tx_head) | (r_curr_state == s_ld_tail); - - // TX_CRC7_PIPO Generate Tail - assign o_TX_CRC7_PIPO_RST = (r_curr_state == s_ld_head); - - assign o_TX_CRC7_PIPO_EN = (r_curr_state == s_tx_head); - - // TX_PISO8 Transmit Command Tail - assign o_TX_PISO8_LOAD = (r_curr_state == s_ld_tail); - - assign o_TX_PISO8_EN = (r_curr_state == s_tx_tail); - - // RX_CRC7_SIPO Calculate the CRC7 of the first 47-bits of reply (should be zero) - assign o_RX_CRC7_SIPO_RST = (r_curr_state == s_setup_rx); - - assign o_RX_CRC7_SIPO_EN = (r_curr_state == s_rx_48) & (i_COUNTER_OUT > 0); // or (r_curr_state == s_rx_48_b) - - // RX_SIPO40 Content bits of response - assign o_RX_SIPO48_RST = (r_curr_state == s_setup_rx); - - assign o_RX_SIPO48_EN = (r_curr_state == s_rx_48 | r_curr_state == s_rx_48); - - // Fatal Error Signal Wire - assign o_FATAL_ERROR = (r_curr_state == s_error_bad_card) | (r_curr_state == s_error_no_response) | - (r_curr_state == s_Error_TX_Failed) | (r_curr_state == s_error_dat_time_out); - - assign o_DAT_ERROR_FD_RST = (r_curr_state == s_ld_head); - - // I'm debating the merit of creating yet another state for sd_cmd_fsm.vhd to go into when and if sd_dat_fsm.vhd - // times out while waiting for start bit on the DAT bus resulting in Error_Time_Out going high in - // sd_Dat_fsm.vhd while sd_cmd_fsm.vhd is still in s_idle_for_dat - - // TX source selection bits for mux - assign o_TX_SOURCE_SELECT = (r_curr_state == s_idle_supply_sd_clk) ? c_tx_high : - ((r_curr_state == s_ld_head) - | (r_curr_state == s_tx_head) - | (r_curr_state == s_ld_tail)) ? c_tx_head : - (r_curr_state == s_tx_tail) ? c_tx_tail : - c_tx_high; // This occurs when not transmitting anything - - // Study Response - assign w_rx_crc7_check = (r_curr_state == s_idle_nrc) & - ((i_R_TYPE != c_response_type_R0_NONE) & - (i_R_TYPE != c_response_type_R3_OCR) & - (i_R_TYPE != c_response_type_R2_CID_CSD)); - - assign w_rx_index_check = (r_curr_state == s_idle_nrc) & - ((i_R_TYPE != c_response_type_R0_NONE) & - (i_R_TYPE != c_response_type_R3_OCR) & - (i_R_TYPE != c_response_type_R2_CID_CSD)); - - assign w_redo_result = i_RESPONSE_CONTENT & i_NO_REDO_MASK; - - assign w_rx_bad_reply = ((r_curr_state == s_idle_nrc | r_curr_state == s_study_response) & (w_redo_result != i_NO_REDO_ANS)); - - assign w_rx_bad_crc7 = ((r_curr_state == s_idle_nrc | r_curr_state == s_study_response) & ((w_rx_crc7_check) & (i_RX_CRC7 != 7'b0))); - - assign w_rx_bad_index = ((r_curr_state == s_idle_nrc | r_curr_state == s_study_response) - & ((w_rx_index_check) & (i_RESPONSE_INDEX != i_OPCODE[5:0]))); - - assign w_resend_last_command = ((r_curr_state == s_idle_nrc | r_curr_state == s_study_response) & - ((w_rx_bad_reply) | (w_rx_bad_index) | (w_rx_bad_crc7))) | - ((r_curr_state == s_idle_nrc) & - ((i_ERROR_CRC16) & - ((i_USES_DAT == c_DAT_block) | (i_USES_DAT == c_DAT_wide)))); - - assign w_error_result = i_RESPONSE_CONTENT & i_NO_ERROR_MASK; - - // Make assignment based on what was read from the OCR Register. - // Bit 31, Card power up status bit: '1' == SD Flash Card power up procedure is finished. - // '0' == SD Flash Card power up procedure is not finished. - // Bit 30, Card capacity status bit: '1' == Extended capacity card is in use (64 GB in size or greater). - // '0' == Extended capacity card is not in use. - assign w_ACMD41_init_done = ((i_IC_OUT == 3) & (i_OPCODE == ({c_ACMD, c_SD_Send_OCR}))) & - (~w_rx_bad_reply) & (r_curr_state == s_study_response); - - assign w_bad_card = ((r_curr_state == s_study_response) & (w_error_result != i_NO_ERROR_ANS) & - ((~w_ACMD41_times_out_FLAG) | (w_ACMD41_init_done))); - - // Communication with core - assign o_READY_FOR_READ = (r_curr_state == s_idle_for_read_request); - - assign o_SD_RESTARTING = (r_curr_state == s_Error_TX_Failed) | - (r_curr_state == s_error_dat_time_out) | - (r_curr_state == s_error_bad_card) | - (r_curr_state == s_error_no_response); - - - - -endmodule diff --git a/pipelined/src/uncore/sdc/sd_dat_fsm.sv b/pipelined/src/uncore/sdc/sd_dat_fsm.sv deleted file mode 100644 index c38073e34..000000000 --- a/pipelined/src/uncore/sdc/sd_dat_fsm.sv +++ /dev/null @@ -1,253 +0,0 @@ -/////////////////////////////////////////// -// sd_dat_fsm.sv -// -// Written: Richard Davis -// Modified: Ross Thompson September 19, 2021 -// -// Purpose: Runs in parallel with sd_cmd_fsm to control activity on the DAT -// bus of the SD card. -// 14 State Mealy FSM + Safe state = 15 State Mealy FSM -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module sd_dat_fsm ( - input logic CLK, // HS Clock (48 MHz) - input logic i_RST, - // Timer module control - input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer - output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals - output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz - input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0 - // Nibble counter module control - output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter - input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits - // CRC16 Generation control - (* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines) - (* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero - // For R1b - output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b - (* mark_debug = "true" *)input logic i_DAT0_Q, - // Storage Buffers for DAT bits read - output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out) - // From LUT - (* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus - // For communicating with core - output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid - output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent - // For communication with sd_cmd_fsm - (* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA - (* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card - (* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions) - (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_RST, - (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission - input logic LIMIT_SD_TIMERS -); - - (* mark_debug = "true" *) logic [3:0] r_curr_state; - logic [3:0] w_next_state; - - logic r_error_crc16_fd_Q; - - logic [22:0] Identify_Timer_In; - logic [22:0] Data_TX_Timer_In; - - localparam logic [3:0] s_reset = 4'b0000; - localparam logic [3:0] s_idle = 4'b0001; - localparam logic [3:0] s_idle_for_start_bit = 4'b0010; - localparam logic [3:0] s_read_r1b = 4'b0011; - localparam logic [3:0] s_notify_r1b_completed = 4'b0100; - localparam logic [3:0] s_error_time_out = 4'b0101; - localparam logic [3:0] s_rx_wide_data = 4'b0110; - localparam logic [3:0] s_rx_block_data = 4'b0111; - localparam logic [3:0] s_rx_crc16 = 4'b1000; - localparam logic [3:0] s_error_crc16_fail = 4'b1001; - localparam logic [3:0] s_publish_block_data = 4'b1010; - localparam logic [3:0] s_publish_wide_data = 4'b1011; - localparam logic [3:0] s_reset_wide_data = 4'b1100; - localparam logic [3:0] s_reset_block_data = 4'b1101; - localparam logic [3:0] s_reset_nibble_counter = 4'b1110; // Before publishing CMD17 Block Data - - localparam logic [1:0] c_DAT_none = 2'b00; - localparam logic [1:0] c_DAT_busy = 2'b01; - localparam logic [1:0] c_DAT_wide = 2'b10; - localparam logic [1:0] c_DAT_block = 2'b11; - - localparam logic c_start_bit = 0; - localparam logic c_busy_bit = 0; - - // load values in for timers and counters - localparam logic c_slow_clock = 1'b1; // use during initialization (card identification mode) - localparam logic c_HS_clock = 1'b0; // use after CMD6 switches clock frequency (CMD17) - - - logic TIMER_OUT_GT_0; - logic TIMER_OUT_EQ_0; - logic COUNTER_OUT_EQ_1023; - logic COUNTER_OUT_LT_1023; - logic COUNTER_OUT_LT_128; - logic COUNTER_OUT_EQ_128; - logic COUNTER_OUT_LT_144; - logic COUNTER_OUT_EQ_144; - logic COUNTER_OUT_LT_1040; - logic COUNTER_OUT_EQ_1040; - - - assign Identify_Timer_In = LIMIT_SD_TIMERS ? 23'b00000000000000001100011 : 23'b00000001001110001000000; // 40,000 unsigned. - assign Data_TX_Timer_In = LIMIT_SD_TIMERS ? 23'b00000000000000001100011 : 23'b11110100001001000000000; // 8,000,000 unsigned. - - flopenr #(4) stateReg(.clk(CLK), - .reset(i_RST), - .en(1'b1), - .d(w_next_state), - .q(r_curr_state)); - - assign TIMER_OUT_GT_0 = i_TIMER_OUT > 0; - assign TIMER_OUT_EQ_0 = i_TIMER_OUT == 0; - assign COUNTER_OUT_EQ_1023 = i_COUNTER_OUT == 1023; - assign COUNTER_OUT_LT_1023 = i_COUNTER_OUT < 1023; - assign COUNTER_OUT_LT_128 = i_COUNTER_OUT < 128; - assign COUNTER_OUT_EQ_128 = i_COUNTER_OUT == 128; - assign COUNTER_OUT_LT_144 = i_COUNTER_OUT < 144; - assign COUNTER_OUT_EQ_144 = i_COUNTER_OUT == 144; - assign COUNTER_OUT_LT_1040 = i_COUNTER_OUT < 1040; - assign COUNTER_OUT_EQ_1040 = i_COUNTER_OUT == 1040; - - assign w_next_state = ((i_RST) | - (r_curr_state == s_error_time_out) | // noticed this change is needed during emulation - (r_curr_state == s_notify_r1b_completed) | - (r_curr_state == s_error_crc16_fail) | - (r_curr_state == s_publish_wide_data) | - ((r_curr_state == s_publish_block_data) & (COUNTER_OUT_EQ_1023))) ? s_reset : - - ((r_curr_state == s_reset) | - ((r_curr_state == s_idle) & ((i_USES_DAT == c_DAT_none) | ((i_USES_DAT != c_DAT_none) & (~i_CMD_TX_DONE))))) ? s_idle : - - ((r_curr_state == s_idle) & (i_USES_DAT == c_DAT_wide) & (i_CMD_TX_DONE)) ? s_reset_wide_data : - - ((r_curr_state == s_idle) & (i_USES_DAT == c_DAT_block) & (i_CMD_TX_DONE)) ? s_reset_block_data : - - ((r_curr_state == s_reset_wide_data) | - ((r_curr_state == s_idle) & (i_USES_DAT == c_DAT_busy) & (i_CMD_TX_DONE)) | - (r_curr_state == s_reset_block_data) | - ((r_curr_state == s_idle_for_start_bit) & (TIMER_OUT_GT_0) & (i_DAT0_Q != c_start_bit))) ? s_idle_for_start_bit : - - ((r_curr_state == s_idle_for_start_bit) & // Apparently R1b's busy signal is optional, - (TIMER_OUT_EQ_0) & // Even if it never shows up, - (i_USES_DAT == c_DAT_busy)) ? s_notify_r1b_completed : // pretend it did, & move on - - (((r_curr_state == s_idle_for_start_bit) & (TIMER_OUT_GT_0) & - (i_DAT0_Q == c_start_bit) & (i_USES_DAT == c_DAT_busy)) | - ((r_curr_state == s_read_r1b) & (TIMER_OUT_GT_0) & (i_DAT0_Q == c_busy_bit))) ? s_read_r1b : - - (((r_curr_state == s_read_r1b) & (TIMER_OUT_EQ_0)) | - ((r_curr_state == s_idle_for_start_bit) & (TIMER_OUT_EQ_0) & - (i_USES_DAT != c_DAT_busy))) ? s_error_time_out : - - ((r_curr_state == s_read_r1b) & (i_DAT0_Q != c_busy_bit)) ? s_notify_r1b_completed : - - (((r_curr_state == s_idle_for_start_bit) & (TIMER_OUT_GT_0) & (i_DAT0_Q == c_start_bit) & - (i_USES_DAT == c_DAT_wide)) | - ((r_curr_state == s_rx_wide_data) & (COUNTER_OUT_LT_128))) ? s_rx_wide_data : - - (((r_curr_state == s_idle_for_start_bit) & (TIMER_OUT_GT_0) & - (i_DAT0_Q == c_start_bit) & (i_USES_DAT == c_DAT_block)) | - ((r_curr_state == s_rx_block_data) & (COUNTER_OUT_LT_1023))) ? s_rx_block_data : - - (((r_curr_state == s_rx_wide_data) & (COUNTER_OUT_EQ_128)) | - ((r_curr_state == s_rx_block_data) & (COUNTER_OUT_EQ_1023)) | - ((r_curr_state == s_rx_crc16) & - (((i_USES_DAT == c_DAT_wide) & (COUNTER_OUT_LT_144)) | - ((i_USES_DAT == c_DAT_block) & (COUNTER_OUT_LT_1040))))) ? s_rx_crc16 : - - ((r_curr_state == s_rx_crc16) & - (((i_USES_DAT == c_DAT_wide) & (COUNTER_OUT_EQ_144)) | - ((i_USES_DAT == c_DAT_block) & (COUNTER_OUT_EQ_1040))) & - (~i_DATA_CRC16_GOOD)) ? s_error_crc16_fail : - - ((r_curr_state == s_rx_crc16) & (i_USES_DAT == c_DAT_wide) & (COUNTER_OUT_EQ_144) & - (i_DATA_CRC16_GOOD)) ? s_publish_wide_data : - - ((r_curr_state == s_rx_crc16) & - (i_USES_DAT == c_DAT_block) & (COUNTER_OUT_EQ_1040) & (i_DATA_CRC16_GOOD)) ? s_reset_nibble_counter : - - ((r_curr_state == s_reset_nibble_counter)) ? s_publish_block_data : - - s_reset; - - assign o_TIMER_IN = (r_curr_state == s_reset) & (i_SD_CLK_SELECTED == c_slow_clock) ? Identify_Timer_In : Data_TX_Timer_In; - - assign o_TIMER_LOAD = ((r_curr_state == s_reset) | - (r_curr_state == s_reset_block_data)); - - assign o_TIMER_EN = ((r_curr_state == s_idle_for_start_bit) | - (r_curr_state == s_read_r1b)); - - // Nibble Counter module - assign o_COUNTER_RST = (r_curr_state == s_reset) | (r_curr_state == s_reset_nibble_counter); - - assign o_COUNTER_EN = ((r_curr_state == s_rx_block_data) | - (r_curr_state == s_rx_wide_data) | - (r_curr_state == s_rx_crc16)) | (r_curr_state == s_publish_block_data); - - // CRC16 Generation module - assign o_CRC16_RST = (r_curr_state == s_reset); - - assign o_CRC16_EN = ((r_curr_state == s_rx_block_data) | - (r_curr_state == s_rx_wide_data) | - (r_curr_state == s_rx_crc16)); - - // Flip Flop Module (for R1b) - assign o_BUSY_RST = (r_curr_state == s_reset); - - //o_BUSY_EN = '1' when ((r_curr_state == s_idle_for_start_bit) | - // (r_curr_state == s_read_r1b)) else - // '0'; - assign o_BUSY_EN = 1'b1; // Always sample data - - // DAT Storage Modules - assign o_NIBO_EN = (r_curr_state == s_rx_block_data); - - // To sd_cmd_fsm - assign o_DAT_RX_DONE = ((r_curr_state == s_error_time_out) | - (r_curr_state == s_notify_r1b_completed) | - (r_curr_state == s_error_crc16_fail) | - (r_curr_state == s_publish_wide_data) | - (r_curr_state == s_publish_block_data)); - - assign o_ERROR_DAT_TIMES_OUT = (r_curr_state == s_error_time_out); - - - // o_RESEND_READ_WIDE (Error! This is not defined. Indicates switch command must be re-rent), - // should be a function of block busy logic - - // For Communication with core - assign o_DATA_VALID = (r_curr_state == s_publish_block_data); - - assign o_LAST_NIBBLE = ((r_curr_state == s_publish_block_data) - & (COUNTER_OUT_EQ_1023)) | (r_curr_state == s_error_time_out); // notify done if errors occur - - // o_ERROR_CRC16 (note: saved to flip flop because otherwise is only 1 clock cycle, not what I want) - assign o_DAT_ERROR_FD_RST = (r_curr_state == s_reset_block_data) | (r_curr_state == s_reset_wide_data); - assign o_DAT_ERROR_FD_EN = (r_curr_state == s_rx_crc16); - - - - - -endmodule diff --git a/pipelined/src/uncore/sdc/sd_top.sv b/pipelined/src/uncore/sdc/sd_top.sv deleted file mode 100644 index 3cac14ed9..000000000 --- a/pipelined/src/uncore/sdc/sd_top.sv +++ /dev/null @@ -1,652 +0,0 @@ -/////////////////////////////////////////// -// sd_top.sv -// -// Written: Richard Davis -// Modified: Ross Thompson September 19, 2021 -// -// Purpose: SD card controller -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -/// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module sd_top #(parameter g_COUNT_WIDTH = 8) ( - input logic CLK, // 1.2 GHz (1.0 GHz typical) - input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles) - // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK! - // io_SD_CMD_z : inout std_logic; // SD CMD Bus - (* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card - (* mark_debug = "true" *)output logic o_SD_CMD, // CMD Command from host - (* mark_debug = "true" *)output logic o_SD_CMD_OE, // Direction of SD_CMD - (* mark_debug = "true" *)input logic [3:0] i_SD_DAT, // SD DAT Bus - (* mark_debug = "true" *)output logic o_SD_CLK, // SD CLK Bus - // For communication with core cpu - input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used) - output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and - // sd card is ready to read a 512 byte block to the core. - // Held high during idle until i_READ_REQUEST is received - output logic o_SD_RESTARTING, // inform core the need to restart - - input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will - // pulse this bit high to indicate it wants the block at this address - output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is - output logic [4095:0] ReadData, // full 512 bytes to Bus - // being published - output logic o_DATA_VALID, // held high while data being read to core to indicate that it is valid - output logic o_LAST_NIBBLE, // pulse when last nibble is sent - output logic [2:0] o_ERROR_CODE_Q, // indicates which error occured - output logic o_FATAL_ERROR, // indicates that the FATAL ERROR register has updated - // For tuning - input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX, - input logic LIMIT_SD_TIMERS -); - - localparam logic c_CMD = 1'b0; - localparam logic c_ACMD = 1'b1; - - // packet bit names - localparam logic c_start_bit = 1'b0; // bit 47 - localparam logic c_stop_bit = 1'b1; // bit 0, AKA "end bit" - // transmitter bit, bit 46 - localparam logic c_tx_host_command = 1'b1; - localparam logic c_tx_card_response = 1'b0; - - // response types - localparam logic [2:0] c_response_type_R0_NONE = 3'd0; - localparam logic [2:0] c_response_type_R1_NORMAL = 3'd1; - localparam logic [2:0] c_response_type_R2_CID_CSD = 3'd2; - localparam logic [2:0] c_response_type_R3_OCR = 3'd3; - localparam logic [2:0] c_response_type_R6_RCA = 3'd6; - localparam logic [2:0] c_response_type_R7_CIC = 3'd7; - - // uses dat - localparam logic [1:0] c_DAT_none = 2'b00; - localparam logic [1:0] c_DAT_busy = 2'b01; - localparam logic [1:0] c_DAT_wide = 2'b10; - localparam logic [1:0] c_DAT_block = 2'b11; - - // tx source selection - localparam logic [1:0] c_tx_low = 2'b00; - localparam logic [1:0] c_tx_high = 2'b01; - localparam logic [1:0] c_tx_head = 2'b10; - localparam logic [1:0] c_tx_tail = 2'b11; - - // command indexes - localparam logic [45:40] c_Go_Idle_State = 6'd00; // CMD0 - localparam logic [45:40] c_All_Send_CID = 6'd02; // CMD2 - localparam logic [45:40] c_SD_Send_RCA = 6'd03; // CMD3 - localparam logic [45:40] c_Switch_Function = 6'd06; // CMD6 - localparam logic [45:40] c_Set_Bus_Width = 6'd06; // ACMD6 - localparam logic [45:40] c_Select_Card = 6'd07; // CMD7 - localparam logic [45:40] c_Send_IF_State = 6'd08; // CMD8 - localparam logic [45:40] c_Read_Single_Block = 6'd17; // CMD17 - localparam logic [45:40] c_SD_Send_OCR = 6'd41; // ACMD41 - localparam logic [45:40] c_App_Command = 6'd55; // CMD55 - - // bitmasks - localparam logic [127:96] c_CMD0_mask_check_redo_bits = 32'h00000000; // Go_Idle_State - localparam logic [127:96] c_CMD0_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD0_mask_check_error_bits = 32'h00000000; - localparam logic [127:96] c_CMD0_ans_error_free = 32'h00000000; - - localparam logic [127:96] c_CMD2_mask_check_redo_bits = 32'h00000000; // All_Send_CID - localparam logic [127:96] c_CMD2_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD2_mask_check_error_bits = 32'h00000000; - localparam logic [127:96] c_CMD2_ans_error_free = 32'h00000000; - - localparam logic [127:96] c_CMD3_mask_check_redo_bits = 32'h00000000; // SD_Send_RCA - localparam logic [127:96] c_CMD3_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD3_mask_check_error_bits = 32'h00002000; - localparam logic [127:96] c_CMD3_ans_error_free = 32'h00000000; - - localparam logic [127:96] c_CMD6_mask_check_redo_bits = 32'h00000000; // Switch_Function - localparam logic [127:96] c_CMD6_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD6_mask_check_error_bits = 32'h82380000; - localparam logic [127:96] c_CMD6_ans_error_free = 32'h00000000; - - localparam logic [127:96] c_ACMD6_mask_check_redo_bits = 32'h00000000; // Set_Bus_Width - localparam logic [127:96] c_ACMD6_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_ACMD6_mask_check_error_bits = 32'h8F398020; - localparam logic [127:96] c_ACMD6_ans_error_free = 32'h00000020; - - localparam logic [127:96] c_CMD7_mask_check_redo_bits = 32'h00000000; // Select_Card - localparam logic [127:96] c_CMD7_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD7_mask_check_error_bits = 32'h0F398000; - localparam logic [127:96] c_CMD7_ans_error_free = 32'h00000000; - - localparam logic [127:96] c_CMD8_mask_check_redo_bits = 32'h00000000; // Send_IF_State - localparam logic [127:96] c_CMD8_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD8_mask_check_error_bits = 32'h00000FFF; - localparam logic [127:96] c_CMD8_ans_error_free = 32'h000001FF; - - localparam logic [127:96] c_CMD17_mask_check_redo_bits = 32'h00000000; // Read_Single_Block - localparam logic [127:96] c_CMD17_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD17_mask_check_error_bits = 32'hCF398000; - localparam logic [127:96] c_CMD17_ans_error_free = 32'h00000000; - - localparam logic [127:96] c_ACMD41_mask_check_redo_bits = 32'h80000000; //32'h80000000; // SD_Send_OCR - localparam logic [127:96] c_ACMD41_ans_dont_redo = 32'h80000000; //32'h80000000; - localparam logic [127:96] c_ACMD41_mask_check_error_bits = 32'h41FF8000; // 32'h41FF8000; - localparam logic [127:96] c_ACMD41_ans_error_free = 32'h40FF8000; // 32'h40FF8000 - - localparam logic [127:96] c_CMD55_mask_check_redo_bits = 32'h00000000; // App_Command - localparam logic [127:96] c_CMD55_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_CMD55_mask_check_error_bits = 32'h0F398000; - localparam logic [127:96] c_CMD55_ans_error_free = 32'h00000000; - - localparam logic [127:96] c_ACMD55_mask_check_redo_bits = 32'h00000000; // App_Command - localparam logic [127:96] c_ACMD55_ans_dont_redo = 32'h00000000; - localparam logic [127:96] c_ACMD55_mask_check_error_bits = 32'h0F398000; - localparam logic [127:96] c_ACMD55_ans_error_free = 32'h00000000; - - // SD_CMD_FSM Connections - logic w_TIMER_LOAD, w_TIMER_EN; - logic [18:0] w_TIMER_IN; - logic [18:0] r_TIMER_OUT; - logic w_COUNTER_LOAD, w_COUNTER_EN; - logic [7:0] w_COUNTER_IN; - logic [7:0] r_COUNTER_OUT; - logic w_SD_CLK_EN; - logic w_CLOCK_CHANGE_DONE, w_START_CLOCK_CHANGE; // to clk fsm - logic w_HS_TO_INIT_CLK_DIVIDER_RST; - (* mark_debug = "true" *)logic w_IC_RST, w_IC_EN, w_IC_UP_DOWN; - (* mark_debug = "true" *)logic w_SD_CMD_OE; - logic w_TX_PISO40_LOAD, w_TX_PISO40_EN; - logic w_TX_PISO8_LOAD, w_TX_PISO8_EN; - logic w_TX_CRC7_PIPO_RST, w_TX_CRC7_PIPO_EN; - logic [1:0] w_TX_SOURCE_SELECT; - logic w_CMD_TX_IS_CMD55_RST; - logic w_CMD_TX_IS_CMD55_EN; - logic w_RX_SIPO48_RST, w_RX_SIPO48_EN; - (* mark_debug = "true" *)logic [39:8] r_RESPONSE_CONTENT; - (* mark_debug = "true" *)logic [45:40] r_RESPONSE_INDEX; - logic w_RX_CRC7_SIPO_RST, w_RX_CRC7_SIPO_EN; - logic [6:0] r_RX_CRC7_Q; - logic w_RCA_REGISTER_RST, w_RCA_REGISTER_EN; - logic w_CMD_TX_DONE; - logic w_DAT_RX_DONE; - logic w_DAT_ERROR_FD_RST_DAT, w_DAT_ERROR_FD_RST_CMD, w_DAT_ERROR_FD_RST, w_DAT_ERROR_FD_EN; - (* mark_debug = "true" *)logic r_DAT_ERROR_Q; // CRC16 error or time out - (* mark_debug = "true" *)logic w_NOT_DAT_ERROR_Q; // '0'=no error, '1'=tx error on DAT bus - (* mark_debug = "true" *)logic w_ERROR_DAT_TIMES_OUT; - (* mark_debug = "true" *)logic w_FATAL_ERROR; - (* mark_debug = "true" *)logic [2:0] r_ERROR_CODE_Q; // indicates which fatal error occured - - // Communication with core - (* mark_debug = "true" *)logic w_READY_FOR_READ; - (* mark_debug = "true" *)logic w_READ_REQUEST; - (* mark_debug = "true" *)logic [3:0] r_DATA_TO_CORE; - (* mark_debug = "true" *)logic w_DATA_VALID; - (* mark_debug = "true" *)logic w_LAST_NIBBLE; - - //SD_DAT_FSM Connections - logic w_DAT_TIMER_LOAD, w_DAT_TIMER_EN; - logic w_DAT_COUNTER_RST, w_DAT_COUNTER_EN; - logic w_CRC16_EN, w_CRC16_RST; - logic w_BUSY_RST, w_BUSY_EN; - logic w_NIBO_EN; - logic w_DATA_CRC16_GOOD; - logic [22:0] w_DAT_TIMER_IN; - logic [22:0] r_DAT_TIMER_OUT; - logic [10:0] r_DAT_COUNTER_OUT; - (* mark_debug = "true" *)logic [3:0] r_DAT_Q; - - // RCA Register - logic [15:0] w_RCA_D_Q; - logic [15:0] r_RCA_Q2; - - // Multiplexer Logics - logic [132:0] w_instruction_control_bits; - logic [132:130] w_R_TYPE ; - logic [129:128] w_USES_DAT ; - logic [127:96] w_NO_REDO_MASK ; - logic [95:64] w_NO_REDO_ANS ; - logic [63:32] w_NO_ERROR_MASK ; - logic [31:0] w_NO_ERROR_ANS ; - logic [45:40] w_command_index ; - logic [39:8] w_command_arguments ; - logic [47:8] w_command_head ; - (* mark_debug = "true" *)logic [6:0] w_OPCODE_Q ; - - // TOP_LEVEL Connections - logic [40:9] w_BLOCK_ADDR ; - (* mark_debug = "true" *)logic [3:0] r_IC_OUT ; - logic [2:0] r_command_index_is_55_history ; // [0] is live index, [1] is currently saved index, [2] is index of previous command - logic r_previous_command_index_was_55_q; // is index of previous command 55, wired to r_command_index_is_55_history[2] - logic r_ACMD_Q; // if the previous command sent to the SD card successfully had index 55, then the SD card thinks the current command is ACMD - - // TX - logic [45:8] w_command_content; // first 40 bits of command packet - logic w_tx_head_Q; // transmission of first part of command packet - logic w_tx_tail_Q; // transmission of last part of command packet - logic [7:0] r_command_tail; // last 8 bits of command packet - logic [6:0] r_TX_CRC7; - - // RX - logic [47:0] r_RX_RESPONSE; - - // Tri state IO Driver BC18MIMS - logic w_SD_CMD_TX_Q; // Write Data - logic w_SD_CMD_RX; // Read Data - - - // CLOCKS - //logic r_CLK_HS := '0'; // 50 MHz Divided Clock [static] - //logic r_SD_CLK_ungated := '0'; // Selected clock before it is clock gated - - //logic r_SD_CLK := '0'; // GATED CLOCKS - logic r_TO_SD_CLK; // What is actually sent to the SD card - - logic w_G_CLK_SD_EN; - logic r_CLK_SD, r_G_CLK_SD; // clocks - logic [15:0] r_CLK_FSM_RST ; // a_rst logic delayed by one 1.2 GHz period - logic w_SD_CLK_SELECTED; - - //DAT FSM Connections - logic [15:0] r_DAT3_CRC16, r_DAT2_CRC16, r_DAT1_CRC16; - logic [15:0] r_DAT0_CRC16; - - assign w_BLOCK_ADDR = {8'h00, i_BLOCK_ADDR}; // (40 downto 36 are zero since card is 64 GB) - // (35 downto 32 are zero since memeory is only 8GB total) - - assign o_READY_FOR_READ = w_READY_FOR_READ; - assign w_READ_REQUEST = i_READ_REQUEST; - assign o_DATA_TO_CORE = r_DATA_TO_CORE; - assign o_DATA_VALID = w_DATA_VALID; - assign o_LAST_NIBBLE = (w_LAST_NIBBLE | w_FATAL_ERROR); // indicate done if (last nibble OR Fatal Error go high) - assign o_FATAL_ERROR = w_FATAL_ERROR; - - sd_cmd_fsm my_sd_cmd_fsm - ( - .CLK(r_G_CLK_SD), - .i_RST(a_RST), - .o_TIMER_LOAD(w_TIMER_LOAD), - .o_TIMER_EN(w_TIMER_EN), - .o_TIMER_IN(w_TIMER_IN), - .i_TIMER_OUT(r_TIMER_OUT), - .o_COUNTER_LOAD(w_COUNTER_LOAD), - .o_COUNTER_EN(w_COUNTER_EN), - .o_COUNTER_IN(w_COUNTER_IN), - .i_COUNTER_OUT(r_COUNTER_OUT), - .o_SD_CLK_EN(w_SD_CLK_EN), - .i_CLOCK_CHANGE_DONE(w_CLOCK_CHANGE_DONE), - .o_START_CLOCK_CHANGE(w_START_CLOCK_CHANGE), - .o_IC_RST(w_IC_RST), - .o_IC_EN(w_IC_EN), - .o_IC_UP_DOWN(w_IC_UP_DOWN), - .i_IC_OUT(r_IC_OUT), - .i_USES_DAT(w_USES_DAT), - .i_OPCODE(w_OPCODE_Q), - .i_R_TYPE(w_R_TYPE), - .i_NO_REDO_MASK(w_NO_REDO_MASK), - .i_NO_REDO_ANS(w_NO_REDO_ANS), - .i_NO_ERROR_MASK(w_NO_ERROR_MASK), - .i_NO_ERROR_ANS(w_NO_ERROR_ANS), - .o_SD_CMD_OE(w_SD_CMD_OE), - .o_TX_PISO40_LOAD(w_TX_PISO40_LOAD), - .o_TX_PISO40_EN(w_TX_PISO40_EN), - .o_TX_PISO8_LOAD(w_TX_PISO8_LOAD), - .o_TX_PISO8_EN(w_TX_PISO8_EN), - .o_TX_CRC7_PIPO_RST(w_TX_CRC7_PIPO_RST), - .o_TX_CRC7_PIPO_EN(w_TX_CRC7_PIPO_EN), - .o_TX_SOURCE_SELECT(w_TX_SOURCE_SELECT), - .o_CMD_TX_IS_CMD55_RST(w_CMD_TX_IS_CMD55_RST), - .o_CMD_TX_IS_CMD55_EN(w_CMD_TX_IS_CMD55_EN), - .i_SD_CMD_RX(w_SD_CMD_RX), - .o_RX_SIPO48_RST(w_RX_SIPO48_RST), - .o_RX_SIPO48_EN(w_RX_SIPO48_EN), - .i_RESPONSE_CONTENT(r_RESPONSE_CONTENT), - .i_RESPONSE_INDEX(r_RESPONSE_INDEX), - .o_RX_CRC7_SIPO_RST(w_RX_CRC7_SIPO_RST), - .o_RX_CRC7_SIPO_EN(w_RX_CRC7_SIPO_EN), - .i_RX_CRC7(r_RX_CRC7_Q), - .o_RCA_REGISTER_RST(w_RCA_REGISTER_RST), - .o_RCA_REGISTER_EN(w_RCA_REGISTER_EN), - .o_CMD_TX_DONE(w_CMD_TX_DONE), - .i_DAT_RX_DONE(w_DAT_RX_DONE), - .i_ERROR_CRC16(w_NOT_DAT_ERROR_Q), - .i_ERROR_DAT_TIMES_OUT(w_ERROR_DAT_TIMES_OUT), - .i_READ_REQUEST(w_READ_REQUEST), - .o_READY_FOR_READ(w_READY_FOR_READ), - .o_SD_RESTARTING(o_SD_RESTARTING), - .o_DAT_ERROR_FD_RST(w_DAT_ERROR_FD_RST_CMD), - .o_ERROR_CODE_Q(r_ERROR_CODE_Q), - .o_FATAL_ERROR(w_FATAL_ERROR), - .LIMIT_SD_TIMERS(LIMIT_SD_TIMERS)); - - assign o_ERROR_CODE_Q = r_ERROR_CODE_Q; - - sd_dat_fsm my_sd_dat_fsm - (.CLK(r_G_CLK_SD), - .i_RST(a_RST), - .o_TIMER_LOAD(w_DAT_TIMER_LOAD), - .o_TIMER_EN(w_DAT_TIMER_EN), - .o_TIMER_IN(w_DAT_TIMER_IN), - .i_TIMER_OUT(r_DAT_TIMER_OUT), - .i_SD_CLK_SELECTED(w_SD_CLK_SELECTED), - .o_COUNTER_RST(w_DAT_COUNTER_RST), - .o_COUNTER_EN(w_DAT_COUNTER_EN), - .i_COUNTER_OUT(r_DAT_COUNTER_OUT), - .o_CRC16_EN(w_CRC16_EN), - .o_CRC16_RST(w_CRC16_RST), - .i_DATA_CRC16_GOOD(w_DATA_CRC16_GOOD), - .o_BUSY_RST(w_BUSY_RST), - .o_BUSY_EN(w_BUSY_EN), - .i_DAT0_Q(r_DAT_Q[0]), - .o_NIBO_EN(w_NIBO_EN), - .i_USES_DAT(w_USES_DAT), - .i_CMD_TX_DONE(w_CMD_TX_DONE), - .o_DAT_RX_DONE(w_DAT_RX_DONE), - .o_ERROR_DAT_TIMES_OUT(w_ERROR_DAT_TIMES_OUT), - .o_DATA_VALID(w_DATA_VALID), - .o_LAST_NIBBLE(w_LAST_NIBBLE), - .o_DAT_ERROR_FD_RST(w_DAT_ERROR_FD_RST_DAT), - .o_DAT_ERROR_FD_EN(w_DAT_ERROR_FD_EN), - .LIMIT_SD_TIMERS(LIMIT_SD_TIMERS)); - - assign w_DAT_ERROR_FD_RST = w_DAT_ERROR_FD_RST_CMD | w_DAT_ERROR_FD_RST_DAT; - - flopenr #(1) dat_error_fd - (.clk(r_G_CLK_SD), - .d(w_DATA_CRC16_GOOD), - .q(r_DAT_ERROR_Q), - .en(w_DAT_ERROR_FD_EN), - .reset((w_DAT_ERROR_FD_RST))); - - assign w_NOT_DAT_ERROR_Q = ~r_DAT_ERROR_Q; - - up_down_counter #(23) dat_fsm_timer - ( - .CountIn(w_DAT_TIMER_IN), - .CountOut(r_DAT_TIMER_OUT), - .Load(w_DAT_TIMER_LOAD), - .Enable(w_DAT_TIMER_EN), - .UpDown(1'b0), // Count DOWN only - .clk(r_G_CLK_SD), - .reset(1'b0)); // No Reset, Just Load - - SDCcounter #(11) dat_nibble_counter - ( - .CountIn('0), - .CountOut(r_DAT_COUNTER_OUT), - .Load(1'b0), - .Enable(w_DAT_COUNTER_EN), - .clk(r_G_CLK_SD), - .reset(w_DAT_COUNTER_RST)); - - regfile_p2r1w1_nibo #(.DEPTH(10), .WIDTH(4) ) regfile_cmd17_data_block // Nibble In - Nibble Out (NINO) - (.clk(r_G_CLK_SD), - .we1(w_NIBO_EN), - .ra1(r_DAT_COUNTER_OUT[9:0]), // Nibble Read (to core) Address - .rd1(r_DATA_TO_CORE), // output nibble to core - .Rd1All(ReadData), - .wa1(r_DAT_COUNTER_OUT[9:0]), // Nibble Write (to host) Address - .wd1(r_DAT_Q)); // input nibble from card - - crc16_sipo_np_ce crc16_sipo_np_ce_DAT3 - (.CLK(r_G_CLK_SD), - .RST(w_CRC16_RST), - .i_enable(w_CRC16_EN), - .i_message_bit(r_DAT_Q[3]), - .o_crc16(r_DAT3_CRC16)); - - crc16_sipo_np_ce crc16_sipo_np_ce_DAT2 - (.CLK(r_G_CLK_SD), - .RST(w_CRC16_RST), - .i_enable(w_CRC16_EN), - .i_message_bit(r_DAT_Q[2]), - .o_crc16(r_DAT2_CRC16)); - - crc16_sipo_np_ce crc16_sipo_np_ce_DAT1 - (.CLK(r_G_CLK_SD), - .RST(w_CRC16_RST), - .i_enable(w_CRC16_EN), - .i_message_bit(r_DAT_Q[1]), - .o_crc16(r_DAT1_CRC16)); - - crc16_sipo_np_ce crc16_sipo_np_ce_DAT0 - (.CLK(r_G_CLK_SD), - .RST(w_CRC16_RST), - .i_enable(w_CRC16_EN), - .i_message_bit(r_DAT_Q[0]), - .o_crc16(r_DAT0_CRC16)); - - - assign w_DATA_CRC16_GOOD = ({r_DAT3_CRC16, r_DAT2_CRC16, r_DAT1_CRC16, r_DAT0_CRC16}) == 64'h0000000000000000; - - flopenr #(4) busy_bit_fd - (.en(w_BUSY_EN), - .clk(r_G_CLK_SD), - .d(i_SD_DAT), - .q(r_DAT_Q), - .reset(w_BUSY_RST)); - - sd_clk_fsm my_clk_fsm - (.CLK(CLK), - .i_RST(a_RST), - .o_DONE(w_CLOCK_CHANGE_DONE), - .i_START(w_START_CLOCK_CHANGE), - .o_HS_TO_INIT_CLK_DIVIDER_RST(w_HS_TO_INIT_CLK_DIVIDER_RST), - .o_SD_CLK_SELECTED(w_SD_CLK_SELECTED), - .i_FATAL_ERROR(w_FATAL_ERROR), - .o_G_CLK_SD_EN(w_G_CLK_SD_EN)); - - up_down_counter #(19) cmd_fsm_timer - (.CountIn(w_TIMER_IN), - .CountOut(r_TIMER_OUT), - .Load(w_TIMER_LOAD), - .Enable(w_TIMER_EN), - .UpDown(1'b0), // Count DOWN only - .clk(r_G_CLK_SD), - .reset(1'b0)); // No Reset, Just Load - - up_down_counter #(8) cmd_fsm_counter - (.CountIn(w_COUNTER_IN), - .CountOut(r_COUNTER_OUT), - .Load(w_COUNTER_LOAD), - .Enable(w_COUNTER_EN), - .UpDown(1'b0), // Count DOWN only - .clk(r_G_CLK_SD), - .reset(1'b0)); // No RESET, only LOAD - - up_down_counter #(4) instruction_counter - (.CountIn('0), // No CountIn, only RESET - .CountOut(r_IC_OUT), - .Load(1'b0), // No LOAD, only RESET - .Enable(w_IC_EN), - .UpDown(w_IC_UP_DOWN), - .clk(r_G_CLK_SD), - .reset(w_IC_RST | a_RST)); - - // Clock selection - clkdivider #(g_COUNT_WIDTH) slow_clk_divider // Divide 50 MHz to <400 KHz (Initial clock) - (.i_COUNT_IN_MAX(i_COUNT_IN_MAX), - .i_EN(w_SD_CLK_SELECTED), - //.i_EN(1'b1), - //.i_RST(w_HS_TO_INIT_CLK_DIVIDER_RST), - .i_RST(a_RST), - .i_CLK(CLK), - .o_CLK(r_CLK_SD)); - - clockgater sd_clk_gater // Select which clock goes to components - (.CLK(r_CLK_SD), - .E(w_G_CLK_SD_EN | a_RST), - .SE(1'b0), - .ECLK(r_G_CLK_SD)); - - clockgater to_sd_clk_gater // Enable activity on the SD_CLK line - (.CLK(r_G_CLK_SD), - .E(w_SD_CLK_EN), - .SE(1'b0), - .ECLK(r_TO_SD_CLK)); - - flopenr #(16) RCA_register_CE - (.clk(r_G_CLK_SD), - .en(w_RCA_REGISTER_EN), - .d(w_RCA_D_Q), - .q(r_RCA_Q2), - .reset(w_RCA_REGISTER_RST)); - - // ACMD_Detector - flopenr #(1) index_history_fd_2to1 - (.clk(r_G_CLK_SD), - .reset(w_CMD_TX_IS_CMD55_RST), - .en(w_CMD_TX_IS_CMD55_EN), - .d(r_command_index_is_55_history[2]), - .q(r_command_index_is_55_history[1])); - - flopenr #(1) index_history_fd_1to0 - (.clk(r_G_CLK_SD), - .reset(w_CMD_TX_IS_CMD55_RST), - .en(w_CMD_TX_IS_CMD55_EN), - .d(r_command_index_is_55_history[1]), - .q(r_command_index_is_55_history[0])); - - - - assign r_command_index_is_55_history[2] = (w_command_index == 55); - - - assign r_previous_command_index_was_55_q = r_command_index_is_55_history[0]; - assign r_ACMD_Q = r_previous_command_index_was_55_q; // if the previous command WAS 55, the current command is ACMD - - assign o_SD_CLK = r_TO_SD_CLK; - - - - // Multiplexers - //Fetch index and argument of command - assign w_command_content = (r_IC_OUT == 0) ? ({c_Go_Idle_State, 32'h00000000}) : // CMD0 - (r_IC_OUT == 1) ? ({c_Send_IF_State, 32'h000001FF}) : // CMD8 - (r_IC_OUT == 2) ? ({c_App_Command, 32'h00000000}) : // CMD55 - (r_IC_OUT == 3) ? ({c_SD_Send_OCR, 32'h40FF8000}) : // ACMD41 - (r_IC_OUT == 4) ? ({c_All_Send_CID, 32'h00000000}) : // CMD2 - (r_IC_OUT == 5) ? ({c_SD_Send_RCA, 32'h00000000}) : // CMD3 - (r_IC_OUT == 6) ? ({c_Select_Card, r_RCA_Q2[15:0], 16'h0000}) : // CMD7 - (r_IC_OUT == 7) ? ({c_App_Command, r_RCA_Q2[15:0], 16'h0000}) : // CMD55 - (r_IC_OUT == 8) ? ({c_Set_Bus_Width, 32'h00000002}) : // ACMD6 - (r_IC_OUT == 9) ? ({c_Switch_Function, 32'h80FFFFF1}) : // CMD6 - (r_IC_OUT == 10) ? ({c_Read_Single_Block, w_BLOCK_ADDR}) : // CMD17 - ({c_Read_Single_Block, w_BLOCK_ADDR}); // when in doubt just send CMD17 - - assign w_command_index = w_command_content[45:40]; - assign w_command_arguments = w_command_content[39:8]; - assign w_command_head = {c_start_bit, c_tx_host_command, w_command_content}; - - assign w_OPCODE_Q = {r_ACMD_Q, w_command_index}; - - // TX - - crc7_pipo tx_crc7_pipo - (.CLK(r_G_CLK_SD), - .i_DATA(w_command_head), - .i_CRC_ENABLE(w_TX_CRC7_PIPO_EN), - .RST(w_TX_CRC7_PIPO_RST), - .o_CRC(r_TX_CRC7)); - - assign r_command_tail = {r_TX_CRC7, c_stop_bit}; - - piso_generic_ce #(40) tx_piso40_command_head - (.clk(r_G_CLK_SD), - .i_load(w_TX_PISO40_LOAD), - .i_data(w_command_head), - .i_en(w_TX_PISO40_EN), - .o_data(w_tx_head_Q)); - - piso_generic_ce #(8) tx_piso8_command_tail - (.clk(r_G_CLK_SD), - .i_load(w_TX_PISO8_LOAD), - .i_data(r_command_tail), - .i_en(w_TX_PISO8_EN), - .o_data(w_tx_tail_Q)); - - assign w_SD_CMD_TX_Q = (w_TX_SOURCE_SELECT == c_tx_low) ? 1'b0 : - (w_TX_SOURCE_SELECT == c_tx_high) ? 1'b1 : - (w_TX_SOURCE_SELECT == c_tx_head) ? w_tx_head_Q : - (w_TX_SOURCE_SELECT == c_tx_tail) ? w_tx_tail_Q : - 1'b0; - - assign w_SD_CMD_RX = i_SD_CMD; - - flopenr #(1) sd_cmd_out_reg - (.d(w_SD_CMD_TX_Q), - .q(o_SD_CMD), - .en(1'b1), - .clk(~r_G_CLK_SD), - .reset(a_RST)); - - flopenr #(1) sd_cmd_out_oe_reg - (.d(w_SD_CMD_OE), - .q(o_SD_CMD_OE), - .en(1'b1), - .clk(~r_G_CLK_SD), - .reset(a_RST)); - - // RX - sipo_generic_ce #(48) rx_sipo48_response_content - (.clk(r_G_CLK_SD), - .rst(w_RX_SIPO48_RST), - .i_enable(w_RX_SIPO48_EN), - .i_message_bit(w_SD_CMD_RX), - .o_data(r_RX_RESPONSE)); - - assign r_RESPONSE_CONTENT = r_RX_RESPONSE[39:8]; - assign r_RESPONSE_INDEX = r_RX_RESPONSE[45:40]; - assign w_RCA_D_Q = r_RESPONSE_CONTENT[39:24]; - - crc7_sipo_np_ce rx_crc7_sipo - (.clk(r_G_CLK_SD), - .rst(w_RX_CRC7_SIPO_RST), - .i_enable(w_RX_CRC7_SIPO_EN), - .i_message_bit(w_SD_CMD_RX), - .o_crc7(r_RX_CRC7_Q)); - - // Fetch control bits using r_opcode - assign w_instruction_control_bits = (w_OPCODE_Q == ({c_CMD, c_Go_Idle_State})) ? ({c_response_type_R0_NONE, c_DAT_none, c_CMD0_mask_check_redo_bits, c_CMD0_ans_dont_redo, c_CMD0_mask_check_error_bits, c_CMD0_ans_error_free}) : // CMD0 - - (w_OPCODE_Q == ({c_CMD, c_All_Send_CID})) ? ({c_response_type_R2_CID_CSD, c_DAT_none, c_CMD2_mask_check_redo_bits, c_CMD2_ans_dont_redo, c_CMD2_mask_check_error_bits, c_CMD2_ans_error_free}): // CMD2 - - (w_OPCODE_Q == ({c_CMD, c_SD_Send_RCA})) ? ({c_response_type_R6_RCA, c_DAT_none, c_CMD3_mask_check_redo_bits, c_CMD3_ans_dont_redo, c_CMD3_mask_check_error_bits, c_CMD3_ans_error_free}) : // CMD3 - - (w_OPCODE_Q == ({c_CMD, c_Switch_Function})) ? ({c_response_type_R1_NORMAL, c_DAT_wide, c_CMD6_mask_check_redo_bits, c_CMD6_ans_dont_redo, c_CMD6_mask_check_error_bits, c_CMD6_ans_error_free}): // CMD6 - - (w_OPCODE_Q == ({c_ACMD, c_Set_Bus_Width})) ? ({c_response_type_R1_NORMAL, c_DAT_none, c_ACMD6_mask_check_redo_bits, c_ACMD6_ans_dont_redo, c_ACMD6_mask_check_error_bits, c_ACMD6_ans_error_free}): //ACMD6 - - (w_OPCODE_Q == ({c_CMD, c_Select_Card})) ? ({c_response_type_R1_NORMAL, c_DAT_busy, c_CMD7_mask_check_redo_bits, c_CMD7_ans_dont_redo, c_CMD7_mask_check_error_bits, c_CMD7_ans_error_free}): // CMD7 - - (w_OPCODE_Q == ({c_CMD, c_Send_IF_State})) ? ({c_response_type_R7_CIC, c_DAT_none, c_CMD8_mask_check_redo_bits, c_CMD8_ans_dont_redo, c_CMD8_mask_check_error_bits, c_CMD8_ans_error_free}): // CMD8 - - (w_OPCODE_Q == ({c_CMD, c_Read_Single_Block})) ? ({c_response_type_R1_NORMAL, c_DAT_block, c_CMD17_mask_check_redo_bits, c_CMD17_ans_dont_redo, c_CMD17_mask_check_error_bits, c_CMD17_ans_error_free}): // CMD17 - - (w_OPCODE_Q == ({c_ACMD, c_SD_Send_OCR})) ? ({c_response_type_R3_OCR, c_DAT_none, c_ACMD41_mask_check_redo_bits, c_ACMD41_ans_dont_redo, c_ACMD41_mask_check_error_bits, c_ACMD41_ans_error_free}) : //ACMD41 - - (w_OPCODE_Q == ({c_CMD, c_App_Command})) ? ({c_response_type_R1_NORMAL, c_DAT_none, c_CMD55_mask_check_redo_bits, c_CMD55_ans_dont_redo, c_CMD55_mask_check_error_bits, c_CMD55_ans_error_free}) : // CMD55 - - (w_OPCODE_Q == ({c_ACMD, c_App_Command})) ? ({c_response_type_R1_NORMAL, c_DAT_none, c_ACMD55_mask_check_redo_bits, c_ACMD55_ans_dont_redo, c_ACMD55_mask_check_error_bits, c_ACMD55_ans_error_free}) : //ACMD55 - - ({c_response_type_R1_NORMAL, c_DAT_none, c_ACMD55_mask_check_redo_bits, c_ACMD55_ans_dont_redo, c_ACMD55_mask_check_error_bits, c_ACMD55_ans_error_free}); // when in doubt just send ACMD55 - - assign w_R_TYPE = w_instruction_control_bits[132:130]; - assign w_USES_DAT = w_instruction_control_bits[129:128]; - assign w_NO_REDO_MASK = w_instruction_control_bits[127:96]; - assign w_NO_REDO_ANS = w_instruction_control_bits[95:64]; - assign w_NO_ERROR_MASK = w_instruction_control_bits[63:32]; - assign w_NO_ERROR_ANS = w_instruction_control_bits[31:0]; - - -endmodule - diff --git a/pipelined/src/uncore/sdc/sd_top_wrapper.v b/pipelined/src/uncore/sdc/sd_top_wrapper.v deleted file mode 100644 index 96d1bbc46..000000000 --- a/pipelined/src/uncore/sdc/sd_top_wrapper.v +++ /dev/null @@ -1,98 +0,0 @@ - -/////////////////////////////////////////// -// sd_top_wrapper.sv -// -// Written: Richard Davis -// Modified: Ross Thompson September 19, 2021 -// -// Purpose: SD card controller wrapper -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -/// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - - -module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8) ( - input logic clk_in1_p, - input logic clk_in1_n, - input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles) - // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK! - // io_SD_CMD_z : inout std_logic; // SD CMD Bus - inout SD_CMD, // CMD Response from card - input logic [3:0] i_SD_DAT, // SD DAT Bus - output logic o_SD_CLK, // SD CLK Bus - // For communication with core cpu - output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and - // sd card is ready to read a 512 byte block to the core. - // Held high during idle until i_READ_REQUEST is received - output logic o_SD_RESTARTING, // inform core the need to restart - - input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will - // pulse this bit high to indicate it wants the block at this address - output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is being published - output logic o_DATA_VALID // held high while data being read to core to indicate that it is valid -); - - wire CLK; - wire LIMIT_SD_TIMERS; - wire [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX; - wire [4095:0] ReadData; // full 512 bytes to Bus - wire [32:9] i_BLOCK_ADDR; // see "Addressing" in parts.fods (only 8GB total capacity is used) - wire o_SD_CMD; // CMD Command from host - wire i_SD_CMD; // CMD Command from host - wire o_SD_CMD_OE; // Direction of SD_CMD - wire [2:0] o_ERROR_CODE_Q; // indicates which error occured - wire o_FATAL_ERROR; // indicates that the FATAL ERROR register has updated - wire o_LAST_NIBBLE; // pulse when last nibble is sent - - assign LIMIT_SD_TIMERS = 1'b0; - assign i_COUNT_IN_MAX = -8'd62; - assign i_BLOCK_ADDR = 23'h0; - - clk_wiz_0 clk_wiz_0(.clk_in1_p(clk_in1_p), - .clk_in1_n(clk_in1_n), - .reset(1'b0), - .clk_out1(CLK), - .locked(locked)); - - IOBUF SDCMDIODriver(.T(~o_SD_CMD_OE), - .I(o_SD_CMD), - .O(i_SD_CMD), - .IO(SD_CMD)); - - - sd_top #(g_COUNT_WIDTH) - sd_top(.CLK(CLK), - .a_RST(a_RST), - .i_SD_CMD(i_SD_CMD), // CMD Response from card - .o_SD_CMD(o_SD_CMD), // CMD Command from host - .o_SD_CMD_OE(o_SD_CMD_OE), // Direction of SD_CMD - .i_SD_DAT(i_SD_DAT), // SD DAT Bus - .o_SD_CLK(o_SD_CLK), // SD CLK Bus - .i_BLOCK_ADDR(i_BLOCK_ADDR), // see "Addressing" in parts.fods (only 8GB total capacity is used) - .o_READY_FOR_READ(o_READY_FOR_READ), // tells core that initialization sequence is completed and - .o_SD_RESTARTING(o_SD_RESTARTING), // inform core the need to restart - .i_READ_REQUEST(i_READ_REQUEST), // After Ready for read is sent to the core, the core will - .o_DATA_TO_CORE(o_DATA_TO_CORE), // nibble being sent to core when DATA block is - .ReadData(ReadData), // full 512 bytes to Bus - .o_DATA_VALID(o_DATA_VALID), // held high while data being read to core to indicate that it is valid - .o_LAST_NIBBLE(o_LAST_NIBBLE), // pulse when last nibble is sent - .o_ERROR_CODE_Q(o_ERROR_CODE_Q), // indicates which error occured - .o_FATAL_ERROR(o_FATAL_ERROR), // indicates that the FATAL ERROR register has updated - .i_COUNT_IN_MAX(i_COUNT_IN_MAX), - .LIMIT_SD_TIMERS(LIMIT_SD_TIMERS) - ); - -endmodule diff --git a/pipelined/src/uncore/sdc/simple_timer.sv b/pipelined/src/uncore/sdc/simple_timer.sv deleted file mode 100644 index 09dbf048c..000000000 --- a/pipelined/src/uncore/sdc/simple_timer.sv +++ /dev/null @@ -1,54 +0,0 @@ -/////////////////////////////////////////// -// simple_timer.sv -// -// Written: Ross Thompson September 20, 2021 -// Modified: -// -// Purpose: SD card controller -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module simple_timer #(parameter BUS_WIDTH = 4) ( - input logic [BUS_WIDTH-1:0] VALUE, - input logic START, - output logic FLAG, - input logic RST, - input logic CLK -); - - - logic [BUS_WIDTH-1:0] count; - logic timer_en; - - assign timer_en = count != 0; - - always_ff @(posedge CLK, posedge RST) begin - if (RST) begin - count <= '0; - end else if (START) begin - count <= VALUE - 1'b1; - end else if(timer_en) begin - count <= count - 1'b1; - end - end - - assign FLAG = count != 0; - -endmodule - diff --git a/pipelined/src/uncore/sdc/sipo_generic_ce.sv b/pipelined/src/uncore/sdc/sipo_generic_ce.sv deleted file mode 100644 index 7b749b654..000000000 --- a/pipelined/src/uncore/sdc/sipo_generic_ce.sv +++ /dev/null @@ -1,51 +0,0 @@ -/////////////////////////////////////////// -// sipo_generic_ce -// -// Written: Richard Davis -// Modified: Ross Thompson September 20, 2021 -// -// Purpose: serial to n-bit parallel shift register using register_ce. -// When given a n-bit word as input transmit the message serially MSB (leftmost) -// bit first. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module sipo_generic_ce #(g_BUS_WIDTH) ( - input logic clk, - input logic rst, - input logic i_enable, // data valid, write to register - input logic i_message_bit, // serial data - output logic [g_BUS_WIDTH-1:0] o_data // message received, parallel data -); - - logic [g_BUS_WIDTH-1:0] w_reg_d; - logic [g_BUS_WIDTH-1:0] r_reg_q; - - flopenr #(g_BUS_WIDTH) shiftReg - (.d(w_reg_d), - .q(r_reg_q), - .en(i_enable), - .reset(rst), - .clk(clk)); - - assign w_reg_d = {r_reg_q[g_BUS_WIDTH-2:0], i_message_bit}; - - assign o_data = r_reg_q; - -endmodule diff --git a/pipelined/src/uncore/sdc/up_down_counter.sv b/pipelined/src/uncore/sdc/up_down_counter.sv deleted file mode 100644 index 4424386ac..000000000 --- a/pipelined/src/uncore/sdc/up_down_counter.sv +++ /dev/null @@ -1,45 +0,0 @@ -/////////////////////////////////////////// -// counter.sv -// -// Written: Ross Thompson -// Modified: -// -// Purpose: basic up counter -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module up_down_counter #(parameter integer WIDTH=32) ( - input logic [WIDTH-1:0] CountIn, - output logic [WIDTH-1:0] CountOut, - input logic Load, - input logic Enable, - input logic UpDown, - input logic clk, - input logic reset -); - - logic [WIDTH-1:0] NextCount; - logic [WIDTH-1:0] CountP1; - - assign CountP1 = UpDown ? CountOut + 1'b1 : CountOut - 1'b1; - assign NextCount = Load ? CountIn : CountP1; - flopenr #(WIDTH) reg1(clk, reset, Enable | Load, NextCount, CountOut); -endmodule - - From 3d71d0196c76d7dbed1d3d91ea964f318ae02d97 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 15:01:54 -0600 Subject: [PATCH 019/294] Updated figure cache references. --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/cache/cacheLRU.sv | 2 +- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/cache/cacheway.sv | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 4761241d5..72b97a313 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -7,7 +7,7 @@ // // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.11, and 7.20) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index 8dfce6797..be42036e0 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -7,7 +7,7 @@ // // Purpose: Implements Pseudo LRU. Tested for Powers of 2. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.16 to 7.19) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 2f9bca061..bc9982e59 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for the dcache fsm // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.15 and Table 7.1) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index d5fc0b7d1..d3e996729 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -7,7 +7,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.12) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) // // A component of the CORE-V-WALLY configurable RISC-V project. // From 11c61060222b715e5f06e3b8c3576a819913c6dc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 15:26:52 -0600 Subject: [PATCH 020/294] Repaired fpga debugger. --- fpga/constraints/debug2.xdc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index bdc073ee1..69d295f85 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -82,12 +82,12 @@ connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/b create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe15] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63]} ]] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[63]} ]] create_debug_port u_ila_0 probe @@ -109,7 +109,7 @@ connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/d create_debug_port u_ila_0 probe set_property port_width 63 [get_debug_ports u_ila_0/probe20] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[63]} ]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]] create_debug_port u_ila_0 probe @@ -674,7 +674,7 @@ connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/ create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe130] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130] -connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]] +connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe131] From 0f68fccf8249242a2e40d9561ec1dcade3617fe2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 20 Jan 2023 14:19:07 -0800 Subject: [PATCH 021/294] Started adding bit manipulation unit --- pipelined/config/shared/wally-constants.vh | 1 + pipelined/config/shared/wally-shared.vh | 6 +++ pipelined/src/bmu/bmu.sv | 45 ++++++++++++++++++++++ pipelined/src/ieu/datapath.sv | 11 +++++- pipelined/src/ieu/ieu.sv | 11 ++++-- pipelined/src/wally/wallypipelinedcore.sv | 19 ++++++++- 6 files changed, 85 insertions(+), 8 deletions(-) create mode 100644 pipelined/src/bmu/bmu.sv diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh index a865cfd5c..0acc12b86 100644 --- a/pipelined/config/shared/wally-constants.vh +++ b/pipelined/config/shared/wally-constants.vh @@ -52,6 +52,7 @@ // macros to define supported modes `define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA `define C_SUPPORTED ((`MISA >> 2) % 2 == 1) `define D_SUPPORTED ((`MISA >> 3) % 2 == 1) `define E_SUPPORTED ((`MISA >> 4) % 2 == 1) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 1e961c64a..2fcb3af7a 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -26,6 +26,12 @@ `define RADIX 32'h4 `define DIVCOPIES 32'h4 +// eventually move to each config +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + // Memory synthesis configuration `define USE_SRAM 0 diff --git a/pipelined/src/bmu/bmu.sv b/pipelined/src/bmu/bmu.sv new file mode 100644 index 000000000..ba6ab0b08 --- /dev/null +++ b/pipelined/src/bmu/bmu.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// bmu.sv +// +// Written: kekim@g.hmc.edu, David_Harris@hmc.edu 20 January 2023 +// Modified: +// +// Purpose: Bit manipulation extensions Zba, Zbb, Zbc, Zbs +// Single-cycle operation in Execute stage +// +// Documentation: n/a +// See RISC-V Bit-Manipulation ISA-extensions +// Version 1.0.0-38-g865e7a7, 2021-06-28: Release candidate +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module bmu( + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output + input logic [31:0] InstrD, // instruction + output logic BMUE, // bit manipulation instruction + output logic [`XLEN-1:0] BMUResultE // bit manipulation result +); + + + +endmodule // mdu + + diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 5c4ad5ef0..84e3dc9cb 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -48,6 +48,7 @@ module datapath ( output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B + input logic BMUE, // Bit manipulation instruction // Memory stage signals input logic StallM, FlushM, // Stall, flush Memory stage input logic FWriteIntM, FCvtIntW, // FPU writes integer register file, FPU converts float to int @@ -61,7 +62,9 @@ module datapath ( input logic [2:0] ResultSrcW, // Select source of result to write back to register file input logic [`XLEN-1:0] FCvtIntResW, // FPU convert fp to integer result input logic [`XLEN-1:0] ReadDataW, // Read data from LSU - input logic [`XLEN-1:0] CSRReadValW, MDUResultW, // CSR read result, MDU (Multiply/divide unit) result + input logic [`XLEN-1:0] CSRReadValW, // CSR read result + input logic [`XLEN-1:0] MDUResultW, // MDU (Multiply/divide unit) result + input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result input logic [`XLEN-1:0] FIntDivResultW, // FPU's integer divide result // Hazard Unit signals output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, // Register sources to read in Decode or Execute stage @@ -78,6 +81,7 @@ module datapath ( logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage + logic [`XLEN-1:0] IEUBResultE; // IEUResultE before optional bit manipulation mux // Memory stage signals logic [`XLEN-1:0] IEUResultM; // Result from execution stage logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register @@ -110,7 +114,10 @@ module datapath ( mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); - mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); + mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUBResultE); + if (`B_SUPPORTED) + mux2 #(`XLEN) bmuresultmux(IEUResultE, BMUResultE, BMUE, IEUResultE); + else assign IEUResultE = IEUBResultE; // Memory stage pipeline register flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index db0ddb2cc..fd8a74c2b 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -43,6 +43,7 @@ module ieu ( output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction output logic [2:0] Funct3E, // Funct3 instruction field output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B + input logic BMUE, // This is a bit manipulation instruction output logic [4:0] RdE, // Destination register // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU @@ -56,8 +57,10 @@ module ieu ( output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidM, // Instruction is valid // Writeback stage signals - input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt - input logic [`XLEN-1:0] CSRReadValW, MDUResultW, // CSR read value, MDU (multiply/divide unit) result + input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) + input logic [`XLEN-1:0] CSRReadValW, // CSR read value, + input logic [`XLEN-1:0] MDUResultW, // multiply/divide unit result + input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result input logic [`XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result input logic FCvtIntW, // FPU converts float to int output logic [4:0] RdW, // Destination register @@ -102,10 +105,10 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, - .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); + .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); forward fw( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index daefca9af..2e6b63035 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -163,6 +163,10 @@ module wallypipelinedcore ( logic FCvtIntE; logic CommittedF; + // Bit manipulation unit + logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU + logic BMUE; // is this a BMU instruction + // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -190,7 +194,7 @@ module wallypipelinedcore ( .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU @@ -200,7 +204,7 @@ module wallypipelinedcore ( .SrcAM, // to privilege and fpu .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage - .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), + .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .FCvtIntResW, .FCvtIntW, // hazards .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -357,4 +361,15 @@ module wallypipelinedcore ( assign SetFflagsM = 0; assign FpLoadStoreM = 0; end + + // bit manipulation unit + if (`B_SUPPORTED) begin:bmu + bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE); + end else begin // no B instructions supported + assign BMUResultE = 0; + assign BMUE = 0; + end + + + endmodule From b173112f86894575f538d743a5b5e30fbefe1daa Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 20 Jan 2023 14:27:13 -0800 Subject: [PATCH 022/294] Continued framework for B instructions --- pipelined/testbench/testbench.sv | 1 + pipelined/testbench/tests.vh | 8 ++++++++ tests/riscof/spike/spike_rv32imc_isa.yaml | 2 +- tests/riscof/spike/spike_rv64gc_isa.yaml | 2 +- 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 8c05c8a42..5456ce8b9 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -133,6 +133,7 @@ logic [3:0] dummy; "wally32periph": tests = wally32periph; "embench": tests = embench; "coremark": tests = coremark; + "arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; endcase end if (tests.size() == 0) begin diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index ec83f8c69..bbc82d9ad 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -944,6 +944,14 @@ string imperas32f[] = '{ "rv32i_m/Zifencei/src/Fencei.S" }; + string arch32ba[] = '{ + `RISCVARCHTEST, + // *** unclear why add.uw isn't in the list + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh1add-02.S", + "rv64i_m/B/src/sh1add-013.S" + }; + string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index 04a5da180..3438e17a0 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,6 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zifencei + ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index d3dad15c4..a8837ac76 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,6 +1,6 @@ hart_ids: [0] hart0: - ISA: RV64IMAFDCSUZicsr_Zifencei + ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] From c2f7f7324d01014fe252ce40778dbb98820b7dd6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 20 Jan 2023 15:23:38 -0800 Subject: [PATCH 023/294] test --- pipelined/regression/test | 1 + 1 file changed, 1 insertion(+) create mode 100644 pipelined/regression/test diff --git a/pipelined/regression/test b/pipelined/regression/test new file mode 100644 index 000000000..9daeafb98 --- /dev/null +++ b/pipelined/regression/test @@ -0,0 +1 @@ +test From 6ccb3a01471b0c775bd52ad972f5504bec0e7563 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 17:27:09 -0600 Subject: [PATCH 024/294] Test commit. --- fpga/constraints/test.file | 1 + 1 file changed, 1 insertion(+) create mode 100644 fpga/constraints/test.file diff --git a/fpga/constraints/test.file b/fpga/constraints/test.file new file mode 100644 index 000000000..ea8c7d25a --- /dev/null +++ b/fpga/constraints/test.file @@ -0,0 +1 @@ +test to make sure i can still merge my code into the new open hardware group. From 07308e2c141dc682c51bf0cc7080ec9873f38140 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 18:47:36 -0600 Subject: [PATCH 025/294] Removed mark_debug from all source code. --- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/ebu/buscachefsm.sv | 2 +- pipelined/src/ebu/busfsm.sv | 2 +- pipelined/src/ebu/ebu.sv | 24 +++++------ pipelined/src/hazard/hazard.sv | 20 ++++----- pipelined/src/ieu/datapath.sv | 2 +- pipelined/src/ieu/regfile.sv | 2 +- pipelined/src/ifu/ifu.sv | 44 +++++++++---------- pipelined/src/ifu/spill.sv | 2 +- pipelined/src/lsu/lsu.sv | 24 +++++------ pipelined/src/mmu/hptw.sv | 52 +++++++++++------------ pipelined/src/privileged/csr.sv | 8 ++-- pipelined/src/privileged/csrc.sv | 2 +- pipelined/src/privileged/csri.sv | 4 +- pipelined/src/privileged/csrm.sv | 12 +++--- pipelined/src/privileged/csrs.sv | 34 +++++++-------- pipelined/src/privileged/privileged.sv | 4 +- pipelined/src/privileged/trap.sv | 14 +++--- pipelined/src/uncore/clint_apb.sv | 4 +- pipelined/src/uncore/plic_apb.sv | 26 ++++++------ pipelined/src/uncore/uartPC16550D.sv | 52 +++++++++++------------ pipelined/src/uncore/uart_apb.sv | 6 +-- pipelined/src/wally/wallypipelinedcore.sv | 21 +++++---- 23 files changed, 181 insertions(+), 182 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index bc9982e59..d7af193b1 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -85,7 +85,7 @@ module cachefsm ( STATE_FLUSH, STATE_FLUSH_WRITEBACK} statetype; - (* mark_debug = "true" *) statetype CurrState, NextState; + statetype CurrState, NextState; assign AMO = CacheAtomic[1] & (&CacheRW); assign StoreAMO = AMO | CacheRW[0]; diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 97002cabc..c3be92fd8 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -67,7 +67,7 @@ module buscachefsm #( typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; - (* mark_debug = "true" *) busstatetype CurrState, NextState; + busstatetype CurrState, NextState; logic [AHBWLOGBWPL-1:0] NextBeatCount; logic FinalBeatCount; diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 830253227..019708a3d 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -50,7 +50,7 @@ module busfsm ( typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; - (* mark_debug = "true" *) busstatetype CurrState, NextState; + busstatetype CurrState, NextState; always_ff @(posedge HCLK) if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index bc162e08e..4a4cd5d5b 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -52,18 +52,18 @@ module ebu ( output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals - (* mark_debug = "true" *) output logic HCLK, HRESETn, - (* mark_debug = "true" *) input logic HREADY, // AHB peripheral ready - (* mark_debug = "true" *) input logic HRESP, // AHB peripheral response. 0: OK 1: Error - (* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration - (* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration - (* mark_debug = "true" *) output logic HWRITE, // AHB transaction direction after arbitration - (* mark_debug = "true" *) output logic [2:0] HSIZE, // AHB transaction size after arbitration - (* mark_debug = "true" *) output logic [2:0] HBURST, // AHB burst length after arbitration - (* mark_debug = "true" *) output logic [3:0] HPROT, // AHB protection. Wally does not use - (* mark_debug = "true" *) output logic [1:0] HTRANS, // AHB transaction request after arbitration - (* mark_debug = "true" *) output logic HMASTLOCK // AHB master lock. Wally does not use + output logic HCLK, HRESETn, + input logic HREADY, // AHB peripheral ready + input logic HRESP, // AHB peripheral response. 0: OK 1: Error + output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic HWRITE, // AHB transaction direction after arbitration + output logic [2:0] HSIZE, // AHB transaction size after arbitration + output logic [2:0] HBURST, // AHB burst length after arbitration + output logic [3:0] HPROT, // AHB protection. Wally does not use + output logic [1:0] HTRANS, // AHB transaction request after arbitration + output logic HMASTLOCK // AHB master lock. Wally does not use ); typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index ba9e7e21f..9dd3c0e4b 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -28,18 +28,18 @@ `include "wally-config.vh" -module hazard( +module hazard ( // Detect hazards -(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM, -(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, -(* mark_debug = "true" *) input logic LSUStallM, IFUStallF, -(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD, -(* mark_debug = "true" *) input logic DivBusyE, FDivBusyE, -(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM, -(* mark_debug = "true" *) input logic WFIStallM, + input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM, + input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, + input logic LSUStallM, IFUStallF, + input logic FCvtIntStallD, FPUStallD, + input logic DivBusyE, FDivBusyE, + input logic EcallFaultM, BreakpointFaultM, + input logic WFIStallM, // Stall & flush outputs -(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, -(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW + output logic StallF, StallD, StallE, StallM, StallW, + output logic FlushD, FlushE, FlushM, FlushW ); logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 84e3dc9cb..9ca880836 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -57,7 +57,7 @@ module datapath ( output logic [`XLEN-1:0] WriteDataM, // Write data in Memory stage // Writeback stage signals input logic StallW, FlushW, // Stall, flush Writeback stage -(* mark_debug = "true" *) input logic RegWriteW, IntDivW, // Write register file, integer divide instruction + input logic RegWriteW, IntDivW, // Write register file, integer divide instruction input logic SquashSCW, // Squash a store conditional when a conflict arose input logic [2:0] ResultSrcW, // Select source of result to write back to register file input logic [`XLEN-1:0] FCvtIntResW, // FPU convert fp to integer result diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 6ff506ef5..cc0439c08 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -38,7 +38,7 @@ module regfile ( localparam NUMREGS = `E_SUPPORTED ? 16 : 32; // only 16 registers in E mode -(* mark_debug = "true" *) logic [`XLEN-1:0] rf[NUMREGS-1:1]; + logic [`XLEN-1:0] rf[NUMREGS-1:1]; integer i; // Three ported register file diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 1101e6dd4..476f666ff 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -28,32 +28,32 @@ `include "wally-config.vh" module ifu ( - input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, -(* mark_debug = "true" *) output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation + input logic clk, reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, + output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation // Command from CPU - input logic InvalidateICacheM, // Clears all instruction cache valid bits - input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE) + input logic InvalidateICacheM, // Clears all instruction cache valid bits + input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE) // Bus interface -(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU -(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU -(* mark_debug = "true" *) input logic IFUHREADY, // Bus ready from IFU to EBU -(* mark_debug = "true" *) output logic IFUHWRITE, // Bus write operation from IFU to EBU -(* mark_debug = "true" *) output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU -(* mark_debug = "true" *) output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU -(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU + output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU + input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU + input logic IFUHREADY, // Bus ready from IFU to EBU + output logic IFUHWRITE, // Bus write operation from IFU to EBU + output logic [2:0] IFUHSIZE, // Bus operation size from IFU to EBU + output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU + output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU -(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Fetch stage instruction address - // Execute + output logic [`XLEN-1:0] PCF, // Fetch stage instruction address + // Execute output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address output logic [`XLEN-1:0] PCE, // Execution stage instruction address output logic BPPredWrongE, // Prediction is wrong - // Mem + // Mem output logic CommittedF, // I$ or bus memory operation started, delay interrupts - input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes. + input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes. output logic [`XLEN-1:0] PCNext2F, // Selected PC between branch prediction and next valid PC if CSRWriteFence output logic [31:0] InstrD, // The decoded instruction in Decode stage output logic [31:0] InstrM, // The decoded instruction in Memory stage @@ -91,7 +91,7 @@ module ifu ( localparam [31:0] nop = 32'h00000013; // instruction for NOP - (* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4 + logic [`XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4 logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed) logic [`XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed) logic [`XLEN-1:0] PCNextFSpill; // Next PCF after possible + 2 to handle spill @@ -100,14 +100,14 @@ module ifu ( logic [`XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F logic [`XLEN-1:0] PCD; // Decode stage instruction address logic [`XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence -(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // Physical address after address translation + logic [`PA_BITS-1:0] PCPF; // Physical address after address translation logic [`XLEN+1:0] PCFExt; // logic [31:0] IROMInstrF; // Instruction from the IROM logic [31:0] ICacheInstrF; // Instruction from the I$ logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus logic CompressedF; // The fetched instruction is compressed -(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill + logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage logic [1:0] IFURWF; // IFU alreays read IFURWF = 10 diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv index c1a1d8fac..9df9fca18 100644 --- a/pipelined/src/ifu/spill.sv +++ b/pipelined/src/ifu/spill.sv @@ -58,7 +58,7 @@ module spill #( logic SpillSaveF; logic [15:0] InstrFirstHalf; typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; - (* mark_debug = "true" *) statetype CurrState, NextState; + statetype CurrState, NextState; //////////////////////////////////////////////////////////////////////////////////////////////////// // PC logic diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index d84334a85..d59934f55 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -47,8 +47,8 @@ module lsu ( output logic DCacheAccess, // D cache memory access for performance counters // address and write data input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address - (* mark_debug = "true" *) output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address - (* mark_debug = "true" *) input logic [`XLEN-1:0] WriteDataM, // Write data from IEU + output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address + input logic [`XLEN-1:0] WriteDataM, // Write data from IEU output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU // cpu privilege input logic [1:0] PrivilegeModeW, // Current privilege mode @@ -66,15 +66,15 @@ module lsu ( output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault output logic StoreAmoAccessFaultM, // Store or AMO access fault // connect to ahb - (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU - (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU - (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU - (* mark_debug = "true" *) input logic LSUHREADY, // Bus ready from LSU to EBU - (* mark_debug = "true" *) output logic LSUHWRITE, // Bus write operation from LSU to EBU - (* mark_debug = "true" *) output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU - (* mark_debug = "true" *) output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU - (* mark_debug = "true" *) output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU - (* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU + output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU + input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU + output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU + input logic LSUHREADY, // Bus ready from LSU to EBU + output logic LSUHWRITE, // Bus write operation from LSU to EBU + output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU + output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU + output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU + output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU // page table walker input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege @@ -93,7 +93,7 @@ module lsu ( logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer logic [`PA_BITS-1:0] PAdrM; // Physical memory address - (* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address + logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 5e798eed4..9e8ac65ba 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -53,7 +53,7 @@ module hptw ( input logic DataDAPageFaultM, output logic [`XLEN-1:0] PTE, // page table entry to TLBs output logic [1:0] PageType, // page type to TLBs - (* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry + output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry output logic [1:0] PreLSURWM, output logic [`XLEN+1:0] IHAdrM, output logic [`XLEN-1:0] IHWriteDataM, @@ -67,36 +67,36 @@ module hptw ( output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM ); - typedef enum logic [3:0] {L0_ADR, L0_RD, + typedef enum logic [3:0] {L0_ADR, L0_RD, L1_ADR, L1_RD, L2_ADR, L2_RD, L3_ADR, L3_RD, LEAF, IDLE, UPDATE_PTE} statetype; - logic DTLBWalk; // register TLBs translation miss requests - logic [`PPN_BITS-1:0] BasePageTablePPN; - logic [`PPN_BITS-1:0] CurrentPPN; - logic Executable, Writable, Readable, Valid, PTE_U; - logic Misaligned, MegapageMisaligned; - logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE; - logic StartWalk; - logic TLBMiss; - logic PRegEn; - logic [1:0] NextPageType; - logic [`SVMODE_BITS-1:0] SvMode; - logic [`XLEN-1:0] TranslationVAdr; - logic [`XLEN-1:0] NextPTE; - logic UpdatePTE; - logic DAPageFault; - logic [`PA_BITS-1:0] HPTWReadAdr; - logic SelHPTWAdr; - logic [`XLEN+1:0] HPTWAdrExt; - logic ITLBMissOrDAFaultF; - logic DTLBMissOrDAFaultM; - logic [`PA_BITS-1:0] HPTWAdr; - logic [1:0] HPTWRW; - logic [2:0] HPTWSize; // 32 or 64 bit access - (* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState; + logic DTLBWalk; // register TLBs translation miss requests + logic [`PPN_BITS-1:0] BasePageTablePPN; + logic [`PPN_BITS-1:0] CurrentPPN; + logic Executable, Writable, Readable, Valid, PTE_U; + logic Misaligned, MegapageMisaligned; + logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE; + logic StartWalk; + logic TLBMiss; + logic PRegEn; + logic [1:0] NextPageType; + logic [`SVMODE_BITS-1:0] SvMode; + logic [`XLEN-1:0] TranslationVAdr; + logic [`XLEN-1:0] NextPTE; + logic UpdatePTE; + logic DAPageFault; + logic [`PA_BITS-1:0] HPTWReadAdr; + logic SelHPTWAdr; + logic [`XLEN+1:0] HPTWAdrExt; + logic ITLBMissOrDAFaultF; + logic DTLBMissOrDAFaultM; + logic [`PA_BITS-1:0] HPTWAdr; + logic [1:0] HPTWRW; + logic [2:0] HPTWSize; // 32 or 64 bit access + statetype WalkerState, NextWalkerState, InitialWalkerState; // map hptw access faults onto either the original LSU load/store fault or instruction access fault assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[1] & ~MemRWM[0]; diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 289e09aef..d6118e203 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -86,11 +86,11 @@ module csr #(parameter ); logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM; -(* mark_debug = "true" *) logic [`XLEN-1:0] CSRReadValM; -(* mark_debug = "true" *) logic [`XLEN-1:0] CSRSrcM; + logic [`XLEN-1:0] CSRReadValM; + logic [`XLEN-1:0] CSRSrcM; logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM; -(* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM; -(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW; + logic [`XLEN-1:0] CSRWriteValM; + logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW; logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW; logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 5d5bb5c96..de5743858 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -63,7 +63,7 @@ module csrc #(parameter ); logic [4:0] CounterNumM; - (* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0]; + logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0]; logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0]; logic LoadStallE, LoadStallM; logic [`COUNTERS-1:0] WriteHPMCOUNTERM; diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 1e68f15fd..0de65beed 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -39,9 +39,9 @@ module csri #(parameter input logic CSRMWriteM, CSRSWriteM, input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, - (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, + input logic MExtInt, SExtInt, MTimerInt, MSwInt, output logic [11:0] MIP_REGW, MIE_REGW, - (* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 + output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index b221fb006..cbeab5fdd 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -78,12 +78,12 @@ module csrm #(parameter input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, input logic [`XLEN-1:0] CSRWriteValM, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, + input logic [11:0] MIP_REGW, MIE_REGW, output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW, - (* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW, + output logic [`XLEN-1:0] MEPC_REGW, output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, -(* mark_debug = "true" *) output logic [`XLEN-1:0] MEDELEG_REGW, -(* mark_debug = "true" *) output logic [11:0] MIDELEG_REGW, + output logic [`XLEN-1:0] MEDELEG_REGW, + output logic [11:0] MIDELEG_REGW, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic WriteMSTATUSM, WriteMSTATUSHM, @@ -91,8 +91,8 @@ module csrm #(parameter ); logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; - (* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW; - (* mark_debug = "true" *) logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW; + logic [`XLEN-1:0] MSCRATCH_REGW; + logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index 438aca977..3dfb2cbea 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -42,21 +42,21 @@ module csrs #(parameter STVAL = 12'h143, SIP= 12'h144, SATP = 12'h180) ( - input logic clk, reset, - input logic InstrValidNotFlushedM, - input logic CSRSWriteM, STrapM, - input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, - input logic STATUS_TVM, - input logic [`XLEN-1:0] CSRWriteValM, - input logic [1:0] PrivilegeModeW, - (* mark_debug = "true" *) output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW, - (* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW, - output logic [31:0] SCOUNTEREN_REGW, - output logic [`XLEN-1:0] SATP_REGW, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, - output logic WriteSSTATUSM, - output logic IllegalCSRSAccessM + input logic clk, reset, + input logic InstrValidNotFlushedM, + input logic CSRSWriteM, STrapM, + input logic [11:0] CSRAdrM, + input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, + input logic STATUS_TVM, + input logic [`XLEN-1:0] CSRWriteValM, + input logic [1:0] PrivilegeModeW, + output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW, + output logic [`XLEN-1:0] SEPC_REGW, + output logic [31:0] SCOUNTEREN_REGW, + output logic [`XLEN-1:0] SATP_REGW, + input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, + output logic WriteSSTATUSM, + output logic IllegalCSRSAccessM ); // Constants @@ -66,8 +66,8 @@ module csrs #(parameter logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; - (* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; - (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; + logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; + logic [`XLEN-1:0] SCAUSE_REGW; // write enables assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 0e5076033..32ef2eb56 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -34,7 +34,7 @@ module privileged ( input logic StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, // CSR Reads and Writes, and values needed for traps -(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, // Read or write CSRs + input logic CSRReadM, CSRWriteM, // Read or write CSRs input logic [`XLEN-1:0] SrcAM, // GPR register to write input logic [31:0] InstrM, // Instruction input logic [`XLEN-1:0] IEUAdrM, // address from IEU @@ -104,7 +104,7 @@ module privileged ( logic DelegateM; // trap should be delegated logic wfiM; // wait for interrupt instruction logic IntPendingM; // interrupt is pending, even if not enabled. ends wfi - (* mark_debug = "true" *) logic InterruptM; // interrupt occuring + logic InterruptM; // interrupt occuring // track the current privilege level diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 4ca281567..d8ad28f56 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -30,14 +30,14 @@ module trap ( input logic reset, - (* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, IllegalInstrFaultM, - (* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM, - (* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, - (* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources - (* mark_debug = "true" *) input logic mretM, sretM, // return instructions + input logic InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, IllegalInstrFaultM, + input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM, + input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, + input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources + input logic mretM, sretM, // return instructions input logic wfiM, // wait for interrupt instruction input logic [1:0] PrivilegeModeW, // current privilege mode - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs + input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs input logic [`XLEN-1:0] MEDELEG_REGW, // exception delegation SR input logic STATUS_MIE, STATUS_SIE, // machine/supervisor interrupt enables input logic InstrValidM, // current instruction is valid, not flushed @@ -55,7 +55,7 @@ module trap ( logic ExceptionM; // exception is occurring logic Committed; // LSU or IFU has committed to a bus operation that can't be interrupted logic BothInstrAccessFaultM; // instruction or HPTW ITLB fill caused an Instruction Access Fault - (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; // interrupts are pending, valid, or enabled + logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; // interrupts are pending, valid, or enabled /////////////////////////////////////////// // Determine pending enabled interrupts diff --git a/pipelined/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv index 6784a2a3e..bbf072d44 100644 --- a/pipelined/src/uncore/clint_apb.sv +++ b/pipelined/src/uncore/clint_apb.sv @@ -39,14 +39,14 @@ module clint_apb ( input logic PENABLE, output logic [`XLEN-1:0] PRDATA, output logic PREADY, - (* mark_debug = "true" *) output logic [63:0] MTIME, + output logic [63:0] MTIME, output logic MTimerInt, MSwInt ); logic MSIP; logic [15:0] entry; logic memwrite; - (* mark_debug = "true" *) logic [63:0] MTIMECMP; + logic [63:0] MTIMECMP; integer i, j; assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index ad9e6f0c1..76b0ebbdc 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -53,27 +53,27 @@ module plic_apb ( output logic [`XLEN-1:0] PRDATA, output logic PREADY, input logic UARTIntr,GPIOIntr, - (* mark_debug = "true" *) output logic MExtInt, SExtInt + output logic MExtInt, SExtInt ); logic memwrite, memread; logic [23:0] entry; - (* mark_debug = "true" *) logic [31:0] Din, Dout; + logic [31:0] Din, Dout; // context-independent signals - (* mark_debug = "true" *) logic [`N:1] requests; - (* mark_debug = "true" *) logic [`N:1][2:0] intPriority; - (* mark_debug = "true" *) logic [`N:1] intInProgress, intPending, nextIntPending; + logic [`N:1] requests; + logic [`N:1][2:0] intPriority; + logic [`N:1] intInProgress, intPending, nextIntPending; // context-dependent signals - (* mark_debug = "true" *) logic [`C-1:0][2:0] intThreshold; - (* mark_debug = "true" *) logic [`C-1:0][`N:1] intEn; - (* mark_debug = "true" *) logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources - (* mark_debug = "true" *) logic [`C-1:0][7:1][`N:1] irqMatrix; - (* mark_debug = "true" *) logic [`C-1:0][7:1] priorities_with_irqs; - (* mark_debug = "true" *) logic [`C-1:0][7:1] max_priority_with_irqs; - (* mark_debug = "true" *) logic [`C-1:0][`N:1] irqs_at_max_priority; - (* mark_debug = "true" *) logic [`C-1:0][7:1] threshMask; + logic [`C-1:0][2:0] intThreshold; + logic [`C-1:0][`N:1] intEn; + logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources + logic [`C-1:0][7:1][`N:1] irqMatrix; + logic [`C-1:0][7:1] priorities_with_irqs; + logic [`C-1:0][7:1] max_priority_with_irqs; + logic [`C-1:0][`N:1] irqs_at_max_priority; + logic [`C-1:0][7:1] threshMask; // ======= // AHB I/O diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 3666a4493..a4aed45bf 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -56,10 +56,10 @@ module uartPC16550D( typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; // Registers - (* mark_debug = "true" *) logic [10:0] RBR; - (* mark_debug = "true" *) logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM; - (* mark_debug = "true" *) logic [3:0] IER, MSR; - (* mark_debug = "true" *) logic [4:0] MCR; + logic [10:0] RBR; + logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM; + logic [3:0] IER, MSR; + logic [4:0] MCR; // Syncrhonized and delayed UART signals logic SINd, DSRbd, DCDbd, CTSbd, RIbd; @@ -72,50 +72,50 @@ module uartPC16550D( logic DLAB; // Divisor Latch Access Bit (LCR bit 7) // Baud and rx/tx timing - (* mark_debug = "true" *) logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period + logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period logic [16+`UART_PRESCALE-1:0] baudcount; logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16 logic [3:0] rxbitsreceived, txbitssent; - (* mark_debug = "true" *) statetype rxstate, txstate; + statetype rxstate, txstate; // shift registrs and FIFOs logic [9:0] rxshiftreg; - (* mark_debug = "true" *) logic [10:0] rxfifo[15:0]; - (* mark_debug = "true" *) logic [7:0] txfifo[15:0]; + logic [10:0] rxfifo[15:0]; + logic [7:0] txfifo[15:0]; logic [4:0] rxfifotailunwrapped; -(* mark_debug = "true" *) logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; -(* mark_debug = "true" *) logic [3:0] rxfifoentries, txfifoentries; + logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; + logic [3:0] rxfifoentries, txfifoentries; logic [3:0] rxbitsexpected, txbitsexpected; // receive data - (* mark_debug = "true" *) logic [10:0] RXBR; - (* mark_debug = "true" *) logic [9:0] rxtimeoutcnt; + logic [10:0] RXBR; + logic [9:0] rxtimeoutcnt; logic rxcentered; logic rxparity, rxparitybit, rxstopbit; - (* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr; -(* mark_debug = "true" *) logic rxdataready; -(* mark_debug = "true" *) logic rxfifoempty, rxfifotriggered, rxfifotimeout; + logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr; + logic rxdataready; + logic rxfifoempty, rxfifotriggered, rxfifotimeout; logic rxfifodmaready; logic [8:0] rxdata9; - (* mark_debug = "true" *) logic [7:0] rxdata; - (* mark_debug = "true" *) logic [15:0] RXerrbit, rxfullbit; - (* mark_debug = "true" *) logic [31:0] rxfullbitunwrapped; + logic [7:0] rxdata; + logic [15:0] RXerrbit, rxfullbit; + logic [31:0] rxfullbitunwrapped; // transmit data logic [7:0] TXHR, nexttxdata; - (* mark_debug = "true" *) logic [11:0] txdata, txsr; - (* mark_debug = "true" *) logic txnextbit, txhrfull, txsrfull; + logic [11:0] txdata, txsr; + logic txnextbit, txhrfull, txsrfull; logic txparity; - (* mark_debug = "true" *) logic txfifoempty, txfifofull, txfifodmaready; + logic txfifoempty, txfifofull, txfifodmaready; // control signals -(* mark_debug = "true" *) logic fifoenabled, fifodmamodesel, evenparitysel; + logic fifoenabled, fifodmamodesel, evenparitysel; // interrupts -(* mark_debug = "true" *) logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP; -(* mark_debug = "true" *) logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP; -(* mark_debug = "true" *) logic rxdataavailintr, modemstatusintr, intrpending; -(* mark_debug = "true" *) logic [2:0] intrID; + logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP; + logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP; + logic rxdataavailintr, modemstatusintr, intrpending; + logic [2:0] intrID; logic baudpulseComb; logic HeadPointerLastMove; diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv index 916f61687..5c0ec1bd5 100644 --- a/pipelined/src/uncore/uart_apb.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -40,9 +40,9 @@ module uart_apb ( input logic PENABLE, output logic [`XLEN-1:0] PRDATA, output logic PREADY, - (* mark_debug = "true" *) input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface - (* mark_debug = "true" *) output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface - (* mark_debug = "true" *) output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU + input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface + output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface + output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU // UART interface signals logic [2:0] entry; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 2e6b63035..3e1bd5846 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -52,23 +52,23 @@ module wallypipelinedcore ( logic StallF, StallD, StallE, StallM, StallW; logic FlushD, FlushE, FlushM, FlushW; logic RetM; - (* mark_debug = "true" *) logic TrapM; + logic TrapM; // signals that must connect through DP logic IntDivE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; logic [1:0] AtomicM; logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; -(* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM; + logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; logic [31:0] InstrD; - (* mark_debug = "true" *) logic [31:0] InstrM; + logic [31:0] InstrM; logic [`XLEN-1:0] PCF, PCE, PCLinkE; - (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; - (* mark_debug = "true" *) logic [1:0] MemRWM; - (* mark_debug = "true" *) logic InstrValidM; + logic [`XLEN-1:0] PCM; + logic [`XLEN-1:0] CSRReadValW, MDUResultW; + logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; + logic [1:0] MemRWM; + logic InstrValidM; logic InstrMisalignedFaultM; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; @@ -110,7 +110,6 @@ module wallypipelinedcore ( logic sfencevmaM, WFIStallM; logic SelHPTW; - // PMA checker signals var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; @@ -122,8 +121,8 @@ module wallypipelinedcore ( // cpu lsu interface logic [2:0] Funct3M; logic [`XLEN-1:0] IEUAdrE; - (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM; - (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; + logic [`XLEN-1:0] WriteDataM; + logic [`XLEN-1:0] IEUAdrM; logic [`LLEN-1:0] ReadDataW; logic CommittedM; From 25bd2e46708a6976238eab4f8422adec6f49f97f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 19:43:18 -0600 Subject: [PATCH 026/294] Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory. --- fpga/constraints/marked_debug.txt | 132 +++++++++++++++++++++++++ fpga/generator/Makefile | 6 +- fpga/generator/insert_debug_comment.sh | 27 +++++ 3 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 fpga/constraints/marked_debug.txt create mode 100755 fpga/generator/insert_debug_comment.sh diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt new file mode 100644 index 000000000..97ac1ead3 --- /dev/null +++ b/fpga/constraints/marked_debug.txt @@ -0,0 +1,132 @@ +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic WriteDataM +lsu/lsu.sv: logic LSUHADDR +lsu/lsu.sv: logic HRDATA +lsu/lsu.sv: logic LSUHWDATA +lsu/lsu.sv: logic LSUHREADY +lsu/lsu.sv: logic LSUHWRITE +lsu/lsu.sv: logic LSUHSIZE +lsu/lsu.sv: logic LSUHBURST +lsu/lsu.sv: logic LSUHTRANS +lsu/lsu.sv: logic LSUHWSTRB +lsu/lsu.sv: logic IHAdrM +ieu/regfile.sv: logic rf +ieu/datapath.sv: logic RegWriteW +hazard/hazard.sv: logic BPPredWrongE +hazard/hazard.sv: logic LoadStallD +hazard/hazard.sv: logic LSUStallM +hazard/hazard.sv: logic FCvtIntStallD +hazard/hazard.sv: logic DivBusyE +hazard/hazard.sv: logic EcallFaultM +hazard/hazard.sv: logic WFIStallM +hazard/hazard.sv: logic StallF +hazard/hazard.sv: logic FlushD +cache/cachefsm.sv: statetype CurrState +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic SrcAM +wally/wallypipelinedcore.sv: logic InstrM +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic MemRWM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic WriteDataM +wally/wallypipelinedcore.sv: logic IEUAdrM +ifu/spill.sv: statetype CurrState +ifu/ifu.sv: logic IFUStallF +ifu/ifu.sv: logic IFUHADDR +ifu/ifu.sv: logic HRDATA +ifu/ifu.sv: logic IFUHREADY +ifu/ifu.sv: logic IFUHWRITE +ifu/ifu.sv: logic IFUHSIZE +ifu/ifu.sv: logic IFUHBURST +ifu/ifu.sv: logic IFUHTRANS +ifu/ifu.sv: logic PCF +ifu/ifu.sv: logic PCNextF +ifu/ifu.sv: logic PCPF +ifu/ifu.sv: logic PostSpillInstrRawF +mmu/hptw.sv: logic ITLBWriteF +mmu/hptw.sv: statetype WalkerState +privileged/csrs.sv: logic CSRSReadValM +privileged/csrs.sv: logic SEPC_REGW +privileged/csrs.sv: logic MIP_REGW +privileged/csrs.sv: logic SSCRATCH_REGW +privileged/csrs.sv: logic SCAUSE_REGW +privileged/csr.sv: logic CSRReadValM +privileged/csr.sv: logic CSRSrcM +privileged/csr.sv: logic CSRWriteValM +privileged/csr.sv: logic MSTATUS_REGW +privileged/trap.sv: logic InstrMisalignedFaultM +privileged/trap.sv: logic BreakpointFaultM +privileged/trap.sv: logic LoadAccessFaultM +privileged/trap.sv: logic LoadPageFaultM +privileged/trap.sv: logic mretM +privileged/trap.sv: logic MIP_REGW +privileged/trap.sv: logic PendingIntsM +privileged/privileged.sv: logic CSRReadM +privileged/privileged.sv: logic InterruptM +privileged/csrc.sv: logic HPMCOUNTER_REGW +privileged/csri.sv: logic MExtInt +privileged/csri.sv: logic MIP_REGW_writeabl +privileged/csrm.sv: logic MIP_REGW +privileged/csrm.sv: logic MEPC_REGW +privileged/csrm.sv: logic MEDELEG_REGW +privileged/csrm.sv: logic MIDELEG_REGW +privileged/csrm.sv: logic MSCRATCH_REGW +privileged/csrm.sv: logic MCAUSE_REGW +uncore/uart_apb.sv: logic SIN +uncore/uart_apb.sv: logic SOUT +uncore/uart_apb.sv: logic OUT1b +uncore/uartPC16550D.sv: logic RBR +uncore/uartPC16550D.sv: logic FCR +uncore/uartPC16550D.sv: logic IER +uncore/uartPC16550D.sv: logic MCR +uncore/uartPC16550D.sv: logic baudpulse +uncore/uartPC16550D.sv: statetype rxstate +uncore/uartPC16550D.sv: logic rxfifo +uncore/uartPC16550D.sv: logic txfifo +uncore/uartPC16550D.sv: logic rxfifohead +uncore/uartPC16550D.sv: logic rxfifoentries +uncore/uartPC16550D.sv: logic RXBR +uncore/uartPC16550D.sv: logic rxtimeoutcnt +uncore/uartPC16550D.sv: logic rxparityerr +uncore/uartPC16550D.sv: logic rxdataready +uncore/uartPC16550D.sv: logic rxfifoempty +uncore/uartPC16550D.sv: logic rxdata +uncore/uartPC16550D.sv: logic RXerrbit +uncore/uartPC16550D.sv: logic rxfullbitunwrapped +uncore/uartPC16550D.sv: logic txdata +uncore/uartPC16550D.sv: logic txnextbit +uncore/uartPC16550D.sv: logic txfifoempty +uncore/uartPC16550D.sv: logic fifoenabled +uncore/uartPC16550D.sv: logic RXerr +uncore/uartPC16550D.sv: logic THRE +uncore/uartPC16550D.sv: logic rxdataavailintr +uncore/uartPC16550D.sv: logic intrID +uncore/plic_apb.sv: logic MExtInt +uncore/plic_apb.sv: logic Din +uncore/plic_apb.sv: logic requests +uncore/plic_apb.sv: logic intPriority +uncore/plic_apb.sv: logic intInProgress +uncore/plic_apb.sv: logic intThreshold +uncore/plic_apb.sv: logic intEn +uncore/plic_apb.sv: logic intClaim +uncore/plic_apb.sv: logic irqMatrix +uncore/plic_apb.sv: logic priorities_with_irqs +uncore/plic_apb.sv: logic max_priority_with_irqs +uncore/plic_apb.sv: logic irqs_at_max_priority +uncore/plic_apb.sv: logic threshMask +uncore/clint_apb.sv: logic MTIME +uncore/clint_apb.sv: logic MTIMECMP +ebu/ebu.sv: logic HCLK +ebu/ebu.sv: logic HREADY +ebu/ebu.sv: logic HRESP +ebu/ebu.sv: logic HADDR +ebu/ebu.sv: logic HWDATA +ebu/ebu.sv: logic HWSTRB +ebu/ebu.sv: logic HWRITE +ebu/ebu.sv: logic HSIZE +ebu/ebu.sv: logic HBURST +ebu/ebu.sv: logic HPROT +ebu/ebu.sv: logic HTRANS +ebu/ebu.sv: logic HMASTLOC +ebu/buscachefsm.sv: busstatetype CurrState +ebu/busfsm.sv: busstatetype CurrState diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index b61c51ed5..ab55605d0 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -13,7 +13,7 @@ export board := vcu108 all: FPGA -FPGA: IP SDC +FPGA: PreProcessFiles IP SDC vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log IP: $(dst)/xlnx_proc_sys_reset.log \ @@ -25,6 +25,10 @@ SDC: cp $(sdc_src) ../src/ tar xzf ../src/sdc.tar.gz -C ../src +PreProcessFiles: + cp -r ../../pipelined/src/ ../src/pipelined + ./insert_debug_comment.sh + $(dst)/%.log: %.tcl mkdir -p IP cd IP;\ diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh new file mode 100755 index 000000000..96d379c90 --- /dev/null +++ b/fpga/generator/insert_debug_comment.sh @@ -0,0 +1,27 @@ +#!/bin/bash + + +fileC="../src/pipelined/ebu/busfsm.sv" +signal="CurrState" +type="busstatetype" +#find ../src/pipelined/ -wholename $fileC | xargs sed "s/\(.*\(logic|statetype|busstatetype\).*$signal\)/(\* mark_debug = \"true\" \*)\1/g" | grep -i $signal + +#fileC="../src/pipelined/lsu/lsu.sv" +#signal="IEUAdrM" +#type="logic" +echo "file = $fileC" +echo "signal = $signal" + +echo $signal +find ../src/pipelined/ -wholename $fileC | xargs sed "s/\(.*$type.*$signal\)/(\* mark_debug = \"true\" \*)\1/g" | grep -i $signal +#exit 0 +while read line; do + readarray -d ":" -t StrArray <<< "$line" + file="../src/pipelined/${StrArray[0]}" + #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` + signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` + readarray -d " " -t SigArray <<< $signal + sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'` + sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'` + find ../src/pipelined/ -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" +done < ../constraints/marked_debug.txt From 9c83b2dff546aa5bec023fe8fa9ff738a4d898dc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 19:45:17 -0600 Subject: [PATCH 027/294] Updated ignore to exclude copied files. --- .gitignore | 1 + fpga/generator/Makefile | 2 +- fpga/generator/insert_debug_comment.sh | 20 +++----------------- 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/.gitignore b/.gitignore index 587fc73a5..c4c71a623 100644 --- a/.gitignore +++ b/.gitignore @@ -128,3 +128,4 @@ tests/custom/crt0/*.a /pipelined/regression/sd_model.log fpga/src/sdc/* fpga/src/sdc.tar.gz +fpga/src/CopiedFiles_do_not_add_to_repo/* diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index ab55605d0..82c5a2ca1 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -26,7 +26,7 @@ SDC: tar xzf ../src/sdc.tar.gz -C ../src PreProcessFiles: - cp -r ../../pipelined/src/ ../src/pipelined + cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/ ./insert_debug_comment.sh $(dst)/%.log: %.tcl diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index 96d379c90..0d7eceff4 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -1,27 +1,13 @@ #!/bin/bash - -fileC="../src/pipelined/ebu/busfsm.sv" -signal="CurrState" -type="busstatetype" -#find ../src/pipelined/ -wholename $fileC | xargs sed "s/\(.*\(logic|statetype|busstatetype\).*$signal\)/(\* mark_debug = \"true\" \*)\1/g" | grep -i $signal - -#fileC="../src/pipelined/lsu/lsu.sv" -#signal="IEUAdrM" -#type="logic" -echo "file = $fileC" -echo "signal = $signal" - -echo $signal -find ../src/pipelined/ -wholename $fileC | xargs sed "s/\(.*$type.*$signal\)/(\* mark_debug = \"true\" \*)\1/g" | grep -i $signal -#exit 0 +copiedDir="../src/CopiedFiles_do_not_add_to_repo" while read line; do readarray -d ":" -t StrArray <<< "$line" - file="../src/pipelined/${StrArray[0]}" + file="${copiedDir}/${StrArray[0]}" #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` readarray -d " " -t SigArray <<< $signal sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'` sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'` - find ../src/pipelined/ -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" + find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" done < ../constraints/marked_debug.txt From 4ccea17648cb7ebf4310f81f5d8271f1f0d3bcac Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 19:50:33 -0600 Subject: [PATCH 028/294] Added license and comments to new script. --- fpga/generator/insert_debug_comment.sh | 34 +++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index 0d7eceff4..5e85d17be 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -1,13 +1,39 @@ #!/bin/bash +########################################### +## insert_debug_comment.sh +## +## Written: Ross Thompson ross1728@gmail.com +## Created: 20 January 2023 +## Modified: 20 January 2023 +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org#licenses#SHL-2.1# +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ -copiedDir="../src/CopiedFiles_do_not_add_to_repo" +# This script copies wally's pipelined#src to fpga#src#CopiedFiles_do_not_add_to_repo +# Then it processes them to add mark_debug on signals needed by the FPGA's ILA. +copiedDir="..#src#CopiedFiles_do_not_add_to_repo" while read line; do readarray -d ":" -t StrArray <<< "$line" - file="${copiedDir}/${StrArray[0]}" + file="${copiedDir}#${StrArray[0]}" #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` readarray -d " " -t SigArray <<< $signal sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'` sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'` - find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" -done < ../constraints/marked_debug.txt + find $copiedDir -wholename $file | xargs sed -i "s#\(.*${sigType}.*${sigName}\)#(\* mark_debug = \"true\" \*)\1#g" +done < ..#constraints#marked_debug.txt From 0ed9811e31a6264dac5c5e40bdbbbee4cb1efdca Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 20:16:33 -0600 Subject: [PATCH 029/294] Updated fpga constraints. --- fpga/constraints/debug2.xdc | 2 +- fpga/generator/Makefile | 1 + fpga/generator/insert_debug_comment.sh | 9 ++++----- fpga/generator/wally.tcl | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 69d295f85..0acdcf6e4 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -87,7 +87,7 @@ connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv. create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[63]} ]] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]] create_debug_port u_ila_0 probe diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 82c5a2ca1..3ab35b34b 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -26,6 +26,7 @@ SDC: tar xzf ../src/sdc.tar.gz -C ../src PreProcessFiles: + rm -rf ../src/CopiedFiles_do_not_add_to_repo/ cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/ ./insert_debug_comment.sh diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index 5e85d17be..66c232e16 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -26,14 +26,13 @@ # This script copies wally's pipelined#src to fpga#src#CopiedFiles_do_not_add_to_repo # Then it processes them to add mark_debug on signals needed by the FPGA's ILA. -copiedDir="..#src#CopiedFiles_do_not_add_to_repo" +copiedDir="../src/CopiedFiles_do_not_add_to_repo" while read line; do readarray -d ":" -t StrArray <<< "$line" - file="${copiedDir}#${StrArray[0]}" - #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` + file="${copiedDir}/${StrArray[0]}" signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` readarray -d " " -t SigArray <<< $signal sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'` sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'` - find $copiedDir -wholename $file | xargs sed -i "s#\(.*${sigType}.*${sigName}\)#(\* mark_debug = \"true\" \*)\1#g" -done < ..#constraints#marked_debug.txt + find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" +done < ../constraints/marked_debug.txt diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index b2597f60d..45444d577 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -15,7 +15,7 @@ read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/x read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci -read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] +read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] read_verilog {../src/fpgaTop.v} read_verilog -sv [glob -type f ../src/sdc/*.sv] From e28ea2d6301e15314bbec3b6c97496856537069d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 20:18:04 -0600 Subject: [PATCH 030/294] Fixed fpga constraints. --- fpga/constraints/debug2.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 0acdcf6e4..bf174368f 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -356,7 +356,7 @@ connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/St create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe69] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause08_in]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe70] From 61efb22db11362009105f7dffb9871a37cb02616 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 20:28:21 -0600 Subject: [PATCH 031/294] More fixes to fpga ila debugger. --- fpga/constraints/debug2.xdc | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index bf174368f..f101c7042 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -434,9 +434,10 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83] connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe84] +set_property port_width 53 [get_debug_ports u_ila_0/probe84] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84] -connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWDATA[0]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[1]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[2]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[3]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[4]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[5]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[6]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[7]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[8]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[9]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[10]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[11]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[12]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[13]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[14]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[15]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[16]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[17]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[18]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[19]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[20]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[21]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[22]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[23]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[24]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[25]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[26]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[27]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[28]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[29]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[30]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[31]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[32]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[33]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[34]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[35]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[36]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[37]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[38]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[39]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[40]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[41]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[42]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[43]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[44]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[45]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[46]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[47]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[48]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[49]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[50]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[51]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[52]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[53]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[54]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[55]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[56]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[57]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[58]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[59]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[60]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[61]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[62]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[63]}]] +connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]] + create_debug_port u_ila_0 probe @@ -531,7 +532,7 @@ connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe102] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102] -connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/SpillSupport.spillsupport/CurrState[0] ]] +connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]] create_debug_port u_ila_0 probe @@ -1143,8 +1144,3 @@ set_property port_width 53 [get_debug_ports u_ila_0/probe223] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223] connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]] -create_debug_port u_ila_0 probe -set_property port_width 53 [get_debug_ports u_ila_0/probe224] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe224] -connect_debug_port u_ila_0/probe224 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]] - From 2fc47bab9ca9d0f8bbcf41ab5a030aafa5f426e9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 20:48:19 -0600 Subject: [PATCH 032/294] More fixes for the debug2.xdc constraints. --- fpga/constraints/debug2.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index f101c7042..8b0b7c448 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -675,7 +675,7 @@ connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/ create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe130] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130] -connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[63]} ]] +connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe131] From 4a73f173bba098862d84398de7b282fb6ebd04c4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 14:03:30 -0600 Subject: [PATCH 033/294] Created a tool chain install script for ubuntu 22.04. --- bin/wally-tool-chain-install.sh | 81 +++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 bin/wally-tool-chain-install.sh diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh new file mode 100644 index 000000000..b66e01da8 --- /dev/null +++ b/bin/wally-tool-chain-install.sh @@ -0,0 +1,81 @@ +export RISCV=/opt/riscv +export PATH=$PATH:$RISCV/bin + +NUM_THREADS=4 + +# UPDATE / UPGRADE +apt update + +# INSTALL +apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev + +# gcc cross-compiler +git clone https://github.com/riscv/riscv-gnu-toolchain && \ + cd riscv-gnu-toolchain && \ + ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \ + make -j $(NUM_THREADS) && \ + make install + +# elf2hex +export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +git clone https://github.com/sifive/elf2hex.git && \ + cd elf2hex && \ + autoreconf -i && \ + ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \ + make && \ + make install + +# Update Python3.6 for QEMU +apt-get -y update +apt-get -y install python3-pip +apt-get -y install pkg-config +apt-get -y install libglib2.0-dev + +# QEMU +git clone --recurse-submodules https://github.com/qemu/qemu && \ + cd qemu && \ + ./configure --target-list=riscv64-softmmu --prefix=$RISCV && \ + make -j $(NUM_THREADS) && \ + make install + +# Spike +git clone https://github.com/riscv-software-src/riscv-isa-sim && \ + mkdir riscv-isa-sim/build && \ + cd riscv-isa-sim/build && \ + ../configure --prefix=$RISCV --enable-commitlog && \ + make -j $(NUM_THREADS) && \ + make install && \ + cd ../arch_test_target/spike/device && \ + sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \ + sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include + +# SAIL +apt-get install -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev && \ + git clone https://github.com/Z3Prover/z3.git && \ + cd z3 && \ + python scripts/mk_make.py && \ + cd build && \ + make -j $(NUM_THREADS) && \ + make install && \ + cd ../.. && \ + pip3 install chardet==3.0.4 && \ + pip3 install urllib3==1.22 && \ + opam init -y --disable-sandboxing && \ + opam switch create ocaml-base-compiler.4.06.1 && \ + opam install sail -y + +eval $(opam config env) && \ + git clone https://github.com/riscv/sail-riscv.git && \ + cd sail-riscv && \ + make -j $(NUM_THREADS) && \ + ARCH=RV32 make -j $(NUM_THREADS) && \ + ARCH=RV64 make -j $(NUM_THREADS) && \ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 && \ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 + +pip3 install testresources && \ + pip3 install riscof --ignore-installed PyYAML + +# Verilator +apt install verilator + From 8c70705ecf55e7e137ff895dba160faef4860aaf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 17:24:21 -0600 Subject: [PATCH 034/294] Updates to tool install script --- bin/wally-tool-chain-install.sh | 100 ++++++++++++++++---------------- 1 file changed, 50 insertions(+), 50 deletions(-) mode change 100644 => 100755 bin/wally-tool-chain-install.sh diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh old mode 100644 new mode 100755 index b66e01da8..fa3685939 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -7,23 +7,23 @@ NUM_THREADS=4 apt update # INSTALL -apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev +apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev # gcc cross-compiler -git clone https://github.com/riscv/riscv-gnu-toolchain && \ - cd riscv-gnu-toolchain && \ - ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \ - make -j $(NUM_THREADS) && \ - make install +git clone https://github.com/riscv/riscv-gnu-toolchain +cd riscv-gnu-toolchain +./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +make -j $(NUM_THREADS) +make install # elf2hex export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH -git clone https://github.com/sifive/elf2hex.git && \ - cd elf2hex && \ - autoreconf -i && \ - ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \ - make && \ - make install +git clone https://github.com/sifive/elf2hex.git +cd elf2hex +autoreconf -i +./configure --target=riscv64-unknown-elf --prefix=$RISCV +make +make install # Update Python3.6 for QEMU apt-get -y update @@ -32,50 +32,50 @@ apt-get -y install pkg-config apt-get -y install libglib2.0-dev # QEMU -git clone --recurse-submodules https://github.com/qemu/qemu && \ - cd qemu && \ - ./configure --target-list=riscv64-softmmu --prefix=$RISCV && \ - make -j $(NUM_THREADS) && \ - make install +git clone --recurse-submodules https://github.com/qemu/qemu +cd qemu +./configure --target-list=riscv64-softmmu --prefix=$RISCV +make -j $(NUM_THREADS) +make install # Spike -git clone https://github.com/riscv-software-src/riscv-isa-sim && \ - mkdir riscv-isa-sim/build && \ - cd riscv-isa-sim/build && \ - ../configure --prefix=$RISCV --enable-commitlog && \ - make -j $(NUM_THREADS) && \ - make install && \ - cd ../arch_test_target/spike/device && \ - sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \ - sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include +git clone https://github.com/riscv-software-src/riscv-isa-sim +mkdir riscv-isa-sim/build +cd riscv-isa-sim/build +../configure --prefix=$RISCV --enable-commitlog +make -j $(NUM_THREADS) +make install +cd ../arch_test_target/spike/device +sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include +sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # SAIL -apt-get install -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev && \ - git clone https://github.com/Z3Prover/z3.git && \ - cd z3 && \ - python scripts/mk_make.py && \ - cd build && \ - make -j $(NUM_THREADS) && \ - make install && \ - cd ../.. && \ - pip3 install chardet==3.0.4 && \ - pip3 install urllib3==1.22 && \ - opam init -y --disable-sandboxing && \ - opam switch create ocaml-base-compiler.4.06.1 && \ - opam install sail -y +apt-get install -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev +git clone https://github.com/Z3Prover/z3.git +cd z3 +python scripts/mk_make.py +cd build +make -j $(NUM_THREADS) +make install +cd ../.. +pip3 install chardet==3.0.4 +pip3 install urllib3==1.22 +opam init -y --disable-sandboxing +opam switch create ocaml-base-compiler.4.06.1 +opam install sail -y -eval $(opam config env) && \ - git clone https://github.com/riscv/sail-riscv.git && \ - cd sail-riscv && \ - make -j $(NUM_THREADS) && \ - ARCH=RV32 make -j $(NUM_THREADS) && \ - ARCH=RV64 make -j $(NUM_THREADS) && \ - ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 && \ - ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 +eval $(opam config env) +git clone https://github.com/riscv/sail-riscv.git +cd sail-riscv +make -j $(NUM_THREADS) +ARCH=RV32 make -j $(NUM_THREADS) +ARCH=RV64 make -j $(NUM_THREADS) +ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 +ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 -pip3 install testresources && \ - pip3 install riscof --ignore-installed PyYAML +pip3 install testresources +pip3 install riscof --ignore-installed PyYAML # Verilator -apt install verilator +apt install -y verilator From b522bcc081775f67d65877c7e6f03a436c2ee556 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 17:32:44 -0600 Subject: [PATCH 035/294] fixes to install script. --- bin/wally-tool-chain-install.sh | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fa3685939..c2be7cf0c 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -3,6 +3,8 @@ export PATH=$PATH:$RISCV/bin NUM_THREADS=4 +sudo mkdir -p $RISCV + # UPDATE / UPGRADE apt update @@ -10,6 +12,7 @@ apt update apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev # gcc cross-compiler +cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" @@ -17,6 +20,7 @@ make -j $(NUM_THREADS) make install # elf2hex +cd $RISCV export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH git clone https://github.com/sifive/elf2hex.git cd elf2hex @@ -32,6 +36,7 @@ apt-get -y install pkg-config apt-get -y install libglib2.0-dev # QEMU +cd $RISCV git clone --recurse-submodules https://github.com/qemu/qemu cd qemu ./configure --target-list=riscv64-softmmu --prefix=$RISCV @@ -39,6 +44,7 @@ make -j $(NUM_THREADS) make install # Spike +cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir riscv-isa-sim/build cd riscv-isa-sim/build @@ -50,6 +56,7 @@ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # SAIL +cd $RISCV apt-get install -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev git clone https://github.com/Z3Prover/z3.git cd z3 From 8d6a58f2cfa3b806b78abfd3794f4bcf40c52d9a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 18:00:14 -0600 Subject: [PATCH 036/294] fixes to installer script --- bin/wally-tool-chain-install.sh | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index c2be7cf0c..2f6f1691c 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -1,15 +1,19 @@ export RISCV=/opt/riscv export PATH=$PATH:$RISCV/bin -NUM_THREADS=4 +set -e # break on error + +NUM_THREADS=1 sudo mkdir -p $RISCV # UPDATE / UPGRADE -apt update +#apt update # INSTALL -apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev +#apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev + +ln -sf /usr/bin/python3 /usr/bin/python # this is unforunate. gcc needs python but it looks specifically for python and not python3 or python2. # gcc cross-compiler cd $RISCV From 3667222831b43aeb23fe6600238b04f6e6715f09 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 20:52:58 -0600 Subject: [PATCH 037/294] Working toolchain install script for ubuntu. --- bin/wally-tool-chain-install.sh | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2f6f1691c..4c26bbf51 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -8,10 +8,10 @@ NUM_THREADS=1 sudo mkdir -p $RISCV # UPDATE / UPGRADE -#apt update +apt update # INSTALL -#apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev +apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev ln -sf /usr/bin/python3 /usr/bin/python # this is unforunate. gcc needs python but it looks specifically for python and not python3 or python2. @@ -20,7 +20,7 @@ cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -make -j $(NUM_THREADS) +make make install # elf2hex @@ -44,16 +44,16 @@ cd $RISCV git clone --recurse-submodules https://github.com/qemu/qemu cd qemu ./configure --target-list=riscv64-softmmu --prefix=$RISCV -make -j $(NUM_THREADS) +make make install # Spike cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim -mkdir riscv-isa-sim/build +mkdir -p riscv-isa-sim/build cd riscv-isa-sim/build ../configure --prefix=$RISCV --enable-commitlog -make -j $(NUM_THREADS) +make make install cd ../arch_test_target/spike/device sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include @@ -66,7 +66,7 @@ git clone https://github.com/Z3Prover/z3.git cd z3 python scripts/mk_make.py cd build -make -j $(NUM_THREADS) +make make install cd ../.. pip3 install chardet==3.0.4 @@ -78,9 +78,9 @@ opam install sail -y eval $(opam config env) git clone https://github.com/riscv/sail-riscv.git cd sail-riscv -make -j $(NUM_THREADS) -ARCH=RV32 make -j $(NUM_THREADS) -ARCH=RV64 make -j $(NUM_THREADS) +make +ARCH=RV32 make +ARCH=RV64 make ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 From b73bf728a5548ca45ae73ec4f5e22fc1f70bca07 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 21:23:23 -0600 Subject: [PATCH 038/294] More improvements to the tool install script. --- bin/wally-tool-chain-install.sh | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 4c26bbf51..6d633ed66 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -1,9 +1,11 @@ -export RISCV=/opt/riscv +export RISCV=/mnt/500gbs/riscv export PATH=$PATH:$RISCV/bin set -e # break on error -NUM_THREADS=1 +#NUM_THREADS=1 # for low memory machines > 8GiB +NUM_THREADS=8 # for >= 32GiB +#NUM_THREADS=16 # for >= 64GiB sudo mkdir -p $RISCV @@ -13,14 +15,15 @@ apt update # INSTALL apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev -ln -sf /usr/bin/python3 /usr/bin/python # this is unforunate. gcc needs python but it looks specifically for python and not python3 or python2. +# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3. +ln -sf /usr/bin/python3 /usr/bin/python # gcc cross-compiler cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -make +make -j ${NUM_THREADS} make install # elf2hex @@ -44,7 +47,7 @@ cd $RISCV git clone --recurse-submodules https://github.com/qemu/qemu cd qemu ./configure --target-list=riscv64-softmmu --prefix=$RISCV -make +make -j ${NUM_THREADS} make install # Spike @@ -53,7 +56,7 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir -p riscv-isa-sim/build cd riscv-isa-sim/build ../configure --prefix=$RISCV --enable-commitlog -make +make -j ${NUM_THREADS} make install cd ../arch_test_target/spike/device sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include @@ -66,7 +69,7 @@ git clone https://github.com/Z3Prover/z3.git cd z3 python scripts/mk_make.py cd build -make +make -j ${NUM_THREADS} make install cd ../.. pip3 install chardet==3.0.4 @@ -78,7 +81,7 @@ opam install sail -y eval $(opam config env) git clone https://github.com/riscv/sail-riscv.git cd sail-riscv -make +make -j ${NUM_THREADS} ARCH=RV32 make ARCH=RV64 make ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 From 528f1a0940f40be13de3c9b58334a51f012e6ede Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 21:29:37 -0600 Subject: [PATCH 039/294] Added check for the odd Ubuntu 22.04 python2/3 issue. --- bin/wally-tool-chain-install.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 6d633ed66..559745713 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -16,7 +16,11 @@ apt update apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3. -ln -sf /usr/bin/python3 /usr/bin/python +if ! command -v python &> /dev/null +then + echo "WARNING: python3 was installed as python3 rather than python. Creating symlink." + ln -sf /usr/bin/python3 /usr/bin/python +fi # gcc cross-compiler cd $RISCV From b737c2ab1293402188b817f6d4dea384753f900c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 21:31:47 -0600 Subject: [PATCH 040/294] Added argument to install script for alternate install directory. --- bin/wally-tool-chain-install.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 559745713..14012c644 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -1,4 +1,6 @@ -export RISCV=/mnt/500gbs/riscv +#!/bin/bash + +export RISCV="${1:-/opt/riscv}" export PATH=$PATH:$RISCV/bin set -e # break on error From 1692559c05598f7511300c80f07a834a499e32d7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 21:50:24 -0600 Subject: [PATCH 041/294] Updated install readme. --- Install | 141 ++------------------------------------------------------ 1 file changed, 3 insertions(+), 138 deletions(-) diff --git a/Install b/Install index 28ef1b846..7e509197d 100644 --- a/Install +++ b/Install @@ -14,148 +14,14 @@ installed at base diretory $RISCV. ** TL;DR Open Source Tool-chain Installation - The installing details are involved. The following script assumes installation occurs in RISCV=/opt/riscv + The installing details are involved, but can be skipped using the following script. wally-tool-chain-install.sh installs the open source tools to RISCV=/opt/riscv by default. Change by supplying an alternate path as an argument, (ie. wally-tool-chain-install.sh /mnt/disk1/riscv). This install script does NOT install buildroot or commercial EDA tools; Questa, Design Compiler, or Innovus. It must be run as root or with sudo. - This script only works for Ubuntu. + This script is tested for Ubuntu, 20.04 and 22.04 wally-tool-chain-install.sh -** TL;DR install summery - -*** Environement setup - 1. export RISCV=/opt/riscv - 2. sudo mkdir $RISCV - 3. sudo chown cad $RISCV - 4. sudo su cad (or root, if you don’t have a cad account) - 5. export RISCV=/opt/riscv - 6. chmod 755 $RISCV - 7. mask 0002 - 8. cd $RISCV - -*** Install dependencies - -**** Ubuntu - 1. sudo apt update - 2. sudo apt upgrade - 3. sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog - -**** Red Hat / Fedora *** TODO - -*** Install RISC-V GCC Cross-Compiler - 1. git clone https://github.com/riscv/riscv-gnu-toolchain - 2. cd riscv-gnu-toolchain - 3. git checkout 2022.09.21 - 4. ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - 5. make --jobs - -*** Install elf2hex - 1. cd $RISCV - 2. export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH - 3. git clone https://github.com/sifive/elf2hex.git - 4. cd elf2hex - 5. autoreconf -i - 6. ./configure --target=riscv64-unknown-elf --prefix=$RISCV - 7. make - 8. make install - -*** Install RISC-V Spike Simulator - 1. cd $RISCV - 2. git clone https://github.com/riscv-software-src/riscv-isa-sim - 3. mkdir riscv-isa-sim/build - 4. cd riscv-isa-sim/build - 5. ../configure --prefix=$RISCV --enable-commitlog - 6. make --jobs - 7. make install - 8. cd ../arch_test_target/spike/device - 9. sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include - 10. sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include - -*** Install Sail Simulator - -**** Ubuntu - 1. sudo apt install opam build-essential libgmp-dev z3 pkg-config zlib1g-dev - -**** Red Hat / Fedora - # Parallel make (--jobs) will massively speed up installation; however it requires significant system RAM. Recomemded to have 64GB - 1. sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" - When prompted, put it in /usr/bin - 2. sudo yum groupinstall 'Development Tools' - 3. sudo yum -y install gmp-devel - 4. sudo yum -y install zlib-devel - 5. git clone https://github.com/Z3Prover/z3.git - 6. cd z3 - 7. python scripts/mk_make.py - 8. cd build - 9. make - 10. sudo make install - 11. cd ../.. - 12. sudo pip3 install chardet==3.0.4 - 13. sudo pip3 install urllib3==1.22 - -**** Complete Sail Install with OCaml - # Parallel make (--jobs) will massively speed up installation; however it requires significant system RAM. Recomemded to have 64GB - 1. sudo su cad - 2. opam init -y --disable-sandboxing - 3. opam switch create ocaml-base-compiler.4.06.1 - 4. opam install sail -y - 5. eval $(opam config env) - 6. cd $RISCV - 7. git clone https://github.com/riscv/sail-riscv.git - 8. cd sail-riscv - 9. make - 10. ARCH=RV32 make - 11. ARCH=RV64 make - 12. exit - 13. sudo su - 14. export RISCV=/opt/riscv - 15. ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 - 16. ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 - 17. exit - -*** Install riscof - 1. sudo pip3 install testresources - 2. sudo pip3 install riscof --ignore-installed PyYAML - -*** Install Verilator - -**** Ubuntu - sudo apt install verilator - -**** Red Hat / Fedora *** TODO - -*** Install QEMU Simulator (Only required for linux simulation) - 1. cd $RISCV - 2. git clone --recurse-submodules https://github.com/qemu/qemu - 3. cd qemu - 4. git checkout v6.2.0 # last version tested; newer versions might be ok - 5. ./configure --target-list=riscv64-softmmu --prefix=$RISCV - 6. make --jobs - 7. make install - -*** Cross-Compile Buildroot Linux (Only required for linux simulation) -#May wish to install in another location - 1. cd $RISCV - 2. export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now - 3. git clone https://github.com/buildroot/buildroot.git - 4. cd buildroot - 5. git checkout 2021.05 # last tested working version - 6. cp -r $WALLY/linux/buildroot-config-src/wally ./board - 7. cp ./board/wally/main.config .config - 8. make --jobs - -**** Generate disassembly files - 1. source ~/riscv-wally/setup.sh - 2. cd $WALLY/linux/buildroot-scripts - 3. make all - -*** Download Synthesis Libraries - 1. cd $RISCV - 2. mkdir cad - 3. mkdir cad/lib - 4. cd cad/lib - 5. git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 - + The step by step instructions include Red Hat 8 / Fedora. ** Detailed Tool-chain Instal Guide Section 2.1 described Wally platform requirements and Section 2.2 describes how a user gets started using Wally on a Linux server. This appendix describes how the system administrator installs RISC-V tools. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so this appendix also describes a fallback flow with Docker and Podman. @@ -405,7 +271,6 @@ If you want to implement your own version of the chip, your tool and license com Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection. - * Core-v-wally Repo Installation ** TL;DR Repo Install cd From c1790e67bc7246f8f6e7852a9ac7b08346994e82 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 22:00:26 -0600 Subject: [PATCH 042/294] Defaults to 1 job compiles. --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 14012c644..e9465b058 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -5,8 +5,8 @@ export PATH=$PATH:$RISCV/bin set -e # break on error -#NUM_THREADS=1 # for low memory machines > 8GiB -NUM_THREADS=8 # for >= 32GiB +NUM_THREADS=1 # for low memory machines > 16GiB +#NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB sudo mkdir -p $RISCV From 7f09b8cc88f68df48def2fa00ea0e7e2e9ee13c0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 22:14:58 -0600 Subject: [PATCH 043/294] Found minor bug in install script. --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index e9465b058..6c52ce7c6 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -90,8 +90,8 @@ cd sail-riscv make -j ${NUM_THREADS} ARCH=RV32 make ARCH=RV64 make -ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 -ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 +ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 +ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 pip3 install testresources pip3 install riscof --ignore-installed PyYAML From fec674371614a23782b654a5a20d626323550dd5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 22:16:47 -0600 Subject: [PATCH 044/294] Merge Install script into the README.md --- README.md | 263 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 263 insertions(+) diff --git a/README.md b/README.md index 433eb442a..6092fd74d 100644 --- a/README.md +++ b/README.md @@ -29,3 +29,266 @@ Add the following lines to your .bashrc or .bash_profile if [ -f ~/riscv-wally/setup.sh ]; then source ~/riscv-wally/setup.sh fi + +# Tool-chain Installation (Sys Admin) + +This section describes the open source toolchain installation. These steps should only be done once by the system admin. + +## TL;DR Open Source Tool-chain Installation + +The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. +The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. + +wally-tool-chain-install.sh + +## Detailed Tool-chain Install Guide + + Section 2.1 described Wally platform requirements and Section 2.2 describes how a user gets started using Wally on a Linux server. This appendix describes how the system administrator installs RISC-V tools. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so this appendix also describes a fallback flow with Docker and Podman. + +### Open Source Software Installation + +Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools: + +1. The GCC cross-compiler +2. A RISC-V simulator such as Spike, Sail, and/or QEMU +3. Spike is easy to use but doesn’t support peripherals to boot Linux +4. QEMU is faster and can boot Linux +5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal + +This setup needs to be done once by the administrator + +Note: The following directions assume you have an account called cad to install shared software and files. You can substitute a different user for cad if you prefer. + +Note: Installing software in Linux is unreasonably touchy and varies with the flavor and version of your Linux distribution. Don’t be surprised if the installation directions have changed since the book was written or don’t work on your machine; you may need some ingenuity to adjust them. Browse the openhwgroup/core-v-wally repo and look at the README.md for the latest build instructions. + +### Create the $RISCV Directory + +First, set up a directory for riscv software in some place such as /opt/riscv. We will call this shared directory $RISCV. + +$ export RISCV=/opt/riscv +$ sudo mkdir $RISCV +$ sudo chown cad $RISCV +$ sudo su cad (or root, if you don’t have a cad account) +$ export RISCV=/opt/riscv +$ chmod 755 $RISCV +$ umask 0002 +$ cd $RISCV + +### Update Tools + +Ubuntu users may need to install and update various tools. + +$ sudo apt update +$ sudo apt upgrade +$ sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog + +### Install RISC-V GCC Cross-Compiler + +To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. + +$ git clone https://github.com/riscv/riscv-gnu-toolchain +$ cd riscv-gnu-toolchain +$ git checkout 2022.09.21 +$ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +$ make --jobs + +Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. + +### Install elf2hex + +We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: + +$ cd $RISCV +$ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +$ git clone https://github.com/sifive/elf2hex.git +$ cd elf2hex +$ autoreconf -i +$ ./configure --target=riscv64-unknown-elf --prefix=$RISCV +$ make +$ make install + +Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t handle programs that start at 0x80000000. The SiFive version above is touchy to install. For example, if Python version 2.x is in your path, it won’t install correctly. Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin at the time of compilation, or elf2hex won’t work properly. + +### Install RISC-V Spike Simulator + +Spike also takes a while to install and compile, but this can be done concurrently with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions . + +$ cd $RISCV +$ git clone https://github.com/riscv-software-src/riscv-isa-sim +$ mkdir riscv-isa-sim/build +$ cd riscv-isa-sim/build +$ ../configure --prefix=$RISCV --enable-commitlog +$ make --jobs +$ make install +$ cd ../arch_test_target/spike/device +$ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include +$ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include + +### Install Sail Simulator + +Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which is an object-oriented extension of ML, which in turn is a functional programming language suited to formal verification. OCaml is installed with the opam OCcaml package manager. Sail has so many dependencies that it can be difficult to install. + +On Ubuntu, apt-get makes opam installation fairly simple. + +$ sudo apt-get install opam build-essential libgmp-dev z3 pkg-config zlib1g-dev + +If you are on RedHat/Rocky Linux 8, installation is much more difficult because packages are not available in the default package manager and some need to be built from source. + +$ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" + When prompted, put it in /usr/bin +$ sudo yum groupinstall 'Development Tools' +$ sudo yum -y install gmp-devel +$ sudo yum -y install zlib-devel +$ git clone https://github.com/Z3Prover/z3.git +$ cd z3 +$ python scripts/mk_make.py +$ cd build +$ make +$ sudo make install +$ cd ../.. +$ sudo pip3 install chardet==3.0.4 +$ sudo pip3 install urllib3==1.22 + +Once you have installed the packages on either Ubuntu or RedHat, use opam to install the OCaml compiler and Sail. Run as the cad user because you will be installing Sail in $RISCV. + +$ sudo su cad +$ opam init -y --disable-sandboxing +$ opam switch create ocaml-base-compiler.4.06.1 +$ opam install sail -y + +Now you can clone and compile Sail-RISCV. This will take a while. + +$ eval $(opam config env) +$ cd $RISCV +$ git clone https://github.com/riscv/sail-riscv.git +$ cd sail-riscv +$ make +$ ARCH=RV32 make +$ ARCH=RV64 make +$ exit +$ sudo su +$ export RISCV=/opt/riscv +$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 +$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 +$ exit + +### Install riscof + +riscof is a Python library used as the RISC-V compatibility framework test an implementation such as Wally or Spike against the Sail golden reference. It will be used to compile the riscv-arch-test suite. + +It is most convenient if the sysadmin installs riscof into the server’s Python libraries: + +$ sudo pip3 install testresources +$ sudo pip3 install riscof --ignore-installed PyYAML + +However, riscof can also be installed and run locally by individual users. + +### Install Verilator + +Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression. +$ sudo apt install verilator + +### Install QEMU Simulator + +QEMU is another simulator used when booting Linux in Chapter 17. You can optionally install it using the following commands. + + +The QEMU patch changes the VirtIO driver to match the Wally peripherals, and also adds print statements to log the state of the CSRs (see Section 2.5XREF). + + +$ cd $RISCV +$ git clone --recurse-submodules https://github.com/qemu/qemu +$ cd qemu +$ git checkout v6.2.0 # last version tested; newer versions might be ok +$ ./configure --target-list=riscv64-softmmu --prefix=$RISCV +$ make --jobs +$ make install + +### Cross-Compile Buildroot Linux + +Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. + +Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. + +To configure and build Buildroot: + +$ cd $RISCV +$ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now +$ git clone https://github.com/buildroot/buildroot.git +$ cd buildroot +$ git checkout 2021.05 # last tested working version +$ cp -r $WALLY/linux/buildroot-config-src/wally ./board +$ cp ./board/wally/main.config .config +$ make --jobs + +To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. + +$ source ~/riscv-wally/setup.sh +$ cd $WALLY/linux/buildroot-scripts +$ make all + +Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. + +### Download Synthesis Libraries + +For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library. Clone the OSU 12-track cell library for the Skywater 130 nm process: + +$ cd $RISCV +$ mkdir cad +$ mkdir cad/lib +$ cd cad/lib +$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 + +## Installing EDA Tools + +Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. + +Siemens Quest is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. + +Note: Some EDA tools utilize LM_LICENSE_FILE for their environmental variable to point to their license server. Some operating systems may also utilize MGLS_LICENSE_FILE instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. + +Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. + +Siemens Questa + +Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to +https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. + +Synopsys Design Compiler (DC) + +Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer + +$ firefox & +Navigate to https://solvnet.synopsys.com +Log in with your institution’s username and password +Click on Downloads, then scroll down to Synopsys Installer +Select the latest version (currently 5.4). Click Download Here, agree, +Click on SynopsysInstaller_v5.4.run +Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want. + Click on all parts and the .spf file, then click Download Files near the top +move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, +move other files into /cad/synopsys/downloads and work as user cad from here on +$ cd /cad/synopsys/installer_5.4 +$ ./SynopsysInstaller_v5.4.run +Accept default installation directory +$ ./installer +Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys +When prompted, enter your site ID +Follow prompts + +Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed. + +The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation: + +/import/programs/synopsys/syn/S-2021.06-SP1 + +Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. + +The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. + +If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips. + +Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection. + + + From 06ccf912225e17582bf28bfa7e97ed31f0e7979f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 22:20:53 -0600 Subject: [PATCH 045/294] Readme formatting. --- README.md | 203 +++++++++++++++++++++++++++--------------------------- 1 file changed, 102 insertions(+), 101 deletions(-) diff --git a/README.md b/README.md index 6092fd74d..7c646a0f5 100644 --- a/README.md +++ b/README.md @@ -39,7 +39,7 @@ This section describes the open source toolchain installation. These steps shou The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. -wally-tool-chain-install.sh + wally-tool-chain-install.sh ## Detailed Tool-chain Install Guide @@ -49,11 +49,11 @@ wally-tool-chain-install.sh -$ cd $RISCV -$ git clone --recurse-submodules https://github.com/qemu/qemu -$ cd qemu -$ git checkout v6.2.0 # last version tested; newer versions might be ok -$ ./configure --target-list=riscv64-softmmu --prefix=$RISCV -$ make --jobs -$ make install + $ cd $RISCV + $ git clone --recurse-submodules https://github.com/qemu/qemu + $ cd qemu + $ git checkout v6.2.0 # last version tested; newer versions might be ok + $ ./configure --target-list=riscv64-softmmu --prefix=$RISCV + $ make --jobs + $ make install ### Cross-Compile Buildroot Linux @@ -212,14 +212,14 @@ Buildroot depends on configuration files in riscv-wally, so the cad user must in To configure and build Buildroot: -$ cd $RISCV -$ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now -$ git clone https://github.com/buildroot/buildroot.git -$ cd buildroot -$ git checkout 2021.05 # last tested working version -$ cp -r $WALLY/linux/buildroot-config-src/wally ./board -$ cp ./board/wally/main.config .config -$ make --jobs + $ cd $RISCV + $ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now + $ git clone https://github.com/buildroot/buildroot.git + $ cd buildroot + $ git checkout 2021.05 # last tested working version + $ cp -r $WALLY/linux/buildroot-config-src/wally ./board + $ cp ./board/wally/main.config .config + $ make --jobs To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. @@ -233,11 +233,11 @@ Note: When the make tasks complete, you’ll find source code in $RISCV/buildroo For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library. Clone the OSU 12-track cell library for the Skywater 130 nm process: -$ cd $RISCV -$ mkdir cad -$ mkdir cad/lib -$ cd cad/lib -$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 + $ cd $RISCV + $ mkdir cad + $ mkdir cad/lib + $ cd cad/lib + $ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 ## Installing EDA Tools @@ -258,7 +258,7 @@ Synopsys Design Compiler (DC) Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer -$ firefox & + $ firefox & Navigate to https://solvnet.synopsys.com Log in with your institution’s username and password Click on Downloads, then scroll down to Synopsys Installer @@ -268,19 +268,20 @@ Return to downloads and also get Design Compiler (synthesis) latest version, and Click on all parts and the .spf file, then click Download Files near the top move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, move other files into /cad/synopsys/downloads and work as user cad from here on -$ cd /cad/synopsys/installer_5.4 -$ ./SynopsysInstaller_v5.4.run -Accept default installation directory -$ ./installer -Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys -When prompted, enter your site ID -Follow prompts + + $ cd /cad/synopsys/installer_5.4 + $ ./SynopsysInstaller_v5.4.run + Accept default installation directory + $ ./installer + Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys + When prompted, enter your site ID + Follow prompts Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed. The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation: -/import/programs/synopsys/syn/S-2021.06-SP1 + /import/programs/synopsys/syn/S-2021.06-SP1 Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. From bdf8dcf037a38bab84bc1982e6c0a136de6011d2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 22:22:39 -0600 Subject: [PATCH 046/294] More changes to the readme formatting. --- README.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/README.md b/README.md index 7c646a0f5..3196e3fcf 100644 --- a/README.md +++ b/README.md @@ -39,7 +39,7 @@ This section describes the open source toolchain installation. These steps shou The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. - wally-tool-chain-install.sh + $ wally-tool-chain-install.sh ## Detailed Tool-chain Install Guide @@ -49,11 +49,11 @@ The script installs the open source tools to /opt/riscv by default. This can be Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools: - 1. The GCC cross-compiler - 2. A RISC-V simulator such as Spike, Sail, and/or QEMU - 3. Spike is easy to use but doesn’t support peripherals to boot Linux - 4. QEMU is faster and can boot Linux - 5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal +1. The GCC cross-compiler +2. A RISC-V simulator such as Spike, Sail, and/or QEMU +3. Spike is easy to use but doesn’t support peripherals to boot Linux +4. QEMU is faster and can boot Linux +5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal This setup needs to be done once by the administrator From 963eaad0f5679027a22144d37a138157641164c8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 21 Jan 2023 22:47:47 -0600 Subject: [PATCH 047/294] Added block diagram to readme. --- README.md | 2 ++ wallyriscvTopAll.png | Bin 0 -> 38693 bytes 2 files changed, 2 insertions(+) create mode 100644 wallyriscvTopAll.png diff --git a/README.md b/README.md index 3196e3fcf..88b388350 100644 --- a/README.md +++ b/README.md @@ -3,6 +3,8 @@ Configurable RISC-V Processor Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and boots Linux on an FPGA. +![Wally block diagram](wallyriscvTopAll.png) + Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. See Appendix D for directions installing the RISC-V tool chain needed to use Wally. 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a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 6c52ce7c6..dbed6ed86 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -1,4 +1,30 @@ #!/bin/bash +########################################### +## cache +## +## Written: Ross Thompson ross1728@gmail.com +## Created: 18 January 2023 +## Modified: 22 January 2023 +## +## Purpose: Open source tool chain installation script +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ export RISCV="${1:-/opt/riscv}" export PATH=$PATH:$RISCV/bin From 24618f741a69116186ba68613632f2c136e3f375 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 22 Jan 2023 13:04:31 -0600 Subject: [PATCH 049/294] Added SPDX header to scripts. --- bin/elf2hex.sh | 28 +++++++++++++++-- bin/exe2memfile.pl | 36 ++++++++++++++++++--- bin/extractFunctionRadix.sh | 55 ++++++++++++++++----------------- bin/parseHPMC.py | 25 +++++++++++++++ bin/testcount.pl | 33 +++++++++++++++++--- bin/testlist.pl | 33 +++++++++++++++++--- bin/vclean.pl | 33 +++++++++++++++++--- bin/wally-tool-chain-install.sh | 2 +- 8 files changed, 195 insertions(+), 50 deletions(-) diff --git a/bin/elf2hex.sh b/bin/elf2hex.sh index 5808f4109..56f286135 100755 --- a/bin/elf2hex.sh +++ b/bin/elf2hex.sh @@ -1,8 +1,30 @@ #!/bin/bash -# james.stine@okstate.edu 4 Jan 2022 -# Script to run elf2hex for memfile for -# Imperas and riscv-arch-test benchmarks +########################################### +## Written: james.stine@okstate.edu +## Created: 4 Jan 2022 +## Modified: +## +## Purpose: Script to run elf2hex for memfile for +## Imperas and riscv-arch-test benchmarks +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ for file in work/rv64i_m/*/*.elf ; do memfile=${file%.elf}.elf.memfile diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 70e51167e..2af665bbd 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -1,9 +1,35 @@ #!/usr/bin/perl -w -# exe2memfile.pl -# David_Harris@hmc.edu 26 November 2020 -# Converts an executable file to a series of 32-bit hex instructions -# to read into a Verilog simulation with $readmemh +########################################### +## exe2memfile.pl +## +## Written: David_Harris@hmc.edu +## Created: 26 November 2020 +## Modified: +## +## Purpose: Converts an executable file to a series of 32-bit hex instructions +## to read into a Verilog simulation with $readmemh +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# +# use File::stat; use IO::Handle; @@ -167,4 +193,4 @@ sub fixadr { my $adr = shift; if ($adr =~ s/^8/0/) { return hex($adr); } else { die("address $adr lacks leading 8\n"); } -} \ No newline at end of file +} diff --git a/bin/extractFunctionRadix.sh b/bin/extractFunctionRadix.sh index cb37f5378..42e3db0b2 100755 --- a/bin/extractFunctionRadix.sh +++ b/bin/extractFunctionRadix.sh @@ -1,34 +1,33 @@ #!/bin/bash ###################### -# extractFunctionRadix.sh -# -# Written: Ross Thompson -# email: ross1728@gmail.com -# Created: March 1, 2021 -# Modified: March 10, 2021 -# -# Purpose: Processes all compiled object files into 2 types of files which assist in debuging applications. -# File 1: .addr: A sorted list of function starting addresses. -# When a the PCE is greater than or equal to the function's starting address, the label will be associated with this address. -# File 2: .lab: A sorted list of funciton labels. The names of functions. Modelsim will display these names rather than the function address. -# -# A component of the Wally configurable RISC-V project. -# -# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -# is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -###################### +## extractFunctionRadix.sh +## +## Written: Ross Thompson +## email: ross1728@gmail.com +## Created: March 1, 2021 +## Modified: March 10, 2021 +## +## Purpose: Processes all compiled object files into 2 types of files which assist in debuging applications. +## File 1: .addr: A sorted list of function starting addresses. +## When a the PCE is greater than or equal to the function's starting address, the label will be associated with this address. +## File 2: .lab: A sorted list of funciton labels. The names of functions. Modelsim will display these names rather than the function address. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ function processProgram { diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 2bc998e51..00dcb308c 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -1,5 +1,30 @@ #!/usr/bin/python3 +########################################### +## Written: Ross Thompson ross1728@gmail.com +## Created: 4 Jan 2022 +## Modified: +## +## Purpose: Parses the performance counters from a modelsim trace. +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + import os import sys import matplotlib.pyplot as plt diff --git a/bin/testcount.pl b/bin/testcount.pl index 65d662293..e801ed0e4 100755 --- a/bin/testcount.pl +++ b/bin/testcount.pl @@ -1,8 +1,33 @@ #!/bin/bash -# testcount.pl -# David_Harris@hmc.edu 25 December 2022 -# Read the riscv-test-suite directories from riscv-arch-test -# and count how many tests are in each + +########################################### +## testcount.pl +## +## Written: David_Harris@hmc.edu +## Created: 25 December 2022 +## Modified: Read the riscv-test-suite directories from riscv-arch-test +## and count how many tests are in each +## +## Purpose: Read the riscv-test-suite directories from riscv-arch-test +## and count how many tests are in each +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ for dir in `ls ${WALLY}/addins/riscv-arch-test/riscv-test-suite/rv*/*` do diff --git a/bin/testlist.pl b/bin/testlist.pl index 12be0a913..655cdd6f8 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -1,8 +1,33 @@ #!/bin/perl -W -# testlist.pl -# David_Harris@hmc.edu 25 December 2021 -# Read the work directories from riscv-arch-test or imperas-riscv-tests -# and generate a list of tests and signature addresses for tests.vh + +########################################### +## testlist.pl +## +## Written: David_Harris@hmc.edu +## Created: 25 December 2021 +## Modified: +## +## Purpose: Read the work directories from riscv-arch-test or imperas-riscv-tests +## and generate a list of tests and signature addresses for tests.vh +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + use strict; use warnings; diff --git a/bin/vclean.pl b/bin/vclean.pl index 2bc25d3d3..f947ed9d0 100755 --- a/bin/vclean.pl +++ b/bin/vclean.pl @@ -1,9 +1,32 @@ #!/usr/bin/perl -w -# vclean.pl -# David_Harris@hmc.edu 7 December 2023 -# Identifies unused signals in Verilog files -# verilator should do this, but it also reports partially used signals +########################################### +## vclean.pl +## +## Written: David_Harris@hmc.edu +## Created: 7 December 2023 +## Modified: +## +## Purpose: Identifies unused signals in Verilog files +## verilator should do this, but it also reports partially used signals +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ use strict; @@ -43,4 +66,4 @@ sub clean { printf("$sig not used in $fname\n"); } } -} \ No newline at end of file +} diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index dbed6ed86..3265795c5 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -1,6 +1,6 @@ #!/bin/bash ########################################### -## cache +## Tool chain install script. ## ## Written: Ross Thompson ross1728@gmail.com ## Created: 18 January 2023 From 18f968a63ed685f3871fdff742c48fa18d74e908 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 04:15:31 -0800 Subject: [PATCH 050/294] Switched to fork new cvw repo --- README.md | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 88b388350..26eb930bb 100644 --- a/README.md +++ b/README.md @@ -18,9 +18,17 @@ New users may wish to do the following setup to access the server via a GUI and Then follow Section 2.2 to clone the repo, source setup, make the tests and run regression + If you don't already have a Github account, create one + In a web browser, visit https://github.com/openhwgroup/cvw + In the upper right part of the screen, click on Fork + Create a fork, choosing the owner as your github account and the repository as cvw. + + On the Linux computer where you will be working, log in, clone your fork of the repo, + run the setup script, and build the tests: + $ cd - $ git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally - $ cd riscv-wally + $ git clone --recurse-submodules https://github.com//cvw + $ cd cvw $ source ./setup.sh $ make $ cd pipelined/regression @@ -28,8 +36,8 @@ Then follow Section 2.2 to clone the repo, source setup, make the tests and run Add the following lines to your .bashrc or .bash_profile - if [ -f ~/riscv-wally/setup.sh ]; then - source ~/riscv-wally/setup.sh + if [ -f ~/cvw/setup.sh ]; then + source ~/cvw/setup.sh fi # Tool-chain Installation (Sys Admin) From 7d8a0d9615c5358da9a75ea2b413037af7589ad0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 23 Jan 2023 05:00:11 -0800 Subject: [PATCH 051/294] Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases --- setup.sh | 9 +++++---- tests/riscof/spike/spike_rv32imc_isa.yaml | 3 ++- tests/riscof/spike/spike_rv64gc_isa.yaml | 3 ++- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/setup.sh b/setup.sh index dc1f418d5..27ed893db 100755 --- a/setup.sh +++ b/setup.sh @@ -2,7 +2,7 @@ # setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 -# Set up tools for riscv-wally +# Set up tools for rvw echo "Executing Wally setup.sh" @@ -15,14 +15,15 @@ echo \$WALLY set to ${WALLY} # Must edit these based on your local environment. Ask your sysadmin. export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server -export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Questa -export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler - +export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa +export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler # Path to RISC-V Tools export RISCV=/opt/riscv # change this if you installed the tools in a different location # Tools +# Questa and Synopsys +export PATH=$QUESTAPATH:$SNPSPATH:$PATH # GCC export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index 3438e17a0..478bbe56d 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,6 +1,7 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV32IMAFDCZicsr_Zifencei +# ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index a8837ac76..8037ad6f6 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,6 +1,7 @@ hart_ids: [0] hart0: - ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV64IMAFDCSUZicsr_Zifencei +# ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] From 5b957f809fd3398cb9cc60df2e41c9e3a4a8730f Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 23 Jan 2023 05:06:27 -0800 Subject: [PATCH 052/294] Updated README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 26eb930bb..45e503d94 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ Wally is a 5-stage pipelined processor configurable to support all the standard ![Wally block diagram](wallyriscvTopAll.png) -Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. See Appendix D for directions installing the RISC-V tool chain needed to use Wally. +Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. New users may wish to do the following setup to access the server via a GUI and use a text editor. From b6b67516eb7f4cad63bcb32b75cac52dfd66cb0e Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 23 Jan 2023 10:37:33 -0800 Subject: [PATCH 053/294] Repo cleanup --- .../radixcopiesmultiregression.sh | 0 pipelined/misc/lzd.sv | 136 ------------------ 2 files changed, 136 deletions(-) rename {pipelined => bin}/radixcopiesmultiregression.sh (100%) delete mode 100644 pipelined/misc/lzd.sv diff --git a/pipelined/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh similarity index 100% rename from pipelined/radixcopiesmultiregression.sh rename to bin/radixcopiesmultiregression.sh diff --git a/pipelined/misc/lzd.sv b/pipelined/misc/lzd.sv deleted file mode 100644 index 5ca99bae1..000000000 --- a/pipelined/misc/lzd.sv +++ /dev/null @@ -1,136 +0,0 @@ -// V. G. Oklobdzija, "Algorithmic design of a hierarchical and modular -// leading zero detector circuit," in Electronics Letters, vol. 29, -// no. 3, pp. 283-284, 4 Feb. 1993, doi: 10.1049/el:19930193. - -module lz2 (P, V, B0, B1); - - input logic B0; - input logic B1; - - output logic P; - output logic V; - - assign V = B0 | B1; - assign P = B0 & ~B1; - -endmodule // lz2 - -// Note: This module is not made out of two lz2's - why not? (MJS) - -module lz4 (ZP, ZV, B0, B1, V0, V1); - - output logic [1:0] ZP; - output logic ZV; - - input logic B0; - input logic B1; - input logic V0; - input logic V1; - - assign ZP[0] = V0 ? B0 : B1; - assign ZP[1] = ~V0; - assign ZV = V0 | V1; - -endmodule // lz4 - -// Note: This module is not made out of two lz4's - why not? (MJS) - -module lz8 (ZP, ZV, B); - - input logic [7:0] B; - - output logic [2:0] ZP; - output logic ZV; - - logic s1p0; - logic s1v0; - logic s1p1; - logic s1v1; - logic s2p0; - logic s2v0; - logic s2p1; - logic s2v1; - logic [1:0] ZPa; - logic [1:0] ZPb; - logic ZVa; - logic ZVb; - - lz2 l1(s1p0, s1v0, B[2], B[3]); - lz2 l2(s1p1, s1v1, B[0], B[1]); - lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1); - - lz2 l4(s2p0, s2v0, B[6], B[7]); - lz2 l5(s2p1, s2v1, B[4], B[5]); - lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1); - - assign ZP[1:0] = ZVb ? ZPb : ZPa; - assign ZP[2] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz8 - -module lz16 (ZP, ZV, B); - - input logic [15:0] B; - - output logic [3:0] ZP; - output logic ZV; - - logic [2:0] ZPa; - logic [2:0] ZPb; - logic ZVa; - logic ZVb; - - lz8 l1(ZPa, ZVa, B[7:0]); - lz8 l2(ZPb, ZVb, B[15:8]); - - assign ZP[2:0] = ZVb ? ZPb : ZPa; - assign ZP[3] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz16 - -module lz32 (ZP, ZV, B); - - input logic [31:0] B; - - output logic [4:0] ZP; - output logic ZV; - - logic [3:0] ZPa; - logic [3:0] ZPb; - logic ZVa; - logic ZVb; - - lz16 l1(ZPa, ZVa, B[15:0]); - lz16 l2(ZPb, ZVb, B[31:16]); - - assign ZP[3:0] = ZVb ? ZPb : ZPa; - assign ZP[4] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz32 - -// This module returns the number of leading zeros ZP in the 64-bit -// number B. If there are no ones in B, then ZP and ZV are both 0. - -module lz64 (ZP, ZV, B); - - input logic [63:0] B; - - output logic [5:0] ZP; - output logic ZV; - - logic [4:0] ZPa; - logic [4:0] ZPb; - logic ZVa; - logic ZVb; - - lz32 l1(ZPa, ZVa, B[31:0]); - lz32 l2(ZPb, ZVb, B[63:32]); - - assign ZV = ZVa | ZVb; - assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}}; - assign ZP[5] = ~ZVb & ZV; - -endmodule // lz64 From ad570a4c47c4a8906a0e7b2db204eb5774d9a401 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 12:53:31 -0600 Subject: [PATCH 054/294] Test commit. please merge. --- bugs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bugs.txt b/bugs.txt index f2a22fd81..95d68b0d4 100644 --- a/bugs.txt +++ b/bugs.txt @@ -1,2 +1,5 @@ 1. [X] Cache is suppressing d cache flush if there is a dtlb miss. 1. Fixed by disabling mmu's address translation on flush. + + +2. Test commit. From 678a879415d0e67ccc3635563cd5e3a4f401ba4f Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 23 Jan 2023 10:54:06 -0800 Subject: [PATCH 055/294] formatting --- pipelined/src/wally/wallypipelinedcore.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 3e1bd5846..2b71851f5 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -47,7 +47,7 @@ module wallypipelinedcore ( output logic [3:0] HPROT, output logic [1:0] HTRANS, output logic HMASTLOCK - ); +); logic StallF, StallD, StallE, StallM, StallW; logic FlushD, FlushE, FlushM, FlushW; From a5e1b09a402da9363a27b1005790ea30b3a86de9 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 12:12:14 -0800 Subject: [PATCH 056/294] installation instructions --- README.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/README.md b/README.md index 45e503d94..2957b3490 100644 --- a/README.md +++ b/README.md @@ -26,6 +26,12 @@ Then follow Section 2.2 to clone the repo, source setup, make the tests and run On the Linux computer where you will be working, log in, clone your fork of the repo, run the setup script, and build the tests: +Add the following lines to your .bashrc or .bash_profile + + if [ -f ~/cvw/setup.sh ]; then + source ~/cvw/setup.sh + fi + $ cd $ git clone --recurse-submodules https://github.com//cvw $ cd cvw @@ -34,12 +40,6 @@ Then follow Section 2.2 to clone the repo, source setup, make the tests and run $ cd pipelined/regression $ ./regression-wally (depends on having Questa installed) -Add the following lines to your .bashrc or .bash_profile - - if [ -f ~/cvw/setup.sh ]; then - source ~/cvw/setup.sh - fi - # Tool-chain Installation (Sys Admin) This section describes the open source toolchain installation. These steps should only be done once by the system admin. From 931846906990c4d1310a75b9ca756caa8744bb18 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 12:13:26 -0800 Subject: [PATCH 057/294] installation instructions --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 2957b3490..dfb8060d3 100644 --- a/README.md +++ b/README.md @@ -23,15 +23,15 @@ Then follow Section 2.2 to clone the repo, source setup, make the tests and run In the upper right part of the screen, click on Fork Create a fork, choosing the owner as your github account and the repository as cvw. - On the Linux computer where you will be working, log in, clone your fork of the repo, - run the setup script, and build the tests: + On the Linux computer where you will be working, log in -Add the following lines to your .bashrc or .bash_profile +Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in. if [ -f ~/cvw/setup.sh ]; then source ~/cvw/setup.sh fi +Clone your fork of the repo, run the setup script, and build the tests: $ cd $ git clone --recurse-submodules https://github.com//cvw $ cd cvw From 5f2ddffa9f6053e58cf716722ed1b233264f0fa2 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 12:13:49 -0800 Subject: [PATCH 058/294] installation instructions --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index dfb8060d3..e6872c4a7 100644 --- a/README.md +++ b/README.md @@ -32,6 +32,7 @@ Add the following lines to your .bashrc or .bash_profile to run the setup script fi Clone your fork of the repo, run the setup script, and build the tests: + $ cd $ git clone --recurse-submodules https://github.com//cvw $ cd cvw From 7a5544a450fd8992a62bd21bfa664dada517d060 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 12:14:56 -0800 Subject: [PATCH 059/294] installation instructions --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index e6872c4a7..0e41f952e 100644 --- a/README.md +++ b/README.md @@ -15,6 +15,9 @@ New users may wish to do the following setup to access the server via a GUI and Terminal on Mac, cmd on Windows, xterm on Linux See A.1 about ssh -Y login from a terminal Git started with Git configuration and authentication: B.1 + $ git config --global user.name ″Ben Bitdiddle″ + $ git config --global user.email ″ben_bitdiddle@wally.edu″ + $ git config --global pull.rebase false Then follow Section 2.2 to clone the repo, source setup, make the tests and run regression From 64cf68f684f9d7a974df0305268af0afff0cb310 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 12:24:11 -0800 Subject: [PATCH 060/294] Added sudo to sysadmin install directions --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 0e41f952e..15cd8c757 100644 --- a/README.md +++ b/README.md @@ -53,7 +53,7 @@ This section describes the open source toolchain installation. These steps shou The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. - $ wally-tool-chain-install.sh + $ sudo wally-tool-chain-install.sh ## Detailed Tool-chain Install Guide From ca6748121fe5725318fdce7302c1767170e06537 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 12:30:23 -0800 Subject: [PATCH 061/294] installation instructions --- README.md | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 15cd8c757..92e4c638d 100644 --- a/README.md +++ b/README.md @@ -7,11 +7,13 @@ Wally is a 5-stage pipelined processor configurable to support all the standard Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. +# New User Setup + New users may wish to do the following setup to access the server via a GUI and use a text editor. - Download and install x2go - A.1.1 - Download and install VSCode - A.4.2 - Make sure you can log into Tera acceptly via x2go and via a terminal + Optional: Download and install x2go - A.1.1 + Optional: Download and install VSCode - A.4.2 + Optional: Make sure you can log into your server via x2go and via a terminal Terminal on Mac, cmd on Windows, xterm on Linux See A.1 about ssh -Y login from a terminal Git started with Git configuration and authentication: B.1 @@ -19,7 +21,7 @@ New users may wish to do the following setup to access the server via a GUI and $ git config --global user.email ″ben_bitdiddle@wally.edu″ $ git config --global pull.rebase false -Then follow Section 2.2 to clone the repo, source setup, make the tests and run regression +Then clone the repo, source setup, make the tests and run regression If you don't already have a Github account, create one In a web browser, visit https://github.com/openhwgroup/cvw @@ -41,6 +43,16 @@ Clone your fork of the repo, run the setup script, and build the tests: $ cd cvw $ source ./setup.sh $ make + +Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis. + + export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server + export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server + export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa + export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler + +Run a regression simulation with Questa to prove everything is installed. + $ cd pipelined/regression $ ./regression-wally (depends on having Questa installed) From a03526c1a2c2123b38a5102306f5582d61407873 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 15:17:12 -0600 Subject: [PATCH 062/294] Added github cli (gh) to install script. --- bin/wally-tool-chain-install.sh | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3265795c5..2b45d8e77 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -125,3 +125,10 @@ pip3 install riscof --ignore-installed PyYAML # Verilator apt install -y verilator +# install github cli (gh) +type -p curl >/dev/null || sudo apt install curl -y +curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ +&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \ +&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ +&& sudo apt update \ +&& sudo apt install gh -y From 22fa6835858fb2829c19b9bac97a24823f658586 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 15:30:22 -0600 Subject: [PATCH 063/294] Added details about github cli to README. --- README.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/README.md b/README.md index 92e4c638d..f957792a6 100644 --- a/README.md +++ b/README.md @@ -265,6 +265,17 @@ For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell li $ cd cad/lib $ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 +### Install github cli + +The github cli allows users to directly issue pull requests from their fork back to openhwgroup/cvw using the command line. + + $ type -p curl >/dev/null || sudo apt install curl -y + $ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ && sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \ + && echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ + && sudo apt update \ + && sudo apt install gh -y + + ## Installing EDA Tools Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. From d835974774c24ba894277a3181fb6ccaad3264c6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 15:46:11 -0600 Subject: [PATCH 064/294] Added file to describe instructions on basic git fork work flow commands. --- gitflow.txt | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 gitflow.txt diff --git a/gitflow.txt b/gitflow.txt new file mode 100644 index 000000000..0be54022f --- /dev/null +++ b/gitflow.txt @@ -0,0 +1,38 @@ +########################################### +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +Setup +1. goto github and fork openhwgroup/cvw.git +2. clone: git clone --recurse-submodules git@ross144/cvw.git +3. git remote add upstream https://github.com/openhwgroup/cvw.git + +Once per sessiosn +1. gh auth login +2. Use ssh and point to your public key +3. Copy one-time code from terminal to browser + +Fetch upstream and sync fork +1. git fetch upstream +2. git push + +Create pull request +1. gh pr create +2. Must include a title and strongly encourage a body message explaining your changes. +3. Wait for pull request to be approved, rejected, or needs changes. +4. Finish by fetching the upstream and pushing back to your fork. From 293cc88bd9467b42d63f86d9da7a6005c4fc82f2 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 23 Jan 2023 17:00:24 -0600 Subject: [PATCH 065/294] Added extra core signal to mark_debug.txt. Modified wally.tcl --- fpga/constraints/marked_debug.txt | 1 + fpga/generator/wally.tcl | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 97ac1ead3..ff0fb325c 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -30,6 +30,7 @@ wally/wallypipelinedcore.sv: logic MemRWM wally/wallypipelinedcore.sv: logic InstrValidM wally/wallypipelinedcore.sv: logic WriteDataM wally/wallypipelinedcore.sv: logic IEUAdrM +wally/wallypipelinedcore.sv: logic HRDATA ifu/spill.sv: statetype CurrState ifu/ifu.sv: logic IFUStallF ifu/ifu.sv: logic IFUHADDR diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5cac00f5a..e0de591b7 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -19,7 +19,7 @@ read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossb read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci -read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] +# read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] read_verilog [glob -type f ../../pipelined/src/uncore/newsdc/*.v] read_verilog {../src/fpgaTop.v} @@ -47,6 +47,9 @@ synth_design -rtl -name rtl_1 report_clocks -file reports/clocks.rpt +# Temp +set_param messaging.defaultLimit 100000 + # this does synthesis? wtf? launch_runs synth_1 -jobs 4 From bce47dd3037a45dc15d3e1e025c40807493c66c1 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 15:25:26 -0800 Subject: [PATCH 066/294] Update README.md --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 92e4c638d..74df28f56 100644 --- a/README.md +++ b/README.md @@ -67,9 +67,9 @@ The script installs the open source tools to /opt/riscv by default. This can be $ sudo wally-tool-chain-install.sh -## Detailed Tool-chain Install Guide +## Detailed Toolchain Install Guide - Section 2.1 described Wally platform requirements and Section 2.2 describes how a user gets started using Wally on a Linux server. This appendix describes how the system administrator installs RISC-V tools. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so this appendix also describes a fallback flow with Docker and Podman. +This section describes how to install the tools needed for CORE-V-Wally. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so Appendix D also describes an option with a Docker container. ### Open Source Software Installation From bb11de0f4c31f8f135d5914dac815e5209b6c078 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 17:27:39 -0600 Subject: [PATCH 067/294] Another round of cleanup in the LSU. --- pipelined/src/lsu/lsu.sv | 170 +++++++++++++++++++-------------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index d59934f55..ea3101c8b 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -32,107 +32,107 @@ `include "wally-config.vh" module lsu ( - input logic clk, reset, - input logic StallM, FlushM, StallW, FlushW, - output logic LSUStallM, // LSU stalls pipeline during a multicycle operation + input logic clk,set, + input logic StallM,ushM, StallW, FlushW, + output logic LSUStallM, // LSU stalls pipeline during a multicycle operation // connected to cpu (controls) - input logic [1:0] MemRWM, // Read/Write control - input logic [2:0] Funct3M, // Size of memory operation - input logic [6:0] Funct7M, // Atomic memory operation function - input logic [1:0] AtomicM, // Atomic memory operation - input logic FlushDCacheM, // Flush D cache to next level of memory - output logic CommittedM, // Delay interrupts while memory operation in flight - output logic SquashSCW, // Store conditional failed disable write to GPR - output logic DCacheMiss, // D cache miss for performance counters - output logic DCacheAccess, // D cache memory access for performance counters + input logic [1:0] MemRWM, // Read/Write control + input logic [2:0] Funct3M, // Size of memory operation + input logic [6:0] Funct7M, // Atomic memory operation function + input logic [1:0] AtomicM, // Atomic memory operation + input logic FlushDCacheM, // Flush D cache to next level of memory + output logic CommittedM, // Delay interrupts while memory operation in flight + output logic SquashSCW, // Store conditional failed disable write to GPR + output logic DCacheMiss, // D cache miss for performance counters + output logic DCacheAccess, // D cache memory access for performance counters // address and write data - input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address - output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address - input logic [`XLEN-1:0] WriteDataM, // Write data from IEU - output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU + input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address + output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address + input logic [`XLEN-1:0] WriteDataM, // Write data from IEU + output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU // cpu privilege - input logic [1:0] PrivilegeModeW, // Current privilege mode - input logic BigEndianM, // Swap byte order to big endian - input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries + input logic [1:0] PrivilegeModeW, // Current privilege mode + input logic BigEndianM, // Swap byte order to big endian + input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries // fpu - input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU - input logic FpLoadStoreM, // Selects FPU as store for write data + input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU + input logic FpLoadStoreM, // Selects FPU as store for write data // faults - output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions - output logic LoadMisalignedFaultM, // Load address misaligned fault - output logic LoadAccessFaultM, // Load access fault (PMA) - output logic HPTWInstrAccessFaultM, // HPTW generated access fault during instruction fetch + output logic LoadPageFaultM,oreAmoPageFaultM, // Page fault exceptions + output logic LoadMisalignedFaultM, // Load address misaligned fault + output logic LoadAccessFaultM, // Load access fault (PMA) + output logic HPTWInstrAccessFaultM, // HPTW generated access fault during instruction fetch // cpu hazard unit (trap) - output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault - output logic StoreAmoAccessFaultM, // Store or AMO access fault - // connect to ahb - output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU - input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU - output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU - input logic LSUHREADY, // Bus ready from LSU to EBU - output logic LSUHWRITE, // Bus write operation from LSU to EBU - output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU - output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU - output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU - output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU - // page table walker - input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR - input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege - input logic [1:0] STATUS_MPP, // Machine previous privilege mode - input logic [`XLEN-1:0] PCF, // Fetch PC - input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk - input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits - output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB - output logic [1:0] PageType, // Type of page table entry to write to ITLB - output logic ITLBWriteF, // Write PTE to ITLB - output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE - input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit + output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault + output logic StoreAmoAccessFaultM, // Store or AMO access fault + // connect to ahb + output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU + input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU + output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU + input logic LSUHREADY, // Bus ready from LSU to EBU + output logic LSUHWRITE, // Bus write operation from LSU to EBU + output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU + output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU + output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU + output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU + // page table walker + input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR + input logic STATUS_MXR,ATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege + input logic [1:0] STATUS_MPP, // Machine previous privilege mode + input logic [`XLEN-1:0] PCF, // Fetch PC + input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk + input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits + output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB + output logic [1:0] PageType, // Type of page table entry to write to ITLB + output logic ITLBWriteF, // Write PTE to ITLB + output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE + input var logic [7:0] PMPCFG_ARRAY_REGW[P_ENTRIES-1:0], // PMP configuration from privileged unit input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit ); - logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer - logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer - logic [`PA_BITS-1:0] PAdrM; // Physical memory address - logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address + logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer + logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer + logic [`PA_BITS-1:0] PAdrM; // Physical memory address + logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address - logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal - logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC - logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size - logic [6:0] LSUFunct7M; // AMO function gated by HPTW - logic [1:0] LSUAtomicM; // AMO signal gated by HPTW + logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal + logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC + logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size + logic [6:0] LSUFunct7M; // AMO function gated by HPTW + logic [1:0] LSUAtomicM; // AMO signal gated by HPTW - logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 + logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic DCacheStallM; // D$ busy with multicycle operation - logic BusStall; // Bus interface busy with multicycle operation - logic HPTWStall; // HPTW busy with multicycle operation + logic DCacheStallM; // D$ busy with multicycle operation + logic BusStall; // Bus interface busy with multicycle operation + logic HPTWStall; // HPTW busy with multicycle operation - logic CacheableM; // PMA indicates memory address is cacheable - logic BusCommittedM; // Bus memory operation in flight, delay interrupts - logic DCacheCommittedM; // D$ memory operation started, delay interrupts + logic CacheableM; // PMA indicates memory address is cacheable + logic BusCommittedM; // Bus memory operation in flight, delay interrupts + logic DCacheCommittedM; // D$ memory operation started, delay interrupts - logic [`LLEN-1:0] DTIMReadDataWordM; // DTIM read data - logic [`LLEN-1:0] DCacheReadDataWordM; // D$ read data - logic [`LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data - logic [`LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data - logic [`LLEN-1:0] ReadDataWordM; // Read data before subword selection - logic [`LLEN-1:0] ReadDataM; // Final read data + logic [`LLEN-1:0] DTIMReadDataWordM; // DTIM read data + logic [`LLEN-1:0] DCacheReadDataWordM; // D$ read data + logic [`LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data + logic [`LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data + logic [`LLEN-1:0] ReadDataWordM; // Read data before subword selection + logic [`LLEN-1:0] ReadDataM; // Final read data - logic [`XLEN-1:0] IHWriteDataM; // IEU or HPTW write data - logic [`XLEN-1:0] IMAWriteDataM; // IEU, HPTW, or AMO write data - logic [`LLEN-1:0] IMAFWriteDataM; // IEU, HPTW, AMO, or FPU write data - logic [`LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data - logic [`LLEN-1:0] LSUWriteDataM; // Final write data - logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write + logic [`XLEN-1:0] IHWriteDataM; // IEU or HPTW write data + logic [`XLEN-1:0] IMAWriteDataM; // IEU, HPTW, or AMO write data + logic [`LLEN-1:0] IMAFWriteDataM; // IEU, HPTW, AMO, or FPU write data + logic [`LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data + logic [`LLEN-1:0] LSUWriteDataM; // Final write data + logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write - logic DTLBMissM; // DTLB miss causes HPTW walk - logic DTLBWriteM; // Writes PTE and PageType to DTLB - logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits - logic LSULoadAccessFaultM; // Load acces fault - logic LSUStoreAmoAccessFaultM; // Store access fault - logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle - logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation - logic SelDTIM; // Select DTIM rather than bus or D$ + logic DTLBMissM; // DTLB miss causes HPTW walk + logic DTLBWriteM; // Writes PTE and PageType to DTLB + logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits + logic LSULoadAccessFaultM; // Load acces fault + logic LSUStoreAmoAccessFaultM; // Store access fault + logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle + logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation + logic SelDTIM; // Select DTIM rather than bus or D$ ///////////////////////////////////////////////////////////////////////////////////////////// From a5d402c6ce38e03397427b88083ab01e00f8072e Mon Sep 17 00:00:00 2001 From: James Stine Date: Mon, 23 Jan 2023 17:29:58 -0600 Subject: [PATCH 068/294] This adds the Dockerfile for those who might be interested in building a docker container for Wally --- addins/docker/Dockerfile | 107 +++++++++++++++++++++++++++++++++++++++ addins/docker/README.md | 48 ++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100755 addins/docker/Dockerfile create mode 100644 addins/docker/README.md diff --git a/addins/docker/Dockerfile b/addins/docker/Dockerfile new file mode 100755 index 000000000..e06fa039d --- /dev/null +++ b/addins/docker/Dockerfile @@ -0,0 +1,107 @@ +# Compliance Development Environment Image +FROM debian + +# UPDATE / UPGRADE +RUN apt update + +# INSTALL +RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano + +RUN pip3 install chardet==3.0.4 +RUN pip3 install urllib3==1.22 +RUN pip3 install testresources +RUN pip3 install riscof --ignore-installed PyYAML +RUN echo "root:wally" | chpasswd + +# ADD RISCV +WORKDIR /opt/riscv + +# Create a user group 'xyzgroup' +ARG USERNAME=cad +ARG USER_UID=1000 +ARG USER_GID=$USER_UID + +# Create the user +RUN groupadd --gid $USER_GID $USERNAME \ + && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \ + # [Optional] Add sudo support. Omit if you don't need to install software after connecting. + && apt-get update \ + && apt-get install -y sudo \ + && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \ + && chmod 0440 /etc/sudoers.d/$USERNAME + +# Change RISCV user +run chown -Rf cad:cad /opt + +# Add cad user +USER $USERNAME + +# SET ENVIRONMENT VARIABLES +ENV RISCV=/opt/riscv +ENV PATH=$PATH:$RISCV/bin + +# TOOLCHAIN +RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \ + cd riscv-gnu-toolchain && \ + ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \ + make --jobs && \ + make install + +# elf2hex +ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +WORKDIR /opt/riscv +RUN git clone https://github.com/sifive/elf2hex.git && \ + cd elf2hex && \ + autoreconf -i && \ + ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \ + make && \ + make install + +# QEMU +WORKDIR /opt/riscv +RUN git clone --recurse-submodules https://github.com/qemu/qemu && \ + cd qemu && \ + ./configure --target-list=riscv64-softmmu --prefix=$RISCV && \ + make --jobs && \ + make install + +# Spike +WORKDIR /opt/riscv +RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \ + mkdir riscv-isa-sim/build && \ + cd riscv-isa-sim/build && \ + ../configure --prefix=$RISCV --enable-commitlog && \ + make --jobs && \ + make install && \ + cd ../arch_test_target/spike/device && \ + sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \ + sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include + +# SAIL +WORKDIR /opt/riscv +RUN opam init -y --disable-sandboxing +RUN opam switch create ocaml-base-compiler.4.06.1 +RUN opam install sail -y +RUN eval $(opam config env) && \ + cd $RISCV && \ + git clone https://github.com/riscv/sail-riscv.git && \ + cd sail-riscv && \ + make && \ + ARCH=RV32 make && \ + ARCH=RV64 make && \ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32 + +# Buildroot +WORKDIR /opt/riscv +RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git +ENV export WALLY=/opt/riscv/riscv-wally +RUN git clone https://github.com/buildroot/buildroot.git && \ + cd buildroot && \ + git checkout 2021.05 && \ + cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \ + cp ./board/wally/main.config .config && \ + make --jobs + +# change to cad's hometown +WORKDIR /home/cad diff --git a/addins/docker/README.md b/addins/docker/README.md new file mode 100644 index 000000000..135c7e744 --- /dev/null +++ b/addins/docker/README.md @@ -0,0 +1,48 @@ +Installing Wally, RISC-V tools, and Imperas tests from source gives you maximum control, but has several disadvantages: + +-Building the executables takes several hours. +-Linux is poorly standardized, and the build steps might not work on your version +-The source files are constantly changing, and the versions you download might not be compatible with this textbook flow. + +Docker is a tools to run applications in a prepackaged container +including all of the operating system support required. Wally offers +a ~30GB container image with the open-source tools pre-installed from +Section D.1. In particular, using the container solves the long build +time for gcc and the fussy installation of sail. The container runs on +any platform supporting Docker, including Windows and Mac as well as +Linux. It can access files outside the container, including local +installation of CAD tools such as Questa, and a local clone of the +core-v-wally repository. + +Docker can be run on most operating systems, including Linux, Windows, +and Mac. The Wally Docker container is hosted at DockerHub +(http://docker.io). + +Podman is a more secure and easier-to-use variation of Docker for +Linux developed by RedHat. Both Docker and Podman run the same +containers. + +This directory has a copy of the file utilized to create the Docker +for the toolchain discussed in the text. To build this docker, you can +type the following where the last argument is the name where you want +to store your docker. + +docker build -t docker.io/wallysoc/wally-docker:latest . + +This can also be changed if you make a mistake by using the tag +command. For example, if I wanted to change my docker from +wally-docker to wally-docker2, I would type: + +docker tag wallysoc/wally-docker:latest docker.io/wallysoc/wally-docker2:latest + +Once you build your docker, you can run it as given in the Readme. +However, you can also push it to DockerHub with the following command. + +docker push docker.io/wallysoc/wally-docker:latest + +To run your docker, you can type the following at a command prompt or +terminal. + +docker run -it -p 8080:8080 docker.io/wallysoc/wally-docker + + From e1c121fe0d12a60533c00bf63d595dc75647ae9c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 17:38:30 -0600 Subject: [PATCH 069/294] Oups fixed bug from the last commit. --- pipelined/src/lsu/lrsc.sv | 9 +++++---- pipelined/src/lsu/lsu.sv | 10 +++++----- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index 7edae6b81..c08c9f817 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -31,13 +31,14 @@ `include "wally-config.vh" module lrsc( - input logic clk, reset, + input logic clk, + input logic reset, input logic StallW, - input logic MemReadM, + input logic MemReadM, // Memory read input logic [1:0] PreLSURWM, output logic [1:0] LSURWM, - input logic [1:0] LSUAtomicM, - input logic [`PA_BITS-1:0] PAdrM, // from mmu to dcache + input logic [1:0] LSUAtomicM, + input logic [`PA_BITS-1:0] PAdrM, // from mmu to dcache output logic SquashSCW ); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index ea3101c8b..f89fe0da4 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -32,8 +32,8 @@ `include "wally-config.vh" module lsu ( - input logic clk,set, - input logic StallM,ushM, StallW, FlushW, + input logic clk, reset, + input logic StallM, FlushM, StallW, FlushW, output logic LSUStallM, // LSU stalls pipeline during a multicycle operation // connected to cpu (controls) input logic [1:0] MemRWM, // Read/Write control @@ -58,7 +58,7 @@ module lsu ( input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU input logic FpLoadStoreM, // Selects FPU as store for write data // faults - output logic LoadPageFaultM,oreAmoPageFaultM, // Page fault exceptions + output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions output logic LoadMisalignedFaultM, // Load address misaligned fault output logic LoadAccessFaultM, // Load access fault (PMA) output logic HPTWInstrAccessFaultM, // HPTW generated access fault during instruction fetch @@ -77,7 +77,7 @@ module lsu ( output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU // page table walker input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR - input logic STATUS_MXR,ATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege input logic [1:0] STATUS_MPP, // Machine previous privilege mode input logic [`XLEN-1:0] PCF, // Fetch PC input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk @@ -86,7 +86,7 @@ module lsu ( output logic [1:0] PageType, // Type of page table entry to write to ITLB output logic ITLBWriteF, // Write PTE to ITLB output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE - input var logic [7:0] PMPCFG_ARRAY_REGW[P_ENTRIES-1:0], // PMP configuration from privileged unit + input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit ); From 45094fc7bbb88728125b3237d790bdeb6ee5f4f3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 17:46:28 -0600 Subject: [PATCH 070/294] Added comments to lrsc module. --- pipelined/src/lsu/lrsc.sv | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index c08c9f817..2fe8fb8ad 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -35,18 +35,19 @@ module lrsc( input logic reset, input logic StallW, input logic MemReadM, // Memory read - input logic [1:0] PreLSURWM, - output logic [1:0] LSURWM, - input logic [1:0] LSUAtomicM, - input logic [`PA_BITS-1:0] PAdrM, // from mmu to dcache - output logic SquashSCW + input logic [1:0] PreLSURWM, // Memory operation from the HPTW or IEU [1]: read, [0]: write + output logic [1:0] LSURWM, // Memory operation after potential squash of SC + input logic [1:0] LSUAtomicM, // Atomic memory operaiton + input logic [`PA_BITS-1:0] PAdrM, // Physical memory address + output logic SquashSCW // Squash the store conditional by not allowing rf write ); + // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest. // Handle atomic load reserved / store conditional - logic [`PA_BITS-1:2] ReservationPAdrW; - logic ReservationValidM, ReservationValidW; - logic lrM, scM, WriteAdrMatchM; - logic SquashSCM; + logic [`PA_BITS-1:2] ReservationPAdrW; + logic ReservationValidM, ReservationValidW; + logic lrM, scM, WriteAdrMatchM; + logic SquashSCM; assign lrM = MemReadM & LSUAtomicM[0]; assign scM = PreLSURWM[0] & LSUAtomicM[0]; From 571f11938b76803ecf6eb0c7500f598314d37501 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 17:50:25 -0600 Subject: [PATCH 071/294] Updated gitflow instructions. --- gitflow.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gitflow.txt b/gitflow.txt index 0be54022f..4198302aa 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -29,10 +29,14 @@ Once per sessiosn Fetch upstream and sync fork 1. git fetch upstream -2. git push +2. git merge upstream/main Create pull request 1. gh pr create 2. Must include a title and strongly encourage a body message explaining your changes. 3. Wait for pull request to be approved, rejected, or needs changes. 4. Finish by fetching the upstream and pushing back to your fork. + 1. git fetch upstream + 2. git merge upstream/main + 3. git push + From 1d4c8c8a368e998699868bb8c896092d95d34715 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 17:50:25 -0600 Subject: [PATCH 072/294] Updated gitflow instructions. --- gitflow.txt | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/gitflow.txt b/gitflow.txt index 0be54022f..3ff71a549 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -9,7 +9,7 @@ ## except in compliance with the License, or, at your option, the Apache License version 2.0. You ## may obtain a copy of the License at ## -## https:##solderpad.org/licenses/SHL-2.1/ +## https://solderpad.org/licenses/SHL-2.1/ ## ## Unless required by applicable law or agreed to in writing, any work distributed under the ## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, @@ -29,10 +29,17 @@ Once per sessiosn Fetch upstream and sync fork 1. git fetch upstream -2. git push +2. git merge upstream/main Create pull request -1. gh pr create -2. Must include a title and strongly encourage a body message explaining your changes. -3. Wait for pull request to be approved, rejected, or needs changes. -4. Finish by fetching the upstream and pushing back to your fork. +1. git fetch upstream +2. git merge upstream/main +3. git push +4. gh pr create +5. Must include a title and strongly encourage a body message explaining your changes. +6. Wait for pull request to be approved, rejected, or needs changes. +7. Finish by fetching the upstream and pushing back to your fork. + 1. git fetch upstream + 2. git merge upstream/main + 3. git push + From a9df0cf0106f4e37805483cb8100be3ccd22f9c1 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Mon, 23 Jan 2023 16:39:47 -0800 Subject: [PATCH 073/294] Update README.md --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 52f6fe22d..12d7fe1f6 100644 --- a/README.md +++ b/README.md @@ -56,7 +56,7 @@ Run a regression simulation with Questa to prove everything is installed. $ cd pipelined/regression $ ./regression-wally (depends on having Questa installed) -# Tool-chain Installation (Sys Admin) +# Toolchain Installation (Sys Admin) This section describes the open source toolchain installation. These steps should only be done once by the system admin. @@ -102,11 +102,11 @@ First, set up a directory for riscv software in some place such as /opt/riscv. ### Update Tools -Ubuntu users may need to install and update various tools. +Ubuntu users may need to install and update various tools. Beware when cutting and pasting that some lines are long! $ sudo apt update $ sudo apt upgrade - $ sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog + $ sudo apt install git gawk make texinfo bison flex build-essential python3 zlib1g-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.0-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog ### Install RISC-V GCC Cross-Compiler From c8d487b9e62633ae535d9efb3a2cb4d949ceb9b9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 23 Jan 2023 19:02:01 -0600 Subject: [PATCH 074/294] Created missing wires for axi interfaces in fpgaTop.v. --- fpga/src/fpgaTop.v | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 2bcef6adf..95f4582fa 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -226,6 +226,7 @@ module fpgaTop // 64to32 dwidth converter input interface------------------------- wire s01_axi_aclk; wire s01_axi_aresetn; + wire [3:0]s01_axi_awid; wire [31:0]s01_axi_awaddr; wire [7:0]s01_axi_awlen; wire [2:0]s01_axi_awsize; @@ -242,9 +243,11 @@ module fpgaTop wire s01_axi_wlast; wire s01_axi_wvalid; wire s01_axi_wready; + wire [3:0]m01_axi_bid; wire [1:0]s01_axi_bresp; wire s01_axi_bvalid; wire s01_axi_bready; + wire [3:0]m01_axi_bid; wire [31:0]s01_axi_araddr; wire [7:0]s01_axi_arlen; wire [2:0]s01_axi_arsize; @@ -256,6 +259,7 @@ module fpgaTop wire [3:0]s01_axi_arqos; // wire s01_axi_arvalid; wire s01_axi_arready; + wire [3:0]m01_axi_rid; wire [63:0]s01_axi_rdata; wire [1:0]s01_axi_rresp; wire s01_axi_rlast; @@ -338,6 +342,7 @@ module fpgaTop wire SDCout_axi_rready; // Output Interface + wire [3:0]m01_axi_awid; wire [31:0]m01_axi_awaddr; wire [7:0]m01_axi_awlen; wire [2:0]m01_axi_awsize; @@ -354,9 +359,11 @@ module fpgaTop wire m01_axi_wlast; wire m01_axi_wvalid; wire m01_axi_wready; + wire [3:0] m01_axi_bid; wire [1:0]m01_axi_bresp; wire m01_axi_bvalid; wire m01_axi_bready; + wire [3:0] m01_axi_arid; wire [31:0]m01_axi_araddr; wire [7:0]m01_axi_arlen; wire [2:0]m01_axi_arsize; @@ -368,6 +375,7 @@ module fpgaTop wire [3:0]m01_axi_arqos; wire m01_axi_arvalid; wire m01_axi_arready; + wire [3:0] m01_axi_rid; wire [31:0]m01_axi_rdata; wire [1:0]m01_axi_rresp; wire m01_axi_rlast; From 07e279b5b5d7da29c92d9dbda56b10bad1e4dac1 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 23 Jan 2023 19:30:29 -0600 Subject: [PATCH 075/294] Modified makefile. Added axi protocol converter IP. --- fpga/generator/Makefile | 5 +++-- fpga/generator/wally.tcl | 1 + fpga/generator/xlnx_axi_prtcl_conv.tcl | 23 +++++++++++++++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 fpga/generator/xlnx_axi_prtcl_conv.tcl diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 8efd9f6d1..b200a22de 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,5 +1,5 @@ dst := IP -sdc_src := ~/repos/sdc.tar.gz +sdc_src := ../../../sdc.tar.gz # vcu118 #export XILINX_PART := xcvu9p-flga2104-2L-e #export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 @@ -22,7 +22,8 @@ IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ahblite_axi_bridge.log \ $(dst)/xlnx_axi_crossbar.log \ $(dst)/xlnx_axi_dwidth_conv_32to64.log \ - $(dst)/xlnx_axi_dwidth_conv_64to32.log + $(dst)/xlnx_axi_dwidth_conv_64to32.log \ + $(dst)/xlnx_axi_prtcl_conv.log SDC: cp $(sdc_src) ../src/ diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index e0de591b7..55f65b31b 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -18,6 +18,7 @@ read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci +read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci # read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] diff --git a/fpga/generator/xlnx_axi_prtcl_conv.tcl b/fpga/generator/xlnx_axi_prtcl_conv.tcl new file mode 100644 index 000000000..76b6fc6cd --- /dev/null +++ b/fpga/generator/xlnx_axi_prtcl_conv.tcl @@ -0,0 +1,23 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_prtcl_conv + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 From d495d7b04d96654fbe5d9930d45bc4edcd7f9b5b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 22:03:49 -0600 Subject: [PATCH 076/294] Added comments about needing move ebufsm into a new module. --- gitflow.txt | 4 ++-- pipelined/src/ebu/ebu.sv | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/gitflow.txt b/gitflow.txt index 3ff71a549..b85324605 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -40,6 +40,6 @@ Create pull request 6. Wait for pull request to be approved, rejected, or needs changes. 7. Finish by fetching the upstream and pushing back to your fork. 1. git fetch upstream - 2. git merge upstream/main - 3. git push + 2. git merge upstream/main # sync your clone with the upstream + 3. git push # sync your fork with the upstream and clone diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index 4a4cd5d5b..a75948023 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -144,6 +144,8 @@ module ebu ( // a burst is completed. //////////////////////////////////////////////////////////////////////////////////////////////////// + // *** move into a separate module to match the figures 9.8 and 9.8 + assign both = LSUReq & IFUReq; flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState); always_comb From 89698a929e3215cc0e0ec57d42fe62020fe735e1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 23 Jan 2023 23:10:10 -0600 Subject: [PATCH 077/294] Moved ebufsmarb into its own module. --- pipelined/src/ebu/ebu.sv | 76 ++------------------- pipelined/src/ebu/ebuarbfsm.sv | 121 +++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+), 72 deletions(-) create mode 100644 pipelined/src/ebu/ebuarbfsm.sv diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index a75948023..d4e87de2a 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -66,8 +66,6 @@ module ebu ( output logic HMASTLOCK // AHB master lock. Wally does not use ); - typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; - statetype CurrState, NextState; logic LSUDisable; logic LSUSelect; @@ -75,7 +73,6 @@ module ebu ( logic IFURestore; logic IFUDisable; logic IFUSelect; - logic both; // Both the LSU and IFU request at the same time logic [`PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; @@ -92,12 +89,6 @@ module ebu ( logic IFUReq; logic LSUReq; - logic BeatCntEn; - logic [4-1:0] NextBeatCount, BeatCount; // Position within a burst transfer - logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst - logic CntReset; - logic [3:0] Threshold; // Number of beats derived from HBURST - logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration assign HCLK = clk; @@ -137,68 +128,9 @@ module ebu ( assign HWSTRB = LSUHWSTRB; // HRDATA is sent to all controllers at the core level. - - //////////////////////////////////////////////////////////////////////////////////////////////////// - // Aribtration scheme - // FSM decides if arbitration needed. Arbitration is held until the last beat of - // a burst is completed. - //////////////////////////////////////////////////////////////////////////////////////////////////// - - // *** move into a separate module to match the figures 9.8 and 9.8 - - assign both = LSUReq & IFUReq; - flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState); - always_comb - case (CurrState) - IDLE: if (both) NextState = ARBITRATE; - else NextState = IDLE; - ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE; - else NextState = ARBITRATE; - default: NextState = IDLE; - endcase - - // basic arb always selects LSU when both - // replace this block for more sophisticated arbitration as needed. - // Controller 0 (IFU) - assign IFUSave = CurrState == IDLE & both; - assign IFURestore = CurrState == ARBITRATE; - assign IFUDisable = CurrState == ARBITRATE; - assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq; - // Controller 1 (LSU) - // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. - // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining - // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request. - // This is necessary because the pipeline is stalled for the entire duration of both transactions, - // and the LSU memory request will stil be active. - flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD); - assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD)); - assign LSUSelect = NextState == ARBITRATE ? 1'b1: LSUReq; - - //////////////////////////////////////////////////////////////////////////////////////////////////// - // Burst mode logic - //////////////////////////////////////////////////////////////////////////////////////////////////// - - flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount); - assign NextBeatCount = BeatCount + 1'b1; - - assign CntReset = NextState == IDLE; - assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. - assign BeatCntEn = (NextState == ARBITRATE & HREADY); - - // Used to store data from data phase of AHB. - flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD); - - // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. - always_comb begin - case(HBURST) - 0: Threshold = 4'b0000; - 3: Threshold = 4'b0011; // INCR4 - 5: Threshold = 4'b0111; // INCR8 - 7: Threshold = 4'b1111; // INCR16 - default: Threshold = 4'b0000; // INCR without end. - endcase - end - - + ebufsmarb ebufsmarb(.HCLK, .HRESETn, .HBURST, .HREADY, .LSUReq, .IFUReq, .IFUSave, + .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect); endmodule + + diff --git a/pipelined/src/ebu/ebuarbfsm.sv b/pipelined/src/ebu/ebuarbfsm.sv new file mode 100644 index 000000000..bd5cfb892 --- /dev/null +++ b/pipelined/src/ebu/ebuarbfsm.sv @@ -0,0 +1,121 @@ +/////////////////////////////////////////// +// ebufsmarb +// +// Written: Ross Thompson ross1728@gmail.com +// Created: 23 January 2023 +// Modified: 23 January 2023 +// +// Purpose: Arbitrates requests from instruction and data streams +// LSU has priority. +// +// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ebufsmarb ( + input logic HCLK, + input logic HRESETn, + input logic [2:0] HBURST, + // AHB burst length + + input logic HREADY, + + input logic LSUReq, + input logic IFUReq, + + + output logic IFUSave, + output logic IFURestore, + output logic IFUDisable, + output logic IFUSelect, + output logic LSUDisable, + output logic LSUSelect); + + typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; + statetype CurrState, NextState; + + logic both; // Both the LSU and IFU request at the same time + logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration + logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst + logic BeatCntEn; + logic [4-1:0] NextBeatCount, BeatCount; // Position within a burst transfer + logic CntReset; + logic [3:0] Threshold; // Number of beats derived from HBURST + + //////////////////////////////////////////////////////////////////////////////////////////////////// + // Aribtration scheme + // FSM decides if arbitration needed. Arbitration is held until the last beat of + // a burst is completed. + //////////////////////////////////////////////////////////////////////////////////////////////////// + + assign both = LSUReq & IFUReq; + flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState); + always_comb + case (CurrState) + IDLE: if (both) NextState = ARBITRATE; + else NextState = IDLE; + ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE; + else NextState = ARBITRATE; + default: NextState = IDLE; + endcase + + // basic arb always selects LSU when both + // replace this block for more sophisticated arbitration as needed. + // Controller 0 (IFU) + assign IFUSave = CurrState == IDLE & both; + assign IFURestore = CurrState == ARBITRATE; + assign IFUDisable = CurrState == ARBITRATE; + assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq; + // Controller 1 (LSU) + // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. + // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining + // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request. + // This is necessary because the pipeline is stalled for the entire duration of both transactions, + // and the LSU memory request will stil be active. + flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); + assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD)); + assign LSUSelect = NextState == ARBITRATE ? 1'b1: LSUReq; + + //////////////////////////////////////////////////////////////////////////////////////////////////// + // Burst mode logic + //////////////////////////////////////////////////////////////////////////////////////////////////// + + flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount); + assign NextBeatCount = BeatCount + 1'b1; + + assign CntReset = NextState == IDLE; + assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. + assign BeatCntEn = (NextState == ARBITRATE & HREADY); + + // Used to store data from data phase of AHB. + flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD); + + // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. + always_comb begin + case(HBURST) + 0: Threshold = 4'b0000; + 3: Threshold = 4'b0011; // INCR4 + 5: Threshold = 4'b0111; // INCR8 + 7: Threshold = 4'b1111; // INCR16 + default: Threshold = 4'b0000; // INCR without end. + endcase + end +endmodule From 30b085911ae5b027fe563405b337891a2411982b Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 24 Jan 2023 05:42:34 -0800 Subject: [PATCH 078/294] bpred tab cleanup --- pipelined/src/ifu/bpred.sv | 54 +++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index ab47d678f..94d0d692f 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -29,36 +29,36 @@ `include "wally-config.vh" module bpred ( - input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - // Fetch stage - // the prediction - input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class - input logic [`XLEN-1:0] PCNextF, // Next Fetch Address - input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 - output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction - output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage + input logic clk, reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, + // Fetch stage + // the prediction + input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class + input logic [`XLEN-1:0] PCNextF, // Next Fetch Address + input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 + output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction + output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage - // Update Predictor - input logic [`XLEN-1:0] PCF, // Fetch stage instruction address - input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took - input logic [`XLEN-1:0] PCE, // Execution stage instruction address - input logic [`XLEN-1:0] PCM, // Memory stage instruction address + // Update Predictor + input logic [`XLEN-1:0] PCF, // Fetch stage instruction address + input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took + input logic [`XLEN-1:0] PCE, // Execution stage instruction address + input logic [`XLEN-1:0] PCM, // Memory stage instruction address - // Branch and jump outcome - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) - output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + // Branch and jump outcome + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) + output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br - // Report branch prediction status - output logic BPPredWrongE, // Prediction is wrong - output logic DirPredictionWrongM, // Prediction direction is wrong - output logic BTBPredPCWrongM, // Prediction target wrong - output logic RASPredPCWrongM, // RAS prediction is wrong - output logic PredictionInstrClassWrongM // Class prediction is wrong - ); + // Report branch prediction status + output logic BPPredWrongE, // Prediction is wrong + output logic DirPredictionWrongM, // Prediction direction is wrong + output logic BTBPredPCWrongM, // Prediction target wrong + output logic RASPredPCWrongM, // RAS prediction is wrong + output logic PredictionInstrClassWrongM // Class prediction is wrong +); logic BTBValidF; logic [1:0] DirPredictionF; From 0e5ea5f51d4e7bee18dab0e3fb2402cff4e775f4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 24 Jan 2023 06:14:31 -0800 Subject: [PATCH 079/294] bpred input spacing cleanup --- pipelined/src/ifu/bpred.sv | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 94d0d692f..d321169f4 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -29,27 +29,27 @@ `include "wally-config.vh" module bpred ( - input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, + input logic clk, reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // Fetch stage // the prediction - input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class - input logic [`XLEN-1:0] PCNextF, // Next Fetch Address - input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 + input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class + input logic [`XLEN-1:0] PCNextF, // Next Fetch Address + input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage // Update Predictor - input logic [`XLEN-1:0] PCF, // Fetch stage instruction address - input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took - input logic [`XLEN-1:0] PCE, // Execution stage instruction address - input logic [`XLEN-1:0] PCM, // Memory stage instruction address + input logic [`XLEN-1:0] PCF, // Fetch stage instruction address + input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took + input logic [`XLEN-1:0] PCE, // Execution stage instruction address + input logic [`XLEN-1:0] PCM, // Memory stage instruction address // Branch and jump outcome - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic [`XLEN-1:0] dPCLinkE, // The address following the branch instruction. (AKA Fall through address) output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br // Report branch prediction status From f37153cce879bd24b21c5ae856b9d75ae4edca3d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 11:28:41 -0600 Subject: [PATCH 080/294] Clarified the git fork work flow. --- gitflow.txt | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/gitflow.txt b/gitflow.txt index b85324605..bc89d2bf0 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -21,21 +21,29 @@ Setup 1. goto github and fork openhwgroup/cvw.git 2. clone: git clone --recurse-submodules git@ross144/cvw.git 3. git remote add upstream https://github.com/openhwgroup/cvw.git +4. install gh (github command line interface) +type -p curl >/dev/null || sudo apt install curl -y +curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ +&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \ +&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ +&& sudo apt update \ +&& sudo apt install gh -y -Once per sessiosn +Once per session (This authorizes gh to use your github account) 1. gh auth login 2. Use ssh and point to your public key 3. Copy one-time code from terminal to browser Fetch upstream and sync fork -1. git fetch upstream -2. git merge upstream/main +1. git fetch upstream # fetch the upstream openhwgroup/cvw into your local clone +2. git merge upstream/main # merge the upstream openhwgroup/cvw into your local clone +3. git push # pushes changes back to your fork. Now all three should be in sync Create pull request -1. git fetch upstream -2. git merge upstream/main -3. git push -4. gh pr create +1. git fetch upstream # fetch the upstream openhwgroup/cvw into your local clone +2. git merge upstream/main # merge the upstream openhwgroup/cvw into your local clone +3. git push # pushes changes back to your fork. Now all three should be in sync +4. gh pr create # Create a pull request. 5. Must include a title and strongly encourage a body message explaining your changes. 6. Wait for pull request to be approved, rejected, or needs changes. 7. Finish by fetching the upstream and pushing back to your fork. From 8464af84cee1bdd52b3e0ddb46e2024b8cbbe0fd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 13:24:44 -0600 Subject: [PATCH 081/294] Updated git flow documentation. --- gitflow.txt | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/gitflow.txt b/gitflow.txt index bc89d2bf0..57d79333b 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -35,19 +35,16 @@ Once per session (This authorizes gh to use your github account) 3. Copy one-time code from terminal to browser Fetch upstream and sync fork -1. git fetch upstream # fetch the upstream openhwgroup/cvw into your local clone -2. git merge upstream/main # merge the upstream openhwgroup/cvw into your local clone -3. git push # pushes changes back to your fork. Now all three should be in sync +1. git pull upstream main # fetch and merge the upstream openhwgroup/cvw into your local clone +2. git push # pushes changes back to your fork. Now all three should be in sync Create pull request -1. git fetch upstream # fetch the upstream openhwgroup/cvw into your local clone -2. git merge upstream/main # merge the upstream openhwgroup/cvw into your local clone +1. git pull upstream main # fetch and merge the upstream openhwgroup/cvw into your local clone 3. git push # pushes changes back to your fork. Now all three should be in sync 4. gh pr create # Create a pull request. 5. Must include a title and strongly encourage a body message explaining your changes. 6. Wait for pull request to be approved, rejected, or needs changes. 7. Finish by fetching the upstream and pushing back to your fork. - 1. git fetch upstream - 2. git merge upstream/main # sync your clone with the upstream - 3. git push # sync your fork with the upstream and clone + 1. git pull upstream main # fetch and merge the upstream openhwgroup/cvw into your local clone + 3. git push # sync your fork with the upstream and clone From 879cb77b9027fd856cb418266d080664c049b4c6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 16:00:27 -0600 Subject: [PATCH 082/294] Moved branch predictor files into separate sub-directory. --- pipelined/src/ifu/{ => brpred}/BTBPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/RAsPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/bpred.sv | 0 pipelined/src/ifu/{ => brpred}/foldedgshare.sv | 0 pipelined/src/ifu/{ => brpred}/globalHistoryPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/globalhistory.sv | 0 pipelined/src/ifu/{ => brpred}/gshare.sv | 0 pipelined/src/ifu/{ => brpred}/localHistoryPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/oldgsharepredictor.sv | 0 pipelined/src/ifu/{ => brpred}/oldgsharepredictor2.sv | 0 pipelined/src/ifu/{ => brpred}/optgshare.sv | 0 pipelined/src/ifu/{ => brpred}/satCounter2.sv | 0 pipelined/src/ifu/{ => brpred}/speculativeglobalhistory.sv | 0 pipelined/src/ifu/{ => brpred}/speculativegshare.sv | 0 pipelined/src/ifu/{ => brpred}/twoBitPredictor.sv | 0 15 files changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/ifu/{ => brpred}/BTBPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/RAsPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/bpred.sv (100%) rename pipelined/src/ifu/{ => brpred}/foldedgshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/globalHistoryPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/globalhistory.sv (100%) rename pipelined/src/ifu/{ => brpred}/gshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/localHistoryPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/oldgsharepredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/oldgsharepredictor2.sv (100%) rename pipelined/src/ifu/{ => brpred}/optgshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/satCounter2.sv (100%) rename pipelined/src/ifu/{ => brpred}/speculativeglobalhistory.sv (100%) rename pipelined/src/ifu/{ => brpred}/speculativegshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/twoBitPredictor.sv (100%) diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/brpred/BTBPredictor.sv similarity index 100% rename from pipelined/src/ifu/BTBPredictor.sv rename to pipelined/src/ifu/brpred/BTBPredictor.sv diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv similarity index 100% rename from pipelined/src/ifu/RAsPredictor.sv rename to pipelined/src/ifu/brpred/RAsPredictor.sv diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv similarity index 100% rename from pipelined/src/ifu/bpred.sv rename to pipelined/src/ifu/brpred/bpred.sv diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/brpred/foldedgshare.sv similarity index 100% rename from pipelined/src/ifu/foldedgshare.sv rename to pipelined/src/ifu/brpred/foldedgshare.sv diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/brpred/globalHistoryPredictor.sv similarity index 100% rename from pipelined/src/ifu/globalHistoryPredictor.sv rename to pipelined/src/ifu/brpred/globalHistoryPredictor.sv diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv similarity index 100% rename from pipelined/src/ifu/globalhistory.sv rename to pipelined/src/ifu/brpred/globalhistory.sv diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv similarity index 100% rename from pipelined/src/ifu/gshare.sv rename to pipelined/src/ifu/brpred/gshare.sv diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/brpred/localHistoryPredictor.sv similarity index 100% rename from pipelined/src/ifu/localHistoryPredictor.sv rename to pipelined/src/ifu/brpred/localHistoryPredictor.sv diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/brpred/oldgsharepredictor.sv similarity index 100% rename from pipelined/src/ifu/oldgsharepredictor.sv rename to pipelined/src/ifu/brpred/oldgsharepredictor.sv diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/brpred/oldgsharepredictor2.sv similarity index 100% rename from pipelined/src/ifu/oldgsharepredictor2.sv rename to pipelined/src/ifu/brpred/oldgsharepredictor2.sv diff --git a/pipelined/src/ifu/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv similarity index 100% rename from pipelined/src/ifu/optgshare.sv rename to pipelined/src/ifu/brpred/optgshare.sv diff --git a/pipelined/src/ifu/satCounter2.sv b/pipelined/src/ifu/brpred/satCounter2.sv similarity index 100% rename from pipelined/src/ifu/satCounter2.sv rename to pipelined/src/ifu/brpred/satCounter2.sv diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv similarity index 100% rename from pipelined/src/ifu/speculativeglobalhistory.sv rename to pipelined/src/ifu/brpred/speculativeglobalhistory.sv diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv similarity index 100% rename from pipelined/src/ifu/speculativegshare.sv rename to pipelined/src/ifu/brpred/speculativegshare.sv diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/brpred/twoBitPredictor.sv similarity index 100% rename from pipelined/src/ifu/twoBitPredictor.sv rename to pipelined/src/ifu/brpred/twoBitPredictor.sv From 7ae6b1868eca794bc0da9b060219a2961c251ec6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 16:12:35 -0600 Subject: [PATCH 083/294] Partial BTB cleanup. --- pipelined/src/ifu/brpred/BTBPredictor.sv | 114 ----------------------- pipelined/src/ifu/brpred/bpred.sv | 13 ++- 2 files changed, 6 insertions(+), 121 deletions(-) delete mode 100644 pipelined/src/ifu/brpred/BTBPredictor.sv diff --git a/pipelined/src/ifu/brpred/BTBPredictor.sv b/pipelined/src/ifu/brpred/BTBPredictor.sv deleted file mode 100644 index ba5fe374a..000000000 --- a/pipelined/src/ifu/brpred/BTBPredictor.sv +++ /dev/null @@ -1,114 +0,0 @@ -/////////////////////////////////////////// -// ram2p1r1wb -// -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 15, 2021 -// Modified: -// -// Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want -// to encode to reduce storage), valid, target PC. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module BTBPredictor - #(parameter int Depth = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] LookUpPC, - output logic [`XLEN-1:0] TargetPC, - output logic [3:0] InstrClass, - output logic Valid, - // update - input logic UpdateEN, - input logic [`XLEN-1:0] UpdatePC, - input logic [`XLEN-1:0] UpdateTarget, - input logic [3:0] UpdateInstrClass, - input logic UpdateInvalid - ); - - localparam TotalDepth = 2 ** Depth; - logic [TotalDepth-1:0] ValidBits; - logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ; - logic UpdateENQ; - - - // hashing function for indexing the PC - // We have Depth bits to index, but XLEN bits as the input. - // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if - // using compressed instructions. XOR bit 1 with the MSB of index. - assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]}; - assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]}; - - - flopenr #(Depth) UpdatePCIndexReg(.clk(clk), - .reset(reset), - .en(~StallE), - .d(UpdatePCIndex), - .q(UpdatePCIndexQ)); - - // The valid bit must be resetable. - always_ff @ (posedge clk) begin - if (reset) begin - ValidBits <= #1 {TotalDepth{1'b0}}; - end else - if (UpdateENQ) begin - ValidBits[UpdatePCIndexQ] <= #1 ~ UpdateInvalid; - end - end - assign Valid = ValidBits[LookUpPCIndexQ]; - - - flopenr #(1) UpdateENReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(UpdateEN), - .q(UpdateENQ)); - - - flopenr #(Depth) LookupPCIndexReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(LookUpPCIndex), - .q(LookUpPCIndexQ)); - - - - // the BTB contains the target address. - // Another optimization may be using a PC relative address. - // *** need to add forwarding. - - // *** optimize for byte write enables - // *** switch to ram2p1r1wbefix - ram2p1r1wb #(Depth, `XLEN+4) memory(.clk(clk), - .reset(reset), - .ra1(LookUpPCIndex), - .rd1({{InstrClass, TargetPC}}), - .ren1(~StallF), - .wa2(UpdatePCIndex), - .wd2({UpdateInstrClass, UpdateTarget}), - .wen2(UpdateEN), - .bwe2({4'hF, {`XLEN{1'b1}}})); // *** definitely not right. - - -endmodule diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index ab47d678f..9c5efe306 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -135,20 +135,19 @@ module bpred ( // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets - // *** getting to many false positivies from the BTB, we need a partial TAG to reduce this. - BTBPredictor TargetPredictor(.clk(clk), + btb TargetPredictor(.clk(clk), .reset(reset), .*, // Stalls and flushes - .LookUpPC(PCNextF), - .TargetPC(BTBPredPCF), + .PCNextF, + .BTBPredPCF, .InstrClass(PredInstrClassF), .Valid(BTBValidF), // update .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), - .UpdatePC(PCE), - .UpdateTarget(IEUAdrE), + .PCE, + .IEUAdrE, .UpdateInvalid(PredictionInstrClassWrongE), - .UpdateInstrClass(InstrClassE)); + .InstrClassE); // Part 3 RAS // *** need to add the logic to restore RAS on flushes. We will use incr for this. From 3d07f7a3a2f83a56ca1f76bfd09b53641942ebe0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 17:19:51 -0600 Subject: [PATCH 084/294] Moved and ranamed btb to btb.sv Fixed btb to use the fixed port 2 sram. --- pipelined/src/generic/mem/ram2p1r1wb.sv | 8 +- pipelined/src/generic/mem/ram2p1rwbefix.sv | 4 +- pipelined/src/ifu/brpred/btb.sv | 110 +++++++++++++++++++++ 3 files changed, 117 insertions(+), 5 deletions(-) create mode 100644 pipelined/src/ifu/brpred/btb.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv index 5e79d5e24..7ac29e1df 100644 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -74,12 +74,14 @@ module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) ( flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q); // read port - assign rd1 = mem[ra1q]; + //assign rd1 = mem[ra1q]; + always_ff @(posedge clk) + if(ren1) rd1 <= mem[ra1]; // write port - assign bwe = {WIDTH{wen2q}} & bwe2; + assign bwe = {WIDTH{wen2}} & bwe2; always_ff @(posedge clk) - mem[wa2q] <= wd2q & bwe | mem[wa2q] & ~bwe; + mem[wa2] <= wd2 & bwe | mem[wa2] & ~bwe; endmodule diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index 9b9beaf9b..ac30343b8 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -59,13 +59,13 @@ module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) ( // Write divided into part for bytes and part for extra msbs if(WIDTH >= 8) - always_ff @(posedge clk) + always @(posedge clk) if (ce2 & we2) for(i = 0; i < WIDTH/8; i++) if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always_ff @(posedge clk) + always @(posedge clk) if (ce2 & we2 & bwe2[WIDTH/8]) mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv new file mode 100644 index 000000000..6666c35f9 --- /dev/null +++ b/pipelined/src/ifu/brpred/btb.sv @@ -0,0 +1,110 @@ +/////////////////////////////////////////// +// btb.sv +// +// Written: Ross Thomposn ross1728@gmail.com +// Created: February 15, 2021 +// Modified: 24 January 2023 +// +// Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions. +// It also guesses the type of instrution; jalr(r), return, jump (jr), or branch. +// +// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module btb + #(parameter int Depth = 10 + ) + (input logic clk, + input logic reset, + input logic StallF, StallE, + input logic [`XLEN-1:0] PCNextF, + output logic [`XLEN-1:0] BTBPredPCF, + output logic [3:0] InstrClass, + output logic Valid, + // update + input logic UpdateEN, + input logic [`XLEN-1:0] PCE, + input logic [`XLEN-1:0] IEUAdrE, + input logic [3:0] InstrClassE, + input logic UpdateInvalid + ); + + localparam TotalDepth = 2 ** Depth; + logic [TotalDepth-1:0] ValidBits; + logic [Depth-1:0] PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ; + logic UpdateENQ; + logic [`XLEN-1:0] ResetPC; + + + // hashing function for indexing the PC + // We have Depth bits to index, but XLEN bits as the input. + // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if + // using compressed instructions. XOR bit 1 with the MSB of index. + assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; + assign ResetPC = `RESET_VECTOR; + assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + //assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + + flopenr #(Depth) PCEIndexReg(.clk(clk), + .reset(reset), + .en(~StallE), + .d(PCEIndex), + .q(PCEIndexQ)); + + // The valid bit must be resetable. + always_ff @ (posedge clk) begin + if (reset) begin + ValidBits <= #1 {TotalDepth{1'b0}}; + end else + if (UpdateENQ) begin + ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid; + end + end + assign Valid = ValidBits[PCNextFIndexQ]; + + + flopenr #(1) UpdateENReg(.clk(clk), + .reset(reset), + .en(~StallF), + .d(UpdateEN), + .q(UpdateENQ)); + + + flopenr #(Depth) LookupPCIndexReg(.clk(clk), + .reset(reset), + .en(~StallF), + .d(PCNextFIndex), + .q(PCNextFIndexQ)); + + + + // the BTB contains the target address. + // Another optimization may be using a PC relative address. + // *** need to add forwarding. + + // *** optimize for byte write enables + + ram2p1r1wbefix #(2**Depth, `XLEN+4) memory( + .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), + .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + +endmodule From 0d7653f1c7f17e7bf6f1fc250270366b4994c364 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 17:22:00 -0600 Subject: [PATCH 085/294] Removed the old two port ram and replaced it with the fixed version. The fixed version is renamed to ram2p1r1wb.sv --- pipelined/src/generic/mem/ram2p1r1wb.sv | 88 ------------------- pipelined/src/generic/mem/ram2p1rwbefix.sv | 6 +- pipelined/src/ifu/brpred/btb.sv | 2 +- pipelined/src/ifu/brpred/foldedgshare.sv | 2 +- pipelined/src/ifu/brpred/globalhistory.sv | 2 +- pipelined/src/ifu/brpred/gshare.sv | 2 +- pipelined/src/ifu/brpred/optgshare.sv | 2 +- .../ifu/brpred/speculativeglobalhistory.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 2 +- pipelined/src/ifu/brpred/twoBitPredictor.sv | 2 +- 10 files changed, 11 insertions(+), 99 deletions(-) delete mode 100644 pipelined/src/generic/mem/ram2p1r1wb.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv deleted file mode 100644 index 7ac29e1df..000000000 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ /dev/null @@ -1,88 +0,0 @@ -/////////////////////////////////////////// -// ram2p1r1wb -// -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 14, 2021 -// Modified: -// -// Purpose: Behavioral model of two port SRAM. While this is synthesizable it will produce a flip flop based memory which -// behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm. -// -// -// to preload this memory we can use the following command -// in modelsim's do file. -// mem load -infile -format -// example -// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) ( - input logic clk, - input logic reset, - - // port 1 is read only - input logic [DEPTH-1:0] ra1, - output logic [WIDTH-1:0] rd1, - input logic ren1, - - // port 2 is write only - input logic [DEPTH-1:0] wa2, - input logic [WIDTH-1:0] wd2, - input logic wen2, - input logic [WIDTH-1:0] bwe2 -); - - - logic [DEPTH-1:0] ra1q, wa2q; - logic wen2q; - logic [WIDTH-1:0] wd2q; - - logic [WIDTH-1:0] mem[2**DEPTH-1:0]; - logic [WIDTH-1:0] bwe; - - - // SRAMs address busses are always registered first - // *** likely issued DH and RT 12/20/22 - // wrong enable for write port registers - // prefer to code read like ram1p1rw - // prefer not to have two-cycle write latency - // will require branch predictor changes - - flopenr #(DEPTH) ra1Reg(clk, reset, ren1, ra1, ra1q); - flopenr #(DEPTH) wa2Reg(clk, reset, ren1, wa2, wa2q); - flopr #(1) wen2Reg(clk, reset, wen2, wen2q); - flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q); - - // read port - //assign rd1 = mem[ra1q]; - always_ff @(posedge clk) - if(ren1) rd1 <= mem[ra1]; - - // write port - assign bwe = {WIDTH{wen2}} & bwe2; - always_ff @(posedge clk) - mem[wa2] <= wd2 & bwe | mem[wa2] & ~bwe; - -endmodule - - diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index ac30343b8..49354075b 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// -// 1 port sram. +// 2 port sram. // // Written: ross1728@gmail.com May 3, 2021 -// Basic sram with 1 read write port. +// Two port SRAM 1 read port and 1 write port. // When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. // Write @@ -31,7 +31,7 @@ `include "wally-config.vh" -module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) ( +module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( input logic clk, input logic ce1, ce2, input logic [$clog2(DEPTH)-1:0] ra1, diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 6666c35f9..5f725b83a 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -103,7 +103,7 @@ module btb // *** optimize for byte write enables - ram2p1r1wbefix #(2**Depth, `XLEN+4) memory( + ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); diff --git a/pipelined/src/ifu/brpred/foldedgshare.sv b/pipelined/src/ifu/brpred/foldedgshare.sv index 38e0fe610..2dfa48244 100644 --- a/pipelined/src/ifu/brpred/foldedgshare.sv +++ b/pipelined/src/ifu/brpred/foldedgshare.sv @@ -77,7 +77,7 @@ module foldedgshare assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]}; assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]}; - ram2p1r1wbefix #(2**depth, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(FinalIndexNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv index 86c48f6b5..7aa86dbb9 100644 --- a/pipelined/src/ifu/brpred/globalhistory.sv +++ b/pipelined/src/ifu/brpred/globalhistory.sv @@ -51,7 +51,7 @@ module globalhistory logic PCSrcM; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(GHR), .rd1(DirPredictionF), diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv index ca801a27c..ce189d268 100644 --- a/pipelined/src/ifu/brpred/gshare.sv +++ b/pipelined/src/ifu/brpred/gshare.sv @@ -54,7 +54,7 @@ module gshare assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv index d911ec03e..fae59c675 100644 --- a/pipelined/src/ifu/brpred/optgshare.sv +++ b/pipelined/src/ifu/brpred/optgshare.sv @@ -153,7 +153,7 @@ module optgshare assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv index 6a4e3da04..094adca99 100644 --- a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv @@ -60,7 +60,7 @@ module speculativeglobalhistory logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(GHRNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 3dd66366e..05753c76d 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -70,7 +70,7 @@ module speculativegshare assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/twoBitPredictor.sv b/pipelined/src/ifu/brpred/twoBitPredictor.sv index 3e41dfc4e..5a04a5fcf 100644 --- a/pipelined/src/ifu/brpred/twoBitPredictor.sv +++ b/pipelined/src/ifu/brpred/twoBitPredictor.sv @@ -56,7 +56,7 @@ module twoBitPredictor assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), From 42553d1d94b0e887e8751faa22cf1880855ea6c4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 17:26:54 -0600 Subject: [PATCH 086/294] Removed old versions of gshare. --- .../src/ifu/brpred/globalHistoryPredictor.sv | 123 ----------------- .../src/ifu/brpred/oldgsharepredictor.sv | 130 ------------------ .../src/ifu/brpred/oldgsharepredictor2.sv | 130 ------------------ 3 files changed, 383 deletions(-) delete mode 100644 pipelined/src/ifu/brpred/globalHistoryPredictor.sv delete mode 100644 pipelined/src/ifu/brpred/oldgsharepredictor.sv delete mode 100644 pipelined/src/ifu/brpred/oldgsharepredictor2.sv diff --git a/pipelined/src/ifu/brpred/globalHistoryPredictor.sv b/pipelined/src/ifu/brpred/globalHistoryPredictor.sv deleted file mode 100644 index 92a3f9a1a..000000000 --- a/pipelined/src/ifu/brpred/globalHistoryPredictor.sv +++ /dev/null @@ -1,123 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module globalHistoryPredictor - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] PCNextF, - output logic [1:0] BPPredF, - // update - input logic [4:0] InstrClassE, - input logic [4:0] BPInstrClassE, - input logic [4:0] BPInstrClassD, - input logic [4:0] BPInstrClassF, - input logic BPPredDirWrongE, - - input logic [`XLEN-1:0] PCE, - input logic PCSrcE, - input logic [1:0] UpdateBPPredE - - ); - logic [k+1:0] GHR, GHRNext; - logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; - logic PHTUpdateEN; - logic BPClassWrongNonCFI; - logic BPClassWrongCFI; - logic BPClassRightNonCFI; - logic BPClassRightBPWrong; - logic BPClassRightBPRight; - - logic [6:0] GHRMuxSel; - logic GHRUpdateEN; - logic [k-1:0] GHRLookup; - - assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; - assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & BPPredDirWrongE; - assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~BPPredDirWrongE; - - - // GHR update selection, 1 hot encoded. - assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight); - assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]); - assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0]; - assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0]; - assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight)); - assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF; - - // hoping this created a AND-OR mux. - always_comb begin - case (GHRMuxSel) - 7'b000_0001: GHRNext = GHR[k-1+2:0]; // no change - 7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update - 7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1 - 7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction - 7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2 - 7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1 - 7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update - default: GHRNext = GHR[k-1+2:0]; - endcase - end - - flopenr #(k+2) GlobalHistoryRegister(.clk(clk), - .reset(reset), - .en((GHRUpdateEN)), - .d(GHRNext), - .q(GHR)); - - // if actively updating the GHR at the time of prediction we want to us - // GHRNext as the lookup rather than GHR. - - assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0]; - assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1]; - assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0; - assign PHTUpdateEN = InstrClassE[0] & ~StallE; - - assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0]; - - // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - ram2p1r1wb #(k, 2) PHT(.clk(clk), - .reset(reset), - //.RA1(GHR[k-1:0]), - .ra1(GHRLookup), - .rd1(BPPredF), - .ren1(~StallF), - .wa2(PHTUpdateAdr), - .wd2(UpdateBPPredE), - .wen2(PHTUpdateEN), - .bwe2(2'b11)); - -endmodule diff --git a/pipelined/src/ifu/brpred/oldgsharepredictor.sv b/pipelined/src/ifu/brpred/oldgsharepredictor.sv deleted file mode 100644 index 29a622517..000000000 --- a/pipelined/src/ifu/brpred/oldgsharepredictor.sv +++ /dev/null @@ -1,130 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Gshare predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" -module oldgsharepredictor - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - output logic [1:0] DirPredictionF, - // update - input logic [4:0] InstrClassE, - input logic [4:0] BPInstrClassE, - input logic [4:0] BPInstrClassD, - input logic [4:0] BPInstrClassF, - output logic DirPredictionWrongE, - - input logic PCSrcE - - ); - logic [`BPRED_SIZE+1:0] GHR, GHRNext; - logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; - logic PHTUpdateEN; - logic BPClassWrongNonCFI; - logic BPClassWrongCFI; - logic BPClassRightNonCFI; - logic BPClassRightBPWrong; - logic BPClassRightBPRight; - logic [1:0] DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE; - - logic [6:0] GHRMuxSel; - logic GHRUpdateEN; - logic [`BPRED_SIZE-1:0] GHRLookup; - - assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; - assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE; - assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE; - - - // GHR update selection, 1 hot encoded. - assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight); - assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]); - assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0]; - assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0]; - assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight)); - assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF; - - // hoping this created a AND-OR mux. - always_comb begin - case (GHRMuxSel) - 7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change - 7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update - 7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1 - 7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction - 7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2 - 7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1 - 7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update - default: GHRNext = GHR[`BPRED_SIZE-1+2:0]; - endcase - end - - flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk), - .reset(reset), - .en((GHRUpdateEN)), - .d(GHRNext), - .q(GHR)); - - // if actively updating the GHR at the time of prediction we want to us - // GHRNext as the lookup rather than GHR. - - assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0]; - assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1]; - assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0; - assign PHTUpdateEN = InstrClassE[0] & ~StallE; - - assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; - - // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk), - .reset(reset), - //.RA1(GHR[`BPRED_SIZE-1:0]), - .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), - .rd1(DirPredictionF), - .ren1(~StallF), - .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]), - .wd2(NewDirPredictionE), - .wen2(PHTUpdateEN), - .bwe2(2'b11)); - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; - -endmodule // gsharePredictor diff --git a/pipelined/src/ifu/brpred/oldgsharepredictor2.sv b/pipelined/src/ifu/brpred/oldgsharepredictor2.sv deleted file mode 100644 index 679358e37..000000000 --- a/pipelined/src/ifu/brpred/oldgsharepredictor2.sv +++ /dev/null @@ -1,130 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Gshare predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" -module oldgsharepredictor2 - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - output logic [1:0] DirPredictionF, - // update - input logic [4:0] InstrClassE, - input logic [4:0] BPInstrClassE, - input logic [4:0] BPInstrClassD, - input logic [4:0] BPInstrClassF, - output logic DirPredictionWrongE, - - input logic PCSrcE - - ); - logic [`BPRED_SIZE+1:0] GHR, GHRNext; - logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; - logic PHTUpdateEN; - logic BPClassWrongNonCFI; - logic BPClassWrongCFI; - logic BPClassRightNonCFI; - logic BPClassRightBPWrong; - logic BPClassRightBPRight; - logic [1:0] DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE; - - logic [6:0] GHRMuxSel; - logic GHRUpdateEN; - logic [`BPRED_SIZE-1:0] GHRLookup; - - assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; - assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE; - assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE; - - - // GHR update selection, 1 hot encoded. - assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight); - assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]); - assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0]; - assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0]; - assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight)); - assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF; - - // hoping this created a AND-OR mux. - always_comb begin - case (GHRMuxSel) - 7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change - 7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update - 7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1 - 7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction - 7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2 - 7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1 - 7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update - default: GHRNext = GHR[`BPRED_SIZE-1+2:0]; - endcase - end - - flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk), - .reset(reset), - .en((GHRUpdateEN)), - .d(GHRNext), - .q(GHR)); - - // if actively updating the GHR at the time of prediction we want to us - // GHRNext as the lookup rather than GHR. - - assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0]; - assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1]; - assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0; - assign PHTUpdateEN = InstrClassE[0] & ~StallE; - - assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; - - // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk), - .reset(reset), - //.RA1(GHR[`BPRED_SIZE-1:0]), - .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), - .rd1(DirPredictionF), - .ren1(~StallF), - .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]), - .wd2(NewDirPredictionE), - .wen2(PHTUpdateEN), - .bwe2(2'b11)); - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; - -endmodule // gsharePredictor From 1e7fda64103707269ba0a56bbb9ff589ea0311f2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 10:14:30 -0600 Subject: [PATCH 087/294] Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv --- pipelined/src/generic/mem/ram2p1rwbefix.sv | 72 ---------------------- pipelined/src/ifu/brpred/optgshare.sv | 24 +++----- 2 files changed, 10 insertions(+), 86 deletions(-) delete mode 100644 pipelined/src/generic/mem/ram2p1rwbefix.sv diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv deleted file mode 100644 index 49354075b..000000000 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ /dev/null @@ -1,72 +0,0 @@ -/////////////////////////////////////////// -// 2 port sram. -// -// Written: ross1728@gmail.com May 3, 2021 -// Two port SRAM 1 read port and 1 write port. -// When clk rises Addr and LineWriteData are sampled. -// Following the clk edge read data is output from the sampled Addr. -// Write -// -// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words - -`include "wally-config.vh" - -module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( - input logic clk, - input logic ce1, ce2, - input logic [$clog2(DEPTH)-1:0] ra1, - input logic [WIDTH-1:0] wd2, - input logic [$clog2(DEPTH)-1:0] wa2, - input logic we2, - input logic [(WIDTH-1)/8:0] bwe2, - output logic [WIDTH-1:0] rd1 -); - - logic [WIDTH-1:0] mem[DEPTH-1:0]; - - // *************************************************************************** - // TRUE Smem macro - // *************************************************************************** - - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** - integer i; - - // Read - always_ff @(posedge clk) - if(ce1) rd1 <= #1 mem[ra1]; - - // Write divided into part for bytes and part for extra msbs - if(WIDTH >= 8) - always @(posedge clk) - if (ce2 & we2) - for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; - - if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always @(posedge clk) - if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; - -endmodule diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv index fae59c675..1f99cfd26 100644 --- a/pipelined/src/ifu/brpred/optgshare.sv +++ b/pipelined/src/ifu/brpred/optgshare.sv @@ -12,22 +12,18 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" From a5bd78a62226115d91c1ad95bfeca10c4fe64ca0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 10:17:43 -0600 Subject: [PATCH 088/294] Renamed file missed from last commit. --- pipelined/src/generic/mem/ram2p1rwbe.sv | 72 +++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 pipelined/src/generic/mem/ram2p1rwbe.sv diff --git a/pipelined/src/generic/mem/ram2p1rwbe.sv b/pipelined/src/generic/mem/ram2p1rwbe.sv new file mode 100644 index 000000000..49354075b --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1rwbe.sv @@ -0,0 +1,72 @@ +/////////////////////////////////////////// +// 2 port sram. +// +// Written: ross1728@gmail.com May 3, 2021 +// Two port SRAM 1 read port and 1 write port. +// When clk rises Addr and LineWriteData are sampled. +// Following the clk edge read data is output from the sampled Addr. +// Write +// +// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words + +`include "wally-config.vh" + +module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( + input logic clk, + input logic ce1, ce2, + input logic [$clog2(DEPTH)-1:0] ra1, + input logic [WIDTH-1:0] wd2, + input logic [$clog2(DEPTH)-1:0] wa2, + input logic we2, + input logic [(WIDTH-1)/8:0] bwe2, + output logic [WIDTH-1:0] rd1 +); + + logic [WIDTH-1:0] mem[DEPTH-1:0]; + + // *************************************************************************** + // TRUE Smem macro + // *************************************************************************** + + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** + integer i; + + // Read + always_ff @(posedge clk) + if(ce1) rd1 <= #1 mem[ra1]; + + // Write divided into part for bytes and part for extra msbs + if(WIDTH >= 8) + always @(posedge clk) + if (ce2 & we2) + for(i = 0; i < WIDTH/8; i++) + if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; + + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 + always @(posedge clk) + if (ce2 & we2 & bwe2[WIDTH/8]) + mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; + +endmodule From 5030a56f57a8473f396b690aad21c93b0829da82 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 11:41:16 -0600 Subject: [PATCH 089/294] Optomized gshare. --- pipelined/src/ifu/brpred/speculativegshare.sv | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 05753c76d..eee2abc95 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -45,7 +45,7 @@ module speculativegshare input logic PCSrcE ); - logic MatchF, MatchD, MatchE, MatchM; + logic MatchF, MatchD, MatchE; logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; @@ -57,7 +57,7 @@ module speculativegshare logic [k:-1] GHRNextD, OldGHRD; logic [k:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; - logic [k-1:0] IndexD, IndexE, IndexM; + logic [k-1:0] IndexD, IndexE; logic PCSrcM, PCSrcW; logic [`XLEN-1:0] PCW; @@ -68,15 +68,14 @@ module speculativegshare assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]}; assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; - assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableDirPredictionF), - .wa2(IndexM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallW & ~FlushW), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage @@ -84,15 +83,13 @@ module speculativegshare assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); - assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM); - assign MatchNextX = MatchF | MatchD | MatchE | MatchM; + assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : MatchD ? NewDirPredictionD : - MatchE ? NewDirPredictionE : - NewDirPredictionM; + NewDirPredictionE ; flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); From a0bca35b5043c8f8e7cd6a11aca25187f1823714 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:05:13 -0600 Subject: [PATCH 090/294] BTB cleanup. --- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/btb.sv | 46 +++++++------------------------ 2 files changed, 11 insertions(+), 37 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 9c5efe306..6817dfd59 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -143,7 +143,7 @@ module bpred ( .InstrClass(PredInstrClassF), .Valid(BTBValidF), // update - .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), + .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), .PCE, .IEUAdrE, .UpdateInvalid(PredictionInstrClassWrongE), diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 5f725b83a..8eba026ec 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -35,7 +35,7 @@ module btb ) (input logic clk, input logic reset, - input logic StallF, StallE, + input logic StallF, StallE, StallM, FlushM, input logic [`XLEN-1:0] PCNextF, output logic [`XLEN-1:0] BTBPredPCF, output logic [3:0] InstrClass, @@ -50,7 +50,7 @@ module btb localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; - logic [Depth-1:0] PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ; + logic [Depth-1:0] PCNextFIndex, PCEIndex; logic UpdateENQ; logic [`XLEN-1:0] ResetPC; @@ -60,51 +60,25 @@ module btb // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if // using compressed instructions. XOR bit 1 with the MSB of index. assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; + + // must output a valid PC and valid bit during reset. Because the PCNextF logic of the IFU and trap units + // does not mux in RESET_VECTOR we have to do it here. This is a performance optimization. assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - //assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - - flopenr #(Depth) PCEIndexReg(.clk(clk), - .reset(reset), - .en(~StallE), - .d(PCEIndex), - .q(PCEIndexQ)); - // The valid bit must be resetable. always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; - end else - if (UpdateENQ) begin - ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid; + end else if (UpdateEN & ~StallM & ~FlushM) begin + ValidBits[PCEIndex] <= #1 ~ UpdateInvalid; end + Valid = ValidBits[PCNextFIndex]; end - assign Valid = ValidBits[PCNextFIndexQ]; - - flopenr #(1) UpdateENReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(UpdateEN), - .q(UpdateENQ)); - - - flopenr #(Depth) LookupPCIndexReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(PCNextFIndex), - .q(PCNextFIndexQ)); - - - - // the BTB contains the target address. - // Another optimization may be using a PC relative address. + // An optimization may be using a PC relative address. // *** need to add forwarding. - - // *** optimize for byte write enables - ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), - .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); endmodule From 85e015d61ec5717190176fbe8521881476258350 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:08:54 -0600 Subject: [PATCH 091/294] Found minor bug in gshare. --- pipelined/config/rv32ic/wally-config.vh | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 311ce8ab2..dbe29a2ee 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -132,7 +132,7 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index eee2abc95..489024491 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -70,7 +70,7 @@ module speculativegshare assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), + .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(TableDirPredictionF), .wa2(IndexE), From 62d812b150af3a37d84381f335b337c2ea2b0eda Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:09:02 -0600 Subject: [PATCH 092/294] Updated gitflow. --- gitflow.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gitflow.txt b/gitflow.txt index 57d79333b..57300830a 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -48,3 +48,6 @@ Create pull request 1. git pull upstream main # fetch and merge the upstream openhwgroup/cvw into your local clone 3. git push # sync your fork with the upstream and clone + +If the pull request need changes, modify accordingly, commit, and push changes back to the fork. +The pull request will automatically update. From 541524a7549bb2e28af69927e6c881b97007c8cf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:14:18 -0600 Subject: [PATCH 093/294] More btb cleanup. --- pipelined/src/ifu/brpred/bpred.sv | 10 +++++----- pipelined/src/ifu/brpred/btb.sv | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6817dfd59..dd7b9e850 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -60,7 +60,7 @@ module bpred ( output logic PredictionInstrClassWrongM // Class prediction is wrong ); - logic BTBValidF; + logic PredValidF; logic [1:0] DirPredictionF; logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; @@ -128,9 +128,9 @@ module bpred ( // 1) A direction (1 = Taken, 0 = Not Taken) // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) | + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | PredInstrClassF[2] | - (PredInstrClassF[1] & BTBValidF) ; + (PredInstrClassF[1] & PredValidF) ; // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets @@ -140,8 +140,8 @@ module bpred ( .*, // Stalls and flushes .PCNextF, .BTBPredPCF, - .InstrClass(PredInstrClassF), - .Valid(BTBValidF), + .PredInstrClassF, + .PredValidF, // update .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), .PCE, diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 8eba026ec..839b1b7d5 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -38,8 +38,8 @@ module btb input logic StallF, StallE, StallM, FlushM, input logic [`XLEN-1:0] PCNextF, output logic [`XLEN-1:0] BTBPredPCF, - output logic [3:0] InstrClass, - output logic Valid, + output logic [3:0] PredInstrClassF, + output logic PredValidF, // update input logic UpdateEN, input logic [`XLEN-1:0] PCE, @@ -72,13 +72,13 @@ module btb end else if (UpdateEN & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 ~ UpdateInvalid; end - Valid = ValidBits[PCNextFIndex]; + PredValidF = ValidBits[PCNextFIndex]; end // An optimization may be using a PC relative address. // *** need to add forwarding. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( - .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), + .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); endmodule From d4004c2c22d3674509020db29d48a0ef4c433f1b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 13:02:20 -0600 Subject: [PATCH 094/294] Added logic to forward btb prediction results. --- pipelined/src/ifu/brpred/btb.sv | 42 ++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 839b1b7d5..bcf5dcfd9 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -35,8 +35,8 @@ module btb ) (input logic clk, input logic reset, - input logic StallF, StallE, StallM, FlushM, - input logic [`XLEN-1:0] PCNextF, + input logic StallF, StallD, StallE, StallM, FlushD, FlushM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, output logic [`XLEN-1:0] BTBPredPCF, output logic [3:0] PredInstrClassF, output logic PredValidF, @@ -50,22 +50,44 @@ module btb localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; - logic [Depth-1:0] PCNextFIndex, PCEIndex; + logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic UpdateENQ; logic [`XLEN-1:0] ResetPC; - - + logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; + logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+3:0] TableBTBPredictionF; + logic [`XLEN-1:0] BTBPredPCD; + logic [3:0] PredInstrClassD; // copy of reg outside module + + // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if // using compressed instructions. XOR bit 1 with the MSB of index. + assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]}; + assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]}; assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; // must output a valid PC and valid bit during reset. Because the PCNextF logic of the IFU and trap units // does not mux in RESET_VECTOR we have to do it here. This is a performance optimization. assign ResetPC = `RESET_VECTOR; - assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + + assign MatchF = PCNextFIndex == PCFIndex; + assign MatchD = PCNextFIndex == PCDIndex; + assign MatchE = PCNextFIndex == PCEIndex; + assign MatchNextX = MatchF | MatchD | MatchE; + flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); + + assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, BTBPredPCF} : + MatchD ? {PredInstrClassD, BTBPredPCD} : + {InstrClassE, IEUAdrE} ; + + flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + + assign {PredInstrClassF, BTBPredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; @@ -76,9 +98,13 @@ module btb end // An optimization may be using a PC relative address. - // *** need to add forwarding. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( - .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}), + .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD}); + + + + endmodule From bb89bf82bfd08a6ed87457db7915ce9087a51bf4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 15:16:53 -0600 Subject: [PATCH 095/294] Fixed subtle bug in btb. --- pipelined/src/ifu/brpred/bpred.sv | 1 - pipelined/src/ifu/brpred/btb.sv | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index dd7b9e850..485875b66 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -146,7 +146,6 @@ module bpred ( .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), .PCE, .IEUAdrE, - .UpdateInvalid(PredictionInstrClassWrongE), .InstrClassE); // Part 3 RAS diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index bcf5dcfd9..aba3826b3 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -44,8 +44,7 @@ module btb input logic UpdateEN, input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] IEUAdrE, - input logic [3:0] InstrClassE, - input logic UpdateInvalid + input logic [3:0] InstrClassE ); localparam TotalDepth = 2 ** Depth; @@ -92,7 +91,7 @@ module btb if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; end else if (UpdateEN & ~StallM & ~FlushM) begin - ValidBits[PCEIndex] <= #1 ~ UpdateInvalid; + ValidBits[PCEIndex] <= #1 |InstrClassE; end PredValidF = ValidBits[PCNextFIndex]; end From 3d285312f03ccb4fcc7e13ac15ffcee5a401967c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 15:29:55 -0600 Subject: [PATCH 096/294] Cleaned up branch predictor. --- pipelined/src/ifu/brpred/bpred.sv | 3 +-- pipelined/src/ifu/brpred/btb.sv | 14 ++++++-------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 485875b66..d259b3b3d 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -142,8 +142,7 @@ module bpred ( .BTBPredPCF, .PredInstrClassF, .PredValidF, - // update - .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), + .PredictionInstrClassWrongE, .PCE, .IEUAdrE, .InstrClassE); diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index aba3826b3..fdac1c54d 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -41,7 +41,7 @@ module btb output logic [3:0] PredInstrClassF, output logic PredValidF, // update - input logic UpdateEN, + input logic PredictionInstrClassWrongE, input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] IEUAdrE, input logic [3:0] InstrClassE @@ -50,7 +50,6 @@ module btb localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; - logic UpdateENQ; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; @@ -67,8 +66,10 @@ module btb assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]}; assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; - // must output a valid PC and valid bit during reset. Because the PCNextF logic of the IFU and trap units - // does not mux in RESET_VECTOR we have to do it here. This is a performance optimization. + // must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid + // during reset. The BTB must produce a non X PC1NextF to allow the simulation to run. + // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus. + // For now it is optimal to leave it here. assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; @@ -90,7 +91,7 @@ module btb always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; - end else if (UpdateEN & ~StallM & ~FlushM) begin + end else if ((|InstrClassE | PredictionInstrClassWrongE) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end PredValidF = ValidBits[PCNextFIndex]; @@ -103,7 +104,4 @@ module btb flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD}); - - - endmodule From 56aa798d5c2a131c24afcf19b9d6ecd2099500a8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 16:03:02 -0600 Subject: [PATCH 097/294] More branch predictor improvements. --- pipelined/src/ifu/brpred/bpred.sv | 17 +++-- pipelined/src/ifu/brpred/btb.sv | 39 ++++++------ .../ifu/brpred/speculativeglobalhistory.sv | 62 ++++++++++--------- pipelined/src/ifu/brpred/speculativegshare.sv | 8 +-- 4 files changed, 60 insertions(+), 66 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index d259b3b3d..35dffa964 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -64,7 +64,7 @@ module bpred ( logic [1:0] DirPredictionF; logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; - logic [`XLEN-1:0] BTBPredPCF, RASPCF; + logic [`XLEN-1:0] PredPCF, RASPCF; logic TargetWrongE; logic FallThroughWrongE; logic PredictionPCWrongE; @@ -95,8 +95,8 @@ module bpred ( speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), - .BranchInstrW(InstrClassW[0]), .PCSrcE); - + .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); + end else if (`BPTYPE == "BPGSHARE") begin:Predictor gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, @@ -135,15 +135,12 @@ module bpred ( // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets - btb TargetPredictor(.clk(clk), - .reset(reset), - .*, // Stalls and flushes - .PCNextF, - .BTBPredPCF, + btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, + .PCNextF, .PCF, .PCD, .PCE, + .PredPCF, .PredInstrClassF, .PredValidF, .PredictionInstrClassWrongE, - .PCE, .IEUAdrE, .InstrClassE); @@ -160,7 +157,7 @@ module bpred ( .incr(1'b0), .PCLinkE); - assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTBPredPCF; + assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; // the branch predictor needs a compact decoding of the instruction class. assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index fdac1c54d..a81af5bb4 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -35,16 +35,15 @@ module btb ) (input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, FlushD, FlushM, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, - output logic [`XLEN-1:0] BTBPredPCF, - output logic [3:0] PredInstrClassF, - output logic PredValidF, + input logic StallF, StallD, StallM, FlushD, FlushM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages + output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC + output logic [3:0] PredInstrClassF, // BTB's guess at instruction class + output logic PredValidF, // BTB's guess is valid // update - input logic PredictionInstrClassWrongE, - input logic [`XLEN-1:0] PCE, - input logic [`XLEN-1:0] IEUAdrE, - input logic [3:0] InstrClassE + input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong + input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassE // Instruction class to insert into btb ); localparam TotalDepth = 2 ** Depth; @@ -54,10 +53,10 @@ module btb logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; - logic [`XLEN-1:0] BTBPredPCD; - logic [3:0] PredInstrClassD; // copy of reg outside module - - + logic [`XLEN-1:0] PredPCD; + logic [3:0] PredInstrClassD; // *** copy of reg outside module + logic UpdateEn; + // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if @@ -80,28 +79,30 @@ module btb flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, BTBPredPCF} : - MatchD ? {PredInstrClassD, BTBPredPCD} : + assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, PredPCF} : + MatchD ? {PredInstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {PredInstrClassF, BTBPredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {PredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; - end else if ((|InstrClassE | PredictionInstrClassWrongE) & ~StallM & ~FlushM) begin + end else if ((UpdateEn) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end PredValidF = ValidBits[PCNextFIndex]; end + assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; + // An optimization may be using a PC relative address. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), - .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD}); + flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); endmodule diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv index 094adca99..ecc7a3b0f 100644 --- a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv @@ -40,52 +40,56 @@ module speculativeglobalhistory output logic DirPredictionWrongE, // update input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic [3:0] WrongPredInstrClassD, input logic PCSrcE ); - logic MatchF, MatchD, MatchE, MatchM, MatchW; + logic MatchF, MatchD, MatchE; logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW; + logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; - logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW; - logic PCSrcM, PCSrcW; + logic [k:-1] GHRNextD, OldGHRD; + logic [k:0] GHRNextE, GHRNextM, GHRNextW; + logic [k-1:0] IndexNextF, IndexF; + logic [k-1:0] IndexD, IndexE; + logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; + assign IndexNextF = GHRNextF; + assign IndexF = GHRF; + assign IndexD = GHRD[k-1:0]; + assign IndexE = GHRE[k-1:0]; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), - .ra1(GHRNextF), + .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), + .ra1(IndexNextF), .rd1(TableDirPredictionF), - .wa2(GHRW[k-1:0]), - .wd2(NewDirPredictionW), - .we2(BranchInstrW & ~StallW & ~FlushW), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage - // and then register for use in the Fetch stage. - assign MatchF = BranchInstrF & ~FlushD & (GHRNextF == GHRF); - assign MatchD = BranchInstrD & ~FlushE & (GHRNextF == GHRD[k-1:0]); - assign MatchE = BranchInstrE & ~FlushM & (GHRNextF == GHRE[k-1:0]); - assign MatchM = BranchInstrM & ~FlushW & (GHRNextF == GHRM[k-1:0]); - assign MatchW = BranchInstrW & (GHRNextF == GHRW[k-1:0]); - assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW; + // and then register for use in the Fetch stage. + assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); + assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); + assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); + assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : MatchD ? NewDirPredictionD : - MatchE ? NewDirPredictionE : - MatchM ? NewDirPredictionM : - NewDirPredictionW; - + NewDirPredictionE ; + flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; @@ -95,16 +99,11 @@ module speculativeglobalhistory flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); // New prediction pipeline - satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF)); + assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]}; + flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM); - flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW); - // PCSrc pipeline - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW); - // GHR pipeline assign GHRNextF = FlushD ? GHRNextD[k:1] : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : @@ -112,8 +111,11 @@ module speculativeglobalhistory flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF}; - flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; + flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); + assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left + OldGHRD[k:0]; assign GHRNextE = FlushE ? GHRNextM : GHRD; flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 489024491..b72aacb44 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -49,7 +49,7 @@ module speculativegshare logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM; + logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; @@ -59,7 +59,6 @@ module speculativegshare logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; - logic PCSrcM, PCSrcW; logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -104,12 +103,7 @@ module speculativegshare flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM); - // PCSrc pipeline - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW); - // GHR pipeline assign GHRNextF = FlushD ? GHRNextD[k:1] : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : From 172c40d44b9ffb2e890a8548884c911b803e6a16 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 17:06:25 -0600 Subject: [PATCH 098/294] Improved RAS. --- pipelined/config/rv64gc/wally-config.vh | 7 ++++--- pipelined/src/ifu/brpred/RAsPredictor.sv | 16 ++++++++++------ pipelined/src/ifu/brpred/bpred.sv | 21 +++++++++++---------- pipelined/src/ifu/brpred/globalhistory.sv | 9 ++++----- pipelined/src/ifu/brpred/gshare.sv | 15 +++++++-------- 5 files changed, 36 insertions(+), 32 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 29148944f..6ecab2845 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -135,9 +135,10 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index c71ff2966..422a785cc 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -32,13 +32,10 @@ module RASPredictor #(parameter int StackSize = 16 ) (input logic clk, - input logic reset, - input logic PopF, + input logic reset, StallF, StallD, StallE, output logic [`XLEN-1:0] RASPCF, input logic [3:0] WrongPredInstrClassD, - input logic [3:0] InstrClassD, - input logic PushE, - input logic incr, + input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, input logic [`XLEN-1:0] PCLinkE ); @@ -51,8 +48,15 @@ module RASPredictor logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; + logic PopF; + logic PushE; - assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2]; + + + assign PopF = PredInstrClassF[2] & ~StallF; + assign PushE = InstrClassE[3] & ~StallE; + + assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1; diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 35dffa964..1669ee4f3 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -99,7 +99,7 @@ module bpred ( end else if (`BPTYPE == "BPGSHARE") begin:Predictor gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, + .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor @@ -147,15 +147,9 @@ module bpred ( // Part 3 RAS // *** need to add the logic to restore RAS on flushes. We will use incr for this. // *** needs to include flushX - RASPredictor RASPredictor(.clk(clk), - .reset(reset), - .PopF(PredInstrClassF[2] & ~StallF), - .WrongPredInstrClassD, - .InstrClassD, - .RASPCF, - .PushE(InstrClassE[3] & ~StallE), - .incr(1'b0), - .PCLinkE); + RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, + .PredInstrClassF, .InstrClassD, .InstrClassE, + .WrongPredInstrClassD, .RASPCF, .PCLinkE); assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; @@ -227,5 +221,12 @@ module bpred ( // end else begin // assign NextValidPCE = PCE; // end + + // performance counters + // 1. class (class wrong / minstret) + // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) + // 3. target ras (ras target wrong / class[2]) + // 4. direction (br dir wrong / class[0]) + endmodule diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv index 7aa86dbb9..55b6827cd 100644 --- a/pipelined/src/ifu/brpred/globalhistory.sv +++ b/pipelined/src/ifu/brpred/globalhistory.sv @@ -46,7 +46,7 @@ module globalhistory logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; + logic [k-1:0] GHRF, GHRD, GHRE, GHR; logic [k-1:0] GHRNext; logic PCSrcM; @@ -55,9 +55,9 @@ module globalhistory .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(GHR), .rd1(DirPredictionF), - .wa2(GHRM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallM & ~FlushM), + .wa2(GHRE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -76,7 +76,6 @@ module globalhistory flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); endmodule diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv index ce189d268..ff24c84d3 100644 --- a/pipelined/src/ifu/brpred/gshare.sv +++ b/pipelined/src/ifu/brpred/gshare.sv @@ -39,28 +39,28 @@ module gshare output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCM, + input logic [`XLEN-1:0] PCNextF, PCE, input logic BranchInstrE, BranchInstrM, PCSrcE ); - logic [k-1:0] IndexNextF, IndexM; + logic [k-1:0] IndexNextF, IndexE; logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; + logic [k-1:0] GHRF, GHRD, GHRE, GHR; logic [k-1:0] GHRNext; logic PCSrcM; assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]}; + assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), - .wa2(IndexM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallM & ~FlushM), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -78,7 +78,6 @@ module gshare flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); endmodule From 0b9f78763530119556672c8f2ab2d4f730d5b57c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 17:10:52 -0600 Subject: [PATCH 099/294] Improved RAS again. --- pipelined/regression/wave.do | 83 ++++++++++-------------- pipelined/src/ifu/brpred/RAsPredictor.sv | 15 ++--- pipelined/src/ifu/brpred/bpred.sv | 2 +- 3 files changed, 44 insertions(+), 56 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index be29ed870..393f6ee11 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -41,12 +41,12 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpi add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/core/PCF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/core/PCE -add wave -noupdate -expand -group PCS /testbench/dut/core/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/core/PCF +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/core/PCE +add wave -noupdate -group PCS /testbench/dut/core/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -55,15 +55,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName @@ -85,25 +85,18 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF +add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF +add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF @@ -148,20 +141,15 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR @@ -463,10 +451,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE @@ -484,7 +468,6 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay @@ -571,7 +554,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y @@ -603,8 +585,15 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Br add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1 +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1 +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -620,4 +609,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {118528 ns} {128752 ns} +WaveRestoreZoom {79760 ns} {171462 ns} diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 422a785cc..28d15ebbe 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -32,15 +32,13 @@ module RASPredictor #(parameter int StackSize = 16 ) (input logic clk, - input logic reset, StallF, StallD, StallE, + input logic reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, output logic [`XLEN-1:0] RASPCF, input logic [3:0] WrongPredInstrClassD, input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, input logic [`XLEN-1:0] PCLinkE ); - // *** need to update so it either doesn't push until the memory stage - // or need to repair flushed push. // *** need to repair popped and then flushed returns. logic CounterEn; localparam Depth = $clog2(StackSize); @@ -50,19 +48,20 @@ module RASPredictor integer index; logic PopF; logic PushE; + logic RepairD; - assign PopF = PredInstrClassF[2] & ~StallF; - assign PushE = InstrClassE[3] & ~StallE; + assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; + assign RepairD = InstrClassD[2] & ~StallE & ~FlushE; + assign PushE = InstrClassE[3] & ~StallM & ~FlushM; assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; - assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1; + assign PtrD = PopF | RepairD ? PtrM1 : PtrP1; assign PtrM1 = PtrQ - 1'b1; assign PtrP1 = PtrQ + 1'b1; - // may have to handle a PushE and an incr at the same time. // *** what happens if jal is executing and there is a return being flushed in Decode? flopenr #(Depth) PTR(.clk(clk), @@ -75,7 +74,7 @@ module RASPredictor always_ff @ (posedge clk) begin if(reset) begin for(index=0; index Date: Wed, 25 Jan 2023 17:18:07 -0600 Subject: [PATCH 100/294] RAS is now compliant with our header and documentation guide. --- pipelined/src/ifu/brpred/RAsPredictor.sv | 40 +++++++++++++----------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 28d15ebbe..42c484393 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -1,13 +1,14 @@ /////////////////////////////////////////// // RASPredictor.sv // -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 15, 2021 -// Modified: +// Written: Ross Thomposn ross1728@gmail.com +// Created: 15 February 2021 +// Modified: 25 January 2023 // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // +// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University @@ -28,41 +29,42 @@ `include "wally-config.vh" -module RASPredictor - #(parameter int StackSize = 16 - ) - (input logic clk, - input logic reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, - output logic [`XLEN-1:0] RASPCF, - input logic [3:0] WrongPredInstrClassD, - input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, - input logic [`XLEN-1:0] PCLinkE +module RASPredictor #(parameter int StackSize = 16 +)(input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, + input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong + input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class + input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal + output logic [`XLEN-1:0] RASPCF // Top of the stack ); - // *** need to repair popped and then flushed returns. logic CounterEn; localparam Depth = $clog2(StackSize); logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; + logic PopF; logic PushE; logic RepairD; + logic PossibleRepairD; + logic DecrementPtr; - assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - assign RepairD = InstrClassD[2] & ~StallE & ~FlushE; + assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE; + assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE; assign PushE = InstrClassE[3] & ~StallM & ~FlushM; - assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; + assign CounterEn = PopF | PushE | RepairD; - assign PtrD = PopF | RepairD ? PtrM1 : PtrP1; + assign DecrementPtr = PopF | PossibleRepairD; + mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD); assign PtrM1 = PtrQ - 1'b1; assign PtrP1 = PtrQ + 1'b1; - // *** what happens if jal is executing and there is a return being flushed in Decode? flopenr #(Depth) PTR(.clk(clk), .reset(reset), From 4e858199e5aa5d50706dafcdb3f8352c83352a0c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 18:51:09 -0600 Subject: [PATCH 101/294] Fixed typos. --- pipelined/src/ifu/brpred/bpred.sv | 6 +++--- pipelined/src/ifu/ifu.sv | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index d9f342db1..6803f65d4 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -197,8 +197,8 @@ module bpred ( assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE; // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. - assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1]) & PredictionPCWrongE; - // similar with RAS + assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; + // similar with RAS. Over counts ras if the class prediction was wrong. assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE; // Finally if the real instruction class is non CFI but the predictor said it was we need to count. assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; @@ -223,7 +223,7 @@ module bpred ( // end // performance counters - // 1. class (class wrong / minstret) + // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 476f666ff..f48727500 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -115,7 +115,7 @@ module ifu ( logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush - logic CacheableF; // PMA indicates isntruction address is cacheable + logic CacheableF; // PMA indicates instruction address is cacheable logic SelNextSpillF; // In a spill, stall pipeline and gate local stallF logic BusStall; // Bus interface busy with multicycle operation logic ICacheStallF; // I$ busy with multicycle operation From 43d4ac1c7b67da024a71bda064e9838d8f22cc05 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 19:39:18 -0600 Subject: [PATCH 102/294] Intermediate commit. Passes regression tests, but RAS is not correct. --- pipelined/regression/wave.do | 47 ++++++------------------ pipelined/src/ifu/brpred/RAsPredictor.sv | 3 +- pipelined/src/ifu/brpred/bpred.sv | 40 ++++++++++++++++++-- pipelined/src/ifu/brpred/btb.sv | 8 ++-- pipelined/src/ifu/ifu.sv | 2 +- 5 files changed, 55 insertions(+), 45 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 393f6ee11..ccc5928a5 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -55,11 +55,11 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -group {Memory Stage} /testbench/InstrMName @@ -85,11 +85,8 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE @@ -566,34 +563,12 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1 -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1 -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {117097 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -609,4 +584,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {79760 ns} {171462 ns} +WaveRestoreZoom {117047 ns} {117181 ns} diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 42c484393..6f2cbd059 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -54,7 +54,8 @@ module RASPredictor #(parameter int StackSize = 16 logic DecrementPtr; assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE; + // **********this part is wrong. + assign PossibleRepairD = (InstrClassD[2] & ~StallE & FlushE) | (PredInstrClassF[2] & ~StallD & FlushD); assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE; assign PushE = InstrClassE[3] & ~StallM & ~FlushM; diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6803f65d4..82bdf1f00 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,6 +28,8 @@ `include "wally-config.vh" +`define INSTR_CLASS_PRED 0 + module bpred ( input logic clk, reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -46,6 +48,8 @@ module bpred ( input logic [`XLEN-1:0] PCE, // Execution stage instruction address input logic [`XLEN-1:0] PCM, // Memory stage instruction address + input logic [31:0] PostSpillInstrRawF, // Instruction + // Branch and jump outcome input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address @@ -63,13 +67,13 @@ module bpred ( logic PredValidF; logic [1:0] DirPredictionF; - logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; + logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; logic [`XLEN-1:0] PredPCF, RASPCF; logic TargetWrongE; logic FallThroughWrongE; logic PredictionPCWrongE; logic PredictionInstrClassWrongE; - logic [3:0] InstrClassD, InstrClassE, InstrClassW; + logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic SelBPPredF; @@ -138,7 +142,7 @@ module bpred ( btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, .PCNextF, .PCF, .PCD, .PCE, .PredPCF, - .PredInstrClassF, + .BTBPredInstrClassF, .PredValidF, .PredictionInstrClassWrongE, .IEUAdrE, @@ -154,6 +158,36 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; // the branch predictor needs a compact decoding of the instruction class. + if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode + logic [4:0] CompressedOpcF; + logic [3:0] InstrClassF; + logic cjal, cj, cjr, cjalr; + + assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; + + assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; + assign cj = CompressedOpcF == 5'h0d; + assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + + assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | + (`C_SUPPORTED & CompressedOpcF == 5'h0e); + + assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 + (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); + + assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); + + assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + (`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)); + assign PredInstrClassF = InstrClassF; + end else begin + assign PredInstrClassF = BTBPredInstrClassF; + end + + assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index a81af5bb4..9b6c66b85 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -38,7 +38,7 @@ module btb input logic StallF, StallD, StallM, FlushD, FlushM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC - output logic [3:0] PredInstrClassF, // BTB's guess at instruction class + output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class output logic PredValidF, // BTB's guess is valid // update input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong @@ -79,13 +79,13 @@ module btb flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, PredPCF} : + assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : MatchD ? {PredInstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {PredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; always_ff @ (posedge clk) begin if (reset) begin @@ -103,6 +103,6 @@ module btb .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); + flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f48727500..26227bb9b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -327,7 +327,7 @@ module ifu ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred From 3249cbe42e002ca7c3a7f06315140de253b71e01 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Thu, 26 Jan 2023 04:50:14 +0000 Subject: [PATCH 103/294] Fixed writing config files for synth sweeps --- .gitignore | 2 +- synthDC/Makefile | 72 ++++++++++++++++++++------------------- synthDC/extractSummary.py | 54 ++++++++++++++--------------- synthDC/wallySynth.py | 31 ++++++----------- 4 files changed, 76 insertions(+), 83 deletions(-) diff --git a/.gitignore b/.gitignore index c4c71a623..609ef1487 100644 --- a/.gitignore +++ b/.gitignore @@ -76,7 +76,7 @@ synthDC/runs/ synthDC/newRuns synthDC/ppa/PPAruns synthDC/ppa/plots -synthDC/plots/ +synthDC/wallyplots/ synthDC/runArchive synthDC/hdl /pipelined/regression/power.saif diff --git a/synthDC/Makefile b/synthDC/Makefile index 98b719428..5551e252f 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -8,6 +8,7 @@ NAME := synth export DESIGN ?= wallypipelinedcore export FREQ ?= 3000 export CONFIG ?= rv32e +export MOD ?= orig # title to add a note in the synth's directory name TITLE = # tsmc28, sky130, and sky90 presently supported @@ -22,13 +23,15 @@ export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 -CONFIGDIR ?= ${WALLY}/pipelined/config +configAsList := $(subst _, ,$(CONFIG)) +BASECONFIG := $(word 1, $(configAsList)) +OLDCONFIGDIR ?= ${WALLY}/pipelined/config +CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) -# FREQS = 25 50 100 150 200 250 300 350 400 # k = 3 6 print: @@ -42,8 +45,8 @@ default: @echo "Use wallySynth.py to run a concurrent sweep " -DIRS32 = rv32e rv32gc rv32ic -DIRS64 = rv64ic rv64gc +DIRS32 = rv32e rv32gc rv32ic rv32i # added 32i +DIRS64 = rv64i rv64gc # use just 64i, lose ic DIRS = $(DIRS32) $(DIRS64) # bpred: @@ -51,73 +54,72 @@ DIRS = $(DIRS32) $(DIRS64) # @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) # @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) -copy: - # remove old config files - rm -rf $(CONFIGDIR)/*_* - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) +configs: $(BASECONFIG) +$(BASECONFIG): + @echo $(BASECONFIG) + cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh - @$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) - @$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) - -configs: $(DIRS) -$(DIRS): +ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else + $(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64)) + @echo "Config not in list, RAM_RANGE will be unmodified" +endif # turn off FPU - rm -rf $(CONFIGDIR)/$@_FPUoff cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh # PMP 16 - rm -rf $(CONFIGDIR)/$@_PMP16 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh # PMP 0 - rm -rf $(CONFIGDIR)/$@_PMP0 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh # no muldiv - rm -rf $(CONFIGDIR)/$@_noMulDiv cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh # no priv - rm -rf $(CONFIGDIR)/$@_noPriv cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh +ifeq ($(SAIFPOWER), 1) + cp -f ../pipelined/regression/power.saif . +endif + freqs: @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) -synth: +mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) - @mkdir -p $(OUTPUTDIR)/hdl + @mkdir -p $(OUTPUTDIR)/hdl/config @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -ifeq ($(SAIFPOWER), 1) - cp -f ../pipelined/regression/power.saif . -endif + +synth: mkdirecs configs rundc clean + +rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out -# rm -rf $(OUTPUTDIR)/hdl + +clean: + rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/alib-52 - -clean: rm -f default.svf rm -f command.log rm -f filenames*.log rm -f power.saif rm -f Synopsys_stack_trace_*.txt - rm -f crte_*.txt - -fresh: clean copy configs - @echo "synth directory cleaned and fresh config files written" + rm -f crte_*.txt \ No newline at end of file diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 978365b16..430f86178 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -28,16 +28,16 @@ def synthsintocsv(): file = open("Summary.csv", "w") writer = csv.writer(file) - writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area']) + writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area']) for oneSynth in allSynths: descrip = specReg.findall(oneSynth) width = descrip[2][:4] config = descrip[2][4:] if descrip[3][-2:] == 'nm': - special = '' + mod = '' else: - special = descrip[3] + mod = descrip[3] descrip = descrip[1:] tech = descrip[3][:-2] freq = descrip[4] @@ -57,12 +57,12 @@ def synthsintocsv(): else: delay = 1000/int(freq) - metrics[0] area = metrics[1] - writer.writerow([width, config, special, tech, freq, delay, area]) + writer.writerow([width, config, mod, tech, freq, delay, area]) file.close() def synthsfromcsv(filename): - Synth = namedtuple("Synth", "width config special tech freq delay area") + Synth = namedtuple("Synth", "width config mod tech freq delay area") with open(filename, newline='') as csvfile: csvreader = csv.reader(csvfile) global allSynths @@ -81,14 +81,9 @@ def freqPlot(tech, width, config): ''' plots delay, area for syntheses with specified tech, module, width ''' - current_directory = os.getcwd() - final_directory = os.path.join(current_directory, 'plots/wally') - if not os.path.exists(final_directory): - os.makedirs(final_directory) - freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: - if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): + if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod): ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period freqsL[ind] += [oneSynth.freq] delaysL[ind] += [oneSynth.delay] @@ -130,7 +125,7 @@ def freqPlot(tech, width, config): ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) addFO4axis(fig, ax1, tech) - plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png') + plt.savefig(final_directory + '/freqSweep_' + tech + '_' + width + config + '.png') def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): @@ -168,7 +163,7 @@ def plotFeatures(tech, width, config): if (oneSynth.config == config) & (width == oneSynth.width): delays += [oneSynth.delay] areas += [oneSynth.area] - labels += [oneSynth.special] + labels += [oneSynth.mod] fig, (ax) = plt.subplots(1, 1) @@ -176,28 +171,28 @@ def plotFeatures(tech, width, config): titlestr = tech+'_'+width+config plt.title(titlestr) - plt.savefig('./plots/wally/features_'+titlestr+'.png') + plt.savefig(final_directory + '/features_'+titlestr+'.png') -def plotConfigs(tech, special=''): +def plotConfigs(tech, mod=''): delays, areas, labels = ([] for i in range(3)) freq = techdict[tech].targfreq for oneSynth in allSynths: - if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): - delays += [oneSynth.delay] - areas += [oneSynth.area] - labels += [oneSynth.width + oneSynth.config] + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.width + oneSynth.config] fig, (ax) = plt.subplots(1, 1) fig = areaDelay(tech, delays, areas, labels, fig, ax) - titleStr = tech+'_'+special + titleStr = tech+'_'+mod plt.title(titleStr) - plt.savefig('./plots/wally/configs_' + titleStr + '.png') + plt.savefig(final_directory + '/configs_' + titleStr + '.png') -def normAreaDelay(special=''): +def normAreaDelay(mod=''): fig, (ax) = plt.subplots(1, 1) fullLeg = [] for tech in list(techdict.keys()): @@ -205,7 +200,7 @@ def normAreaDelay(special=''): spec = techdict[tech] freq = spec.targfreq for oneSynth in allSynths: - if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod): delays += [oneSynth.delay] areas += [oneSynth.area] labels += [oneSynth.width + oneSynth.config] @@ -216,7 +211,7 @@ def normAreaDelay(special=''): ax.set_xlabel('Cycle Time (FO4)') ax.set_ylabel('Area (add32)') ax.legend(handles = fullLeg, loc='upper left') - plt.savefig('./plots/wally/normAreaDelay.png') + plt.savefig(final_directory + '/normAreaDelay.png') def addFO4axis(fig, ax, tech): @@ -254,12 +249,17 @@ if __name__ == '__main__': techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) + current_directory = os.getcwd() + final_directory = os.path.join(current_directory, 'wallyplots') + if not os.path.exists(final_directory): + os.makedirs(final_directory) + synthsintocsv() synthsfromcsv('Summary.csv') freqPlot('tsmc28', 'rv32', 'e') freqPlot('sky90', 'rv32', 'e') plotFeatures('sky90', 'rv64', 'gc') plotFeatures('tsmc28', 'rv64', 'gc') - plotConfigs('sky90', special='orig') - plotConfigs('tsmc28', special='orig') - normAreaDelay(special='orig') + plotConfigs('sky90', mod='orig') + plotConfigs('tsmc28', mod='orig') + normAreaDelay(mod='orig') diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 0c1579813..6b10f2e8b 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -5,20 +5,14 @@ import subprocess from multiprocessing import Pool import argparse -def runSynth(config, tech, freq, maxopt): +def runSynth(config, mod, tech, freq, maxopt): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt) pool.map(mask, [command]) def mask(command): subprocess.Popen(command, shell=True) -def freshStart(): - out = subprocess.check_output(['bash','-c', 'make fresh']) - for x in out.decode("utf-8").split('\n')[:-1]: - print(x) - return - if __name__ == '__main__': @@ -41,24 +35,21 @@ if __name__ == '__main__': args = parser.parse_args() - freq = args.targetfreq if args.targetfreq else 3000 tech = args.tech if args.tech else 'sky90' + defaultfreq = 3000 if tech == 'sky90' else 10000 + freq = args.targetfreq if args.targetfreq else defaultfreq maxopt = int(args.maxopt) + mod = 'orig' # until memory integrated if args.freqsweep: sc = args.freqsweep config = args.version if args.version else 'rv32e' - freshStart() for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep - runSynth(config, tech, freq, maxopt) + runSynth(config, mod, tech, freq, maxopt) if args.configsweep: - freshStart() - for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs - config = config + '_orig' # until memory integrated - runSynth(config, tech, freq, maxopt) + for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs + runSynth(config, mod, tech, freq, maxopt) if args.featuresweep: - freshStart() - v = args.version if args.version else 'rv64gc' - for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations - config = v + '_' + mod - runSynth(config, tech, freq, maxopt) + config = args.version if args.version else 'rv64gc' + for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', + runSynth(config, mod, tech, freq, maxopt) From eda3d4c6675f4f38132bf8a5a2abdd0dd95307e3 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Thu, 26 Jan 2023 04:53:43 +0000 Subject: [PATCH 104/294] cleaned up comments --- synthDC/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 5551e252f..81d982251 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -45,8 +45,8 @@ default: @echo "Use wallySynth.py to run a concurrent sweep " -DIRS32 = rv32e rv32gc rv32ic rv32i # added 32i -DIRS64 = rv64i rv64gc # use just 64i, lose ic +DIRS32 = rv32e rv32gc rv32ic rv32i +DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) # bpred: From 6ece31183c4c6bedb2bda7e8e6ef02aafd2df92c Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Thu, 26 Jan 2023 06:58:15 +0200 Subject: [PATCH 105/294] Fixed config file writing for synthesis (#29) * Fixed writing config files for synth sweeps * cleaned up comments --- .gitignore | 2 +- synthDC/Makefile | 72 ++++++++++++++++++++------------------- synthDC/extractSummary.py | 54 ++++++++++++++--------------- synthDC/wallySynth.py | 31 ++++++----------- 4 files changed, 76 insertions(+), 83 deletions(-) diff --git a/.gitignore b/.gitignore index c4c71a623..609ef1487 100644 --- a/.gitignore +++ b/.gitignore @@ -76,7 +76,7 @@ synthDC/runs/ synthDC/newRuns synthDC/ppa/PPAruns synthDC/ppa/plots -synthDC/plots/ +synthDC/wallyplots/ synthDC/runArchive synthDC/hdl /pipelined/regression/power.saif diff --git a/synthDC/Makefile b/synthDC/Makefile index 98b719428..81d982251 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -8,6 +8,7 @@ NAME := synth export DESIGN ?= wallypipelinedcore export FREQ ?= 3000 export CONFIG ?= rv32e +export MOD ?= orig # title to add a note in the synth's directory name TITLE = # tsmc28, sky130, and sky90 presently supported @@ -22,13 +23,15 @@ export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 -CONFIGDIR ?= ${WALLY}/pipelined/config +configAsList := $(subst _, ,$(CONFIG)) +BASECONFIG := $(word 1, $(configAsList)) +OLDCONFIGDIR ?= ${WALLY}/pipelined/config +CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) -# FREQS = 25 50 100 150 200 250 300 350 400 # k = 3 6 print: @@ -42,8 +45,8 @@ default: @echo "Use wallySynth.py to run a concurrent sweep " -DIRS32 = rv32e rv32gc rv32ic -DIRS64 = rv64ic rv64gc +DIRS32 = rv32e rv32gc rv32ic rv32i +DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) # bpred: @@ -51,73 +54,72 @@ DIRS = $(DIRS32) $(DIRS64) # @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) # @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) -copy: - # remove old config files - rm -rf $(CONFIGDIR)/*_* - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) +configs: $(BASECONFIG) +$(BASECONFIG): + @echo $(BASECONFIG) + cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh - @$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) - @$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) - -configs: $(DIRS) -$(DIRS): +ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else + $(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64)) + @echo "Config not in list, RAM_RANGE will be unmodified" +endif # turn off FPU - rm -rf $(CONFIGDIR)/$@_FPUoff cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh # PMP 16 - rm -rf $(CONFIGDIR)/$@_PMP16 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh # PMP 0 - rm -rf $(CONFIGDIR)/$@_PMP0 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh # no muldiv - rm -rf $(CONFIGDIR)/$@_noMulDiv cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh # no priv - rm -rf $(CONFIGDIR)/$@_noPriv cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh +ifeq ($(SAIFPOWER), 1) + cp -f ../pipelined/regression/power.saif . +endif + freqs: @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) -synth: +mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) - @mkdir -p $(OUTPUTDIR)/hdl + @mkdir -p $(OUTPUTDIR)/hdl/config @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -ifeq ($(SAIFPOWER), 1) - cp -f ../pipelined/regression/power.saif . -endif + +synth: mkdirecs configs rundc clean + +rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out -# rm -rf $(OUTPUTDIR)/hdl + +clean: + rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/alib-52 - -clean: rm -f default.svf rm -f command.log rm -f filenames*.log rm -f power.saif rm -f Synopsys_stack_trace_*.txt - rm -f crte_*.txt - -fresh: clean copy configs - @echo "synth directory cleaned and fresh config files written" + rm -f crte_*.txt \ No newline at end of file diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 978365b16..430f86178 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -28,16 +28,16 @@ def synthsintocsv(): file = open("Summary.csv", "w") writer = csv.writer(file) - writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area']) + writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area']) for oneSynth in allSynths: descrip = specReg.findall(oneSynth) width = descrip[2][:4] config = descrip[2][4:] if descrip[3][-2:] == 'nm': - special = '' + mod = '' else: - special = descrip[3] + mod = descrip[3] descrip = descrip[1:] tech = descrip[3][:-2] freq = descrip[4] @@ -57,12 +57,12 @@ def synthsintocsv(): else: delay = 1000/int(freq) - metrics[0] area = metrics[1] - writer.writerow([width, config, special, tech, freq, delay, area]) + writer.writerow([width, config, mod, tech, freq, delay, area]) file.close() def synthsfromcsv(filename): - Synth = namedtuple("Synth", "width config special tech freq delay area") + Synth = namedtuple("Synth", "width config mod tech freq delay area") with open(filename, newline='') as csvfile: csvreader = csv.reader(csvfile) global allSynths @@ -81,14 +81,9 @@ def freqPlot(tech, width, config): ''' plots delay, area for syntheses with specified tech, module, width ''' - current_directory = os.getcwd() - final_directory = os.path.join(current_directory, 'plots/wally') - if not os.path.exists(final_directory): - os.makedirs(final_directory) - freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: - if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): + if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod): ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period freqsL[ind] += [oneSynth.freq] delaysL[ind] += [oneSynth.delay] @@ -130,7 +125,7 @@ def freqPlot(tech, width, config): ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) addFO4axis(fig, ax1, tech) - plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png') + plt.savefig(final_directory + '/freqSweep_' + tech + '_' + width + config + '.png') def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): @@ -168,7 +163,7 @@ def plotFeatures(tech, width, config): if (oneSynth.config == config) & (width == oneSynth.width): delays += [oneSynth.delay] areas += [oneSynth.area] - labels += [oneSynth.special] + labels += [oneSynth.mod] fig, (ax) = plt.subplots(1, 1) @@ -176,28 +171,28 @@ def plotFeatures(tech, width, config): titlestr = tech+'_'+width+config plt.title(titlestr) - plt.savefig('./plots/wally/features_'+titlestr+'.png') + plt.savefig(final_directory + '/features_'+titlestr+'.png') -def plotConfigs(tech, special=''): +def plotConfigs(tech, mod=''): delays, areas, labels = ([] for i in range(3)) freq = techdict[tech].targfreq for oneSynth in allSynths: - if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): - delays += [oneSynth.delay] - areas += [oneSynth.area] - labels += [oneSynth.width + oneSynth.config] + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.width + oneSynth.config] fig, (ax) = plt.subplots(1, 1) fig = areaDelay(tech, delays, areas, labels, fig, ax) - titleStr = tech+'_'+special + titleStr = tech+'_'+mod plt.title(titleStr) - plt.savefig('./plots/wally/configs_' + titleStr + '.png') + plt.savefig(final_directory + '/configs_' + titleStr + '.png') -def normAreaDelay(special=''): +def normAreaDelay(mod=''): fig, (ax) = plt.subplots(1, 1) fullLeg = [] for tech in list(techdict.keys()): @@ -205,7 +200,7 @@ def normAreaDelay(special=''): spec = techdict[tech] freq = spec.targfreq for oneSynth in allSynths: - if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod): delays += [oneSynth.delay] areas += [oneSynth.area] labels += [oneSynth.width + oneSynth.config] @@ -216,7 +211,7 @@ def normAreaDelay(special=''): ax.set_xlabel('Cycle Time (FO4)') ax.set_ylabel('Area (add32)') ax.legend(handles = fullLeg, loc='upper left') - plt.savefig('./plots/wally/normAreaDelay.png') + plt.savefig(final_directory + '/normAreaDelay.png') def addFO4axis(fig, ax, tech): @@ -254,12 +249,17 @@ if __name__ == '__main__': techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) + current_directory = os.getcwd() + final_directory = os.path.join(current_directory, 'wallyplots') + if not os.path.exists(final_directory): + os.makedirs(final_directory) + synthsintocsv() synthsfromcsv('Summary.csv') freqPlot('tsmc28', 'rv32', 'e') freqPlot('sky90', 'rv32', 'e') plotFeatures('sky90', 'rv64', 'gc') plotFeatures('tsmc28', 'rv64', 'gc') - plotConfigs('sky90', special='orig') - plotConfigs('tsmc28', special='orig') - normAreaDelay(special='orig') + plotConfigs('sky90', mod='orig') + plotConfigs('tsmc28', mod='orig') + normAreaDelay(mod='orig') diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 0c1579813..6b10f2e8b 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -5,20 +5,14 @@ import subprocess from multiprocessing import Pool import argparse -def runSynth(config, tech, freq, maxopt): +def runSynth(config, mod, tech, freq, maxopt): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt) pool.map(mask, [command]) def mask(command): subprocess.Popen(command, shell=True) -def freshStart(): - out = subprocess.check_output(['bash','-c', 'make fresh']) - for x in out.decode("utf-8").split('\n')[:-1]: - print(x) - return - if __name__ == '__main__': @@ -41,24 +35,21 @@ if __name__ == '__main__': args = parser.parse_args() - freq = args.targetfreq if args.targetfreq else 3000 tech = args.tech if args.tech else 'sky90' + defaultfreq = 3000 if tech == 'sky90' else 10000 + freq = args.targetfreq if args.targetfreq else defaultfreq maxopt = int(args.maxopt) + mod = 'orig' # until memory integrated if args.freqsweep: sc = args.freqsweep config = args.version if args.version else 'rv32e' - freshStart() for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep - runSynth(config, tech, freq, maxopt) + runSynth(config, mod, tech, freq, maxopt) if args.configsweep: - freshStart() - for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs - config = config + '_orig' # until memory integrated - runSynth(config, tech, freq, maxopt) + for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs + runSynth(config, mod, tech, freq, maxopt) if args.featuresweep: - freshStart() - v = args.version if args.version else 'rv64gc' - for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations - config = v + '_' + mod - runSynth(config, tech, freq, maxopt) + config = args.version if args.version else 'rv64gc' + for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', + runSynth(config, mod, tech, freq, maxopt) From 29d4cd7ffa3705f31285bf4e763291481f5aae37 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 23:33:03 -0600 Subject: [PATCH 106/294] Modified the RAS to correctly repair itself. --- pipelined/src/ifu/brpred/RAsPredictor.sv | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 6f2cbd059..17ebbd1c4 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -49,29 +49,33 @@ module RASPredictor #(parameter int StackSize = 16 logic PopF; logic PushE; logic RepairD; - logic PossibleRepairD; + logic IncrRepairD, DecRepairD; logic DecrementPtr; assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - // **********this part is wrong. - assign PossibleRepairD = (InstrClassD[2] & ~StallE & FlushE) | (PredInstrClassF[2] & ~StallD & FlushD); - assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE; + + assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) | // Wrong class undo increment or decrement. + (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed + (~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed + + assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed + (~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed + (WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not + + assign DecRepairD = (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret. + assign PushE = InstrClassE[3] & ~StallM & ~FlushM; assign CounterEn = PopF | PushE | RepairD; - assign DecrementPtr = PopF | PossibleRepairD; + assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD; mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD); assign PtrM1 = PtrQ - 1'b1; assign PtrP1 = PtrQ + 1'b1; - flopenr #(Depth) PTR(.clk(clk), - .reset(reset), - .en(CounterEn), - .d(PtrD), - .q(PtrQ)); + flopenr #(Depth) PTR(clk, reset, CounterEn, PtrD, PtrQ); // RAS must be reset. always_ff @ (posedge clk) begin From 2ee6ffe74b75c7c132003ae5c51dcc528b1c43b1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 10:54:43 -0600 Subject: [PATCH 107/294] Improved no class prediction mode. --- pipelined/src/ifu/brpred/bpred.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 82bdf1f00..ff26904ce 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -132,9 +132,6 @@ module bpred ( // 1) A direction (1 = Taken, 0 = Not Taken) // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | - PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) ; // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets @@ -183,8 +180,14 @@ module bpred ( assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 (`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)); assign PredInstrClassF = InstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | + PredInstrClassF[2] | + (PredInstrClassF[1]) ; end else begin assign PredInstrClassF = BTBPredInstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | + PredInstrClassF[2] | + (PredInstrClassF[1] & PredValidF) ; end From 36526734870bd5eaef40a81b1e2d3443bfe8e120 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 11:07:47 -0600 Subject: [PATCH 108/294] Fixed compressed branch class decode. --- pipelined/src/ifu/brpred/bpred.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index ff26904ce..b55738ae8 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 0 +`define INSTR_CLASS_PRED 1 module bpred ( input logic clk, reset, @@ -178,7 +178,7 @@ module bpred ( (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 - (`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)); + (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | PredInstrClassF[2] | From e0ca23cdd67788bf44a373660cdd8390fb967db1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 12:19:33 -0600 Subject: [PATCH 109/294] Fixed another bug with the compressed instruction class decode. --- pipelined/src/ifu/brpred/bpred.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index b55738ae8..38fd39bc3 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 1 +`define INSTR_CLASS_PRED 0 module bpred ( input logic clk, reset, @@ -168,7 +168,7 @@ module bpred ( assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | - (`C_SUPPORTED & CompressedOpcF == 5'h0e); + (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 From bbb47fc94344a9b9d387045d6669860e9e2513cb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 13:21:16 -0600 Subject: [PATCH 110/294] Changed the performance counters to track different data. Now rather than tracking jump(r) we track jump(r) and taken branches. --- pipelined/regression/wave.do | 35 +++++++++++++++++----- pipelined/src/ifu/brpred/bpred.sv | 36 +++++++++++++++++++++-- pipelined/src/ifu/ifu.sv | 3 +- pipelined/src/privileged/csr.sv | 3 +- pipelined/src/privileged/csrc.sv | 3 +- pipelined/src/privileged/privileged.sv | 3 +- pipelined/src/wally/wallypipelinedcore.sv | 5 ++-- 7 files changed, 72 insertions(+), 16 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index ccc5928a5..1e34435a5 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -1,4 +1,5 @@ onerror {resume} +quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset @@ -36,11 +37,11 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF add wave -noupdate -group PCS /testbench/dut/core/PCF add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD @@ -567,8 +568,28 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/CompressedOpcF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/InstrClassF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjal +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cj +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjr +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjalr +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD +add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {117097 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {48955828 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -584,4 +605,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {117047 ns} {117181 ns} +WaveRestoreZoom {48955732 ns} {48955990 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 38fd39bc3..6af314646 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -55,6 +55,7 @@ module bpred ( input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br // Report branch prediction status output logic BPPredWrongE, // Prediction is wrong @@ -82,7 +83,18 @@ module bpred ( logic [`XLEN-1:0] PCNext0F; logic [`XLEN-1:0] PCCorrectE; logic [3:0] WrongPredInstrClassD; + + +//************ new resolve issues + logic BTBTargetWrongE; + logic RASTargetWrongE; + logic JumpOrTakenBranchE; + + + logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; + + // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. if (`BPTYPE == "BPTWOBIT") begin:Predictor @@ -200,6 +212,7 @@ module bpred ( flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); + flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); // branch predictor flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, @@ -234,9 +247,13 @@ module bpred ( assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE; // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. - assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; + //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; + //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE; + assign BTBPredPCWrongE = BTBTargetWrongE; + // similar with RAS. Over counts ras if the class prediction was wrong. - assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE; + //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE; + assign RASPredPCWrongE = RASTargetWrongE; // Finally if the real instruction class is non CFI but the predictor said it was we need to count. assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; @@ -260,10 +277,23 @@ module bpred ( // end // performance counters - // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) + // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) + assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; + + assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; + + flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE); + + flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); + flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); + + + endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 26227bb9b..9be88d568 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -60,6 +60,7 @@ module ifu ( output logic [`XLEN-1:0] PCM, // Memory stage instruction address // branch predictor output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + output logic JumpOrTakenBranchM, output logic DirPredictionWrongM, // Prediction direction is wrong output logic BTBPredPCWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong @@ -327,7 +328,7 @@ module ifu ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index d6118e203..9a91d371e 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -62,6 +62,7 @@ module csr #(parameter input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, input logic [3:0] InstrClassM, + input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, input logic DCacheAccess, input logic ICacheMiss, @@ -255,7 +256,7 @@ module csr #(parameter if (`ZICOUNTERS_SUPPORTED) begin:counters csrc counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index de5743858..83e3ccdfe 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -49,6 +49,7 @@ module csrc #(parameter input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, input logic [3:0] InstrClassM, + input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, input logic DCacheAccess, input logic ICacheMiss, @@ -87,7 +88,7 @@ module csrc #(parameter assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM; // branch predictor wrong target - assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM; // jump instructions + assign CounterEvent[7] = JumpOrTakenBranchM & InstrValidNotFlushedM; // jump or taken branch instructions assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 32ef2eb56..c3f321753 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -51,6 +51,7 @@ module privileged ( input logic RASPredPCWrongM, // return adddress stack guessed wrong target input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class input logic [3:0] InstrClassM, // actual instruction class + input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, // data cache miss input logic DCacheAccess, // data cache accessed (hit or miss) input logic ICacheMiss, // instruction cache miss @@ -124,7 +125,7 @@ module privileged ( .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, - .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, + .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 2b71851f5..c6f5240a3 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -161,6 +161,7 @@ module wallypipelinedcore ( logic BigEndianM; logic FCvtIntE; logic CommittedF; + logic JumpOrTakenBranchM; // Bit manipulation unit logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU @@ -177,7 +178,7 @@ module wallypipelinedcore ( .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, // Mem .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, + .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, // Faults out .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, @@ -291,7 +292,7 @@ module wallypipelinedcore ( .FRegWriteM, .LoadStallD, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, - .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, + .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, From 7004f262c9db2f84b00d5b09731f844d07dc32ad Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 26 Jan 2023 14:51:39 -0800 Subject: [PATCH 111/294] Added DWARF symbols for QEMU simulation --- examples/C/sum/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/C/sum/Makefile b/examples/C/sum/Makefile index 7c21cce23..a302309ff 100644 --- a/examples/C/sum/Makefile +++ b/examples/C/sum/Makefile @@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET) riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump $(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ + riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\ -march=rv64gc -mabi=lp64d -mcmodel=medany \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ -T../common/test.ld -I../common \ From 5df4679bcb8ecfa0a683f574eaf2d55d578d9fb6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 26 Jan 2023 14:53:25 -0800 Subject: [PATCH 112/294] Removed old link to imperas-riscv-tests --- addins/imperas-riscv-tests | 1 - 1 file changed, 1 deletion(-) delete mode 120000 addins/imperas-riscv-tests diff --git a/addins/imperas-riscv-tests b/addins/imperas-riscv-tests deleted file mode 120000 index c3f365a40..000000000 --- a/addins/imperas-riscv-tests +++ /dev/null @@ -1 +0,0 @@ -/opt/riscv/imperas-riscv-tests/ \ No newline at end of file From e682b8d0d40590d6c4047a28eea030201c41b21c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 05:55:31 -0800 Subject: [PATCH 113/294] renamed brpred to bpred --- pipelined/src/ifu/{brpred => bpred}/RAsPredictor.sv | 0 pipelined/src/ifu/{brpred => bpred}/bpred.sv | 0 pipelined/src/ifu/{brpred => bpred}/btb.sv | 0 pipelined/src/ifu/{brpred => bpred}/foldedgshare.sv | 0 pipelined/src/ifu/{brpred => bpred}/globalhistory.sv | 0 pipelined/src/ifu/{brpred => bpred}/gshare.sv | 0 pipelined/src/ifu/{brpred => bpred}/localHistoryPredictor.sv | 0 pipelined/src/ifu/{brpred => bpred}/optgshare.sv | 0 pipelined/src/ifu/{brpred => bpred}/satCounter2.sv | 0 pipelined/src/ifu/{brpred => bpred}/speculativeglobalhistory.sv | 0 pipelined/src/ifu/{brpred => bpred}/speculativegshare.sv | 0 pipelined/src/ifu/{brpred => bpred}/twoBitPredictor.sv | 0 12 files changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/ifu/{brpred => bpred}/RAsPredictor.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/bpred.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/btb.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/foldedgshare.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/globalhistory.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/gshare.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/localHistoryPredictor.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/optgshare.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/satCounter2.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/speculativeglobalhistory.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/speculativegshare.sv (100%) rename pipelined/src/ifu/{brpred => bpred}/twoBitPredictor.sv (100%) diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RAsPredictor.sv similarity index 100% rename from pipelined/src/ifu/brpred/RAsPredictor.sv rename to pipelined/src/ifu/bpred/RAsPredictor.sv diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv similarity index 100% rename from pipelined/src/ifu/brpred/bpred.sv rename to pipelined/src/ifu/bpred/bpred.sv diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv similarity index 100% rename from pipelined/src/ifu/brpred/btb.sv rename to pipelined/src/ifu/bpred/btb.sv diff --git a/pipelined/src/ifu/brpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv similarity index 100% rename from pipelined/src/ifu/brpred/foldedgshare.sv rename to pipelined/src/ifu/bpred/foldedgshare.sv diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/bpred/globalhistory.sv similarity index 100% rename from pipelined/src/ifu/brpred/globalhistory.sv rename to pipelined/src/ifu/bpred/globalhistory.sv diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/bpred/gshare.sv similarity index 100% rename from pipelined/src/ifu/brpred/gshare.sv rename to pipelined/src/ifu/bpred/gshare.sv diff --git a/pipelined/src/ifu/brpred/localHistoryPredictor.sv b/pipelined/src/ifu/bpred/localHistoryPredictor.sv similarity index 100% rename from pipelined/src/ifu/brpred/localHistoryPredictor.sv rename to pipelined/src/ifu/bpred/localHistoryPredictor.sv diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/bpred/optgshare.sv similarity index 100% rename from pipelined/src/ifu/brpred/optgshare.sv rename to pipelined/src/ifu/bpred/optgshare.sv diff --git a/pipelined/src/ifu/brpred/satCounter2.sv b/pipelined/src/ifu/bpred/satCounter2.sv similarity index 100% rename from pipelined/src/ifu/brpred/satCounter2.sv rename to pipelined/src/ifu/bpred/satCounter2.sv diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv similarity index 100% rename from pipelined/src/ifu/brpred/speculativeglobalhistory.sv rename to pipelined/src/ifu/bpred/speculativeglobalhistory.sv diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv similarity index 100% rename from pipelined/src/ifu/brpred/speculativegshare.sv rename to pipelined/src/ifu/bpred/speculativegshare.sv diff --git a/pipelined/src/ifu/brpred/twoBitPredictor.sv b/pipelined/src/ifu/bpred/twoBitPredictor.sv similarity index 100% rename from pipelined/src/ifu/brpred/twoBitPredictor.sv rename to pipelined/src/ifu/bpred/twoBitPredictor.sv From 4f7e1b942348fa4bdb2afe2c207af9382eb3d6fe Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 05:55:53 -0800 Subject: [PATCH 114/294] Fixed typo in bpred preventing compiling --- pipelined/src/ifu/bpred/bpred.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 4e1ada3c1..0319d3a08 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -49,7 +49,7 @@ module bpred ( // Branch and jump outcome input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] dPCLinkE, // The address following the branch instruction. (AKA Fall through address) + input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br // Report branch prediction status From b81b5781e18237f684853644d707a67bbf5a1a2b Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 05:56:49 -0800 Subject: [PATCH 115/294] Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested --- .../spike/{spike_rv32imc_isa.yaml => spike_rv32gc_isa.yaml} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename tests/riscof/spike/{spike_rv32imc_isa.yaml => spike_rv32gc_isa.yaml} (100%) diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml similarity index 100% rename from tests/riscof/spike/spike_rv32imc_isa.yaml rename to tests/riscof/spike/spike_rv32gc_isa.yaml From 4744996282f2e9272f28b2a69430df56384dec6e Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 05:57:05 -0800 Subject: [PATCH 116/294] Removed suggestion about make allclean --- pipelined/regression/regression-wally | 3 --- 1 file changed, 3 deletions(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 6bbaa04b9..7398d7cec 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -204,9 +204,6 @@ def main(): # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) - # Remind the user to try `make allclean`, since it may be needed if test - # cases have changed - print("Reminder: have you run `make allclean`?") else: print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}") return num_fail From 7fbbed7927de65ff3135e7bfce63e19210f91ccf Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 05:57:58 -0800 Subject: [PATCH 117/294] Update riscof makefile to use rv32gc config --- tests/riscof/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 2918494dd..d963e4f0d 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -16,7 +16,7 @@ root: mkdir -p $(work) mkdir -p $(arch_workdir) mkdir -p $(wally_workdir) - sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini + sed 's,{0},$(current_dir),g;s,{1},32gc,g' config.ini > config32.ini sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini From 37ba3d0fcde99f79072496173b9a31b172ce175b Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 06:15:20 -0800 Subject: [PATCH 118/294] Removed f tests from rv32e --- tests/riscof/spike/spike_rv32e_isa.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/riscof/spike/spike_rv32e_isa.yaml b/tests/riscof/spike/spike_rv32e_isa.yaml index 7ae54347a..9e9775a9b 100644 --- a/tests/riscof/spike/spike_rv32e_isa.yaml +++ b/tests/riscof/spike/spike_rv32e_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV32EMFCZicsr_Zifencei + ISA: RV32EMCZicsr_Zifencei physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001034 + reset-val: 0x40001014 rv32: accessible: true mxl: From 2af94bf283cc3eb4bc4ed5dc2b5b8c43e97d0527 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 07:21:55 -0800 Subject: [PATCH 119/294] Removed unused reference files --- .../C/references/cadd-01.reference_output | 580 -------------- .../C/references/caddi-01.reference_output | 375 --------- .../references/caddi16sp-01.reference_output | 72 -- .../references/caddi4spn-01.reference_output | 19 - .../C/references/cand-01.reference_output | 586 -------------- .../C/references/candi-01.reference_output | 374 --------- .../C/references/cbeqz-01.reference_output | 84 -- .../C/references/cbnez-01.reference_output | 84 -- .../C/references/cj-01.reference_output | 17 - .../C/references/cjal-01.reference_output | 18 - .../C/references/cjalr-01.reference_output | 15 - .../C/references/cjr-01.reference_output | 15 - .../C/references/cli-01.reference_output | 17 - .../C/references/clui-01.reference_output | 15 - .../C/references/clw-01.reference_output | 13 - .../C/references/clwsp-01.reference_output | 15 - .../C/references/cmv-01.reference_output | 85 -- .../C/references/cnop-01.reference_output | 14 - .../C/references/cor-01.reference_output | 582 -------------- .../C/references/cslli-01.reference_output | 86 --- .../C/references/csrai-01.reference_output | 85 -- .../C/references/csrli-01.reference_output | 87 --- .../C/references/csub-01.reference_output | 581 -------------- .../C/references/csw-01.reference_output | 68 -- .../C/references/cswsp-01.reference_output | 70 -- .../C/references/cxor-01.reference_output | 580 -------------- .../M/references/div-01.reference_output | 581 -------------- .../M/references/divu-01.reference_output | 729 ------------------ .../M/references/mul-01.reference_output | 585 -------------- .../M/references/mulh-01.reference_output | 591 -------------- .../M/references/mulhsu-01.reference_output | 654 ---------------- .../M/references/mulhu-01.reference_output | 724 ----------------- .../M/references/rem-01.reference_output | 586 -------------- .../M/references/remu-01.reference_output | 725 ----------------- .../references/WALLY-fld-01.reference_output | 3 - .../I/references/E-add-01.reference_output | 584 -------------- .../I/references/E-addi-01.reference_output | 564 -------------- .../I/references/E-and-01.reference_output | 588 -------------- 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-fffffaaf -00000550 -00000006 -aaaaaa84 -5555557e -aaaaaccd -aaaaa99e -aaaaaaac -fffefdff -ffff7fff -00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output deleted file mode 100644 index f9c1b5659..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output +++ /dev/null @@ -1,12 +0,0 @@ -00000000 -00000001 -ffffffff -00000001 -00000002 -00000000 -ffffffff -00000000 -fffffffe -b6944260 -83edeb47 -0c939c34 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output deleted file mode 100644 index 6e9ae61d7..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output +++ /dev/null @@ -1,12 +0,0 @@ -00000000 -00000001 -00000000 -00000000 -00000000 -00000000 -00000001 -00000001 -00000000 -00000000 -00000001 -00000001 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output deleted file mode 100644 index 993b67cd3..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output +++ /dev/null @@ -1,12 +0,0 @@ -00000000 -00000001 -00000001 -00000000 -00000000 -00000001 -00000000 -00000000 -00000000 -00000001 -00000001 -00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output deleted file mode 100644 index d35fb3fdb..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output +++ /dev/null @@ -1,12 +0,0 @@ -00000000 -ffffffff -00000001 -00000001 -00000000 -00000002 -ffffffff -fffffffe -00000000 -ebb7926c -e2aa20ca -63a59ba8 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output deleted file mode 100644 index 2448d94c1..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output +++ /dev/null @@ -1,12 +0,0 @@ -00000000 -00000001 -ffffffff -00000001 -00000000 -fffffffe -ffffffff -fffffffe -00000000 -674f4c2c -d1bb1e6e -3395fef6 From cea89f27cf6ae8535e70b7fa470480af48161e07 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 07:25:04 -0800 Subject: [PATCH 120/294] Removed unused WALLY test references --- .../I/references/WALLY-ADD.reference_output | 24 ------------------- .../I/references/WALLY-SLT.reference_output | 24 ------------------- .../I/references/WALLY-SLTU.reference_output | 24 ------------------- .../I/references/WALLY-SUB.reference_output | 24 ------------------- .../I/references/WALLY-XOR.reference_output | 24 ------------------- 5 files changed, 120 deletions(-) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output deleted file mode 100644 index 7e1ab4344..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output +++ /dev/null @@ -1,24 +0,0 @@ -00000000 -00000000 -00000001 -00000000 -ffffffff -ffffffff -00000001 -00000000 -00000002 -00000000 -00000000 -00000000 -ffffffff -ffffffff -00000000 -00000000 -fffffffe -ffffffff -393cb5d1 -72ca6f49 -7b12609b -245889d8 -7f42ac28 -af17a2d3 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output deleted file mode 100644 index 5958e1ed6..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output +++ /dev/null @@ -1,24 +0,0 @@ -00000000 -00000000 -00000001 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000001 -00000000 -00000001 -00000000 -00000000 -00000000 -00000001 -00000000 -00000000 -00000000 -00000000 -00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output deleted file mode 100644 index 476470e4a..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output +++ /dev/null @@ -1,24 +0,0 @@ -00000000 -00000000 -00000001 -00000000 -00000001 -00000000 -00000000 -00000000 -00000000 -00000000 -00000001 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000001 -00000000 -00000000 -00000000 -00000001 -00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output deleted file mode 100644 index cc7461347..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output +++ /dev/null @@ -1,24 +0,0 @@ -00000000 -00000000 -ffffffff -ffffffff -00000001 -00000000 -00000001 -00000000 -00000000 -00000000 -00000002 -00000000 -ffffffff -ffffffff -fffffffe -ffffffff -00000000 -00000000 -0f7dc13a -f51130ed -bb2485d0 -9633d6e4 -4557352f -60fe4e94 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output deleted file mode 100644 index 477289586..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output +++ /dev/null @@ -1,24 +0,0 @@ -00000000 -00000000 -00000001 -00000000 -ffffffff -ffffffff -00000001 -00000000 -00000000 -00000000 -fffffffe -ffffffff -ffffffff -ffffffff -fffffffe -ffffffff -00000000 -00000000 -e6f91511 -a770a807 -87ea008b -3afeadc9 -3e7f1ce8 -a43d2571 From d8f0e3dd709c81b8cc9695943e76e83e1f9e0c73 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 07:25:40 -0800 Subject: [PATCH 121/294] Modified testgen to not produce reference outputs --- tests/testgen/testgen.py | 8 -------- 1 file changed, 8 deletions(-) diff --git a/tests/testgen/testgen.py b/tests/testgen/testgen.py index c1526356b..02d16a319 100755 --- a/tests/testgen/testgen.py +++ b/tests/testgen/testgen.py @@ -76,11 +76,6 @@ def writeVector(a, b, storecmd, xlen): lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" # lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n" f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) testnum = testnum+1 ################################## @@ -114,12 +109,10 @@ for xlen in xlens: pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/" basename = "WALLY-" + test fname = pathname + "src/" + basename + ".S" - refname = pathname + "references/" + basename + ".reference_output" testnum = 0 # print custom header part f = open(fname, "w") - r = open(refname, "w") line = "///////////////////////////////////////////\n" f.write(line) lines="// "+fname+ "\n// " + author + "\n" @@ -154,7 +147,6 @@ for xlen in xlens: # lines = lines + "\nRV_COMPLIANCE_DATA_END\n" f.write(lines) f.close() - r.close() From 6c86c0389c16eede5f474d15f2cfd0677b003663 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 11:34:45 -0600 Subject: [PATCH 122/294] Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction. --- pipelined/regression/wave.do | 30 +++++++++++++++++-- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 19 ++++++++---- 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 1e34435a5..bfa161dad 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -588,8 +588,34 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {48955828 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -605,4 +631,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {48955732 ns} {48955990 ns} +WaveRestoreZoom {2195 ns} {2479 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6af314646..3fd021574 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 0 +`define INSTR_CLASS_PRED 1 module bpred ( input logic clk, reset, diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index b72aacb44..691693af6 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -51,7 +51,8 @@ module speculativegshare logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; - logic [k-1:0] GHRF; + logic [k-1:0] GHRF, OldGHRF; + logic OldGHRExtraF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; logic [k:-1] GHRNextD, OldGHRD; @@ -105,17 +106,23 @@ module speculativegshare satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline - assign GHRNextF = FlushD ? GHRNextD[k:1] : + assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF; - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); + flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); + assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-1:0], OldGHRExtraF} : // shift left **** missing bit + OldGHRF[k:0]; assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; + flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); - assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left - OldGHRD[k:0]; + //assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right + // WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left + // OldGHRD[k:0]; + assign GHRD = OldGHRD[k:0]; assign GHRNextE = FlushE ? GHRNextM : GHRD; flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); From 44c710202693919499627b8d947cff4a05cb8ba5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 09:54:50 -0800 Subject: [PATCH 123/294] Renamed ram2p1rw1be to match modeule name --- pipelined/src/generic/mem/{ram2p1rwbe.sv => ram2p1r1wbe.sv} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/generic/mem/{ram2p1rwbe.sv => ram2p1r1wbe.sv} (100%) diff --git a/pipelined/src/generic/mem/ram2p1rwbe.sv b/pipelined/src/generic/mem/ram2p1r1wbe.sv similarity index 100% rename from pipelined/src/generic/mem/ram2p1rwbe.sv rename to pipelined/src/generic/mem/ram2p1r1wbe.sv From cf49c7ddc12f7862643707bda3cc0cc33d4c13f6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 13:13:55 -0600 Subject: [PATCH 124/294] Found issue with branch predictor. --- pipelined/src/ifu/brpred/speculativegshare.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 691693af6..00a49ce24 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -113,8 +113,8 @@ module speculativegshare flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-1:0], OldGHRExtraF} : // shift left **** missing bit - OldGHRF[k:0]; + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF} : // shift left **** missing bit + OldGHRF[k-1:0]; assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; From 264f0ba0da0a0b2215984756c9afbe0f82d3aaf4 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 27 Jan 2023 14:35:34 -0600 Subject: [PATCH 125/294] Removed IOBUF's from sdc_controller. --- fpga/src/fpgaTop.v | 216 +++++++++++++----- .../src/uncore/newsdc/axi_sdc_controller.v | 118 +++++----- tests/custom/boot/boot.c | 40 ++++ 3 files changed, 259 insertions(+), 115 deletions(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 95f4582fa..bd7d95638 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -267,39 +267,60 @@ module fpgaTop wire s01_axi_rready; // Output Interface + wire [31:0]axi4in_axi_awaddr; + wire [7:0]axi4in_axi_awlen; + wire [2:0]axi4in_axi_awsize; + wire [1:0]axi4in_axi_awburst; + wire [0:0]axi4in_axi_awlock; + wire [3:0]axi4in_axi_awcache; + wire [2:0]axi4in_axi_awprot; + wire [3:0]axi4in_axi_awregion; + wire [3:0]axi4in_axi_awqos; + wire axi4in_axi_awvalid; + wire axi4in_axi_awready; + wire [31:0]axi4in_axi_wdata; + wire [3:0]axi4in_axi_wstrb; + wire axi4in_axi_wlast; + wire axi4in_axi_wvalid; + wire axi4in_axi_wready; + wire [1:0]axi4in_axi_bresp; + wire axi4in_axi_bvalid; + wire axi4in_axi_bready; + wire [31:0]axi4in_axi_araddr; + wire [7:0]axi4in_axi_arlen; + wire [2:0]axi4in_axi_arsize; + wire [1:0]axi4in_axi_arburst; + wire [0:0]axi4in_axi_arlock; + wire [3:0]axi4in_axi_arcache; + wire [2:0]axi4in_axi_arprot; + wire [3:0]axi4in_axi_arregion; + wire [3:0]axi4in_axi_arqos; + wire axi4in_axi_arvalid; + wire axi4in_axi_arready; + wire [31:0]axi4in_axi_rdata; + wire [1:0]axi4in_axi_rresp; + wire axi4in_axi_rlast; + wire axi4in_axi_rvalid; + wire axi4in_axi_rready; + + // AXI4 to AXI4-Lite Protocol converter output wire [31:0]SDCin_axi_awaddr; - wire [7:0]SDCin_axi_awlen; - wire [2:0]SDCin_axi_awsize; - wire [1:0]SDCin_axi_awburst; - wire [0:0]SDCin_axi_awlock; - wire [3:0]SDCin_axi_awcache; wire [2:0]SDCin_axi_awprot; - wire [3:0]SDCin_axi_awregion; - wire [3:0]SDCin_axi_awqos; wire SDCin_axi_awvalid; wire SDCin_axi_awready; wire [31:0]SDCin_axi_wdata; wire [3:0]SDCin_axi_wstrb; - wire SDCin_axi_wlast; wire SDCin_axi_wvalid; wire SDCin_axi_wready; wire [1:0]SDCin_axi_bresp; wire SDCin_axi_bvalid; wire SDCin_axi_bready; wire [31:0]SDCin_axi_araddr; - wire [7:0]SDCin_axi_arlen; - wire [2:0]SDCin_axi_arsize; - wire [1:0]SDCin_axi_arburst; - wire [0:0]SDCin_axi_arlock; - wire [3:0]SDCin_axi_arcache; wire [2:0]SDCin_axi_arprot; - wire [3:0]SDCin_axi_arregion; - wire [3:0]SDCin_axi_arqos; wire SDCin_axi_arvalid; wire SDCin_axi_arready; wire [31:0]SDCin_axi_rdata; wire [1:0]SDCin_axi_rresp; - wire SDCin_axi_rlast; wire SDCin_axi_rvalid; wire SDCin_axi_rready; // ---------------------------------------------------------------- @@ -408,6 +429,14 @@ module fpgaTop end endgenerate + // IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); + + + // reset controller XILINX IP xlnx_proc_sys_reset xlnx_proc_sys_reset_0 (.slowest_sync_clk(CPUCLK), @@ -514,7 +543,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({m_axi_awid, m01_axi_awid}), + .s_axi_awid({m_axi_awid, 8'b0}), .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), @@ -534,7 +563,7 @@ module fpgaTop .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), .s_axi_bready({m_axi_bready, m01_axi_bready}), - .s_axi_arid({m_axi_arid, m01_axi_arid}), + .s_axi_arid({m_axi_arid, 8'b0}), .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), @@ -570,7 +599,7 @@ module fpgaTop .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), .m_axi_wready({s00_axi_wready, s01_axi_wready}), - .m_axi_bid({s00_axi_bid, s01_axi_bid}), + .m_axi_bid({s00_axi_bid, 8'b0}), .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), .m_axi_bready({s00_axi_bready, s01_axi_bready}), @@ -586,7 +615,7 @@ module fpgaTop .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), .m_axi_arready({s00_axi_arready, s01_axi_arready}), - .m_axi_rid({s00_axi_rid, s01_axi_rid}), + .m_axi_rid({s00_axi_rid, 8'b0}), .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), @@ -645,42 +674,107 @@ module fpgaTop .s_axi_rready(s01_axi_rready), // Master interface - .m_axi_awaddr(SDCin_axi_awaddr), - .m_axi_awlen(SDCin_axi_awlen), - .m_axi_awsize(SDCin_axi_awsize), - .m_axi_awburst(SDCin_axi_awburst), - .m_axi_awlock(SDCin_axi_awlock), - .m_axi_awcache(SDCin_axi_awcache), - .m_axi_awprot(SDCin_axi_awprot), - .m_axi_awregion(SDCin_axi_awregion), - .m_axi_awqos(SDCin_axi_awqos), - .m_axi_awvalid(SDCin_axi_awvalid), - .m_axi_awready(SDCin_axi_awready), - .m_axi_wdata(SDCin_axi_wdata), - .m_axi_wstrb(SDCin_axi_wstrb), - .m_axi_wlast(SDCin_axi_wlast), - .m_axi_wvalid(SDCin_axi_wvalid), - .m_axi_wready(SDCin_axi_wready), - .m_axi_bresp(SDCin_axi_bresp), - .m_axi_bvalid(SDCin_axi_bvalid), - .m_axi_bready(SDCin_axi_bready), - .m_axi_araddr(SDCin_axi_araddr), - .m_axi_arlen(SDCin_axi_arlen), - .m_axi_arsize(SDCin_axi_arsize), - .m_axi_arburst(SDCin_axi_arburst), - .m_axi_arlock(SDCin_axi_arlock), - .m_axi_arcache(SDCin_axi_arcache), - .m_axi_arprot(SDCin_axi_arprot), - .m_axi_arregion(SDCin_axi_arregion), - .m_axi_arqos(SDCin_axi_arqos), - .m_axi_arvalid(SDCin_axi_arvalid), - .m_axi_arready(SDCin_axi_arready), - .m_axi_rdata(SDCin_axi_rdata), - .m_axi_rresp(SDCin_axi_rresp), - .m_axi_rlast(SDCin_axi_rlast), - .m_axi_rvalid(SDCin_axi_rvalid), - .m_axi_rready(SDCin_axi_rready) + .m_axi_awaddr(axi4in_axi_awaddr), + .m_axi_awlen(axi4in_axi_awlen), + .m_axi_awsize(axi4in_axi_awsize), + .m_axi_awburst(axi4in_axi_awburst), + .m_axi_awlock(axi4in_axi_awlock), + .m_axi_awcache(axi4in_axi_awcache), + .m_axi_awprot(axi4in_axi_awprot), + .m_axi_awregion(axi4in_axi_awregion), + .m_axi_awqos(axi4in_axi_awqos), + .m_axi_awvalid(axi4in_axi_awvalid), + .m_axi_awready(axi4in_axi_awready), + .m_axi_wdata(axi4in_axi_wdata), + .m_axi_wstrb(axi4in_axi_wstrb), + .m_axi_wlast(axi4in_axi_wlast), + .m_axi_wvalid(axi4in_axi_wvalid), + .m_axi_wready(axi4in_axi_wready), + .m_axi_bresp(axi4in_axi_bresp), + .m_axi_bvalid(axi4in_axi_bvalid), + .m_axi_bready(axi4in_axi_bready), + .m_axi_araddr(axi4in_axi_araddr), + .m_axi_arlen(axi4in_axi_arlen), + .m_axi_arsize(axi4in_axi_arsize), + .m_axi_arburst(axi4in_axi_arburst), + .m_axi_arlock(axi4in_axi_arlock), + .m_axi_arcache(axi4in_axi_arcache), + .m_axi_arprot(axi4in_axi_arprot), + .m_axi_arregion(axi4in_axi_arregion), + .m_axi_arqos(axi4in_axi_arqos), + .m_axi_arvalid(axi4in_axi_arvalid), + .m_axi_arready(axi4in_axi_arready), + .m_axi_rdata(axi4in_axi_rdata), + .m_axi_rresp(axi4in_axi_rresp), + .m_axi_rlast(axi4in_axi_rlast), + .m_axi_rvalid(axi4in_axi_rvalid), + .m_axi_rready(axi4in_axi_rready) ); + + xlnx_axi_prtcl_conv axi4tolite + (.aclk(CPUCLK), + .aresetn(peripheral_aresetn), + + // AXI4 In + .s_axi_awaddr(axi4in_axi_awaddr), + .s_axi_awlen(axi4in_axi_awlen), + .s_axi_awsize(axi4in_axi_awsize), + .s_axi_awburst(axi4in_axi_awburst), + .s_axi_awlock(axi4in_axi_awlock), + .s_axi_awcache(axi4in_axi_awcache), + .s_axi_awprot(axi4in_axi_awprot), + .s_axi_awregion(axi4in_axi_awregion), + .s_axi_awqos(axi4in_axi_awqos), + .s_axi_awvalid(axi4in_axi_awvalid), + .s_axi_awready(axi4in_axi_awready), + .s_axi_wdata(axi4in_axi_wdata), + .s_axi_wstrb(axi4in_axi_wstrb), + .s_axi_wlast(axi4in_axi_wlast), + .s_axi_wvalid(axi4in_axi_wvalid), + .s_axi_wready(axi4in_axi_wready), + .s_axi_bresp(axi4in_axi_bresp), + .s_axi_bvalid(axi4in_axi_bvalid), + .s_axi_bready(axi4in_axi_bready), + .s_axi_araddr(axi4in_axi_araddr), + .s_axi_arlen(axi4in_axi_arlen), + .s_axi_arsize(axi4in_axi_arsize), + .s_axi_arburst(axi4in_axi_arburst), + .s_axi_arlock(axi4in_axi_arlock), + .s_axi_arcache(axi4in_axi_arcache), + .s_axi_arprot(axi4in_axi_arprot), + .s_axi_arregion(axi4in_axi_arregion), + .s_axi_arqos(axi4in_axi_arqos), + .s_axi_arvalid(axi4in_axi_arvalid), + .s_axi_arready(axi4in_axi_arready), + .s_axi_rdata(axi4in_axi_rdata), + .s_axi_rresp(axi4in_axi_rresp), + .s_axi_rlast(axi4in_axi_rlast), + .s_axi_rvalid(axi4in_axi_rvalid), + .s_axi_rready(axi4in_axi_rready), + + // AXI4Lite Out + .m_axi_awaddr(SDCin_axi_awaddr), + .m_axi_awprot(SDCin_axi_awprot), + .m_axi_awvalid(SDCin_axi_awvalid), + .m_axi_awready(SDCin_axi_awready), + .m_axi_wdata(SDCin_axi_wdata), + .m_axi_wstrb(SDCin_axi_wstrb), + .m_axi_wvalid(SDCin_axi_wvalid), + .m_axi_wready(SDCin_axi_wready), + .m_axi_bresp(SDCin_axi_bresp), + .m_axi_bvalid(SDCin_axi_bvalid), + .m_axi_bready(SDCin_axi_bready), + .m_axi_araddr(SDCin_axi_araddr), + .m_axi_arprot(SDCin_axi_arprot), + .m_axi_arvalid(SDCin_axi_arvalid), + .m_axi_arready(SDCin_axi_arready), + .m_axi_rdata(SDCin_axi_rdata), + .m_axi_rresp(SDCin_axi_rresp), + .m_axi_rvalid(SDCin_axi_rvalid), + .m_axi_rready(SDCin_axi_rready) + + ); + sdc_controller axiSDC (.clock(CPUCLK), @@ -724,13 +818,15 @@ module fpgaTop .m_axi_rlast(SDCout_axi_rlast), .m_axi_rresp(SDCout_axi_rresp), .m_axi_rvalid(SDCout_axi_rvalid), - .m_axi_rready(SDCout_axi_rready) + .m_axi_rready(SDCout_axi_rready), // SDC interface - //.sdio_cmd(SDCcmd), - //.sdio_dat(SDCdat), - //.sdio_cd() + //.sdio_cmd(1'b0), + //.sdio_dat(4'b0), + //.sdio_cd(1'b0) + .sd_dat_i(4'b0), + .sd_cmd_i(1'b0) ); @@ -771,7 +867,7 @@ module fpgaTop .s_axi_arvalid(SDCout_axi_arvalid), .s_axi_arready(SDCout_axi_arready), .s_axi_rdata(SDCout_axi_rdata), - //.s_axi_rresp(), + .s_axi_rresp(SDCout_axi_rresp), .s_axi_rlast(SDCout_axi_rlast), .s_axi_rvalid(SDCout_axi_rvalid), .s_axi_rready(SDCout_axi_rready), diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v index 989c05881..d900ddbbd 100644 --- a/pipelined/src/uncore/newsdc/axi_sdc_controller.v +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -37,101 +37,109 @@ module sdc_controller #( parameter voltage_controll_reg = 3300, parameter capabilies_reg = 16'b0000_0000_0000_0011 ) ( - input wire async_resetn, + input wire async_resetn, (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *) (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF M_AXI:S_AXI_LITE, FREQ_HZ 100000000" *) - input wire clock, + input wire clock, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32" *) - input wire [15:0] s_axi_awaddr, + input wire [15:0] s_axi_awaddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) - input wire s_axi_awvalid, + input wire s_axi_awvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) - output wire s_axi_awready, + output wire s_axi_awready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) - input wire [31:0] s_axi_wdata, + input wire [31:0] s_axi_wdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) - input wire s_axi_wvalid, + input wire s_axi_wvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) - output wire s_axi_wready, + output wire s_axi_wready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) - output reg [1:0] s_axi_bresp, + output reg [1:0] s_axi_bresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) - output reg s_axi_bvalid, + output reg s_axi_bvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) - input wire s_axi_bready, + input wire s_axi_bready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) - input wire [15:0] s_axi_araddr, + input wire [15:0] s_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) - input wire s_axi_arvalid, + input wire s_axi_arvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) - output wire s_axi_arready, + output wire s_axi_arready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) - output reg [31:0] s_axi_rdata, + output reg [31:0] s_axi_rdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) - output reg [1:0] s_axi_rresp, + output reg [1:0] s_axi_rresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) - output reg s_axi_rvalid, + output reg s_axi_rvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) - input wire s_axi_rready, + input wire s_axi_rready, (* X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) - output reg [dma_addr_bits-1:0] m_axi_awaddr, + output reg [dma_addr_bits-1:0] m_axi_awaddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) - output reg [7:0] m_axi_awlen, + output reg [7:0] m_axi_awlen, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) - output reg m_axi_awvalid, + output reg m_axi_awvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) - input wire m_axi_awready, + input wire m_axi_awready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) - output wire [31:0] m_axi_wdata, + output wire [31:0] m_axi_wdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) - output reg m_axi_wlast, + output reg m_axi_wlast, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) - output reg m_axi_wvalid, + output reg m_axi_wvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) - input wire m_axi_wready, + input wire m_axi_wready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) - input wire [1:0] m_axi_bresp, + input wire [1:0] m_axi_bresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) - input wire m_axi_bvalid, + input wire m_axi_bvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) - output wire m_axi_bready, + output wire m_axi_bready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) - output reg [dma_addr_bits-1:0] m_axi_araddr, + output reg [dma_addr_bits-1:0] m_axi_araddr, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) - output reg [7:0] m_axi_arlen, + output reg [7:0] m_axi_arlen, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) - output reg m_axi_arvalid, + output reg m_axi_arvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) - input wire m_axi_arready, + input wire m_axi_arready, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) - input wire [31:0] m_axi_rdata, + input wire [31:0] m_axi_rdata, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) - input wire m_axi_rlast, + input wire m_axi_rlast, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) - input wire [1:0] m_axi_rresp, + input wire [1:0] m_axi_rresp, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) - input wire m_axi_rvalid, + input wire m_axi_rvalid, (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) - output wire m_axi_rready, + output wire m_axi_rready, // SD BUS - inout wire sdio_cmd, - inout wire [3:0] sdio_dat, + //inout wire sdio_cmd, + //inout wire [3:0] sdio_dat, (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sdio_clk CLK" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) - output reg sdio_clk, + output reg sdio_clk, (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sdio_reset RST" *) (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *) - output reg sdio_reset, - input wire sdio_cd, + output reg sdio_reset, + input wire sdio_cd, + + output reg sd_dat_reg_t, + output reg [3:0] sd_dat_reg_o, + input wire [3:0] sd_dat_i, + + output reg sd_cmd_reg_t, + output reg sd_cmd_reg_o, + input wire sd_cmd_i, // Interrupts - output wire interrupt + output wire interrupt ); `include "sd_defines.h" @@ -240,22 +248,22 @@ end // ------ SD IO Buffers -wire sd_cmd_i; +// wire sd_cmd_i; wire sd_cmd_o; wire sd_cmd_oe; -reg sd_cmd_reg_o; -reg sd_cmd_reg_t; -wire [3:0] sd_dat_i; +// reg sd_cmd_reg_o; +// reg sd_cmd_reg_t; +// wire [3:0] sd_dat_i; wire [3:0] sd_dat_o; wire sd_dat_oe; -reg [3:0] sd_dat_reg_o; -reg sd_dat_reg_t; +// reg [3:0] sd_dat_reg_o; +// reg sd_dat_reg_t; -IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); -IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); -IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); -IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); -IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); +// IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); +// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); always @(negedge clock) begin // Output data delayed by 1/2 clock cycle (5ns) to ensure diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index b79802ef3..8546861f9 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -369,6 +369,46 @@ static int ini_sd(void) { return 0; } +DRESULT disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { + + if (!count) return RES_PARERR; + if (drv_status & STA_NOINIT) return RES_NOTRDY; + + /* Convert LBA to byte address if needed */ + if (!(card_type & CT_BLOCK)) sector *= 512; + while (count > 0) { + UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; + unsigned bytes = bcnt * 512; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; + if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; + sector += (card_type & CT_BLOCK) ? bcnt : bytes; + count -= bcnt; + buf += bytes; + } + + return RES_OK; +} + +void disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { + + if (!count) return RES_PARERR; + if (drv_status & STA_NOINIT) return RES_NOTRDY; + + /* Convert LBA to byte address if needed */ + if (!(card_type & CT_BLOCK)) sector *= 512; + while (count > 0) { + UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; + unsigned bytes = bcnt * 512; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; + if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; + sector += (card_type & CT_BLOCK) ? bcnt : bytes; + count -= bcnt; + buf += bytes; + } + + return RES_OK; +} + int main() { ini_sd(); From c36d32f850477ce1ab884c8cd8c4e27147c7e126 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 27 Jan 2023 14:57:36 -0600 Subject: [PATCH 126/294] Flipped crossbar inputs and outputs to correctly place masters. --- fpga/src/fpgaTop.v | 148 ++++++++++++++++++++++----------------------- 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index bd7d95638..bf910257d 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -543,84 +543,84 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({m_axi_awid, 8'b0}), - .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), - .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), - .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), - .s_axi_awburst({m_axi_awburst, m01_axi_awburst}), - .s_axi_awlock({m_axi_awlock, m01_axi_awlock}), - .s_axi_awcache({m_axi_awcache, m01_axi_awcache}), - .s_axi_awprot({m_axi_awprot, m01_axi_awprot}), + .s_axi_awid({8'b0, m_axi_awid}), + .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), + .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), + .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), + .s_axi_awburst({m01_axi_awburst, m_axi_awburst}), + .s_axi_awlock({m01_axi_awlock, m_axi_awlock}), + .s_axi_awcache({m01_axi_awcache, m_axi_awcache}), + .s_axi_awprot({m01_axi_awprot, m_axi_awprot}), .s_axi_awqos(8'b0), - .s_axi_awvalid({m_axi_awvalid, m01_axi_awvalid}), - .s_axi_awready({m_axi_awready, m01_axi_awready}), - .s_axi_wdata({m_axi_wdata, m01_axi_wdata}), - .s_axi_wstrb({m_axi_wstrb, m01_axi_wstrb}), - .s_axi_wlast({m_axi_wlast, m01_axi_wlast}), - .s_axi_wvalid({m_axi_wvalid, m01_axi_wvalid}), - .s_axi_wready({m_axi_wready, m01_axi_wready}), - .s_axi_bid({m_axi_bid, m01_axi_bid}), - .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), - .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), - .s_axi_bready({m_axi_bready, m01_axi_bready}), - .s_axi_arid({m_axi_arid, 8'b0}), - .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), - .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), - .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), - .s_axi_arburst({m_axi_arburst, m01_axi_arburst}), - .s_axi_arlock({m_axi_arlock, m01_axi_arlock}), - .s_axi_arcache({m_axi_arcache, m01_axi_arcache}), - .s_axi_arprot({m_axi_arprot, m01_axi_arprot}), + .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}), + .s_axi_awready({m01_axi_awready, m_axi_awready}), + .s_axi_wdata({m01_axi_wdata, m_axi_wdata}), + .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}), + .s_axi_wlast({m01_axi_wlast, m_axi_wlast}), + .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}), + .s_axi_wready({m01_axi_wready, m_axi_wready}), + .s_axi_bid({m01_axi_bid, m_axi_bid}), + .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), + .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), + .s_axi_bready({m01_axi_bready, m_axi_bready}), + .s_axi_arid({8'b0, m_axi_arid}), + .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), + .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), + .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), + .s_axi_arburst({m01_axi_arburst, m_axi_arburst}), + .s_axi_arlock({m01_axi_arlock, m_axi_arlock}), + .s_axi_arcache({m01_axi_arcache, m_axi_arcache}), + .s_axi_arprot({m01_axi_arprot, m_axi_arprot}), .s_axi_arqos(8'b0), - .s_axi_arvalid({m_axi_arvalid, m01_axi_arvalid}), - .s_axi_arready({m_axi_arready, m01_axi_arready}), - .s_axi_rid({m_axi_rid, m01_axi_rid}), - .s_axi_rdata({m_axi_rdata, m01_axi_rdata}), - .s_axi_rresp({m_axi_rresp, m01_axi_rresp}), - .s_axi_rlast({m_axi_rlast, m01_axi_rlast}), - .s_axi_rvalid({m_axi_rvalid, m01_axi_rvalid}), - .s_axi_rready({m_axi_rready, m01_axi_rready}), + .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}), + .s_axi_arready({m01_axi_arready, m_axi_arready}), + .s_axi_rid({m01_axi_rid, m_axi_rid}), + .s_axi_rdata({m01_axi_rdata, m_axi_rdata}), + .s_axi_rresp({m01_axi_rresp, m_axi_rresp}), + .s_axi_rlast({m01_axi_rlast, m_axi_rlast}), + .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}), + .s_axi_rready({m01_axi_rready, m_axi_rready}), // Connect Slaves - .m_axi_awid({s00_axi_awid, s01_axi_awid}), - .m_axi_awlen({s00_axi_awlen, s01_axi_awlen}), - .m_axi_awsize({s00_axi_awsize, s01_axi_awsize}), - .m_axi_awburst({s00_axi_awburst, s01_axi_awburst}), - .m_axi_awcache({s00_axi_awcache, s01_axi_awcache}), - .m_axi_awaddr({s00_axi_awaddr, s01_axi_awaddr}), - .m_axi_awprot({s00_axi_awprot, s01_axi_awprot}), - .m_axi_awregion({s00_axi_awregion, s01_axi_awregion}), - .m_axi_awqos({s00_axi_awqos, s01_axi_awqos}), - .m_axi_awvalid({s00_axi_awvalid, s01_axi_awvalid}), - .m_axi_awready({s00_axi_awready, s01_axi_awready}), - .m_axi_awlock({s00_axi_awlock, s01_axi_awlock}), - .m_axi_wdata({s00_axi_wdata, s01_axi_wdata}), - .m_axi_wstrb({s00_axi_wstrb, s01_axi_wstrb}), - .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), - .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), - .m_axi_wready({s00_axi_wready, s01_axi_wready}), - .m_axi_bid({s00_axi_bid, 8'b0}), - .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), - .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), - .m_axi_bready({s00_axi_bready, s01_axi_bready}), - .m_axi_arid({s00_axi_arid, s01_axi_arid}), - .m_axi_arlen({s00_axi_arlen, s01_axi_arlen}), - .m_axi_arsize({s00_axi_arsize, s01_axi_arsize}), - .m_axi_arburst({s00_axi_arburst, s01_axi_arburst}), - .m_axi_arprot({s00_axi_arprot, s01_axi_arprot}), - .m_axi_arregion({s00_axi_arregion, s01_axi_arregion}), - .m_axi_arqos({s00_axi_arqos, s01_axi_arqos}), - .m_axi_arcache({s00_axi_arcache, s01_axi_arcache}), - .m_axi_arvalid({s00_axi_arvalid, s01_axi_arvalid}), - .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), - .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), - .m_axi_arready({s00_axi_arready, s01_axi_arready}), - .m_axi_rid({s00_axi_rid, 8'b0}), - .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), - .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), - .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), - .m_axi_rlast({s00_axi_rlast, s01_axi_rlast}), - .m_axi_rready({s00_axi_rready, s01_axi_rready}) + .m_axi_awid({s01_axi_awid, s00_axi_awid}), + .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}), + .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}), + .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}), + .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}), + .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}), + .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}), + .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}), + .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}), + .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}), + .m_axi_awready({s01_axi_awready, s00_axi_awready}), + .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}), + .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}), + .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}), + .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), + .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), + .m_axi_wready({s01_axi_wready, s00_axi_wready}), + .m_axi_bid({8'b0, s00_axi_bid}), + .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), + .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), + .m_axi_bready({s01_axi_bready, s00_axi_bready}), + .m_axi_arid({s01_axi_arid, s00_axi_arid}), + .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}), + .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}), + .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}), + .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}), + .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}), + .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}), + .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}), + .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}), + .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), + .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), + .m_axi_arready({s01_axi_arready, s00_axi_arready}), + .m_axi_rid({8'b0, s00_axi_rid}), + .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), + .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), + .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), + .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}), + .m_axi_rready({s01_axi_rready, s00_axi_rready}) ); // ----------------------------------------------------- From 121fbd9646bd0797b3f0fdf12cac929390d0f4a7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 15:28:31 -0600 Subject: [PATCH 127/294] Removed pessimistic x propagation issue for wally32priv test in the branch predictor. --- pipelined/src/ifu/brpred/speculativegshare.sv | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 00a49ce24..f1810f627 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -106,9 +106,21 @@ module speculativegshare satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline + // this version fails the regression test do to pessimistic x propagation. +/* -----\/----- EXCLUDED -----\/----- assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF; + -----/\----- EXCLUDED -----/\----- */ + + always_comb begin + if(FlushD) begin + if(BranchInstrE) GHRNextF = GHRNextD[k:1]; + else GHRNextF = GHRNextD[k-1:0]; + end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; + else GHRNextF = GHRF; + end + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); From 717cb4e6c50830f961e2d00ee34a1ac6d67c9843 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 14:27:04 -0800 Subject: [PATCH 128/294] Removed int/integer from parameters) --- pipelined/src/ebu/ahbcacheinterface.sv | 8 ++--- pipelined/src/ebu/buscachefsm.sv | 4 +-- pipelined/src/ifu/bpred/RAsPredictor.sv | 24 +++++++------- pipelined/src/ifu/bpred/btb.sv | 32 +++++++++---------- pipelined/src/ifu/bpred/foldedgshare.sv | 27 +++++++--------- pipelined/src/ifu/bpred/globalhistory.sv | 26 +++++++-------- pipelined/src/ifu/bpred/gshare.sv | 24 +++++++------- .../src/ifu/bpred/localHistoryPredictor.sv | 29 ++++++++--------- pipelined/src/ifu/bpred/optgshare.sv | 26 +++++++-------- .../src/ifu/bpred/speculativeglobalhistory.sv | 26 +++++++-------- pipelined/src/ifu/bpred/speculativegshare.sv | 28 ++++++++-------- pipelined/src/ifu/bpred/twoBitPredictor.sv | 24 +++++++------- 12 files changed, 128 insertions(+), 150 deletions(-) diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index a127e0fab..8bd1bc083 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -30,10 +30,10 @@ `include "wally-config.vh" module ahbcacheinterface #( - parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline - parameter integer AHBWLOGBWPL, // Log2 of ^ - parameter integer LINELEN, // Number of bits in cacheline - parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline + parameter AHBWLOGBWPL, // Log2 of ^ + parameter LINELEN, // Number of bits in cacheline + parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) )( input logic HCLK, HRESETn, // bus interface controls diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index c3be92fd8..8467f3029 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -32,8 +32,8 @@ // HCLK and clk must be the same clock! module buscachefsm #( - parameter integer BeatCountThreshold, // Largest beat index - parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE + parameter BeatCountThreshold, // Largest beat index + parameter AHBWLOGBWPL // Log2 of BEATSPERLINE )( input logic HCLK, input logic HRESETn, diff --git a/pipelined/src/ifu/bpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RAsPredictor.sv index c71ff2966..ae5b31999 100644 --- a/pipelined/src/ifu/bpred/RAsPredictor.sv +++ b/pipelined/src/ifu/bpred/RAsPredictor.sv @@ -28,19 +28,17 @@ `include "wally-config.vh" -module RASPredictor - #(parameter int StackSize = 16 - ) - (input logic clk, - input logic reset, - input logic PopF, - output logic [`XLEN-1:0] RASPCF, - input logic [3:0] WrongPredInstrClassD, - input logic [3:0] InstrClassD, - input logic PushE, - input logic incr, - input logic [`XLEN-1:0] PCLinkE - ); +module RASPredictor #(parameter StackSize = 16) ( + input logic clk, + input logic reset, + input logic PopF, + output logic [`XLEN-1:0] RASPCF, + input logic [3:0] WrongPredInstrClassD, + input logic [3:0] InstrClassD, + input logic PushE, + input logic incr, + input logic [`XLEN-1:0] PCLinkE +); // *** need to update so it either doesn't push until the memory stage // or need to repair flushed push. diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index 5f725b83a..c228964da 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -30,23 +30,21 @@ `include "wally-config.vh" -module btb - #(parameter int Depth = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] PCNextF, - output logic [`XLEN-1:0] BTBPredPCF, - output logic [3:0] InstrClass, - output logic Valid, - // update - input logic UpdateEN, - input logic [`XLEN-1:0] PCE, - input logic [`XLEN-1:0] IEUAdrE, - input logic [3:0] InstrClassE, - input logic UpdateInvalid - ); +module btb #(parameter Depth = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallE, + input logic [`XLEN-1:0] PCNextF, + output logic [`XLEN-1:0] BTBPredPCF, + output logic [3:0] InstrClass, + output logic Valid, + // update + input logic UpdateEN, + input logic [`XLEN-1:0] PCE, + input logic [`XLEN-1:0] IEUAdrE, + input logic [3:0] InstrClassE, + input logic UpdateInvalid +); localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; diff --git a/pipelined/src/ifu/bpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv index 2dfa48244..9de5d5c95 100644 --- a/pipelined/src/ifu/bpred/foldedgshare.sv +++ b/pipelined/src/ifu/bpred/foldedgshare.sv @@ -28,22 +28,19 @@ `include "wally-config.vh" -module foldedgshare - #(parameter int k = 16, - parameter int depth = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module foldedgshare #(parameter k = 16, depth = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/globalhistory.sv b/pipelined/src/ifu/bpred/globalhistory.sv index 7aa86dbb9..a8493a8d4 100644 --- a/pipelined/src/ifu/bpred/globalhistory.sv +++ b/pipelined/src/ifu/bpred/globalhistory.sv @@ -28,20 +28,18 @@ `include "wally-config.vh" -module globalhistory - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, -// input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCM, - input logic BranchInstrE, BranchInstrM, PCSrcE - ); +module globalhistory #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + // input logic [`XLEN-1:0] LookUpPC, + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCM, + input logic BranchInstrE, BranchInstrM, PCSrcE +); logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; diff --git a/pipelined/src/ifu/bpred/gshare.sv b/pipelined/src/ifu/bpred/gshare.sv index ce189d268..2fb0c6eaf 100644 --- a/pipelined/src/ifu/bpred/gshare.sv +++ b/pipelined/src/ifu/bpred/gshare.sv @@ -28,20 +28,18 @@ `include "wally-config.vh" -module gshare - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, +module gshare #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCM, - input logic BranchInstrE, BranchInstrM, PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCM, + input logic BranchInstrE, BranchInstrM, PCSrcE +); logic [k-1:0] IndexNextF, IndexM; logic [1:0] DirPredictionD, DirPredictionE; diff --git a/pipelined/src/ifu/bpred/localHistoryPredictor.sv b/pipelined/src/ifu/bpred/localHistoryPredictor.sv index 1709772dd..cde1fa7d3 100644 --- a/pipelined/src/ifu/bpred/localHistoryPredictor.sv +++ b/pipelined/src/ifu/bpred/localHistoryPredictor.sv @@ -28,23 +28,20 @@ `include "wally-config.vh" -module localHistoryPredictor - #( parameter int m = 6, // 2^m = number of local history branches - parameter int k = 10 // number of past branches stored - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] Prediction, - // update - input logic [`XLEN-1:0] UpdatePC, - input logic UpdateEN, PCSrcE, - input logic [1:0] UpdatePrediction - - ); +module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches + k = 10) ( // number of past branches stored + input logic clk, + input logic reset, + input logic StallF, StallE, + input logic [`XLEN-1:0] LookUpPC, + output logic [1:0] Prediction, + // update + input logic [`XLEN-1:0] UpdatePC, + input logic UpdateEN, PCSrcE, + input logic [1:0] UpdatePrediction +); - logic [2**m-1:0] [k-1:0] LHRNextF; + logic [2**m-1:0][k-1:0] LHRNextF; logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext; logic [m-1:0] LookUpPCIndex, UpdatePCIndex; logic [1:0] PredictionMemory; diff --git a/pipelined/src/ifu/bpred/optgshare.sv b/pipelined/src/ifu/bpred/optgshare.sv index 1f99cfd26..78c98c5e6 100644 --- a/pipelined/src/ifu/bpred/optgshare.sv +++ b/pipelined/src/ifu/bpred/optgshare.sv @@ -28,21 +28,19 @@ `include "wally-config.vh" -module optgshare - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module optgshare #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv index 094adca99..232351c86 100644 --- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv @@ -28,21 +28,19 @@ `include "wally-config.vh" -module speculativeglobalhistory - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module speculativeglobalhistory #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 05753c76d..98b590bed 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -28,22 +28,20 @@ `include "wally-config.vh" -module speculativegshare - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module speculativegshare #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic [3:0] WrongPredInstrClassD, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic [3:0] WrongPredInstrClassD, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/twoBitPredictor.sv b/pipelined/src/ifu/bpred/twoBitPredictor.sv index 5a04a5fcf..4a7be674d 100644 --- a/pipelined/src/ifu/bpred/twoBitPredictor.sv +++ b/pipelined/src/ifu/bpred/twoBitPredictor.sv @@ -28,19 +28,17 @@ `include "wally-config.vh" -module twoBitPredictor - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, - input logic [`XLEN-1:0] PCNextF, PCM, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - input logic BranchInstrE, BranchInstrM, - input logic PCSrcE - ); +module twoBitPredictor #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + input logic [`XLEN-1:0] PCNextF, PCM, + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + input logic BranchInstrE, BranchInstrM, + input logic PCSrcE +); logic [k-1:0] IndexNextF, IndexM; logic [1:0] PredictionMemory; From a99fc74976ad605ee57875645debfbe2c8cc55f7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 14:40:06 -0800 Subject: [PATCH 129/294] Removed integer from localparams --- pipelined/src/cache/cacheLRU.sv | 6 ++--- pipelined/src/cache/cacheway.sv | 16 ++++++------- pipelined/src/ebu/ahbcacheinterface.sv | 12 +++++----- pipelined/src/ifu/bpred/foldedgshare.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 8 +++---- pipelined/src/ifu/spill.sv | 8 +++---- pipelined/src/lsu/lsu.sv | 16 ++++++------- pipelined/testbench/sdc/sd_top_tb.sv | 2 +- pipelined/testbench/testbench.sv | 30 ++++++++++++------------- 9 files changed, 49 insertions(+), 53 deletions(-) diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index be42036e0..2e3057f0c 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -81,8 +81,8 @@ module cacheLRU // expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ... for(row = 0; row < LOGNUMWAYS; row++) begin localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1); - localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1; - localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2; + localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1; + localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2; assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}}; end @@ -109,8 +109,6 @@ module cacheLRU for(s = NUMWAYS/2-1; s >= 0; s--) begin localparam int0 = (NUMWAYS/2-1-s)*2; localparam int1 = int0 + 1; - //localparam int0 = s*2; - //localparam int1 = int0 + 1; assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; end diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index d3e996729..671bbcaff 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -55,11 +55,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, output logic DirtyWay, // This way is dirty output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid - localparam integer WORDSPERLINE = LINELEN/`XLEN; - localparam integer BYTESPERLINE = LINELEN/8; + localparam WORDSPERLINE = LINELEN/`XLEN; + localparam BYTESPERLINE = LINELEN/8; localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGXLENBYTES = $clog2(`XLEN/8); - localparam integer BYTESPERWORD = `XLEN/8; + localparam BYTESPERWORD = `XLEN/8; logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] DirtyBits; @@ -128,12 +128,12 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, // Data Array ///////////////////////////////////////////////////////////////////////////////////////////// - genvar words; + genvar words; - localparam integer SRAMLEN = 128; - localparam integer NUMSRAM = LINELEN/SRAMLEN; - localparam integer SRAMLENINBYTES = SRAMLEN/8; - localparam integer LOGNUMSRAM = $clog2(NUMSRAM); + localparam SRAMLEN = 128; + localparam NUMSRAM = LINELEN/SRAMLEN; + localparam SRAMLENINBYTES = SRAMLEN/8; + localparam LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr), diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 8bd1bc083..7278f4f93 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -72,12 +72,12 @@ module ahbcacheinterface #( output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt - localparam integer BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index - logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation - logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage - logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data + localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index + logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage + logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data genvar index; diff --git a/pipelined/src/ifu/bpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv index 9de5d5c95..85b7db383 100644 --- a/pipelined/src/ifu/bpred/foldedgshare.sv +++ b/pipelined/src/ifu/bpred/foldedgshare.sv @@ -54,13 +54,13 @@ module foldedgshare #(parameter k = 16, depth = 10) ( logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE, IndexM, IndexW; - logic [depth-1:0] FinalIndexNextF, FinalIndexW; + logic [depth-1:0] FinalIndexNextF, FinalIndexW; logic PCSrcM, PCSrcW; logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - localparam int delta = 2 * depth - k; + localparam delta = 2 * depth - k; assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 476f666ff..0ff6dc3f9 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -210,11 +210,11 @@ module ifu ( end if (`BUS) begin : bus // **** must fix words per line vs beats per line as in lsu. - localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; - localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; + localparam WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; + localparam LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; if(`ICACHE) begin : icache - localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; - localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + localparam LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; + localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv index 9df9fca18..aa93c4397 100644 --- a/pipelined/src/ifu/spill.sv +++ b/pipelined/src/ifu/spill.sv @@ -50,15 +50,15 @@ module spill #( output logic CompressedF); // The fetched instruction is compressed // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1] - localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; + typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; + statetype CurrState, NextState; + localparam SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; logic [`XLEN-1:0] PCPlus2F; logic TakeSpillF; logic SpillF; logic SelSpillF; - logic SpillSaveF; + logic SpillSaveF; logic [15:0] InstrFirstHalf; - typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; - statetype CurrState, NextState; //////////////////////////////////////////////////////////////////////////////////////////////////// // PC logic diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index f89fe0da4..19f5ba960 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -238,12 +238,12 @@ module lsu ( end if (`BUS) begin : bus if(`DCACHE) begin : dcache - localparam integer LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline - localparam integer LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ - localparam integer BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline - localparam integer AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^ - localparam integer LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline - localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline + localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ + localparam BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline + localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^ + localparam LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline + localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline logic [`PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback. @@ -251,10 +251,10 @@ module lsu ( logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface - logic [1:0] BusRW; // Uncached bus memory access + logic [1:0] BusRW; // Uncached bus memory access logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11) - logic [1:0] CacheAtomicM; // Cache AMO + logic [1:0] CacheAtomicM; // Cache AMO assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/pipelined/testbench/sdc/sd_top_tb.sv index 3282c0e2a..65d9ed454 100644 --- a/pipelined/testbench/sdc/sd_top_tb.sv +++ b/pipelined/testbench/sdc/sd_top_tb.sv @@ -32,7 +32,7 @@ module sd_top_tb(); - localparam integer g_COUNT_WIDTH = 8; + localparam g_COUNT_WIDTH = 8; logic a_RST; logic i_SD_CMD; diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 5456ce8b9..fbd720109 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -205,8 +205,8 @@ logic [3:0] dummy; InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests - localparam integer MemStartAddr = 0; - localparam integer MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32); + localparam MemStartAddr = 0; + localparam MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32); initial begin @@ -570,25 +570,23 @@ module DCacheFlushFSM logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; if(`DCACHE) begin - localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; - localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; - localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; - -//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM; - localparam integer numwords = sramlen/`XLEN; - localparam integer lognumlines = $clog2(numlines); - localparam integer loglinebytelen = $clog2(linebytelen); - localparam integer lognumways = $clog2(numways); - localparam integer tagstart = lognumlines + loglinebytelen; + localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; + localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; + localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; + localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; + localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; + localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + localparam numwords = sramlen/`XLEN; + localparam lognumlines = $clog2(numlines); + localparam loglinebytelen = $clog2(linebytelen); + localparam lognumways = $clog2(numways); + localparam tagstart = lognumlines + loglinebytelen; genvar index, way, cacheWord; logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - logic [sramlen-1:0] cacheline; + logic [sramlen-1:0] cacheline; logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; From a953954909142baadfcaf0572fe6bba75aa5bfd3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 16:40:20 -0600 Subject: [PATCH 130/294] Clarified gshare bp. --- pipelined/src/ifu/brpred/speculativegshare.sv | 21 +++++++------------ 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index f1810f627..85cb3654c 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -55,7 +55,7 @@ module speculativegshare logic OldGHRExtraF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; - logic [k:-1] GHRNextD, OldGHRD; + logic [k:0] GHRNextD; logic [k:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; @@ -107,11 +107,9 @@ module speculativegshare // GHR pipeline // this version fails the regression test do to pessimistic x propagation. -/* -----\/----- EXCLUDED -----\/----- - assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : - BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - GHRF; - -----/\----- EXCLUDED -----/\----- */ + // assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : + // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : + // GHRF; always_comb begin if(FlushD) begin @@ -121,20 +119,15 @@ module speculativegshare else GHRNextF = GHRF; end - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF} : // shift left **** missing bit + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left OldGHRF[k-1:0]; - assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; + assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF}; - flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); - //assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right - // WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left - // OldGHRD[k:0]; - assign GHRD = OldGHRD[k:0]; + flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); assign GHRNextE = FlushE ? GHRNextM : GHRD; flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); From 848ccd8b909873261c4c3af2b8940ad0246b61e8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 15:17:17 -0800 Subject: [PATCH 131/294] Fixed license header for config files to SolderPad --- pipelined/config/buildroot/wally-config.vh | 21 +++++++++++---------- pipelined/config/fpga/wally-config.vh | 21 +++++++++++---------- pipelined/config/rv32e/wally-config.vh | 21 +++++++++++---------- pipelined/config/rv32gc/wally-config.vh | 21 +++++++++++---------- pipelined/config/rv32i/wally-config.vh | 21 +++++++++++---------- pipelined/config/rv32ic/wally-config.vh | 21 +++++++++++---------- pipelined/config/rv64fpquad/wally-config.vh | 21 +++++++++++---------- pipelined/config/rv64gc/wally-config.vh | 21 +++++++++++---------- pipelined/config/rv64i/wally-config.vh | 21 +++++++++++---------- pipelined/config/shared/wally-constants.vh | 21 +++++++++++---------- pipelined/config/shared/wally-shared.vh | 21 +++++++++++---------- 11 files changed, 121 insertions(+), 110 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 56292c842..5ab833be6 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 16f7ca45d..4989b571b 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index f029e0e68..66d4049f8 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 4d346e5a6..85c207e91 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 7fb355c57..b6330579f 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 311ce8ab2..085bbad3b 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 2df9867fa..aab3df73e 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 29148944f..606c95eb8 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index c7304c724..203ee4552 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -11,18 +11,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // include shared configuration `include "wally-shared.vh" diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh index 0acc12b86..0999fc207 100644 --- a/pipelined/config/shared/wally-constants.vh +++ b/pipelined/config/shared/wally-constants.vh @@ -15,18 +15,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // constants defining different privilege modes // defined in Table 1.1 of the privileged spec diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 2fcb3af7a..4e43c7217 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -9,18 +9,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// // division constants `define RADIX 32'h4 From 5547179a3c5662974252c0b0ee809fe496f48daf Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 15:23:32 -0800 Subject: [PATCH 132/294] Added missing PLIC_GPIO_ID to two config files --- pipelined/config/buildroot/wally-config.vh | 1 + pipelined/config/fpga/wally-config.vh | 1 + 2 files changed, 2 insertions(+) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 5ab833be6..814e37761 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -127,6 +127,7 @@ // Interrupt configuration `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 10 +`define PLIC_GPIO_ID 3 `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 4989b571b..6b977fcbc 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -137,6 +137,7 @@ // Interrupt configuration `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 10 +`define PLIC_GPIO_ID 3 `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt" `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt" From c2ce2947f9663dd2f8357825a192a66d0241f280 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 15:47:15 -0800 Subject: [PATCH 133/294] Removed unused BMU, added CVW configuration --- pipelined/src/bmu/bmu.sv | 45 ------- pipelined/src/ieu/datapath.sv | 8 +- pipelined/src/ieu/ieu.sv | 6 +- pipelined/src/wally/cvw.sv | 218 ++++++++++++++++++++++++++++++++++ 4 files changed, 221 insertions(+), 56 deletions(-) delete mode 100644 pipelined/src/bmu/bmu.sv create mode 100644 pipelined/src/wally/cvw.sv diff --git a/pipelined/src/bmu/bmu.sv b/pipelined/src/bmu/bmu.sv deleted file mode 100644 index ba6ab0b08..000000000 --- a/pipelined/src/bmu/bmu.sv +++ /dev/null @@ -1,45 +0,0 @@ -/////////////////////////////////////////// -// bmu.sv -// -// Written: kekim@g.hmc.edu, David_Harris@hmc.edu 20 January 2023 -// Modified: -// -// Purpose: Bit manipulation extensions Zba, Zbb, Zbc, Zbs -// Single-cycle operation in Execute stage -// -// Documentation: n/a -// See RISC-V Bit-Manipulation ISA-extensions -// Version 1.0.0-38-g865e7a7, 2021-06-28: Release candidate -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module bmu( - input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output - input logic [31:0] InstrD, // instruction - output logic BMUE, // bit manipulation instruction - output logic [`XLEN-1:0] BMUResultE // bit manipulation result -); - - - -endmodule // mdu - - diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 9ca880836..60d43de92 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -48,7 +48,6 @@ module datapath ( output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B - input logic BMUE, // Bit manipulation instruction // Memory stage signals input logic StallM, FlushM, // Stall, flush Memory stage input logic FWriteIntM, FCvtIntW, // FPU writes integer register file, FPU converts float to int @@ -64,7 +63,6 @@ module datapath ( input logic [`XLEN-1:0] ReadDataW, // Read data from LSU input logic [`XLEN-1:0] CSRReadValW, // CSR read result input logic [`XLEN-1:0] MDUResultW, // MDU (Multiply/divide unit) result - input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result input logic [`XLEN-1:0] FIntDivResultW, // FPU's integer divide result // Hazard Unit signals output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, // Register sources to read in Decode or Execute stage @@ -81,7 +79,6 @@ module datapath ( logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage - logic [`XLEN-1:0] IEUBResultE; // IEUResultE before optional bit manipulation mux // Memory stage signals logic [`XLEN-1:0] IEUResultM; // Result from execution stage logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register @@ -114,10 +111,7 @@ module datapath ( mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); - mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUBResultE); - if (`B_SUPPORTED) - mux2 #(`XLEN) bmuresultmux(IEUResultE, BMUResultE, BMUE, IEUResultE); - else assign IEUResultE = IEUBResultE; + mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); // Memory stage pipeline register flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index fd8a74c2b..681bd9826 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -43,7 +43,6 @@ module ieu ( output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction output logic [2:0] Funct3E, // Funct3 instruction field output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B - input logic BMUE, // This is a bit manipulation instruction output logic [4:0] RdE, // Destination register // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU @@ -60,7 +59,6 @@ module ieu ( input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) input logic [`XLEN-1:0] CSRReadValW, // CSR read value, input logic [`XLEN-1:0] MDUResultW, // multiply/divide unit result - input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result input logic [`XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result input logic FCvtIntW, // FPU converts float to int output logic [4:0] RdW, // Destination register @@ -105,10 +103,10 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, - .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); + .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); forward fw( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv new file mode 100644 index 000000000..e35b22fb2 --- /dev/null +++ b/pipelined/src/wally/cvw.sv @@ -0,0 +1,218 @@ +////////////////////////////////////////// +// cvw.sv +// +// Written: David_Harris@hmc.edu 27 January 2022 +// +// Purpose: package with shared CORE-V-Wally global parameters +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// Usiing global `define statements isn't ideal in a large SystemVerilog system because +// of the risk of `define name conflicts across different subsystems. +// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package +// that is referenced by all Wally modules but not by other subsystems. + +// Load configuration-specific information +`include "wally-config.vh" + +// Place configuration in a package +package cvw; + parameter XLEN = `XLEN; + parameter FPGA = `FPGA; + parameter QEMU = `QEMU; + parameter DESIGN_COMPILER = `DESIGN_COMPILER; + parameter IEEE754 = `IEEE754; + parameter MISA = `MISA; + parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED; + parameter ZIFENCEI_SUPPORTED = `ZIFENCEI_SUPPORTED; + parameter COUNTERS = `COUNTERS; + parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED; + parameter ZFH_SUPPORTED = `ZFH_SUPPORTED; + parameter BUS = `BUS; + parameter DCACHE = `DCACHE; + parameter ICACHE = `ICACHE; + parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED; + parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED; + parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED; + parameter ITLB_ENTRIES = `ITLB_ENTRIES; + parameter DTLB_ENTRIES = `DTLB_ENTRIES; + parameter DCACHE_NUMWAYS = `DCACHE_NUMWAYS; + parameter DCACHE_WAYSIZEINBYTES = `DCACHE_WAYSIZEINBYTES; + parameter DCACHE_LINELENINBITS = `DCACHE_LINELENINBITS; + parameter ICACHE_NUMWAYS = `ICACHE_NUMWAYS; + parameter ICACHE_WAYSIZEINBYTES = `ICACHE_WAYSIZEINBYTES; + parameter ICACHE_LINELENINBITS = `ICACHE_LINELENINBITS; + parameter IDIV_BITSPERCYCLE = `IDIV_BITSPERCYCLE; + parameter IDIV_ON_FPU = `IDIV_ON_FPU; + parameter PMP_ENTRIES = `PMP_ENTRIES; + parameter RESET_VECTOR = `RESET_VECTOR; + parameter WFI_TIMEOUT_BIT = `WFI_TIMEOUT_BIT; + parameter DTIM_SUPPORTED = `DTIM_SUPPORTED; + parameter DTIM_BASE = `DTIM_BASE; + parameter DTIM_RANGE = `DTIM_RANGE; + parameter IROM_SUPPORTED = `IROM_SUPPORTED; + parameter IROM_BASE = `IROM_BASE; + parameter IROM_RANGE = `IROM_RANGE; + parameter BOOTROM_SUPPORTED = `BOOTROM_SUPPORTED; + parameter BOOTROM_BASE = `BOOTROM_BASE; + parameter BOOTROM_RANGE = `BOOTROM_RANGE; + parameter UNCORE_RAM_SUPPORTED = `UNCORE_RAM_SUPPORTED; + parameter UNCORE_RAM_BASE = `UNCORE_RAM_BASE; + parameter UNCORE_RAM_RANGE = `UNCORE_RAM_RANGE; + parameter EXT_MEM_SUPPORTED = `EXT_MEM_SUPPORTED; + parameter EXT_MEM_BASE = `EXT_MEM_BASE; + parameter EXT_MEM_RANGE = `EXT_MEM_RANGE; + parameter CLINT_SUPPORTED = `CLINT_SUPPORTED; + parameter CLINT_BASE = `CLINT_BASE; + parameter CLINT_RANGE = `CLINT_RANGE; + parameter GPIO_SUPPORTED = `GPIO_SUPPORTED; + parameter GPIO_BASE = `GPIO_BASE; + parameter GPIO_RANGE = `GPIO_RANGE; + parameter UART_SUPPORTED = `UART_SUPPORTED; + parameter UART_BASE = `UART_BASE; + parameter UART_RANGE = `UART_RANGE; + parameter PLIC_SUPPORTED = `PLIC_SUPPORTED; + parameter PLIC_BASE = `PLIC_BASE; + parameter PLIC_RANGE = `PLIC_RANGE; + parameter SDC_SUPPORTED = `SDC_SUPPORTED; + parameter SDC_BASE = `SDC_BASE; + parameter SDC_RANGE = `SDC_RANGE; + parameter AHBW = `AHBW; + parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST; + parameter UART_PRESCALE = `UART_PRESCALE; + parameter PLIC_NUM_SRC = `PLIC_NUM_SRC; +// parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32; + parameter PLIC_GPIO_ID = `PLIC_GPIO_ID; + parameter PLIC_UART_ID = `PLIC_UART_ID; + parameter BPRED_ENABLED = `BPRED_ENABLED; + parameter BPTYPE = `BPTYPE; + parameter TESTSBP = `TESTSBP; + parameter BPRED_SIZE = `BPRED_SIZE; + parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED; +// parameter = `; + + + // Shared parameters + + // constants defining different privilege modes + // defined in Table 1.1 of the privileged spec + parameter M_MODE = (2'b11); + parameter S_MODE = (2'b01); + parameter U_MODE = (2'b00); + + // Virtual Memory Constants + parameter VPN_SEGMENT_BITS = (`XLEN == 32 ? 10 : 9); + parameter VPN_BITS = (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)); + parameter PPN_BITS = (`XLEN==32 ? 22 : 44); + parameter PA_BITS = (`XLEN==32 ? 34 : 56); + parameter SVMODE_BITS = (`XLEN==32 ? 1 : 4); + parameter ASID_BASE = (`XLEN==32 ? 22 : 44); + parameter ASID_BITS = (`XLEN==32 ? 9 : 16); + + // constants to check SATP_MODE against + // defined in Table 4.3 of the privileged spec + parameter NO_TRANSLATE = 0; + parameter SV32 = 1; + parameter SV39 = 8; + parameter SV48 = 9; + + // macros to define supported modes + parameter A_SUPPORTED = ((`MISA >> 0) % 2 == 1); + parameter B_SUPPORTED = ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)); // not based on MISA + parameter C_SUPPORTED = ((`MISA >> 2) % 2 == 1); + parameter D_SUPPORTED = ((`MISA >> 3) % 2 == 1); + parameter E_SUPPORTED = ((`MISA >> 4) % 2 == 1); + parameter F_SUPPORTED = ((`MISA >> 5) % 2 == 1); + parameter I_SUPPORTED = ((`MISA >> 8) % 2 == 1); + parameter M_SUPPORTED = ((`MISA >> 12) % 2 == 1); + parameter Q_SUPPORTED = ((`MISA >> 16) % 2 == 1); + parameter S_SUPPORTED = ((`MISA >> 18) % 2 == 1); + parameter U_SUPPORTED = ((`MISA >> 20) % 2 == 1); + // N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 + + // logarithm of XLEN, used for number of index bits to select + parameter LOG_XLEN = (`XLEN == 32 ? 5 : 6); + + // Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) + parameter PMPCFG_ENTRIES = (`PMP_ENTRIES/8); + + // Floating point constants for Quad, Double, Single, and Half precisions + parameter Q_LEN = 32'd128; + parameter Q_NE = 32'd15; + parameter Q_NF = 32'd112; + parameter Q_BIAS = 32'd16383; + parameter Q_FMT = 2'd3; + parameter D_LEN = 32'd64; + parameter D_NE = 32'd11; + parameter D_NF = 32'd52; + parameter D_BIAS = 32'd1023; + parameter D_FMT = 2'd1; + parameter S_LEN = 32'd32; + parameter S_NE = 32'd8; + parameter S_NF = 32'd23; + parameter S_BIAS = 32'd127; + parameter S_FMT = 2'd0; + parameter H_LEN = 32'd16; + parameter H_NE = 32'd5; + parameter H_NF = 32'd10; + parameter H_BIAS = 32'd15; + parameter H_FMT = 2'd2; + + // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits + parameter FLEN = (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN); + parameter NE = (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE); + parameter NF = (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF); + parameter FMT = (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0); + parameter BIAS = (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS); + + // Floating point constants needed for FPU paramerterization + parameter FPSIZES = ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)); + parameter FMTBITS = ((32)'(`FPSIZES>=3)+1); + parameter LEN1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN); + parameter NE1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE); + parameter NF1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF); + parameter FMT1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2); + parameter BIAS1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS); + parameter LEN2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN); + parameter NE2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE); + parameter NF2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF); + parameter FMT2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2); + parameter BIAS2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS); + + // largest length in IEU/FPU + parameter CVTLEN = ((`NF<`XLEN) ? (`XLEN) : (`NF)); + parameter LLEN = ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN)); + parameter LOGCVTLEN = $unsigned($clog2(`CVTLEN+1)); + parameter NORMSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6))); + parameter LOGNORMSHIFTSZ = ($clog2(`NORMSHIFTSZ)); + parameter CORRSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4))); + + // division constants + + parameter DIVN = (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2); // standard length of input + parameter LOGR = ($clog2(`RADIX)); // r = log(R) + parameter RK = (`LOGR*`DIVCOPIES); // r*k used for intdiv preproc + parameter LOGRK = ($clog2(`RK)); // log2(r*k) + parameter FPDUR = ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4)); + parameter DURLEN = ($clog2(`FPDUR+1)); + parameter DIVb = (`FPDUR*`LOGR*`DIVCOPIES-1); // canonical fdiv size (b) + parameter DIVBLEN = ($clog2(`DIVb+1)-1); + parameter DIVa = (`DIVb+1-`XLEN); // used for idiv on fpu + +endpackage; From aee984ca69815fbd9b6acecb16161bac5a8002fe Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 15:47:36 -0800 Subject: [PATCH 134/294] Use CVW configuration in top-level --- pipelined/src/wally/wallypipelinedcore.sv | 85 ++++++++++------------- pipelined/src/wally/wallypipelinedsoc.sv | 14 ++-- 2 files changed, 43 insertions(+), 56 deletions(-) diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 2b71851f5..fa244b4f4 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -26,7 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" +import cvw::*; // global CORE-V-Wally parameters + /* verilator lint_on UNUSED */ module wallypipelinedcore ( @@ -35,12 +36,12 @@ module wallypipelinedcore ( input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, // Bus Interface - input logic [`AHBW-1:0] HRDATA, + input logic [AHBW-1:0] HRDATA, input logic HREADY, HRESP, output logic HCLK, HRESETn, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, + output logic [PA_BITS-1:0] HADDR, + output logic [AHBW-1:0] HWDATA, + output logic [XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -58,15 +59,15 @@ module wallypipelinedcore ( logic IntDivE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; logic [1:0] AtomicM; - logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; - logic [`XLEN-1:0] SrcAM; + logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; + logic [XLEN-1:0] SrcAM; logic [2:0] Funct3E; logic [31:0] InstrD; logic [31:0] InstrM; - logic [`XLEN-1:0] PCF, PCE, PCLinkE; - logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; + logic [XLEN-1:0] PCF, PCE, PCLinkE; + logic [XLEN-1:0] PCM; + logic [XLEN-1:0] CSRReadValW, MDUResultW; + logic [XLEN-1:0] UnalignedPCNextF, PCNext2F; logic [1:0] MemRWM; logic InstrValidM; logic InstrMisalignedFaultM; @@ -86,9 +87,9 @@ module wallypipelinedcore ( logic [4:0] RdE, RdM, RdW; logic FPUStallD; logic FWriteIntE; - logic [`FLEN-1:0] FWriteDataM; - logic [`XLEN-1:0] FIntResM; - logic [`XLEN-1:0] FCvtIntResW; + logic [FLEN-1:0] FWriteDataM; + logic [XLEN-1:0] FIntResM; + logic [XLEN-1:0] FCvtIntResW; logic FCvtIntW; logic FDivBusyE; logic IllegalFPUInstrM; @@ -96,23 +97,23 @@ module wallypipelinedcore ( logic FCvtIntStallD; logic FpLoadStoreM; logic [4:0] SetFflagsM; - logic [`XLEN-1:0] FIntDivResultW; + logic [XLEN-1:0] FIntDivResultW; // memory management unit signals logic ITLBWriteF; logic ITLBMissF; - logic [`XLEN-1:0] SATP_REGW; + logic [XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP, STATUS_FS; logic [1:0] PrivilegeModeW; - logic [`XLEN-1:0] PTE; + logic [XLEN-1:0] PTE; logic [1:0] PageType; logic sfencevmaM, WFIStallM; logic SelHPTW; // PMA checker signals - var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; - var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; + var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0]; + var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0]; // IMem stalls logic IFUStallF; @@ -120,14 +121,14 @@ module wallypipelinedcore ( // cpu lsu interface logic [2:0] Funct3M; - logic [`XLEN-1:0] IEUAdrE; - logic [`XLEN-1:0] WriteDataM; - logic [`XLEN-1:0] IEUAdrM; - logic [`LLEN-1:0] ReadDataW; + logic [XLEN-1:0] IEUAdrE; + logic [XLEN-1:0] WriteDataM; + logic [XLEN-1:0] IEUAdrM; + logic [LLEN-1:0] ReadDataW; logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] IFUHADDR; + logic [PA_BITS-1:0] IFUHADDR; logic [2:0] IFUHBURST; logic [1:0] IFUHTRANS; logic [2:0] IFUHSIZE; @@ -135,9 +136,9 @@ module wallypipelinedcore ( logic IFUHREADY; // AHB LSU interface - logic [`PA_BITS-1:0] LSUHADDR; - logic [`XLEN-1:0] LSUHWDATA; - logic [`XLEN/8-1:0] LSUHWSTRB; + logic [PA_BITS-1:0] LSUHADDR; + logic [XLEN-1:0] LSUHWDATA; + logic [XLEN/8-1:0] LSUHWSTRB; logic LSUHWRITE; logic LSUHREADY; @@ -161,11 +162,7 @@ module wallypipelinedcore ( logic BigEndianM; logic FCvtIntE; logic CommittedF; - - // Bit manipulation unit - logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU - logic BMUE; // is this a BMU instruction - + // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -193,7 +190,7 @@ module wallypipelinedcore ( .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU @@ -203,7 +200,7 @@ module wallypipelinedcore ( .SrcAM, // to privilege and fpu .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage - .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), + .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]), .InstrValidM, .FCvtIntResW, .FCvtIntW, // hazards .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -242,7 +239,7 @@ module wallypipelinedcore ( .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); - if(`BUS) begin : ebu + if(BUS) begin : ebu ebu ebu(// IFU connections .clk, .reset, // IFU interface @@ -280,7 +277,7 @@ module wallypipelinedcore ( .FlushD, .FlushE, .FlushM, .FlushW); // privileged unit - if (`ZICSR_SUPPORTED) begin:priv + if (ZICSR_SUPPORTED) begin:priv privileged priv( .clk, .reset, .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, @@ -313,7 +310,7 @@ module wallypipelinedcore ( end // multiply/divide unit - if (`M_SUPPORTED) begin:mdu + if (M_SUPPORTED) begin:mdu mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E, @@ -324,12 +321,12 @@ module wallypipelinedcore ( end // floating point unit - if (`F_SUPPORTED) begin:fpu + if (F_SUPPORTED) begin:fpu fpu fpu( .clk, .reset, .FRM_REGW, // Rounding mode from CSR .InstrD, // instruction from IFU - .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory + .ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory .ForwardedSrcAE, // Integer input being processed (from IEU) .StallE, .StallM, .StallW, // stall signals from HZU .FlushE, .FlushM, .FlushW, // flush signals from HZU @@ -360,15 +357,5 @@ module wallypipelinedcore ( assign SetFflagsM = 0; assign FpLoadStoreM = 0; end - - // bit manipulation unit - if (`B_SUPPORTED) begin:bmu - bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE); - end else begin // no B instructions supported - assign BMUResultE = 0; - assign BMUE = 0; - end - - endmodule diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 59f213ad0..26979545c 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -26,21 +26,21 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" +import cvw::*; // global CORE-V-Wally parameters module wallypipelinedsoc ( input logic clk, input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [`AHBW-1:0] HRDATAEXT, + input logic [AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, + output logic [PA_BITS-1:0] HADDR, + output logic [AHBW-1:0] HWDATA, + output logic [XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -63,7 +63,7 @@ module wallypipelinedsoc ( ); // Uncore signals - logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore + logic [AHBW-1:0] HRDATA; // from AHB mux in uncore logic HRESP; // response from AHB logic MTimerInt, MSwInt; // timer and software interrupts from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs @@ -80,7 +80,7 @@ module wallypipelinedsoc ( ); // instantiate uncore if a bus interface exists - if (`BUS) begin : uncore + if (BUS) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, From eeaa5d9982afe4e8f5523e8b5858878313c78181 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 15:48:30 -0800 Subject: [PATCH 135/294] Removed unneeded lint directive from core --- pipelined/src/wally/wallypipelinedcore.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index fa244b4f4..5c2c6efce 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -28,8 +28,6 @@ import cvw::*; // global CORE-V-Wally parameters -/* verilator lint_on UNUSED */ - module wallypipelinedcore ( input logic clk, reset, // Privileged From c2f888d5da48b0cf140181419a37b73812c3bc38 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Sat, 28 Jan 2023 01:00:29 +0000 Subject: [PATCH 136/294] Fixed copying hdl subdirectories and referencing the correct config files for modified features --- synthDC/Makefile | 12 +++++++----- synthDC/scripts/synth.tcl | 9 ++++----- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 81d982251..eeb3de889 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -6,13 +6,14 @@ NAME := synth # defaults export DESIGN ?= wallypipelinedcore -export FREQ ?= 3000 -export CONFIG ?= rv32e +export FREQ ?= 1000 +export CONFIG ?= rv64gc export MOD ?= orig +export CONFIGMOD ?= $(CONFIG)_$(MOD) # title to add a note in the synth's directory name TITLE = # tsmc28, sky130, and sky90 presently supported -export TECH ?= sky90 +export TECH ?= tsmc28 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient # Avoid when doing sweeps of many optimization points in parallel export MAXCORES ?= 1 @@ -29,13 +30,14 @@ export SAIFPOWER ?= 0 configAsList := $(subst _, ,$(CONFIG)) BASECONFIG := $(word 1, $(configAsList)) OLDCONFIGDIR ?= ${WALLY}/pipelined/config -CONFIGDIR ?= $(OUTPUTDIR)/hdl/config +export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) # k = 3 6 print: @echo $(FREQS) + @echo $(BASECONFIG) @echo $(CONFIGFILESTRIM) @@ -108,7 +110,7 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -synth: mkdirecs configs rundc clean +synth: mkdirecs configs rundc #clean TODO rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index ed43a1ab3..8c5d57988 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -18,19 +18,18 @@ set_host_options -max_cores $::env(MAXCORES) # get outputDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) -set cfgName $::env(CONFIG) +set cfgName $::env(CONFIGMOD) # Config set hdl_src "../pipelined/src" -set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) +set cfg $::env(CONFIGDIR)/${cfgName}/wally-config.vh -eval file copy -force ${cfg} {$outputDir/hdl/} -#eval file copy -force ${cfg} $outputDir +eval file copy -force $cfg {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} # Only for FMA class project; comment out when done # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} From e92ccad94fc15cfb52f9e8a748c81d39c0bed141 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Sat, 28 Jan 2023 01:51:34 +0000 Subject: [PATCH 137/294] improved readability for synth scripts --- synthDC/Makefile | 39 ++++++++++++++++++--------------------- synthDC/scripts/synth.tcl | 6 ++---- 2 files changed, 20 insertions(+), 25 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index eeb3de889..06898fa33 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -1,19 +1,18 @@ # # Makefile for synthesis # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 -# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 7/8/2022 +# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 NAME := synth # defaults export DESIGN ?= wallypipelinedcore -export FREQ ?= 1000 -export CONFIG ?= rv64gc +export FREQ ?= 3000 +export CONFIG ?= rv32e export MOD ?= orig -export CONFIGMOD ?= $(CONFIG)_$(MOD) # title to add a note in the synth's directory name TITLE = # tsmc28, sky130, and sky90 presently supported -export TECH ?= tsmc28 +export TECH ?= sky90 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient # Avoid when doing sweeps of many optimization points in parallel export MAXCORES ?= 1 @@ -27,17 +26,14 @@ hash := $(shell git rev-parse --short HEAD) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 -configAsList := $(subst _, ,$(CONFIG)) -BASECONFIG := $(word 1, $(configAsList)) OLDCONFIGDIR ?= ${WALLY}/pipelined/config export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) -# k = 3 6 print: @echo $(FREQS) - @echo $(BASECONFIG) + @echo $(CONFIG) @echo $(CONFIGFILESTRIM) @@ -51,26 +47,27 @@ DIRS32 = rv32e rv32gc rv32ic rv32i DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) +# k = 3 6 # bpred: # @$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) # @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) -configs: $(BASECONFIG) -$(BASECONFIG): - @echo $(BASECONFIG) - cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig - sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh - sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh - sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +configs: $(CONFIG) +$(CONFIG): + @echo $(CONFIG) + cp -r $(OLDCONFIGDIR)/$(CONFIG) $(CONFIGDIR)/$(CONFIG)_orig + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh -ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),) - sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh -else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),) - sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +ifneq ($(filter $ $(CONFIG), $(DIRS32)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh +else ifneq ($(filter $ $(CONFIG), $(DIRS64)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh else - $(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64)) + $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) @echo "Config not in list, RAM_RANGE will be unmodified" endif diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 8c5d57988..4cd80e50c 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -16,15 +16,13 @@ suppress_message {VER-173} # Enable Multicore set_host_options -max_cores $::env(MAXCORES) -# get outputDir from environment (Makefile) +# get outputDir and configDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) -set cfgName $::env(CONFIGMOD) -# Config +set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh set hdl_src "../pipelined/src" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) -set cfg $::env(CONFIGDIR)/${cfgName}/wally-config.vh eval file copy -force $cfg {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/} From 331ae6fffbd9aadeaf3507e5acbfc0f9b82a429c Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Sat, 28 Jan 2023 01:59:08 +0000 Subject: [PATCH 138/294] cleans run directory post run and leaves copy of wally-config --- synthDC/Makefile | 2 +- synthDC/scripts/synth.tcl | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 06898fa33..52f3cc90c 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -107,7 +107,7 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -synth: mkdirecs configs rundc #clean TODO +synth: mkdirecs configs rundc clean rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 4cd80e50c..1d7281fcb 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -25,6 +25,7 @@ set maxopt $::env(MAXOPT) set drive $::env(DRIVE) eval file copy -force $cfg {$outputDir/hdl/} +eval file copy -force $cfg {$outputDir/} eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} From ff9171aba776fa9a8037ba3501f2feee4edf6c7b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 10:22:59 -0800 Subject: [PATCH 139/294] Added libppa.pl to characterize liberty files --- bin/libppa.pl | 246 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 246 insertions(+) create mode 100755 bin/libppa.pl diff --git a/bin/libppa.pl b/bin/libppa.pl new file mode 100755 index 000000000..56b3702dd --- /dev/null +++ b/bin/libppa.pl @@ -0,0 +1,246 @@ +#!/bin/perl -W + +########################################### +## libppa.pl +## +## Written: David_Harris@hmc.edu +## Created: 28 January 2023 +## +## Purpose: Extract PPA information from Liberty files +## presently characterizes Skywater 90 and TSMC28hpc+ +## +## The user will need to change $libpath to point to the desired library in your local installation +## and for TSMC change the $cellname to the actual name of the inverter. +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +use strict; +use warnings; + +# global variables for simplicity +my @index1; my @index2; +my @values; +my @cr; my @cf; my @rt; my @ft; + +# cell and corners to analyze +my $libpath; my $libbase; my $cellname; my @corners; + +# Sky90 +$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib"; +$libbase = "scc9gena_"; +$cellname = "scc9gena_inv_1"; +@corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C"); +printf("Library $libbase Cell $cellname\n"); +foreach my $corner (@corners) { + &analyzeCell($corner); +} + +# TSMC +$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a"; +$libbase = "tcbn28hpcplusbwp30p140"; +$cellname = "INVD1..."; // replace this with the full name of the library cell +@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c"); +printf("\nLibrary $libbase Cell $cellname\n"); +foreach my $corner (@corners) { + &analyzeCell($corner); +} + +############# +# subroutines +############# + +sub analyzeCell { + my $corner = shift; + my $fname = $libpath."/".$libbase.$corner.".lib"; + open (FILE, $fname) || die("Can't read $fname"); + my $incell = 0; + my $inleakage = 0; + my $inpin = 0; + my $incellrise = 0; + my $incellfall = 0; + my $inrisetrans = 0; + my $infalltrans = 0; + my $inindex = 0; + my $invalues = 0; + my $searchstring = "cell (".$cellname.")"; + my $area; my $leakage; my $cap; + while () { + if (index($_, $searchstring) != -1) { $incell = 1;} + elsif ($incell) { + if (/cell \(/) { + $incell = 0; + close(FILE); + last; + } + if (/area\s*:\s*(.*);/) { $area = $1; } + if (/cell_leakage_power\s*:\s*(.*);/) { $leakage = $1; $inleakage = 2; } + if ($inleakage == 0 && /leakage_power/) { $inleakage = 1; } + if ($inleakage == 1 && /value\s*:\s*(.*);/) { + $leakage = $1; + $inleakage = 2; + } + if ($inpin == 0 && /pin/) { $inpin = 1; } + if ($inpin == 1 && /\s+capacitance\s*:\s*(.*);/) { + $cap = $1; + $inpin = 2; + } + if ($inindex == 0 && /index_1/) { $inindex = 1; } + if ($inindex == 1) { + if (/index_1\s*\(\"(.*)\"\);/) { @index1 = split(/, /, $1); } + if (/index_2\s*\(\"(.*)\"\);/) { @index2 = split(/, /, $1); $inindex = 2; } + } + if ($incellrise == 0 && /cell_rise/) { $incellrise = 1; $invalues = 0;} + if ($incellfall == 0 && /cell_fall/) { $incellfall = 1; $invalues = 0; } + if ($inrisetrans == 0 && /rise_trans/) { $inrisetrans = 1; $invalues = 0; } + if ($infalltrans == 0 && /fall_trans/) { $infalltrans = 1; $invalues = 0; } + if ($incellrise == 1 || $incellfall == 1 || $inrisetrans == 1 || $infalltrans == 1) { + if (/values/) { $invalues = 1; @values = (); } + elsif ($invalues == 1) { + if (/\);/) { + $invalues = 2; + if ($incellrise == 1) { @cr = &parseVals(); $incellrise = 2; } + if ($incellfall == 1) { @cf = &parseVals(); $incellfall = 2; } + if ($inrisetrans == 1) { @rt = &parseVals(); $inrisetrans = 2; } + if ($infalltrans == 1) { @ft = &parseVals(); $infalltrans = 2; } + } + elsif (/\"(.*)\"/) { push(@values, $1); } + } + } +# print $_; + } + } + + my $delay = &computeDelay($cap); + my $cornerr = sprintf("%20s", $corner); + my $delayr = sprintf("%2.1f", $delay*1000); + my $leakager = sprintf("%3.1f", $leakage); + + print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n"); + #print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n"); + #print(" index1: @index1\n"); + #print(" index2: @index2\n"); + #print("Cell Rise\n"); printMatrix(\@cr); + #print("Cell Fall\n"); printMatrix(\@cf); + #print("Rise Trans\n"); printMatrix(\@rt); + #print("Fall Trans\n"); printMatrix(\@ft); +} + +sub computeDelay { + # relies on cr, cf, rt, ft, index1, index2 + # index1 for rows of matrix (different trans times, units of ns) + # index2 for cols of matrix (different load capacitances, units of pF) + + # first, given true load, create a rise/fall delay and transition + # as a function of trans time, interpolated + my $cap = shift; + my $fo4cap = 4*$cap; + my @cri = &interp2(\@cr, $fo4cap); + my @cfi = &interp2(\@cf, $fo4cap); + my @rti = &interp2(\@rt, $fo4cap); + my @fti = &interp2(\@ft, $fo4cap); + + # initially guess second smallest transition time + my $tt = $index1[1]; + # assume falling input with this transition, compute rise delay & trans + my $cr0 = &interp1(\@cri, \@index1, $tt); + my $rt0 = &interp1(\@rti, \@index1, $tt); + # now assuming rising input with rt0, compute fall delay & trans + my $cf1 = &interp1(\@cfi, \@index1, $rt0); + my $ft1 = &interp1(\@fti, \@index1, $rt0); + # now assuming falling input with ft1, compute rise delay & trans + my $cr2 = &interp1(\@cri, \@index1, $ft1); + my $rt2 = &interp1(\@rti, \@index1, $ft1); + # now assuming rising input with rt2, compute fall delay & trans + my $cf3 = &interp1(\@cfi, \@index1, $rt2); + my $ft3 = &interp1(\@fti, \@index1, $rt2); + + # delay is average of rising and falling + my $delay = ($cr2 + $cf3)/2; + return $delay; + +# print("tt $tt cr0 $cr0 rt0 $rt0\n"); +# print("cf1 $cf1 ft1 $ft1 cr2 $cr2 rt2 $rt2 cf3 $cf3 ft3 $ft3 delay $delay\n"); +} + +sub interp2 { + my $matref = shift; + my @matrix = @$matref; + my $fo4cap = shift; + my @interp = (); + + my $i; + # interpolate row by row + for ($i=0; $i <= $#index1; $i++) { + my @row = @{$matrix[$i]}; + #print ("Extracted row $i = @row\n"); + $interp[$i] = &interp1(\@row, \@index2, $fo4cap); + } + return @interp; +} + +sub interp1 { + my $vecref = shift; + my @vec = @$vecref; + my $indexref = shift; + my @index = @$indexref; + my $x = shift; + + # find entry i containing the first index greater than x + my $i = 0; + while ($index[$i] < $x) {$i++} + my $start = $index[$i-1]; + my $end = $index[$i]; + my $fract = ($x-$start)/($end-$start); + my $interp = $vec[$i-1] + ($vec[$i] - $vec[$i-1])*$fract; + +# print ("Interpolating $x as $interp from i $i start $start end $end based on index @index and vec @vec\n"); + + return $interp; +} + +sub parseVals { + # relies on global variables @values, @index1, @index2 + my @vals; + my $i; my $j; + for ($i=0; $i <= $#index1; $i++) { + my @row = split(/, /,$values[$i]); + for ($j = 0; $j <= $#index2; $j++) { + $vals[$i][$j] = $row[$j]; + } + } + return @vals; +} + +sub printMatrix { + my $mat = shift; + my @matrix = @$mat; + my $i; my $j; + for ($i=0; $i <= $#index1; $i++) { + for ($j = 0; $j <= $#index2; $j++) { + print($matrix[$i][$j]." "); + } + print("\n"); + } +} + + + + + + From 1041775be4c71210a5e607ff90413e0f392cc38e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 10:51:39 -0800 Subject: [PATCH 140/294] Removed DEISGN_COMPILER configuration paramter --- pipelined/config/buildroot/wally-config.vh | 1 - pipelined/config/fpga/wally-config.vh | 2 -- pipelined/config/rv32e/wally-config.vh | 1 - pipelined/config/rv32gc/wally-config.vh | 1 - pipelined/config/rv32i/wally-config.vh | 1 - pipelined/config/rv32ic/wally-config.vh | 1 - pipelined/config/rv64fpquad/wally-config.vh | 1 - pipelined/config/rv64gc/wally-config.vh | 1 - pipelined/config/rv64i/wally-config.vh | 1 - 9 files changed, 10 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 814e37761..a4ec7fb47 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -42,7 +42,6 @@ `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 `define COUNTERS 32 -`define DESIGN_COMPILER 0 // LSU microarchitectural Features `define BUS 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 6b977fcbc..56bf10402 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 1 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 @@ -44,7 +43,6 @@ `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 `define COUNTERS 32 -`define DESIGN_COMPILER 0 // LSU microarchitectural Features `define BUS 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 66d4049f8..b42633679 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 0 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 85c207e91..2704a9a00 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 0 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index b6330579f..119354aa8 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 0 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 085bbad3b..49281c289 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 0 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index aab3df73e..4d36ff303 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 0 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 606c95eb8..c00e02843 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 0 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 203ee4552..b0df9bc30 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 0 `define QEMU 0 -`define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 From 6c59c21a26eb52857a55eeb5b2670450cdf11d4d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 10:58:02 -0800 Subject: [PATCH 141/294] Updated cvw to be consistent with configs --- pipelined/src/wally/cvw.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index e35b22fb2..5fd28163e 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -36,7 +36,6 @@ package cvw; parameter XLEN = `XLEN; parameter FPGA = `FPGA; parameter QEMU = `QEMU; - parameter DESIGN_COMPILER = `DESIGN_COMPILER; parameter IEEE754 = `IEEE754; parameter MISA = `MISA; parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED; @@ -215,4 +214,4 @@ package cvw; parameter DIVBLEN = ($clog2(`DIVb+1)-1); parameter DIVa = (`DIVb+1-`XLEN); // used for idiv on fpu -endpackage; +endpackage From 1b0b9314c4cd009bdf7af5a1740d958fa4c0f979 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 10:58:36 -0800 Subject: [PATCH 142/294] removed unused memory model --- pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v | 1 - 1 file changed, 1 deletion(-) delete mode 120000 pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v diff --git a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v deleted file mode 120000 index c81975209..000000000 --- a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v +++ /dev/null @@ -1 +0,0 @@ -/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v \ No newline at end of file From ed1aaa6c8f81ae321ed091785fc52e6fb97c08be Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 11:00:05 -0800 Subject: [PATCH 143/294] Comment cleanup in subcachelineread --- pipelined/src/cache/subcachelineread.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 346ec710e..490618070 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -30,8 +30,8 @@ `include "wally-config.vh" module subcachelineread #(parameter LINELEN, WORDLEN, - parameter MUXINTERVAL // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ -)( + parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ + input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. From 3f25123c6358edabf3fa3d7486ce05e542d29853 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 16:14:19 -0600 Subject: [PATCH 144/294] Possible fix for speculative gshare. --- pipelined/regression/wave.do | 78 ++++++++++--------- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 43 +++++----- 3 files changed, 68 insertions(+), 55 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index bfa161dad..b2d2cfd2f 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -61,10 +61,10 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/Inst add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName @@ -99,6 +99,7 @@ add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf @@ -573,12 +574,6 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/CompressedOpcF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/InstrClassF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjal -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cj -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjr -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjalr add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM @@ -588,34 +583,47 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextW +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {5845 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -631,4 +639,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2195 ns} {2479 ns} +WaveRestoreZoom {5721 ns} {5893 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 3fd021574..6af314646 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 1 +`define INSTR_CLASS_PRED 0 module bpred ( input logic clk, reset, diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 85cb3654c..649800975 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -53,10 +53,10 @@ module speculativegshare logic [k-1:0] GHRF, OldGHRF; logic OldGHRExtraF; - logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k:0] GHRNextD; - logic [k:0] GHRNextE, GHRNextM, GHRNextW; + logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; + logic [k-1:0] GHRNextF; + logic [k-1:0] GHRNextD; + logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; @@ -113,31 +113,36 @@ module speculativegshare always_comb begin if(FlushD) begin - if(BranchInstrE) GHRNextF = GHRNextD[k:1]; - else GHRNextF = GHRNextD[k-1:0]; + //if(BranchInstrE) GHRNextF = {PCSrcE, GHRNextD[k-1:1]}; + //else GHRNextF = GHRNextD[k-1:0]; + GHRNextF = GHRNextD[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; end - - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); - flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); - assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left - OldGHRF[k-1:0]; + + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + //flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); + //flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); +// assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right +// WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left +// OldGHRF[k-1:0]; - assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF}; + //assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]}; + assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; - flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - assign GHRNextE = FlushE ? GHRNextM : GHRD; - flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); - assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; + assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed and was mispredicted + FlushE ? GHRNextM : // branch is flushed + GHRD; + flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); + //assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); + flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); + flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; From b52990e2ceeb9bb97eab97ee545573098c105928 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 16:42:19 -0600 Subject: [PATCH 145/294] Possible workign instruction class prediction repair. --- pipelined/src/ifu/brpred/speculativegshare.sv | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 649800975..7760cbef9 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -52,7 +52,7 @@ module speculativegshare logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF, OldGHRF; - logic OldGHRExtraF; + logic GHRExtraF; logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; logic [k-1:0] GHRNextD; @@ -113,30 +113,28 @@ module speculativegshare always_comb begin if(FlushD) begin - //if(BranchInstrE) GHRNextF = {PCSrcE, GHRNextD[k-1:1]}; - //else GHRNextF = GHRNextD[k-1:0]; GHRNextF = GHRNextD[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; end flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - //flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); - //flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); -// assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right -// WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left -// OldGHRF[k-1:0]; - - //assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]}; - assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; + flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF); + + // use with out instruction class prediction + //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; + // with instruction class prediction + assign GHRNextD = FlushD ? GHRNextE[k-1:0] : + WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left + GHRF[k-1:0]; flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed and was mispredicted + assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed FlushE ? GHRNextM : // branch is flushed GHRD; flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); - //assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; assign GHRNextM = FlushM ? GHRNextW : GHRE; flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); From 3ddf95ac6e3d63ed890b5a3f11223cbefc28fc24 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 17:00:50 -0600 Subject: [PATCH 146/294] Found an issue where the btb was not forwarding the valid bit! --- pipelined/src/ifu/brpred/btb.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 9b6c66b85..20500226a 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -56,6 +56,7 @@ module btb logic [`XLEN-1:0] PredPCD; logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; + logic TablePredValidF; // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. @@ -93,9 +94,11 @@ module btb end else if ((UpdateEn) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end - PredValidF = ValidBits[PCNextFIndex]; + TablePredValidF = ValidBits[PCNextFIndex]; end + assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; + assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; // An optimization may be using a PC relative address. From 684a7214cbacc3509f778cbe6e6825e9d0a4f137 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 17:50:46 -0600 Subject: [PATCH 147/294] Added another performance counter to track overall branch miss-predictions. --- pipelined/regression/wave.do | 6 ++++-- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/ifu.sv | 3 ++- pipelined/src/privileged/csr.sv | 3 ++- pipelined/src/privileged/csrc.sv | 4 +++- pipelined/src/privileged/privileged.sv | 11 ++++++----- pipelined/src/wally/wallypipelinedcore.sv | 6 +++--- pipelined/testbench/testbench.sv | 3 ++- 8 files changed, 23 insertions(+), 15 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index b2d2cfd2f..cdae10c6b 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -531,6 +531,7 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -lab add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} @@ -622,8 +623,9 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {5845 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {217131 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -639,4 +641,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {5721 ns} {5893 ns} +WaveRestoreZoom {135840 ns} {362253 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6af314646..639dbcd50 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -59,6 +59,7 @@ module bpred ( // Report branch prediction status output logic BPPredWrongE, // Prediction is wrong + output logic BPPredWrongM, // Prediction is wrong output logic DirPredictionWrongM, // Prediction direction is wrong output logic BTBPredPCWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong @@ -79,7 +80,6 @@ module bpred ( logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; - logic BPPredWrongM; logic [`XLEN-1:0] PCNext0F; logic [`XLEN-1:0] PCCorrectE; logic [3:0] WrongPredInstrClassD; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 9be88d568..242fb6944 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -51,6 +51,7 @@ module ifu ( input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address output logic [`XLEN-1:0] PCE, // Execution stage instruction address output logic BPPredWrongE, // Prediction is wrong + output logic BPPredWrongM, // Prediction is wrong // Mem output logic CommittedF, // I$ or bus memory operation started, delay interrupts input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes. @@ -328,7 +329,7 @@ module ifu ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 9a91d371e..ef4d73cb2 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -61,6 +61,7 @@ module csr #(parameter input logic BTBPredPCWrongM, input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, + input logic BPPredWrongM, // branch predictor is wrong input logic [3:0] InstrClassM, input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, @@ -256,7 +257,7 @@ module csr #(parameter if (`ZICOUNTERS_SUPPORTED) begin:counters csrc counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .BPPredWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 83e3ccdfe..bd5ede793 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -48,6 +48,7 @@ module csrc #(parameter input logic BTBPredPCWrongM, input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, + input logic BPPredWrongM, // branch predictor is wrong input logic [3:0] InstrClassM, input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, @@ -96,7 +97,8 @@ module csrc #(parameter assign CounterEvent[12] = DCacheMiss; // data cache miss assign CounterEvent[13] = ICacheAccess; // instruction cache access assign CounterEvent[14] = ICacheMiss; // instruction cache miss - assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions + assign CounterEvent[15] = BPPredWrongM; // branch predictor wrong + assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end // Counter update and write logic diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index c3f321753..29d65f131 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -46,10 +46,11 @@ module privileged ( // processor events for performance counter logging input logic FRegWriteM, // instruction will write floating-point registers input logic LoadStallD, // load instruction is stalling - input logic DirPredictionWrongM, // branch predictor guessed wrong directoin - input logic BTBPredPCWrongM, // branch predictor guessed wrong target - input logic RASPredPCWrongM, // return adddress stack guessed wrong target - input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class + input logic DirPredictionWrongM, // branch predictor guessed wrong directoin + input logic BTBPredPCWrongM, // branch predictor guessed wrong target + input logic RASPredPCWrongM, // return adddress stack guessed wrong target + input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class + input logic BPPredWrongM, // branch predictor is wrong input logic [3:0] InstrClassM, // actual instruction class input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, // data cache miss @@ -124,7 +125,7 @@ module privileged ( .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredWrongM, .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index c6f5240a3..e2f04682a 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -141,7 +141,7 @@ module wallypipelinedcore ( logic LSUHWRITE; logic LSUHREADY; - logic BPPredWrongE; + logic BPPredWrongE, BPPredWrongM; logic DirPredictionWrongM; logic BTBPredPCWrongM; logic RASPredPCWrongM; @@ -175,7 +175,7 @@ module wallypipelinedcore ( .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, // Execute - .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, + .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM, // Mem .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, @@ -290,7 +290,7 @@ module wallypipelinedcore ( .RetM, .TrapM, .sfencevmaM, .InstrValidM, .CommittedM, .CommittedF, .FRegWriteM, .LoadStallD, - .DirPredictionWrongM, .BTBPredPCWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 5456ce8b9..1e373de57 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -424,7 +424,8 @@ logic [3:0] dummy; "D Cache Access", "D Cache Miss", "I Cache Access", - "I Cache Miss"}; + "I Cache Miss", + "Br Pred Wrong"}; always @(negedge clk) begin if(DCacheFlushStart & ~DCacheFlushDone) begin for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin From 6945eaf045507b97f175f36374b934d74cfaa6d8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 17:56:56 -0600 Subject: [PATCH 148/294] Fixed bug with the new csr. --- pipelined/src/privileged/csrc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index bd5ede793..94dbcaf48 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -97,7 +97,7 @@ module csrc #(parameter assign CounterEvent[12] = DCacheMiss; // data cache miss assign CounterEvent[13] = ICacheAccess; // instruction cache access assign CounterEvent[14] = ICacheMiss; // instruction cache miss - assign CounterEvent[15] = BPPredWrongM; // branch predictor wrong + assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM; // branch predictor wrong assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end From ee1bcf62ee99fda127cc7ab28da731697edef2f4 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sat, 28 Jan 2023 17:29:35 -0800 Subject: [PATCH 149/294] Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. --- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 45 ++++++++++--------- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 45 ++++++++++--------- 2 files changed, 48 insertions(+), 42 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 07813da16..1171786f4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -1068,33 +1068,36 @@ uart_save_iir_status: j test_loop uart_data_wait: - li t2, 0x10000005 // LSR - li t3, 0x10000002 // IIR - li a4, 0x61 -uart_read_LSR_IIR: - lbu t4, 0(t3) // save IIR before reading LSR might clear it - // check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this. - li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending - beq t4, t5, uart_rxfifo_timout - lb t5, 0(t2) // read LSR - andi t6, t5, 0x61 // wait until all transmissions are done and data is ready - bne a4, t6, uart_read_LSR_IIR + li t2, 0x10000002 + lbu t3, 0(t2) // save IIR before reading LSR might clear it + // Check IIR to see if theres an rxfifio or txempty interrupt and handle it before continuing. + li t2, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending + beq t3, t2, uart_rxfifo_timout + li t2, 0xC2 // Value in IIR for Fifo Enabled, with txempty interrupt pending. + beq t3, t2, uart_txempty_intr + li t2, 0x10000005 // There needs to be an instruction here between the beq and the lb or the tests will hang + lb t4, 0(t2) // read LSR + li t2, 0x61 + bne t4, t2, uart_data_wait // wait until all transmissions are done and data is ready j uart_data_ready uart_rxfifo_timout: - li t4, 0x10000000 // read from the fifo to clear the rx timeout error - lb t5, 0(t4) - sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur. - //read the fifo until empty - j uart_read_LSR_IIR - + li t2, 0x10000000 // read from the fifo to clear the rx timeout error + lb t5, 0(t2) + sb t5, 0(t2) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur. + j uart_data_wait +uart_txempty_intr: + li t2, 0x10000002 + lb t5, 0(t2) // Read IIR to clear this bit in LSR + j uart_data_wait uart_data_ready: + li t2, 0x10000002 + lbu t3, 0(t2) // re read IIR + andi t4, t4, 0x9F // mask THRE and TEMT from IIR signature li t2, 0 sw t2, 0(t1) // clear entry deadbeef from memory - lbu t4, 0(t3) // re read IIR - andi t5, t5, 0x9F // mask THRE and TEMT from signature - sb t4, 1(t1) // IIR - sb t5, 0(t1) // LSR + sb t3, 1(t1) // IIR + sb t4, 0(t1) // LSR addi t1, t1, 4 addi a6, a6, 4 j test_loop diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 86568c12b..576636deb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -1107,33 +1107,36 @@ uart_save_iir_status: j test_loop uart_data_wait: - li t2, 0x10000005 // LSR - li t3, 0x10000002 // IIR - li a4, 0x61 -uart_read_LSR_IIR: - lbu t4, 0(t3) // save IIR before reading LSR might clear it - // check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this. - li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending - beq t4, t5, uart_rxfifo_timout - lb t5, 0(t2) // read LSR - andi t6, t5, 0x61 // wait until all transmissions are done and data is ready - bne a4, t6, uart_read_LSR_IIR + li t2, 0x10000002 + lbu t3, 0(t2) // save IIR before reading LSR might clear it + // Check IIR to see if theres an rxfifio or txempty interrupt and handle it before continuing. + li t2, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending + beq t3, t2, uart_rxfifo_timout + li t2, 0xC2 // Value in IIR for Fifo Enabled, with txempty interrupt pending. + beq t3, t2, uart_txempty_intr + li t2, 0x10000005 // There needs to be an instruction here between the beq and the lb or the tests will hang + lb t4, 0(t2) // read LSR + li t2, 0x61 + bne t4, t2, uart_data_wait // wait until all transmissions are done and data is ready j uart_data_ready uart_rxfifo_timout: - li t4, 0x10000000 // read from the fifo to clear the rx timeout error - lb t5, 0(t4) - sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur. - //read the fifo until empty - j uart_read_LSR_IIR - + li t2, 0x10000000 // read from the fifo to clear the rx timeout error + lb t5, 0(t2) + sb t5, 0(t2) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur. + j uart_data_wait +uart_txempty_intr: + li t2, 0x10000002 + lb t5, 0(t2) // Read IIR to clear this bit in LSR + j uart_data_wait uart_data_ready: + li t2, 0x10000002 + lbu t3, 0(t2) // re read IIR + andi t4, t4, 0x9F // mask THRE and TEMT from IIR signature li t2, 0 sd t2, 0(t1) // clear entry deadbeef from memory - lbu t4, 0(t3) // re read IIR - andi t5, t5, 0x9F // mask THRE and TEMT from signature - sb t4, 1(t1) // IIR - sb t5, 0(t1) // LSR + sb t3, 1(t1) // IIR + sb t4, 0(t1) // LSR addi t1, t1, 8 addi a6, a6, 8 j test_loop From 5a0d8aed23d269c33d2f2954a126ef54bfcebe97 Mon Sep 17 00:00:00 2001 From: James Stine Date: Sat, 28 Jan 2023 19:33:00 -0600 Subject: [PATCH 150/294] Modified changes as follows * Add docs directory for Docker including Dockerfile * Change to synthesis script to include fpu stuff * Add wrappers for IP (may need some cleanup but will cleanup shortly) --- docs/D-Docker-Install.md | 206 ++++++++++++++++++ docs/Dockerfile | 132 +++++++++++ pipelined/src/generic/mem/ram1p1rwbe.sv | 28 ++- .../src/generic/mem/ram1p1rwbe_64x128.sv | 40 ++++ pipelined/src/generic/mem/ram1p1rwbe_64x44.sv | 40 ++++ .../src/generic/mem/ram2p1rwbe_1024x69.sv | 48 ++++ pipelined/src/generic/mem/rom1p1r_128x32.sv | 38 ++++ synthDC/scripts/synth.tcl | 1 + 8 files changed, 523 insertions(+), 10 deletions(-) create mode 100644 docs/D-Docker-Install.md create mode 100755 docs/Dockerfile create mode 100755 pipelined/src/generic/mem/ram1p1rwbe_64x128.sv create mode 100644 pipelined/src/generic/mem/ram1p1rwbe_64x44.sv create mode 100755 pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv create mode 100755 pipelined/src/generic/mem/rom1p1r_128x32.sv diff --git a/docs/D-Docker-Install.md b/docs/D-Docker-Install.md new file mode 100644 index 000000000..25fb3c4d1 --- /dev/null +++ b/docs/D-Docker-Install.md @@ -0,0 +1,206 @@ +D Wally Toolchain Docker Container + +Installing RISC-V tools from source gives you maximum control, but has several disadvantages: + +* Building the executables takes several hours. +* Linux is poorly standardized, and the build steps might not work on your version +* The source files are constantly changing, and the versions you download might not be compatible with this textbook flow. + +Docker is a tools to run applications in a prepackaged container including all of the operating system support required. Wally offers a ~30GB container image with the open-source tools pre-installed from Section D.1. In particular, using the container solves the long build time for gcc and the fussy installation of sail. The container runs on any platform supporting Docker, including Windows and Mac as well as Linux. It can access files outside the container, including local installation of CAD tools such as Questa, and a local clone of the core-v-wally repository. + +Docker can be run on most operating systems, including Linux, Windows, and Mac. The Wally Docker container is hosted at DockerHub (http://docker.io). + +Podman is a more secure and easier-to-use variation of Docker for Linux developed by RedHat. Both Docker and Podman run the same containers. + +D.3.1 Podman Installation on Linux + +A system administrator must install Podman if it is not already present. + +For Ubuntu 20.10 or later: + +$ sudo apt-get -y install podman + +For RedHat / Rocky: + +$ sudo yum -y install podman + +D.3.2 Pulling the Wally Container + +Once Podman is installed, a user can pull the Wally container image. The user must sign up for a free account at docker.io, and will be prompted for the credentials when running podman login. + +$ podman login docker.io +$ podman pull docker.io/wallysoc/wally-docker:latest + +D.3.3 Running the Docker Container in Podman + +To activate podman with GUI support, first identify your display port in the /tmp/.X11-unix file as shown below. For example, the user ben is on port X51. + +$ ls -la /tmp/.X11-unix/ +drwxrwxrwt 2 root root 4096 Jan 6 05:01 . +drwxrwxrwt 122 root root 40960 Jan 17 08:09 .. +srwxrwxrwx 1 root root 0 Jan 5 08:48 X0 +srwxrwxrwx 1 xwalter xwalter 0 Jan 5 09:21 X50 +srwxrwxrwx 1 ben ben 0 Jan 6 05:01 X51 + +Then run podman with the display number after the X (51 in this case). The -v options also mount the user’s home directory (/home/ben) and cad tools (/cad) to be visible from the container. Change these as necessary based on your local system configuration. + +$ podman run -it --net=host -e DISPLAY=:51 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/ben:/home/ben -v /cad:/cad -p 8080:8080 docker.io/wallysoc/wally-docker + +Podman sets up all the RISC-V software in the same location of /opt/riscv as the cad user as discussed previously. This shared directory is called $RISCV. This environmental variable should also be set up within the Docker container automatically and ready to use once the container is run. It is important to understand that Docker containers are self-contained, and any data created within your container is lost when you exit the container. Therefore, be sure to work in your mounted home directory (e.g. /home/ben) to permanently save your work outside the container. + +To have permission to write to your mounted home directory, you must become root inside the Wally container. This is an acceptable practice as the security will be maintained within podman for the user that runs podman. To become root once inside your container: + +$ su # when prompted for password, enter wally + +D.3.4 Cleaning up a Podman Container + +The Docker container image is large, so users may need to clean up a container when they aren’t using it anymore. +The images that are loaded can be examined, once you pull the Wally container, by typing: + +$ podman images + +To remove individual podman images, the following Linux command will remove the specific podman image where the image name is obtained from the podman images command (this command also works equally well using the instead of the , as well). + +$ podman rmi -f + +D.3.5 Running the Docker Container on Windows or MacOS + +Docker Desktop is easiest to use for Mac OS or Windows and can be installed by downloading from http://docker.com. Once the desktop application is installed, users can log into their DockerHub account through the Docker Desktop application and manage their containers easily. + +*** with Questa +*** questa unavailable native on Mac + + +D.3.6 Regenerating the Docker File + +We use the following steps to generate the Docker file. You can adapt them is you wish to make your own custom Docker image, such as one with commercial CAD tools installed in your local environment. + +*** how to use this + +# Compliance Development Environment Image +FROM debian + +# UPDATE / UPGRADE +RUN apt update + +# INSTALL +RUN apt install -y git gawk make texinfo bison flex build-essential python libz- +dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build +-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp- +dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zl +ib1g-dev verilator cpio bc vim emacs gedit nano + +RUN pip3 install chardet==3.0.4 +RUN pip3 install urllib3==1.22 +RUN pip3 install testresources +RUN pip3 install riscof --ignore-installed PyYAML +RUN echo "root:wally" | chpasswd + +# ADD RISCV +WORKDIR /opt/riscv + +# Create a user group 'xyzgroup' +ARG USERNAME=cad +ARG USER_UID=1000 +ARG USER_GID=$USER_UID + +# Create the user +RUN groupadd --gid $USER_GID $USERNAME \ + && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \ + # [Optional] Add sudo support. Omit if you don't need to install software af +ter connecting. + && apt-get update \ + && apt-get install -y sudo \ + && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \ + && chmod 0440 /etc/sudoers.d/$USERNAME + +# Change RISCV user +run chown -Rf cad:cad /opt + +# Add cad user +USER $USERNAME + +# SET ENVIRONMENT VARIABLES +ENV RISCV=/opt/riscv +ENV PATH=$PATH:$RISCV/bin + +# TOOLCHAIN +RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \ + cd riscv-gnu-toolchain && \ + ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="r +v32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32 +imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv6 +4imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \ + make --jobs && \ + make install + +# elf2hex +ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +WORKDIR /opt/riscv +RUN git clone https://github.com/sifive/elf2hex.git && \ + cd elf2hex && \ + autoreconf -i && \ + ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \ + make && \ + make install + +# QEMU +WORKDIR /opt/riscv +RUN git clone --recurse-submodules https://github.com/qemu/qemu && \ + cd qemu && \ + ./configure --target-list=riscv64-softmmu --prefix=$RISCV && \ + make --jobs && \ + make install + +# Spike +WORKDIR /opt/riscv +RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \ + mkdir riscv-isa-sim/build && \ + cd riscv-isa-sim/build && \ + ../configure --prefix=$RISCV --enable-commitlog && \ + make --jobs && \ + make install && \ + cd ../arch_test_target/spike/device && \ + sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \ + sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include + +# SAIL +WORKDIR /opt/riscv +RUN opam init -y --disable-sandboxing +RUN opam switch create ocaml-base-compiler.4.06.1 +RUN opam install sail -y +RUN eval $(opam config env) && \ + cd $RISCV && \ + git clone https://github.com/riscv/sail-riscv.git && \ + cd sail-riscv && \ + make && \ + ARCH=RV32 make && \ + ARCH=RV64 make && \ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && +\ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32 + +# Buildroot +WORKDIR /opt/riscv +RUN git clone --recurse-submodules https://stineje:ghp_kXIHqiMSv4tFec2BCAvrhSrIh +3KNUD06IejU@github.com/davidharrishmc/riscv-wally.git +ENV export WALLY=/opt/riscv/riscv-wally +RUN git clone https://github.com/buildroot/buildroot.git && \ + cd buildroot && \ + git checkout 2021.05 && \ + cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \ + cp ./board/wally/main.config .config && \ + make --jobs + +# change to cad's hometown +WORKDIR /home/cad + + +D.3.7 Integrating Commercial CAD Tools into a Local Docker Container + + + +RISC-V System-on-Chip Design Lecture Notes +© 2023 D. Harris, J. Stine, , R. Thompson, and S. Harris +These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed. + diff --git a/docs/Dockerfile b/docs/Dockerfile new file mode 100755 index 000000000..cdc3dbcfc --- /dev/null +++ b/docs/Dockerfile @@ -0,0 +1,132 @@ +########################################### +## Dockerfile +## +## Written: james.stine@okstate.edu 28 January 2023 +## Modified: +## +## Purpose: Dockerfile for Wally docker container creation +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org#licenses#SHL-2.1# +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ +# Compliance Development Environment Image +FROM debian + +# UPDATE / UPGRADE +RUN apt update + +# INSTALL +RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano + +RUN pip3 install chardet==3.0.4 +RUN pip3 install urllib3==1.22 +RUN pip3 install testresources +RUN pip3 install riscof --ignore-installed PyYAML +RUN echo "root:wally" | chpasswd + +# ADD RISCV +WORKDIR /opt/riscv + +# Create a user group 'xyzgroup' +ARG USERNAME=cad +ARG USER_UID=1000 +ARG USER_GID=$USER_UID + +# Create the user +RUN groupadd --gid $USER_GID $USERNAME \ + && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \ + # [Optional] Add sudo support. Omit if you don't need to install software after connecting. + && apt-get update \ + && apt-get install -y sudo \ + && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \ + && chmod 0440 /etc/sudoers.d/$USERNAME + +# Change RISCV user +run chown -Rf cad:cad /opt + +# Add cad user +USER $USERNAME + +# SET ENVIRONMENT VARIABLES +ENV RISCV=/opt/riscv +ENV PATH=$PATH:$RISCV/bin + +# TOOLCHAIN +RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \ + cd riscv-gnu-toolchain && \ + ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \ + make --jobs && \ + make install + +# elf2hex +ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +WORKDIR /opt/riscv +RUN git clone https://github.com/sifive/elf2hex.git && \ + cd elf2hex && \ + autoreconf -i && \ + ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \ + make && \ + make install + +# QEMU +WORKDIR /opt/riscv +RUN git clone --recurse-submodules https://github.com/qemu/qemu && \ + cd qemu && \ + ./configure --target-list=riscv64-softmmu --prefix=$RISCV && \ + make --jobs && \ + make install + +# Spike +WORKDIR /opt/riscv +RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \ + mkdir riscv-isa-sim/build && \ + cd riscv-isa-sim/build && \ + ../configure --prefix=$RISCV --enable-commitlog && \ + make --jobs && \ + make install && \ + cd ../arch_test_target/spike/device && \ + sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \ + sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include + +# SAIL +WORKDIR /opt/riscv +RUN opam init -y --disable-sandboxing +RUN opam switch create ocaml-base-compiler.4.06.1 +RUN opam install sail -y +RUN eval $(opam config env) && \ + cd $RISCV && \ + git clone https://github.com/riscv/sail-riscv.git && \ + cd sail-riscv && \ + make && \ + ARCH=RV32 make && \ + ARCH=RV64 make && \ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \ + ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32 + +# Buildroot +WORKDIR /opt/riscv +RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git +ENV export WALLY=/opt/riscv/riscv-wally +RUN git clone https://github.com/buildroot/buildroot.git && \ + cd buildroot && \ + git checkout 2021.05 && \ + cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \ + cp ./board/wally/main.config .config && \ + make --jobs + +# change to cad's hometown +WORKDIR /home/cad diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 7b79eb35c..47b3f1fe7 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -49,17 +49,25 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if (`USE_SRAM == 1) begin + if (`USE_SRAM == 1 && WIDTH == 128 && `XLEN == 64) begin genvar index; - // 64 x 128-bit SRAM - // check if the size is ok, complain if not*** - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; - TS1N28HPCPSVTB64X128M4SW sram( - .CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + // 64 x 128-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); + + end else if (`USE_SRAM == 1 && WIDTH == 44 && `XLEN == 64) begin + genvar index; + // 64 x 44-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); // *************************************************************************** // READ first SRAM model diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv new file mode 100755 index 000000000..fa8e32f0b --- /dev/null +++ b/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// ram1p1rwbe_64x128.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram1p1rwbe_64x128( + input logic CLK, + input logic CEB, + input logic WEB, + input logic [5:0] A, + input logic [127:0] D, + input logic [127:0] BWEB, + output logic [127:0] Q +); + + // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor + generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + +endmodule diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv new file mode 100644 index 000000000..7fa71f312 --- /dev/null +++ b/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// ram1p1rwbe_64x44.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram1p1rwbe_64x44( + input logic CLK, + input logic CEB, + input logic WEB, + input logic [5:0] A, + input logic [127:0] D, + input logic [127:0] BWEB, + output logic [127:0] Q +); + + // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor + generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + +endmodule diff --git a/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv b/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv new file mode 100755 index 000000000..a287942bd --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// ram2p1rwbe_1024x69.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1rwbe_1024x69( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [9:0] AA, + input logic [9:0] AB, + input logic [68:0] DA, + input logic [68:0] DB, + input logic [68:0] BWEBA, + input logic [68:0] BWEBB, + output logic [68:0] QA, + output logic [68:0] QB, +); + + // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor + generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/pipelined/src/generic/mem/rom1p1r_128x32.sv new file mode 100755 index 000000000..89d46b8f1 --- /dev/null +++ b/pipelined/src/generic/mem/rom1p1r_128x32.sv @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// rom1p1r_128x32.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rom1p1r_128x32( + input logic CLK, + input logic CEB, + input logic [6:0] A, + output logic [31:0] Q +); + + // replace "generic128x32ROM" with "TS3N..128X32.." module from your memory vendor + generic64x128ROM sramIP (.CLK, .CEB, .A, .Q); + +endmodule + diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index ed43a1ab3..b1342456c 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -30,6 +30,7 @@ eval file copy -force ${cfg} {$outputDir/hdl/} #eval file copy -force ${cfg} $outputDir eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/} # Only for FMA class project; comment out when done From 8b4c3920dbf872bd9df2cb1f853c3e8852d00067 Mon Sep 17 00:00:00 2001 From: James Stine Date: Sat, 28 Jan 2023 19:46:43 -0600 Subject: [PATCH 151/294] Update Appendix D + wrapped memories --- addins/docker/Dockerfile | 107 --------------------------------------- addins/docker/README.md | 48 ------------------ 2 files changed, 155 deletions(-) delete mode 100755 addins/docker/Dockerfile delete mode 100644 addins/docker/README.md diff --git a/addins/docker/Dockerfile b/addins/docker/Dockerfile deleted file mode 100755 index e06fa039d..000000000 --- a/addins/docker/Dockerfile +++ /dev/null @@ -1,107 +0,0 @@ -# Compliance Development Environment Image -FROM debian - -# UPDATE / UPGRADE -RUN apt update - -# INSTALL -RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano - -RUN pip3 install chardet==3.0.4 -RUN pip3 install urllib3==1.22 -RUN pip3 install testresources -RUN pip3 install riscof --ignore-installed PyYAML -RUN echo "root:wally" | chpasswd - -# ADD RISCV -WORKDIR /opt/riscv - -# Create a user group 'xyzgroup' -ARG USERNAME=cad -ARG USER_UID=1000 -ARG USER_GID=$USER_UID - -# Create the user -RUN groupadd --gid $USER_GID $USERNAME \ - && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \ - # [Optional] Add sudo support. Omit if you don't need to install software after connecting. - && apt-get update \ - && apt-get install -y sudo \ - && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \ - && chmod 0440 /etc/sudoers.d/$USERNAME - -# Change RISCV user -run chown -Rf cad:cad /opt - -# Add cad user -USER $USERNAME - -# SET ENVIRONMENT VARIABLES -ENV RISCV=/opt/riscv -ENV PATH=$PATH:$RISCV/bin - -# TOOLCHAIN -RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \ - cd riscv-gnu-toolchain && \ - ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \ - make --jobs && \ - make install - -# elf2hex -ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH -WORKDIR /opt/riscv -RUN git clone https://github.com/sifive/elf2hex.git && \ - cd elf2hex && \ - autoreconf -i && \ - ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \ - make && \ - make install - -# QEMU -WORKDIR /opt/riscv -RUN git clone --recurse-submodules https://github.com/qemu/qemu && \ - cd qemu && \ - ./configure --target-list=riscv64-softmmu --prefix=$RISCV && \ - make --jobs && \ - make install - -# Spike -WORKDIR /opt/riscv -RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \ - mkdir riscv-isa-sim/build && \ - cd riscv-isa-sim/build && \ - ../configure --prefix=$RISCV --enable-commitlog && \ - make --jobs && \ - make install && \ - cd ../arch_test_target/spike/device && \ - sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \ - sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include - -# SAIL -WORKDIR /opt/riscv -RUN opam init -y --disable-sandboxing -RUN opam switch create ocaml-base-compiler.4.06.1 -RUN opam install sail -y -RUN eval $(opam config env) && \ - cd $RISCV && \ - git clone https://github.com/riscv/sail-riscv.git && \ - cd sail-riscv && \ - make && \ - ARCH=RV32 make && \ - ARCH=RV64 make && \ - ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \ - ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32 - -# Buildroot -WORKDIR /opt/riscv -RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git -ENV export WALLY=/opt/riscv/riscv-wally -RUN git clone https://github.com/buildroot/buildroot.git && \ - cd buildroot && \ - git checkout 2021.05 && \ - cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \ - cp ./board/wally/main.config .config && \ - make --jobs - -# change to cad's hometown -WORKDIR /home/cad diff --git a/addins/docker/README.md b/addins/docker/README.md deleted file mode 100644 index 135c7e744..000000000 --- a/addins/docker/README.md +++ /dev/null @@ -1,48 +0,0 @@ -Installing Wally, RISC-V tools, and Imperas tests from source gives you maximum control, but has several disadvantages: - --Building the executables takes several hours. --Linux is poorly standardized, and the build steps might not work on your version --The source files are constantly changing, and the versions you download might not be compatible with this textbook flow. - -Docker is a tools to run applications in a prepackaged container -including all of the operating system support required. Wally offers -a ~30GB container image with the open-source tools pre-installed from -Section D.1. In particular, using the container solves the long build -time for gcc and the fussy installation of sail. The container runs on -any platform supporting Docker, including Windows and Mac as well as -Linux. It can access files outside the container, including local -installation of CAD tools such as Questa, and a local clone of the -core-v-wally repository. - -Docker can be run on most operating systems, including Linux, Windows, -and Mac. The Wally Docker container is hosted at DockerHub -(http://docker.io). - -Podman is a more secure and easier-to-use variation of Docker for -Linux developed by RedHat. Both Docker and Podman run the same -containers. - -This directory has a copy of the file utilized to create the Docker -for the toolchain discussed in the text. To build this docker, you can -type the following where the last argument is the name where you want -to store your docker. - -docker build -t docker.io/wallysoc/wally-docker:latest . - -This can also be changed if you make a mistake by using the tag -command. For example, if I wanted to change my docker from -wally-docker to wally-docker2, I would type: - -docker tag wallysoc/wally-docker:latest docker.io/wallysoc/wally-docker2:latest - -Once you build your docker, you can run it as given in the Readme. -However, you can also push it to DockerHub with the following command. - -docker push docker.io/wallysoc/wally-docker:latest - -To run your docker, you can type the following at a command prompt or -terminal. - -docker run -it -p 8080:8080 docker.io/wallysoc/wally-docker - - From c73fe4041e9647d03071fd3717fa8e37b763213c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 18:07:33 -0800 Subject: [PATCH 152/294] Fixed typo in ram2p1r1wbe_1024x69 and renamed for consistency --- .../mem/{ram2p1rwbe_1024x69.sv => ram2p1r1wbe_1024x69.sv} | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename pipelined/src/generic/mem/{ram2p1rwbe_1024x69.sv => ram2p1r1wbe_1024x69.sv} (96%) diff --git a/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv similarity index 96% rename from pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv rename to pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv index a287942bd..4437c09bf 100755 --- a/pipelined/src/generic/mem/ram2p1rwbe_1024x69.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ram2p1rwbe_1024x69( +module ram2p1r1wbe_1024x69( input logic CLKA, input logic CLKB, input logic CEBA, @@ -38,7 +38,7 @@ module ram2p1rwbe_1024x69( input logic [68:0] BWEBA, input logic [68:0] BWEBB, output logic [68:0] QA, - output logic [68:0] QB, + output logic [68:0] QB ); // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor From 8a96dcf0ae61fc6aa1d815051372134fd0ff67a6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 18:17:42 -0800 Subject: [PATCH 153/294] Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED --- pipelined/config/buildroot/wally-config.vh | 2 +- pipelined/config/fpga/wally-config.vh | 4 ++-- pipelined/config/rv32e/wally-config.vh | 4 ++-- pipelined/config/rv32gc/wally-config.vh | 4 ++-- pipelined/config/rv32i/wally-config.vh | 6 +++--- pipelined/config/rv32ic/wally-config.vh | 4 ++-- pipelined/config/rv64fpquad/wally-config.vh | 4 ++-- pipelined/config/rv64gc/wally-config.vh | 2 +- pipelined/config/rv64i/wally-config.vh | 4 ++-- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/wally/cvw.sv | 2 +- pipelined/testbench/testbench.sv | 2 +- pipelined/testbench/testbench_imperas.sv | 2 +- 13 files changed, 21 insertions(+), 21 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index a4ec7fb47..ccad97cb6 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -128,7 +128,7 @@ `define PLIC_UART_ID 10 `define PLIC_GPIO_ID 3 -`define BPRED_ENABLED 1 +`define BPRED_SUPPORTED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 56bf10402..ddbb18c0b 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -71,7 +71,7 @@ `define IDIV_ON_FPU 1 // Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 64 +`define PMP_ENTRIES 16 // Address space `define RESET_VECTOR 64'h0000000000001000 @@ -139,7 +139,7 @@ `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt" `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt" -`define BPRED_ENABLED 1 +`define BPRED_SUPPORTED 1 `define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 1 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index b42633679..c81faeb85 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -69,7 +69,7 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 `define IDIV_BITSPERCYCLE 1 -`define IDIV_ON_FPU 1 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 0 @@ -132,7 +132,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 0 +`define BPRED_SUPPORTED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 2704a9a00..94d56d835 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -68,7 +68,7 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 `define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 @@ -131,7 +131,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 1 +`define BPRED_SUPPORTED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 119354aa8..80a4773d8 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -69,10 +69,10 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 `define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 64 +`define PMP_ENTRIES 0 // Address space `define RESET_VECTOR 32'h80000000 @@ -132,7 +132,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 1 +`define BPRED_SUPPORTED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 49281c289..eb6627624 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -68,7 +68,7 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 `define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 0 @@ -131,7 +131,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 1 +`define BPRED_SUPPORTED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 4d36ff303..2570ff1df 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -72,7 +72,7 @@ `define IDIV_ON_FPU 1 // Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 64 +`define PMP_ENTRIES 16 // Address space `define RESET_VECTOR 64'h0000000080000000 @@ -134,7 +134,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 1 +`define BPRED_SUPPORTED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index c00e02843..bdef122ff 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -134,7 +134,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 1 +`define BPRED_SUPPORTED 1 //`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 //`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index b0df9bc30..bb7b71c0e 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -69,7 +69,7 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 `define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 0 @@ -134,7 +134,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 0 +`define BPRED_SUPPORTED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 0ff6dc3f9..0010403a7 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -322,7 +322,7 @@ module ifu ( //////////////////////////////////////////////////////////////////////////////////////////////// // Branch and Jump Predictor //////////////////////////////////////////////////////////////////////////////////////////////// - if (`BPRED_ENABLED) begin : bpred + if (`BPRED_SUPPORTED) begin : bpred bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index 5fd28163e..66512e947 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -99,7 +99,7 @@ package cvw; // parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32; parameter PLIC_GPIO_ID = `PLIC_GPIO_ID; parameter PLIC_UART_ID = `PLIC_UART_ID; - parameter BPRED_ENABLED = `BPRED_ENABLED; + parameter BPRED_SUPPORTED = `BPRED_SUPPORTED; parameter BPTYPE = `BPTYPE; parameter TESTSBP = `TESTSBP; parameter BPRED_SIZE = `BPRED_SIZE; diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index fbd720109..2bbe1d113 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -465,7 +465,7 @@ logic [3:0] dummy; .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_ENABLED == 1) + if (`BPRED_SUPPORTED == 1) begin genvar adrindex; diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 6e84e879b..7e472a99b 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -219,7 +219,7 @@ module testbench; .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_ENABLED == 1) + if (`BPRED_SUPPORTED == 1) begin genvar adrindex; From fa3643a0643d058a2eda96630d69cb4287af0d69 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 18:35:53 -0800 Subject: [PATCH 154/294] Renamed BUS to BUS_SUPPORTED --- pipelined/config/buildroot/wally-config.vh | 2 +- pipelined/config/fpga/wally-config.vh | 2 +- pipelined/config/rv32e/wally-config.vh | 2 +- pipelined/config/rv32gc/wally-config.vh | 2 +- pipelined/config/rv32i/wally-config.vh | 2 +- pipelined/config/rv32ic/wally-config.vh | 2 +- pipelined/config/rv64fpquad/wally-config.vh | 2 +- pipelined/config/rv64gc/wally-config.vh | 2 +- pipelined/config/rv64i/wally-config.vh | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 4 ++-- pipelined/src/wally/cvw.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 2 +- pipelined/src/wally/wallypipelinedsoc.sv | 2 +- pipelined/testbench/testbench.sv | 4 ++-- pipelined/testbench/testbench_imperas.sv | 6 +++--- 16 files changed, 20 insertions(+), 20 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index ccad97cb6..4ef61acf1 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -44,7 +44,7 @@ `define COUNTERS 32 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index ddbb18c0b..ca5261cfe 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -45,7 +45,7 @@ `define COUNTERS 32 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index c81faeb85..8a1bc54e3 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 94d56d835..e18c99b64 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -45,7 +45,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 80a4773d8..23fa30fa2 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS_SUPPORTED 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index eb6627624..7f210ee88 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -45,7 +45,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 2570ff1df..6072ea459 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 1 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index bdef122ff..c24f4538c 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS_SUPPORTED 1 `define DCACHE 1 `define ICACHE 1 `define VIRTMEM_SUPPORTED 1 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index bb7b71c0e..2f01f50c9 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -46,7 +46,7 @@ `define ZFH_SUPPORTED 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS_SUPPORTED 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 0010403a7..ee0745875 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -208,7 +208,7 @@ module ifu ( end else begin assign IFURWF = 2'b10; end - if (`BUS) begin : bus + if (`BUS_SUPPORTED) begin : bus // **** must fix words per line vs beats per line as in lsu. localparam WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 19f5ba960..c28dc5006 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -206,7 +206,7 @@ module lsu ( assign {LoadPageFaultM, StoreAmoPageFaultM} = '0; assign PAdrM = IHAdrM[`PA_BITS-1:0]; assign CacheableM = 1'b1; - assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no PMA then select dtim if there is a DTIM. If there is + assign SelDTIM = `DTIM_SUPPORTED & ~`BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is // a bus then this is always 0. Cannot have both without PMA. end @@ -236,7 +236,7 @@ module lsu ( .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); end else begin end - if (`BUS) begin : bus + if (`BUS_SUPPORTED) begin : bus if(`DCACHE) begin : dcache localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index 66512e947..5aa6d2321 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -43,7 +43,7 @@ package cvw; parameter COUNTERS = `COUNTERS; parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED; parameter ZFH_SUPPORTED = `ZFH_SUPPORTED; - parameter BUS = `BUS; + parameter BUS_SUPPORTED = `BUS_SUPPORTED; parameter DCACHE = `DCACHE; parameter ICACHE = `ICACHE; parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 5c2c6efce..b50746477 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -237,7 +237,7 @@ module wallypipelinedcore ( .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); - if(BUS) begin : ebu + if(BUS_SUPPORTED) begin : ebu ebu ebu(// IFU connections .clk, .reset, // IFU interface diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 26979545c..e792f6f89 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -80,7 +80,7 @@ module wallypipelinedsoc ( ); // instantiate uncore if a bus interface exists - if (BUS) begin : uncore + if (BUS_SUPPORTED) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 2bbe1d113..6d0eec950 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -246,7 +246,7 @@ logic [3:0] dummy; force dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else begin if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); end @@ -545,7 +545,7 @@ module riscvassertions; assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS."); + assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 7e472a99b..1bd5d45c0 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -100,8 +100,8 @@ module testbench; pathname = "../../tests/riscof/work/wally-riscv-arch-test/"; memfilename = {pathname, testName, "/ref/ref.elf.memfile"}; - if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - else $error("Imperas test bench requires BUS."); + if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + else $error("Imperas test bench requires BUS_SUPPORTED."); ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"}; ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"}; @@ -287,7 +287,7 @@ module riscvassertions; assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS."); + assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); From b89fe9989ec3c91d2adb1cb966c6db491aa58f23 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 18:52:00 -0800 Subject: [PATCH 155/294] Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED --- pipelined/config/buildroot/wally-config.vh | 4 +-- pipelined/config/fpga/wally-config.vh | 4 +-- pipelined/config/rv32e/wally-config.vh | 4 +-- pipelined/config/rv32gc/wally-config.vh | 4 +-- pipelined/config/rv32i/wally-config.vh | 4 +-- pipelined/config/rv32ic/wally-config.vh | 4 +-- pipelined/config/rv64fpquad/wally-config.vh | 4 +-- pipelined/config/rv64gc/wally-config.vh | 4 +-- pipelined/config/rv64i/wally-config.vh | 4 +-- pipelined/src/ieu/controller.sv | 4 +-- pipelined/src/ifu/ifu.sv | 10 +++---- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/wally/cvw.sv | 4 +-- pipelined/testbench/testbench.sv | 32 ++++++++++----------- pipelined/testbench/testbench_imperas.sv | 18 ++++++------ 15 files changed, 53 insertions(+), 53 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 4ef61acf1..bb687da51 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -45,8 +45,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 1 -`define DCACHE 1 -`define ICACHE 1 +`define DCACHE_SUPPORTED 1 +`define ICACHE_SUPPORTED 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index ca5261cfe..a57f98a08 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -46,8 +46,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 1 -`define DCACHE 1 -`define ICACHE 1 +`define DCACHE_SUPPORTED 1 +`define ICACHE_SUPPORTED 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 8a1bc54e3..66cec123b 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -47,8 +47,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 1 -`define DCACHE 0 -`define ICACHE 0 +`define DCACHE_SUPPORTED 0 +`define ICACHE_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 0 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index e18c99b64..b420894ea 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -46,8 +46,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 1 -`define DCACHE 1 -`define ICACHE 1 +`define DCACHE_SUPPORTED 1 +`define ICACHE_SUPPORTED 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 23fa30fa2..8f9e9dd06 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -47,8 +47,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 0 -`define DCACHE 0 -`define ICACHE 0 +`define DCACHE_SUPPORTED 0 +`define ICACHE_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 7f210ee88..bdb0d4f42 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -46,8 +46,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 1 -`define DCACHE 0 -`define ICACHE 0 +`define DCACHE_SUPPORTED 0 +`define ICACHE_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 6072ea459..f92abcb5c 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -47,8 +47,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 1 -`define DCACHE 1 -`define ICACHE 1 +`define DCACHE_SUPPORTED 1 +`define ICACHE_SUPPORTED 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index c24f4538c..dcdda74f4 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -47,8 +47,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 1 -`define DCACHE 1 -`define ICACHE 1 +`define DCACHE_SUPPORTED 1 +`define ICACHE_SUPPORTED 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 2f01f50c9..d35e21632 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -47,8 +47,8 @@ // LSU microarchitectural Features `define BUS_SUPPORTED 0 -`define DCACHE 0 -`define ICACHE 0 +`define DCACHE_SUPPORTED 0 +`define ICACHE_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index e875c99fa..1819de17c 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -200,7 +200,7 @@ module controller( // Fences // Ordinary fence is presently a nop // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented - if (`ZIFENCEI_SUPPORTED & `ICACHE) begin:fencei + if (`ZIFENCEI_SUPPORTED & `ICACHE_SUPPORTED) begin:fencei logic FenceID; assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction? assign InvalidateICacheD = FenceID; @@ -249,5 +249,5 @@ module controller( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write - assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD)); + assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD)); endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index ee0745875..3e3e59743 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -134,7 +134,7 @@ module ifu ( ///////////////////////////////////////////////////////////////////////////////////////////// if(`C_SUPPORTED) begin : Spill - spill #(`ICACHE) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, + spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpill assign PCNextFSpill = PCNextF; @@ -210,10 +210,10 @@ module ifu ( end if (`BUS_SUPPORTED) begin : bus // **** must fix words per line vs beats per line as in lsu. - localparam WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; - localparam LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; - if(`ICACHE) begin : icache - localparam LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; + localparam WORDSPERLINE = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS/`XLEN : 1; + localparam LOGBWPL = `ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1; + if(`ICACHE_SUPPORTED) begin : icache + localparam LINELEN = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS : `XLEN; localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index c28dc5006..2eb8df1e5 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -237,7 +237,7 @@ module lsu ( end else begin end if (`BUS_SUPPORTED) begin : bus - if(`DCACHE) begin : dcache + if(`DCACHE_SUPPORTED) begin : dcache localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ localparam BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index 5aa6d2321..3c32ae05a 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -44,8 +44,8 @@ package cvw; parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED; parameter ZFH_SUPPORTED = `ZFH_SUPPORTED; parameter BUS_SUPPORTED = `BUS_SUPPORTED; - parameter DCACHE = `DCACHE; - parameter ICACHE = `ICACHE; + parameter DCACHE_SUPPORTED = `DCACHE_SUPPORTED; + parameter ICACHE_SUPPORTED = `ICACHE_SUPPORTED; parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED; parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED; parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED; diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 6d0eec950..73b6c1845 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -523,19 +523,19 @@ module riscvassertions; assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); @@ -543,12 +543,12 @@ module riscvassertions; assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); + assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); end @@ -569,7 +569,7 @@ module DCacheFlushFSM logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; - if(`DCACHE) begin + if(`DCACHE_SUPPORTED) begin localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index 1bd5d45c0..bc65a3c5b 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -265,14 +265,14 @@ module riscvassertions; assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACH_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); @@ -285,12 +285,12 @@ module riscvassertions; assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS."); + assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); + assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); end From 799caef2c9551b1beb36757a14f73fe0013d3f92 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 20:06:12 -0800 Subject: [PATCH 156/294] Renamed BPTYPE to BPRED_TYPE --- pipelined/config/buildroot/wally-config.vh | 2 +- pipelined/config/fpga/wally-config.vh | 2 +- pipelined/config/rv32e/wally-config.vh | 2 +- pipelined/config/rv32gc/wally-config.vh | 2 +- pipelined/config/rv32i/wally-config.vh | 2 +- pipelined/config/rv32ic/wally-config.vh | 2 +- pipelined/config/rv64fpquad/wally-config.vh | 2 +- pipelined/config/rv64gc/wally-config.vh | 6 +++--- pipelined/config/rv64i/wally-config.vh | 2 +- pipelined/src/ifu/bpred/bpred.sv | 12 ++++++------ pipelined/src/wally/cvw.sv | 3 +-- 11 files changed, 18 insertions(+), 19 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index bb687da51..f34874dc3 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -129,7 +129,7 @@ `define PLIC_GPIO_ID 3 `define BPRED_SUPPORTED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index a57f98a08..3612185e0 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -140,7 +140,7 @@ `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt" `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt" `define BPRED_SUPPORTED 1 -`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 1 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 66cec123b..84082fdc8 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -133,7 +133,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index b420894ea..ef98b0028 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -132,7 +132,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 8f9e9dd06..1cc0c5b32 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -133,7 +133,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index bdb0d4f42..a80c00e38 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -132,7 +132,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index f92abcb5c..649956fbe 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -135,7 +135,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index dcdda74f4..01b245b3d 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -135,9 +135,9 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 1 -//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +`define BPRED_TYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPRED_TYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index d35e21632..b4621d31d 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -135,7 +135,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 0319d3a08..22889bb3d 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -81,34 +81,34 @@ module bpred ( // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. - if (`BPTYPE == "BPTWOBIT") begin:Predictor + if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - end else if (`BPTYPE == "BPGLOBAL") begin:Predictor + end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - end else if (`BPTYPE == "BPSPECULATIVEGLOBAL") begin:Predictor + end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .BranchInstrW(InstrClassW[0]), .PCSrcE); - end else if (`BPTYPE == "BPGSHARE") begin:Predictor + end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor + end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); - end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor + end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor // *** Fix me /* -----\/----- EXCLUDED -----\/----- localHistoryPredictor DirPredictor(.clk, diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index 3c32ae05a..0a804c9a3 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -96,11 +96,10 @@ package cvw; parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST; parameter UART_PRESCALE = `UART_PRESCALE; parameter PLIC_NUM_SRC = `PLIC_NUM_SRC; -// parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32; parameter PLIC_GPIO_ID = `PLIC_GPIO_ID; parameter PLIC_UART_ID = `PLIC_UART_ID; parameter BPRED_SUPPORTED = `BPRED_SUPPORTED; - parameter BPTYPE = `BPTYPE; + parameter BPRED_TYPE = `BPRED_TYPE; parameter TESTSBP = `TESTSBP; parameter BPRED_SIZE = `BPRED_SIZE; parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED; From 0f13941d3b7a40ca580f54ae4678a31f752f149c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 Jan 2023 20:22:36 -0800 Subject: [PATCH 157/294] Removed unused BPRED file referenes from fpga config --- pipelined/config/fpga/wally-config.vh | 2 -- 1 file changed, 2 deletions(-) diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 3612185e0..d23ef9684 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -137,8 +137,6 @@ `define PLIC_UART_ID 10 `define PLIC_GPIO_ID 3 -`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt" `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 1 From 9e3074689d161a6e83210795ccbeeb9344fbc94a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:33:40 -0600 Subject: [PATCH 158/294] Fixed another bug with the speculative gshare with instruction class prediction. --- pipelined/regression/wave.do | 6 ++++-- pipelined/src/ifu/brpred/speculativegshare.sv | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index cdae10c6b..a17bc502e 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -584,6 +584,8 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE @@ -625,7 +627,7 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Fl add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {217131 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {296884 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -641,4 +643,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {135840 ns} {362253 ns} +WaveRestoreZoom {18545889 ns} {18546113 ns} diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 7760cbef9..6cfb56894 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -112,7 +112,7 @@ module speculativegshare // GHRF; always_comb begin - if(FlushD) begin + if(FlushD | DirPredictionWrongE) begin GHRNextF = GHRNextD[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; @@ -124,7 +124,7 @@ module speculativegshare // use with out instruction class prediction //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; // with instruction class prediction - assign GHRNextD = FlushD ? GHRNextE[k-1:0] : + assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left GHRF[k-1:0]; From c8df460b2842f098a1215ce72599f5391108a967 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:49:23 -0600 Subject: [PATCH 159/294] Fixed bug with the btb's valid bit not beind held on a stall. --- pipelined/src/ifu/brpred/btb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 20500226a..b8c5c6bcd 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -94,7 +94,7 @@ module btb end else if ((UpdateEn) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end - TablePredValidF = ValidBits[PCNextFIndex]; + if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex]; end assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; From 250a8df7c3112bc5e6f3aad30711f9fe8c02bb5b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:56:11 -0600 Subject: [PATCH 160/294] Updated testbench for branch logger. --- pipelined/testbench/testbench.sv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 1e373de57..1c2fbb1f0 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -32,8 +32,8 @@ `include "wally-config.vh" `include "tests.vh" -`define PrintHPMCounters 0 -`define BPRED_LOGGER 0 +`define PrintHPMCounters 1 +`define BPRED_LOGGER 1 module testbench; parameter DEBUG=0; @@ -484,11 +484,13 @@ logic [3:0] dummy; if (`BPRED_LOGGER) begin string direction; int file; + logic PCScrM; + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); always @(posedge clk) begin if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin - direction = dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcM ? "t" : "n"; + direction = PCSrcM ? "t" : "n"; $fwrite(file, "%h %s\n", dut.core.PCM, direction); end end From 6afd7f4fac3b43d2e43ae5c106b6d1ff39321a0d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:58:50 -0600 Subject: [PATCH 161/294] Fixed bug in the branch logger. --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 1c2fbb1f0..1acb8f6a4 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -485,7 +485,7 @@ logic [3:0] dummy; string direction; int file; logic PCScrM; - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); always @(posedge clk) begin From 5c83de4c463290cf919ea9aef8714f1abfb97194 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:59:59 -0600 Subject: [PATCH 162/294] Fixed another bug with the branch logger. --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 1acb8f6a4..8d974f0c0 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -485,7 +485,7 @@ logic [3:0] dummy; string direction; int file; logic PCScrM; - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); + flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); always @(posedge clk) begin From 49a7d10914309c6c2bff0599916ac5809b89b280 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 01:00:52 -0600 Subject: [PATCH 163/294] Fixed typo in testbench branch logger. --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 8d974f0c0..fd83c79b1 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -484,7 +484,7 @@ logic [3:0] dummy; if (`BPRED_LOGGER) begin string direction; int file; - logic PCScrM; + logic PCSrcM; flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); From f37bae1062bb559bfeb8c25328bc4218d79ec438 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:33:54 -0800 Subject: [PATCH 164/294] Converted rv32ic to rv32imc --- pipelined/config/rv32gc/wally-config.vh | 2 +- pipelined/config/{rv32ic => rv32imc}/wally-config.vh | 2 +- pipelined/regression/lint-wally | 2 +- pipelined/regression/regression-wally | 10 +++++----- pipelined/regression/wally-pipelined-batch.do | 4 ++-- synthDC/wallySynth.py | 6 +++--- 6 files changed, 13 insertions(+), 13 deletions(-) rename pipelined/config/{rv32ic => rv32imc}/wally-config.vh (98%) diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index ef98b0028..1be6b25b4 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -68,7 +68,7 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 `define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 0 +`define IDIV_ON_FPU 1 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32imc/wally-config.vh similarity index 98% rename from pipelined/config/rv32ic/wally-config.vh rename to pipelined/config/rv32imc/wally-config.vh index a80c00e38..5b03d2d58 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32imc/wally-config.vh @@ -37,7 +37,7 @@ // IEEE 754 compliance `define IEEE754 0 -`define MISA (32'h00000104 | 1 << 20 | 1 << 18 ) +`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 000b63402..4ff93af60 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do +for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do #for config in rv64gc; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 7398d7cec..f99906284 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -94,13 +94,13 @@ for test in tests32gc: grepstr="All tests ran without failures") configs.append(tc) -tests32icimperas = ["imperas32i", "imperas32c"] # unused -tests32ic = ["arch32i", "arch32c", "wally32periph"] -for test in tests32ic: +tests32imcimperas = ["imperas32i", "imperas32c"] # unused +tests32imc = ["arch32i", "arch32c", "arch32m", "wally32periph"] +for test in tests32imc: tc = TestCase( name=test, - variant="rv32ic", - cmd="vsim > {} -c < {} -c < -# Example: do wally-pipelined-batch.do rv32ic imperas-32i +# Example: do wally-pipelined-batch.do rv32imc imperas-32i # Use this wally-pipelined-batch.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: @@ -37,7 +37,7 @@ if {$2 eq "ahb"} { # because vsim will run vopt # default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined-batch.do ../config/rv32ic rv32ic +# do wally-pipelined-batch.do ../config/rv32imc rv32imc if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 6b10f2e8b..9ac3a995d 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -17,7 +17,7 @@ def mask(command): if __name__ == '__main__': techs = ['sky90', 'tsmc28'] - allConfigs = ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e', 'rv32i', 'rv64i'] + allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] pool = Pool() @@ -25,7 +25,7 @@ if __name__ == '__main__': parser = argparse.ArgumentParser() parser.add_argument("-s", "--freqsweep", type=int, help = "Synthesize wally with target frequencies at given MHz and +/- 2, 4, 6, 8 %%") - parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32ic, 64ic, 32gc, and 64gc") + parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32imc, 64ic, 32gc, and 64gc") parser.add_argument("-f", "--featuresweep", action='store_true', help = "Synthesize wally with features turned off progressively to visualize critical path") parser.add_argument("-v", "--version", choices=allConfigs, help = "Configuration of wally") @@ -47,7 +47,7 @@ if __name__ == '__main__': for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep runSynth(config, mod, tech, freq, maxopt) if args.configsweep: - for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs + for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs runSynth(config, mod, tech, freq, maxopt) if args.featuresweep: config = args.version if args.version else 'rv64gc' From d6b0a8f9a1444c5d4b6065196e1eb1a606305be7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:34:35 -0800 Subject: [PATCH 165/294] Removed unused wally-harvard.do script --- pipelined/regression/wally-harvard.do | 56 --------------------------- 1 file changed, 56 deletions(-) delete mode 100644 pipelined/regression/wally-harvard.do diff --git a/pipelined/regression/wally-harvard.do b/pipelined/regression/wally-harvard.do deleted file mode 100644 index e6050d2c7..000000000 --- a/pipelined/regression/wally-harvard.do +++ /dev/null @@ -1,56 +0,0 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -#switch $argc { -# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -#} -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-harvard.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -vopt +acc work.testbench -G TEST=$2 -o workopt -vsim workopt - -view wave --- display input and output signals as hexidecimal values -#do ./wave-dos/peripheral-waves.do -add log -recursive /* -do wave.do - --- Run the Simulation -#run 3600 -run -all -#quit -#noview ../testbench/testbench-imperas.sv -noview ../testbench/testbench.sv -view wave From a099cbb45bfd1a170514dbd420b06c6e4a008518 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:35:17 -0800 Subject: [PATCH 166/294] Fixed configuration of ram to use macro when depth is corret --- pipelined/src/generic/mem/ram1p1rwbe.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 47b3f1fe7..6ab6590fd 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -49,7 +49,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if (`USE_SRAM == 1 && WIDTH == 128 && `XLEN == 64) begin + if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 64) begin genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -59,7 +59,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if (`USE_SRAM == 1 && WIDTH == 44 && `XLEN == 64) begin + end else if (`USE_SRAM == 1 && WIDTH == 44 && DEPTH == 64) begin genvar index; // 64 x 44-bit SRAM logic [WIDTH-1:0] BitWriteMask; From 2a20d71a1279610608c29a266bfc39cbfc54ca43 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:40:08 -0800 Subject: [PATCH 167/294] Missing files related to rv32imc config --- .gitignore | 31 ------------------------------- synthDC/Makefile | 2 +- 2 files changed, 1 insertion(+), 32 deletions(-) diff --git a/.gitignore b/.gitignore index 609ef1487..3a8e8be91 100644 --- a/.gitignore +++ b/.gitignore @@ -81,37 +81,6 @@ synthDC/runArchive synthDC/hdl /pipelined/regression/power.saif tests/fp/vectors/*.tv -# Temporary configs produced for synthesis -pipelined/config/rv32e_FPUoff -pipelined/config/rv32e_PMP0 -pipelined/config/rv32e_PMP16 -pipelined/config/rv32e_noMulDiv -pipelined/config/rv32e_noPriv -pipelined/config/rv32e_orig -pipelined/config/rv32gc_FPUoff -pipelined/config/rv32gc_PMP0 -pipelined/config/rv32gc_PMP16 -pipelined/config/rv32gc_noMulDiv -pipelined/config/rv32gc_noPriv -pipelined/config/rv32gc_orig -pipelined/config/rv32ic_FPUoff -pipelined/config/rv32ic_PMP0 -pipelined/config/rv32ic_PMP16 -pipelined/config/rv32ic_noMulDiv -pipelined/config/rv32ic_noPriv -pipelined/config/rv32ic_orig -pipelined/config/rv64gc_FPUoff -pipelined/config/rv64gc_PMP0 -pipelined/config/rv64gc_PMP16 -pipelined/config/rv64gc_noMulDiv -pipelined/config/rv64gc_noPriv -pipelined/config/rv64gc_orig -pipelined/config/rv64ic_FPUoff -pipelined/config/rv64ic_PMP0 -pipelined/config/rv64ic_PMP16 -pipelined/config/rv64ic_noMulDiv -pipelined/config/rv64ic_noPriv -pipelined/config/rv64ic_orig synthDC/Summary.csv pipelined/srt/exptestgen pipelined/srt/testgen diff --git a/synthDC/Makefile b/synthDC/Makefile index 81d982251..8ad8b4389 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -45,7 +45,7 @@ default: @echo "Use wallySynth.py to run a concurrent sweep " -DIRS32 = rv32e rv32gc rv32ic rv32i +DIRS32 = rv32e rv32gc rv32imc rv32i DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) From 5fb3a669b15a52d84ea73ac4b2c21e740b064294 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 14:17:45 -0600 Subject: [PATCH 168/294] Updated benchmark parsing script. --- bin/parseHPMC.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 00dcb308c..35bb9c82e 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -45,7 +45,7 @@ def ComputeBranchTargetMissRate(benchmark): 'Computes and inserts branch target miss prediction rate.' # *** this is wrong in the verilog test bench (nameString, opt, dataDict) = benchmark - branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, ret']) + int(dataDict['ret'])) + branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, Jal']) + int(dataDict['ret'])) dataDict['BTMR'] = branchTargetMissRate def ComputeRASMissRate(benchmark): From 244885d3fab49b4e81ac04eb562812116c7fa345 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 15:03:25 -0600 Subject: [PATCH 169/294] Found bug in gshare. --- pipelined/config/rv32gc/wally-config.vh | 3 ++- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 9 +++------ pipelined/testbench/testbench.sv | 6 +++--- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 4d346e5a6..1a1bec35c 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -132,7 +132,8 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 639dbcd50..497d59876 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 0 +`define INSTR_CLASS_PRED 1 module bpred ( input logic clk, reset, diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 6cfb56894..c41282d59 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -51,16 +51,15 @@ module speculativegshare logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; - logic [k-1:0] GHRF, OldGHRF; + logic [k-1:0] GHRF; logic GHRExtraF; - logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; + logic [k-1:0] GHRD, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; logic [k-1:0] GHRNextD; logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; - logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -126,7 +125,7 @@ module speculativegshare // with instruction class prediction assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left + WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left GHRF[k-1:0]; flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); @@ -144,6 +143,4 @@ module speculativegshare assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); - endmodule diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index fd83c79b1..db36d9379 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -32,8 +32,8 @@ `include "wally-config.vh" `include "tests.vh" -`define PrintHPMCounters 1 -`define BPRED_LOGGER 1 +`define PrintHPMCounters 0 +`define BPRED_LOGGER 0 module testbench; parameter DEBUG=0; @@ -408,7 +408,7 @@ logic [3:0] dummy; end // always @ (negedge clk) - if(`PrintHPMCounters) begin + if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin integer HPMCindex; string HPMCnames[] = '{"Mcycle", "------", From 2a336cfb715faf5002e6da3c172b2a98f5e17a23 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 15:06:35 -0600 Subject: [PATCH 170/294] Gshare cleanup. --- pipelined/src/ifu/brpred/speculativegshare.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index c41282d59..e38561fb1 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -106,7 +106,7 @@ module speculativegshare // GHR pipeline // this version fails the regression test do to pessimistic x propagation. - // assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : + // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] : // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : // GHRF; From 7c8b2b685ff0f2d743f0fd845ca8b283c651b8cb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 15:07:45 -0600 Subject: [PATCH 171/294] gshare cleanup. --- pipelined/src/ifu/brpred/speculativegshare.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index e38561fb1..7f696c452 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -35,7 +35,6 @@ module speculativegshare input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, -// input logic [`XLEN-1:0] LookUpPC, output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update From db07c6618b18dbcc8ecaaded303175bdd3c9e534 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 14:19:24 -0800 Subject: [PATCH 172/294] Removed unused TESTSBP parameter --- pipelined/config/buildroot/wally-config.vh | 1 - pipelined/config/fpga/wally-config.vh | 1 - pipelined/config/rv32e/wally-config.vh | 1 - pipelined/config/rv32gc/wally-config.vh | 1 - pipelined/config/rv32i/wally-config.vh | 1 - pipelined/config/rv32imc/wally-config.vh | 1 - pipelined/config/rv64fpquad/wally-config.vh | 1 - pipelined/config/rv64gc/wally-config.vh | 1 - pipelined/config/rv64i/wally-config.vh | 1 - pipelined/src/wally/cvw.sv | 1 - 10 files changed, 10 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index f34874dc3..34056ea74 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -130,7 +130,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index d23ef9684..007f233f5 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -139,7 +139,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define TESTSBP 1 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 84082fdc8..8f779cb83 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -134,7 +134,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 1be6b25b4..9814a79ee 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -133,7 +133,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 1cc0c5b32..448f05aef 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -134,7 +134,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32imc/wally-config.vh b/pipelined/config/rv32imc/wally-config.vh index 5b03d2d58..db0e974ad 100644 --- a/pipelined/config/rv32imc/wally-config.vh +++ b/pipelined/config/rv32imc/wally-config.vh @@ -133,7 +133,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 649956fbe..528b8586d 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -136,7 +136,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 01b245b3d..d0877c075 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -138,7 +138,6 @@ //`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPRED_TYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 //`define BPRED_TYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index b4621d31d..0c78e774c 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -136,7 +136,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index 0a804c9a3..c4541b698 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -100,7 +100,6 @@ package cvw; parameter PLIC_UART_ID = `PLIC_UART_ID; parameter BPRED_SUPPORTED = `BPRED_SUPPORTED; parameter BPRED_TYPE = `BPRED_TYPE; - parameter TESTSBP = `TESTSBP; parameter BPRED_SIZE = `BPRED_SIZE; parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED; // parameter = `; From dd9d2be89cf3e670f3c4574cacd1bc7a867c6f0d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 16:26:44 -0600 Subject: [PATCH 173/294] Updated global history branch predictcor with the gshare improvements. --- pipelined/src/ifu/bpred/bpred.sv | 21 ++----- .../src/ifu/bpred/speculativeglobalhistory.sv | 61 +++++++++++-------- 2 files changed, 42 insertions(+), 40 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index bdb489245..cccbe29f0 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -85,41 +85,37 @@ module bpred ( logic [3:0] WrongPredInstrClassD; -//************ new resolve issues logic BTBTargetWrongE; logic RASTargetWrongE; logic JumpOrTakenBranchE; - - logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; - // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor - twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor - globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor - speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor - gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor - speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); @@ -139,7 +135,6 @@ module bpred ( -----/\----- EXCLUDED -----/\----- */ end - // this predictor will have two pieces of data, // 1) A direction (1 = Taken, 0 = Not Taken) // 2) Any information which is necessary for the predictor to build its next state. @@ -260,7 +255,6 @@ module bpred ( // branch class prediction wrong. assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; - // Selects the BP or PC+2/4. mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); // If the prediction is wrong select the correct address. @@ -292,8 +286,5 @@ module bpred ( flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); - - - endmodule diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv index 47203dbdd..3ed9ba3e5 100644 --- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// globalHistoryPredictor.sv +// speculativeglobalhistory.sv // // Written: Shreya Sanghai // Email: ssanghai@hmc.edu @@ -28,7 +28,7 @@ `include "wally-config.vh" -module speculativeglobalhistory #(parameter k = 10) ( +module speculativeglobalhistory #(parameter int k = 10 ) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -36,7 +36,6 @@ module speculativeglobalhistory #(parameter k = 10) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic [3:0] WrongPredInstrClassD, input logic PCSrcE @@ -49,14 +48,14 @@ module speculativeglobalhistory #(parameter k = 10) ( logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF; - logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k:-1] GHRNextD, OldGHRD; - logic [k:0] GHRNextE, GHRNextM, GHRNextW; + logic GHRExtraF; + logic [k-1:0] GHRD, GHRE, GHRM, GHRW; + logic [k-1:0] GHRNextF; + logic [k-1:0] GHRNextD; + logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; - logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -102,30 +101,42 @@ module speculativeglobalhistory #(parameter k = 10) ( satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline - assign GHRNextF = FlushD ? GHRNextD[k:1] : - BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - GHRF; + // this version fails the regression test do to pessimistic x propagation. + // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] : + // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : + // GHRF; - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - - assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; - flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); - assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left - OldGHRD[k:0]; + always_comb begin + if(FlushD | DirPredictionWrongE) begin + GHRNextF = GHRNextD[k-1:0]; + end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; + else GHRNextF = GHRF; + end - assign GHRNextE = FlushE ? GHRNextM : GHRD; - flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); - assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF); + + // use with out instruction class prediction + //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; + // with instruction class prediction + assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : + WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left + GHRF[k-1:0]; + + flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + + assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed + FlushE ? GHRNextM : // branch is flushed + GHRD; + flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); + flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); + flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); - endmodule From 327303e2e27f6b532a31aa4d8479cf7788ce1ca4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 15:55:37 -0800 Subject: [PATCH 174/294] Moved shared constants into per-processor config and removed wally-constants --- pipelined/config/buildroot/wally-config.vh | 13 ++ pipelined/config/fpga/wally-config.vh | 13 ++ pipelined/config/rv32e/wally-config.vh | 13 ++ pipelined/config/rv32gc/wally-config.vh | 13 ++ pipelined/config/rv32i/wally-config.vh | 13 ++ pipelined/config/rv32imc/wally-config.vh | 13 ++ pipelined/config/rv64fpquad/wally-config.vh | 13 ++ pipelined/config/rv64gc/wally-config.vh | 13 ++ pipelined/config/rv64i/wally-config.vh | 13 ++ pipelined/config/shared/wally-constants.vh | 148 -------------------- pipelined/config/shared/wally-shared.vh | 125 +++++++++++++++-- pipelined/testbench/testbench.sv | 2 +- 12 files changed, 231 insertions(+), 161 deletions(-) delete mode 100644 pipelined/config/shared/wally-constants.vh diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 34056ea74..783b9d91b 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -134,3 +134,16 @@ `define HPTW_WRITES_SUPPORTED 1 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 007f233f5..c4d9cf629 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -143,3 +143,16 @@ `define HPTW_WRITES_SUPPORTED 1 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 8f779cb83..24242b384 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -137,3 +137,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 69ea4b5b2..089a9ada4 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -136,3 +136,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 448f05aef..0a081b415 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -137,3 +137,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32imc/wally-config.vh b/pipelined/config/rv32imc/wally-config.vh index 727a50d57..b4293dcc6 100644 --- a/pipelined/config/rv32imc/wally-config.vh +++ b/pipelined/config/rv32imc/wally-config.vh @@ -136,3 +136,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 528b8586d..3757175a3 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -139,3 +139,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 818030f12..c3dd87295 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -139,3 +139,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 0c78e774c..90d7b4045 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -139,3 +139,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh deleted file mode 100644 index 0999fc207..000000000 --- a/pipelined/config/shared/wally-constants.vh +++ /dev/null @@ -1,148 +0,0 @@ -////////////////////////////////////////// -// wally-constants.vh -// -// Written: tfleming@hmc.edu 4 March 2021 -// Modified: Kmacsaigoren@hmc.edu 31 May 2021 -// Added constants for checking sv mode and changed existing constants to accomodate -// both sv48 and sv39 -// -// Purpose: Specify constants nexessary for different memory virtualization modes. -// These are specific to sv49, defined in section 4.5 of the privileged spec. -// However, despite different constants for different modes, the hardware helps distinguish between -// each mode. -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// constants defining different privilege modes -// defined in Table 1.1 of the privileged spec -`define M_MODE (2'b11) -`define S_MODE (2'b01) -`define U_MODE (2'b00) - -// Virtual Memory Constants -`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) -`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) -`define PPN_BITS (`XLEN==32 ? 22 : 44) -`define PA_BITS (`XLEN==32 ? 34 : 56) -`define SVMODE_BITS (`XLEN==32 ? 1 : 4) -`define ASID_BASE (`XLEN==32 ? 22 : 44) -`define ASID_BITS (`XLEN==32 ? 9 : 16) - -// constants to check SATP_MODE against -// defined in Table 4.3 of the privileged spec -`define NO_TRANSLATE 0 -`define SV32 1 -`define SV39 8 -`define SV48 9 - -// macros to define supported modes -`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) -`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA -`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) -`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) -`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) -`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) -`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) -`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) -`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) -`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) -`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) -// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 - -// logarithm of XLEN, used for number of index bits to select -`define LOG_XLEN (`XLEN == 32 ? 5 : 6) - -// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) -`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) - -// Floating point constants for Quad, Double, Single, and Half precisions -`define Q_LEN 32'd128 -`define Q_NE 32'd15 -`define Q_NF 32'd112 -`define Q_BIAS 32'd16383 -`define Q_FMT 2'd3 -`define D_LEN 32'd64 -`define D_NE 32'd11 -`define D_NF 32'd52 -`define D_BIAS 32'd1023 -`define D_FMT 2'd1 -`define S_LEN 32'd32 -`define S_NE 32'd8 -`define S_NF 32'd23 -`define S_BIAS 32'd127 -`define S_FMT 2'd0 -`define H_LEN 32'd16 -`define H_NE 32'd5 -`define H_NF 32'd10 -`define H_BIAS 32'd15 -`define H_FMT 2'd2 - -// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits -`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF) -`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS) -/* Delete once tested dh 10/10/22 - -`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/ - -// Floating point constants needed for FPU paramerterization -`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) -`define FMTBITS ((32)'(`FPSIZES>=3)+1) -`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) -`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) -`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) -`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) -`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) -`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) - -// largest length in IEU/FPU -`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF)) -`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN)) -`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1)) -`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6))) -`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ)) -`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4))) - -// division constants - -`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input -`define LOGR ($clog2(`RADIX)) // r = log(R) -`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc -`define LOGRK ($clog2(`RK)) // log2(r*k) -`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4)) -`define DURLEN ($clog2(`FPDUR+1)) -`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b) -`define DIVBLEN ($clog2(`DIVb+1)-1) -`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu - -// Disable spurious Verilator warnings - -/* verilator lint_off STMTDLY */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 4e43c7217..507388f7f 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -23,19 +23,120 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// +// constants defining different privilege modes +// defined in Table 1.1 of the privileged spec +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Virtual Memory Constants +`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) +`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) +`define PPN_BITS (`XLEN==32 ? 22 : 44) +`define PA_BITS (`XLEN==32 ? 34 : 56) +`define SVMODE_BITS (`XLEN==32 ? 1 : 4) +`define ASID_BASE (`XLEN==32 ? 22 : 44) +`define ASID_BITS (`XLEN==32 ? 9 : 16) + +// constants to check SATP_MODE against +// defined in Table 4.3 of the privileged spec +`define NO_TRANSLATE 0 +`define SV32 1 +`define SV39 8 +`define SV48 9 + +// macros to define supported modes +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 + +// logarithm of XLEN, used for number of index bits to select +`define LOG_XLEN (`XLEN == 32 ? 5 : 6) + +// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) +`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) + +// Floating point constants for Quad, Double, Single, and Half precisions +`define Q_LEN 32'd128 +`define Q_NE 32'd15 +`define Q_NF 32'd112 +`define Q_BIAS 32'd16383 +`define Q_FMT 2'd3 +`define D_LEN 32'd64 +`define D_NE 32'd11 +`define D_NF 32'd52 +`define D_BIAS 32'd1023 +`define D_FMT 2'd1 +`define S_LEN 32'd32 +`define S_NE 32'd8 +`define S_NF 32'd23 +`define S_BIAS 32'd127 +`define S_FMT 2'd0 +`define H_LEN 32'd16 +`define H_NE 32'd5 +`define H_NF 32'd10 +`define H_BIAS 32'd15 +`define H_FMT 2'd2 + +// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits +`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN) +`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0) +`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS) +/* Delete once tested dh 10/10/22 + +`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) +`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) +`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/ + +// Floating point constants needed for FPU paramerterization +`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) +`define FMTBITS ((32)'(`FPSIZES>=3)+1) +`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) +`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) +`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) +`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) +`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) + +// largest length in IEU/FPU +`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF)) +`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN)) +`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1)) +`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6))) +`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ)) +`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4))) + // division constants -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 -// eventually move to each config -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input +`define LOGR ($clog2(`RADIX)) // r = log(R) +`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc +`define LOGRK ($clog2(`RK)) // log2(r*k) +`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4)) +`define DURLEN ($clog2(`FPDUR+1)) +`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b) +`define DIVBLEN ($clog2(`DIVb+1)-1) +`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu -// Memory synthesis configuration -`define USE_SRAM 0 - -// shared constants -`include "wally-constants.vh" +// Disable spurious Verilator warnings +/* verilator lint_off STMTDLY */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 0696367da..325f9c00a 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -543,7 +543,7 @@ module riscvassertions; assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); + assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); From 4c75a90e39c90a932a7811f13da09c3a2b4c2743 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 17:19:53 -0800 Subject: [PATCH 175/294] Moved WALLY-status-fp-enabled tests from a to priv suites --- pipelined/testbench/tests.vh | 70 +++--------------------------------- 1 file changed, 4 insertions(+), 66 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index bbc82d9ad..1d094254e 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -94,47 +94,6 @@ string tvpaths[] = '{ "bd_sizeopt_speed/src/ud/ud", "bd_sizeopt_speed/src/wikisort/wikisort" }; - - // *** restore CSR tests from Imperas old - string extra64i[] = '{ - `MYIMPERASTEST, - "rv64i_m/I/WALLY-ADD", - "rv64i_m/I/WALLY-SUB", - "rv64i_m/I/WALLY-ADDI", - "rv64i_m/I/WALLY-ANDI", - "rv64i_m/I/WALLY-ORI", - "rv64i_m/I/WALLY-XORI", - "rv64i_m/I/WALLY-SLTI", - "rv64i_m/I/WALLY-SLTIU", - "rv64i_m/I/WALLY-SLLI", - "rv64i_m/I/WALLY-SRLI", - "rv64i_m/I/WALLY-SRAI", - "rv64i_m/I/WALLY-JAL", - "rv64i_m/I/WALLY-JALR", - "rv64i_m/I/WALLY-STORE", - "rv64i_m/I/WALLY-ADDIW", - "rv64i_m/I/WALLY-SLLIW", - "rv64i_m/I/WALLY-SRLIW", - "rv64i_m/I/WALLY-SRAIW", - "rv64i_m/I/WALLY-ADDW", - "rv64i_m/I/WALLY-SUBW", - "rv64i_m/I/WALLY-SLLW", - "rv64i_m/I/WALLY-SRLW", - "rv64i_m/I/WALLY-SRAW", - "rv64i_m/I/WALLY-BEQ", - "rv64i_m/I/WALLY-BNE", - "rv64i_m/I/WALLY-BLTU", - "rv64i_m/I/WALLY-BLT", - "rv64i_m/I/WALLY-BGE", - "rv64i_m/I/WALLY-BGEU", - "rv64i_m/I/WALLY-CSRRW", - "rv64i_m/I/WALLY-CSRRS", - "rv64i_m/I/WALLY-CSRRC", - "rv64i_m/I/WALLY-CSRRWI", - "rv64i_m/I/WALLY-CSRRSI", - "rv64i_m/I/WALLY-CSRRCI" - }; - string imperas32f[] = '{ `IMPERASTEST, @@ -875,40 +834,17 @@ string imperas32f[] = '{ "rv32i_m/I/XORI-01" }; - string imperas32p[] = '{ - `MYIMPERASTEST, - "rv32p/WALLY-MSTATUS", - "rv32p/WALLY-MCAUSE", - "rv32p/WALLY-SCAUSE", - "rv32p/WALLY-MEPC", - "rv32p/WALLY-SEPC", - "rv32p/WALLY-MTVAL", - "rv32p/WALLY-STVAL", - "rv32p/WALLY-MARCHID", - "rv32p/WALLY-MIMPID", - "rv32p/WALLY-MHARTID", - "rv32p/WALLY-MVENDORID", - "rv32p/WALLY-MTVEC", - "rv32p/WALLY-STVEC", - "rv32p/WALLY-MIE", - "rv32p/WALLY-MEDELEG", - "rv32p/WALLY-IP", - "rv32p/WALLY-CSR-PERMISSIONS-M", - "rv32p/WALLY-CSR-PERMISSIONS-S" - }; string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-amo-01.S", - "rv64i_m/privilege/src/WALLY-lrsc-01.S", - "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S" + "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; string wally32a[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-amo-01.S", - "rv32i_m/privilege/src/WALLY-lrsc-01.S", - "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S" + "rv32i_m/privilege/src/WALLY-lrsc-01.S" }; string arch64priv[] = '{ @@ -1825,6 +1761,7 @@ string imperas32f[] = '{ "rv64i_m/privilege/src/WALLY-status-sie-01.S", "rv64i_m/privilege/src/WALLY-status-tw-01.S", "rv64i_m/privilege/src/WALLY-status-tvm-01.S", + "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S", "rv64i_m/privilege/src/WALLY-stvec-01.S", "rv64i_m/privilege/src/WALLY-trap-01.S", "rv64i_m/privilege/src/WALLY-trap-s-01.S", @@ -1912,6 +1849,7 @@ string imperas32f[] = '{ "rv32i_m/privilege/src/WALLY-status-sie-01.S", "rv32i_m/privilege/src/WALLY-status-tw-01.S", "rv32i_m/privilege/src/WALLY-status-tvm-01.S", + "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S", "rv32i_m/privilege/src/WALLY-stvec-01.S", "rv32i_m/privilege/src/WALLY-trap-01.S", "rv32i_m/privilege/src/WALLY-trap-s-01.S", From 63267ff378e9291e421c3dedfd6c4942af9dd538 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 22:39:37 -0600 Subject: [PATCH 176/294] optimized branch predictor by removing unnecessary registers. --- pipelined/src/ifu/bpred/speculativegshare.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index e4d624382..62608f0bb 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -128,15 +128,15 @@ module speculativegshare #(parameter int k = 10 ) ( flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed - FlushE ? GHRNextM : // branch is flushed + FlushE ? GHRE : // branch is flushed GHRD; - flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); + flopenr #(k) GHREReg(clk, reset, (BranchInstrE & ~StallE) | FlushE, GHRNextE, GHRE); - assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); + //assign GHRNextM = FlushM ? GHRM : GHRE; + //flopenr #(k) GHRMReg(clk, reset, (BranchInstrM & ~StallM) | FlushM, GHRNextM, GHRM); - assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); + //assign GHRNextW = FlushW ? GHRW : GHRM; + //flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; From 7a4218788cea70779678c8c979dab64ab7bc2f00 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 30 Jan 2023 11:47:51 -0600 Subject: [PATCH 177/294] Imperas found a real bug in virtual memory. If the instruction address spilled across two pages and the second page misses the TLB, the HPTW received a tlb miss at the address of the first page rather than the second. After the walk the TLB was updated with the PTE from the first page at the address of the second page. Example bug Instruction PCF = 0x2ffe First page in 0x2ffe and second page in 0x3000. The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000. TLB is updated with PTE from 0x2ffe at 0x3000. --- pipelined/regression/wave.do | 541 +++++++++++---------- pipelined/src/ifu/ifu.sv | 8 +- pipelined/src/lsu/lsu.sv | 4 +- pipelined/src/mmu/hptw.sv | 4 +- pipelined/src/wally/wallypipelinedcore.sv | 6 +- pipelined/testbench/common/functionName.sv | 2 +- 6 files changed, 284 insertions(+), 281 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index a17bc502e..d3a9d332c 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -43,7 +43,6 @@ add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/core/PCF add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD add wave -noupdate -group PCS /testbench/dut/core/PCE add wave -noupdate -group PCS /testbench/dut/core/PCM @@ -177,199 +176,204 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk -add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCF -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt @@ -450,77 +454,78 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F -add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} -add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group ifu -expand -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} @@ -601,7 +606,6 @@ add wave -noupdate -expand -group {branch direction} -expand -group ghr /testben add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM @@ -624,10 +628,9 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {296884 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {1211181 ns} 1} {{Cursor 5} {158657 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -643,4 +646,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {18545889 ns} {18546113 ns} +WaveRestoreZoom {158482 ns} {158818 ns} diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 79f16c59a..c64049909 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -44,7 +44,7 @@ module ifu ( output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU - output logic [`XLEN-1:0] PCF, // Fetch stage instruction address + output logic [`XLEN-1:0] PCFSpill, // PCF with possible + 2 to handle spill to HPTW // Execute output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic PCSrcE, // Executation stage branch is taken @@ -97,19 +97,19 @@ module ifu ( logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed) logic [`XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed) logic [`XLEN-1:0] PCNextFSpill; // Next PCF after possible + 2 to handle spill - logic [`XLEN-1:0] PCFSpill; // PCF with possible + 2 to handle spill logic [`XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j) logic [`XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F logic [`XLEN-1:0] PCD; // Decode stage instruction address logic [`XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence - logic [`PA_BITS-1:0] PCPF; // Physical address after address translation + logic [`XLEN-1:0] PCF; // Fetch stage instruction address + logic [`PA_BITS-1:0] PCPF; // Physical address after address translation logic [`XLEN+1:0] PCFExt; // logic [31:0] IROMInstrF; // Instruction from the IROM logic [31:0] ICacheInstrF; // Instruction from the I$ logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus logic CompressedF; // The fetched instruction is compressed - logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill + logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage logic [1:0] IFURWF; // IFU alreays read IFURWF = 10 diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2eb8df1e5..9a8226a5e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -79,7 +79,7 @@ module lsu ( input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege input logic [1:0] STATUS_MPP, // Machine previous privilege mode - input logic [`XLEN-1:0] PCF, // Fetch PC + input logic [`XLEN-1:0] PCFSpill, // Fetch PC input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB @@ -152,7 +152,7 @@ module lsu ( if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, - .FlushW, .DCacheStallM, .SATP_REGW, .PCF, + .FlushW, .DCacheStallM, .SATP_REGW, .PCFSpill, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 9e8ac65ba..5cf58ffdf 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -34,7 +34,7 @@ module hptw ( input logic clk, reset, input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table - input logic [`XLEN-1:0] PCF, // addresses to translate + input logic [`XLEN-1:0] PCFSpill, // addresses to translate input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate input logic [1:0] MemRWM, AtomicM, // system status @@ -109,7 +109,7 @@ module hptw ( assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF); // Determine which address to translate - mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr); + mux2 #(`XLEN) vadrmux(PCFSpill, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr); assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index aae48f29d..7013d0309 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -62,7 +62,7 @@ module wallypipelinedcore ( logic [2:0] Funct3E; logic [31:0] InstrD; logic [31:0] InstrM; - logic [XLEN-1:0] PCF, PCE, PCLinkE; + logic [XLEN-1:0] PCFSpill, PCE, PCLinkE; logic [XLEN-1:0] PCM; logic [XLEN-1:0] CSRReadValW, MDUResultW; logic [XLEN-1:0] UnalignedPCNextF, PCNext2F; @@ -166,7 +166,7 @@ module wallypipelinedcore ( ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, // Fetch - .HRDATA, .PCF, .IFUHADDR, .PCNext2F, + .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, // Execute @@ -235,7 +235,7 @@ module wallypipelinedcore ( .StoreAmoMisalignedFaultM, // connects to privilege .StoreAmoAccessFaultM, // connects to privilege .InstrDAPageFaultF, - .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, + .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); if(BUS_SUPPORTED) begin : ebu diff --git a/pipelined/testbench/common/functionName.sv b/pipelined/testbench/common/functionName.sv index 45a11e8c5..f3cb656f5 100644 --- a/pipelined/testbench/common/functionName.sv +++ b/pipelined/testbench/common/functionName.sv @@ -48,7 +48,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile); logic StallD, StallE, FlushD, FlushE; integer ProgramAddrIndex, ProgramAddrIndexQ; - assign PCF = testbench.dut.core.PCF; + assign PCF = testbench.dut.core.ifu.PCF; assign StallD = testbench.dut.core.StallD; assign StallE = testbench.dut.core.StallE; assign FlushD = testbench.dut.core.FlushD; From fa473130860753669ef81545093235b41553104b Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Mon, 30 Jan 2023 10:54:19 -0800 Subject: [PATCH 178/294] Merged conflicts in fixing synthesis config/hdl writing (#40) * Fixed writing config files for synth sweeps * cleaned up comments * Fixed copying hdl subdirectories and referencing the correct config files for modified features * improved readability for synth scripts * cleans run directory post run and leaves copy of wally-config --- synthDC/Makefile | 49 +++++++++++++++++++++++++-------------- synthDC/scripts/synth.tcl | 11 ++++----- 2 files changed, 36 insertions(+), 24 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 81d982251..ec024984e 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -1,7 +1,7 @@ # # Makefile for synthesis # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 -# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 7/8/2022 +# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 NAME := synth # defaults @@ -24,18 +24,17 @@ export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 -configAsList := $(subst _, ,$(CONFIG)) -BASECONFIG := $(word 1, $(configAsList)) OLDCONFIGDIR ?= ${WALLY}/pipelined/config -CONFIGDIR ?= $(OUTPUTDIR)/hdl/config +export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) -# k = 3 6 print: @echo $(FREQS) + @echo $(CONFIG) @echo $(CONFIGFILESTRIM) @@ -45,30 +44,33 @@ default: @echo "Use wallySynth.py to run a concurrent sweep " +DIRS32 = rv32e rv32gc rv32ic rv32i +DIRS64 = rv64i rv64gc DIRS32 = rv32e rv32gc rv32ic rv32i DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) +# k = 3 6 # bpred: # @$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) # @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) -configs: $(BASECONFIG) -$(BASECONFIG): - @echo $(BASECONFIG) - cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig - sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh - sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh - sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +configs: $(CONFIG) +$(CONFIG): + @echo $(CONFIG) + cp -r $(OLDCONFIGDIR)/$(CONFIG) $(CONFIGDIR)/$(CONFIG)_orig + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh -ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),) - sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh -else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),) - sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +ifneq ($(filter $ $(CONFIG), $(DIRS32)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh +else ifneq ($(filter $ $(CONFIG), $(DIRS64)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh else - $(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64)) + $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) @echo "Config not in list, RAM_RANGE will be unmodified" endif @@ -97,22 +99,35 @@ ifeq ($(SAIFPOWER), 1) cp -f ../pipelined/regression/power.saif . endif +ifeq ($(SAIFPOWER), 1) + cp -f ../pipelined/regression/power.saif . +endif + freqs: @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) +mkdirecs: mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) @mkdir -p $(OUTPUTDIR)/hdl/config + @mkdir -p $(OUTPUTDIR)/hdl/config @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped synth: mkdirecs configs rundc clean +rundc: + +synth: mkdirecs configs rundc clean + rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out +clean: + rm -rf $(OUTPUTDIR)/hdl + clean: rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index b1342456c..1d7281fcb 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -16,22 +16,19 @@ suppress_message {VER-173} # Enable Multicore set_host_options -max_cores $::env(MAXCORES) -# get outputDir from environment (Makefile) +# get outputDir and configDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) -set cfgName $::env(CONFIG) -# Config +set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh set hdl_src "../pipelined/src" -set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) -eval file copy -force ${cfg} {$outputDir/hdl/} -#eval file copy -force ${cfg} $outputDir +eval file copy -force $cfg {$outputDir/hdl/} +eval file copy -force $cfg {$outputDir/} eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/} # Only for FMA class project; comment out when done # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} From 0c20ac010c8ec31094cc26ac0041ea4ff37c8918 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 30 Jan 2023 11:00:41 -0800 Subject: [PATCH 179/294] Updated Questa to 2022.4_2. --- setup.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/setup.sh b/setup.sh index 27ed893db..d54ae7bd4 100755 --- a/setup.sh +++ b/setup.sh @@ -13,9 +13,9 @@ echo \$WALLY set to ${WALLY} # License servers and commercial CAD tool paths # Must edit these based on your local environment. Ask your sysadmin. -export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server +export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server -export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa +export QUESTAPATH=/cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler # Path to RISC-V Tools From 49e45f45b7d97438902e5f1808a6128c57f16625 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 30 Jan 2023 12:48:52 -0800 Subject: [PATCH 180/294] Moved out version of wally using package because synthesis isn't working yet --- .../src/wally/wallypipelinedcore.sv => wallypipelinedcore.sv | 0 pipelined/src/wally/wallypipelinedsoc.sv => wallypipelinedsoc.sv | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/wally/wallypipelinedcore.sv => wallypipelinedcore.sv (100%) rename pipelined/src/wally/wallypipelinedsoc.sv => wallypipelinedsoc.sv (100%) diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/wallypipelinedcore.sv similarity index 100% rename from pipelined/src/wally/wallypipelinedcore.sv rename to wallypipelinedcore.sv diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/wallypipelinedsoc.sv similarity index 100% rename from pipelined/src/wally/wallypipelinedsoc.sv rename to wallypipelinedsoc.sv From 6777fd9b55994d0f4fa4c893d047a597a804ed19 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 30 Jan 2023 12:54:40 -0800 Subject: [PATCH 181/294] Restored top-level modules without import statements --- pipelined/src/wally/wallypipelinedcore.sv | 361 ++++++++++++++++++++++ pipelined/src/wally/wallypipelinedsoc.sv | 93 ++++++ 2 files changed, 454 insertions(+) create mode 100644 pipelined/src/wally/wallypipelinedcore.sv create mode 100644 pipelined/src/wally/wallypipelinedsoc.sv diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv new file mode 100644 index 000000000..2df96d1fb --- /dev/null +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -0,0 +1,361 @@ +/////////////////////////////////////////// +// wallypipelinedcore.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Pipelined RISC-V Processor +// +// Documentation: RISC-V System on Chip Design (Figure 4.1) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +//import cvw::*; // global CORE-V-Wally parameters +`include "wally-config.vh" + +module wallypipelinedcore ( + input logic clk, reset, + // Privileged + input logic MTimerInt, MExtInt, SExtInt, MSwInt, + input logic [63:0] MTIME_CLINT, + // Bus Interface + input logic [`AHBW-1:0] HRDATA, + input logic HREADY, HRESP, + output logic HCLK, HRESETn, + output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK +); + + logic StallF, StallD, StallE, StallM, StallW; + logic FlushD, FlushE, FlushM, FlushW; + logic RetM; + logic TrapM; + + // signals that must connect through DP + logic IntDivE, W64E; + logic CSRReadM, CSRWriteM, PrivilegedM; + logic [1:0] AtomicM; + logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; + logic [`XLEN-1:0] SrcAM; + logic [2:0] Funct3E; + logic [31:0] InstrD; + logic [31:0] InstrM; + logic [`XLEN-1:0] PCFSpill, PCE, PCLinkE; + logic [`XLEN-1:0] PCM; + logic [`XLEN-1:0] CSRReadValW, MDUResultW; + logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; + logic [1:0] MemRWM; + logic InstrValidM; + logic InstrMisalignedFaultM; + logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; + logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; + logic LoadMisalignedFaultM, LoadAccessFaultM; + logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; + logic InvalidateICacheM, FlushDCacheM; + logic PCSrcE; + logic CSRWriteFenceM; + logic DivBusyE; + logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; + logic SquashSCW; + + // floating point unit signals + logic [2:0] FRM_REGW; + logic [4:0] RdE, RdM, RdW; + logic FPUStallD; + logic FWriteIntE; + logic [`FLEN-1:0] FWriteDataM; + logic [`XLEN-1:0] FIntResM; + logic [`XLEN-1:0] FCvtIntResW; + logic FCvtIntW; + logic FDivBusyE; + logic IllegalFPUInstrM; + logic FRegWriteM; + logic FCvtIntStallD; + logic FpLoadStoreM; + logic [4:0] SetFflagsM; + logic [`XLEN-1:0] FIntDivResultW; + + // memory management unit signals + logic ITLBWriteF; + logic ITLBMissF; + logic [`XLEN-1:0] SATP_REGW; + logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; + logic [1:0] STATUS_MPP, STATUS_FS; + logic [1:0] PrivilegeModeW; + logic [`XLEN-1:0] PTE; + logic [1:0] PageType; + logic sfencevmaM, WFIStallM; + logic SelHPTW; + + // PMA checker signals + var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]; + var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; + + // IMem stalls + logic IFUStallF; + logic LSUStallM; + + // cpu lsu interface + logic [2:0] Funct3M; + logic [`XLEN-1:0] IEUAdrE; + logic [`XLEN-1:0] WriteDataM; + logic [`XLEN-1:0] IEUAdrM; + logic [`LLEN-1:0] ReadDataW; + logic CommittedM; + + // AHB ifu interface + logic [`PA_BITS-1:0] IFUHADDR; + logic [2:0] IFUHBURST; + logic [1:0] IFUHTRANS; + logic [2:0] IFUHSIZE; + logic IFUHWRITE; + logic IFUHREADY; + + // AHB LSU interface + logic [`PA_BITS-1:0] LSUHADDR; + logic [`XLEN-1:0] LSUHWDATA; + logic [`XLEN/8-1:0] LSUHWSTRB; + logic LSUHWRITE; + logic LSUHREADY; + + logic BPPredWrongE, BPPredWrongM; + logic DirPredictionWrongM; + logic BTBPredPCWrongM; + logic RASPredPCWrongM; + logic PredictionInstrClassWrongM; + logic [3:0] InstrClassM; + logic InstrAccessFaultF, HPTWInstrAccessFaultM; + logic [2:0] LSUHSIZE; + logic [2:0] LSUHBURST; + logic [1:0] LSUHTRANS; + + logic DCacheMiss; + logic DCacheAccess; + logic ICacheMiss; + logic ICacheAccess; + logic BreakpointFaultM, EcallFaultM; + logic InstrDAPageFaultF; + logic BigEndianM; + logic FCvtIntE; + logic CommittedF; + logic JumpOrTakenBranchM; + + // instruction fetch unit: PC, branch prediction, instruction cache + ifu ifu(.clk, .reset, + .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + // Fetch + .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, + .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, + .ICacheAccess, .ICacheMiss, + // Execute + .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM, + // Mem + .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, + .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, + .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, + // Faults out + .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, + // mmu management + .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, + .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF, + // pmp/pma (inside mmu) signals. + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); + + // integer execution unit: integer register file, datapath and controller + ieu ieu(.clk, .reset, + // Decode Stage interface + .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, + // Execute Stage interface + .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, + // Memory stage interface + .SquashSCW, // from LSU + .MemRWM, // read/write control goes to LSU + .AtomicM, // atomic control goes to LSU + .WriteDataM, // Write data to LSU + .Funct3M, // size and signedness to LSU + .SrcAM, // to privilege and fpu + .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, + // Writeback stage + .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), + .InstrValidM, .FCvtIntResW, .FCvtIntW, + // hazards + .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE, + .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD); + + lsu lsu( + .clk, .reset, .StallM, .FlushM, .StallW, .FlushW, + // CPU interface + .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM, + .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, + .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM, + .ReadDataW, .FlushDCacheM, + // connected to ahb (all stay the same) + .LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, + .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY, + // connect to csr or privilege and stay the same. + .PrivilegeModeW, .BigEndianM, // connects to csr + .PMPCFG_ARRAY_REGW, // connects to csr + .PMPADDR_ARRAY_REGW, // connects to csr + // hptw keep i/o + .SATP_REGW, // from csr + .STATUS_MXR, // from csr + .STATUS_SUM, // from csr + .STATUS_MPRV, // from csr + .STATUS_MPP, // from csr + .sfencevmaM, // connects to privilege + .LoadPageFaultM, // connects to privilege + .StoreAmoPageFaultM, // connects to privilege + .LoadMisalignedFaultM, // connects to privilege + .LoadAccessFaultM, // connects to privilege + .HPTWInstrAccessFaultM, // connects to privilege + .StoreAmoMisalignedFaultM, // connects to privilege + .StoreAmoAccessFaultM, // connects to privilege + .InstrDAPageFaultF, + .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, + .LSUStallM); + + if(`BUS_SUPPORTED) begin : ebu + ebu ebu(// IFU connections + .clk, .reset, + // IFU interface + .IFUHADDR, + .IFUHBURST, + .IFUHTRANS, + .IFUHREADY, + .IFUHSIZE, + // LSU interface + .LSUHADDR, + .LSUHWDATA, + .LSUHWSTRB, + .LSUHSIZE, + .LSUHBURST, + .LSUHTRANS, + .LSUHWRITE, + .LSUHREADY, + // BUS interface + .HREADY, .HRESP, .HCLK, .HRESETn, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, + .HPROT, .HTRANS, .HMASTLOCK); + end + + // global stall and flush control + hazard hzu( + .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM, + .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, + .LSUStallM, .IFUStallF, + .FCvtIntStallD, .FPUStallD, + .DivBusyE, .FDivBusyE, + .EcallFaultM, .BreakpointFaultM, + .WFIStallM, + // Stall & flush outputs + .StallF, .StallD, .StallE, .StallM, .StallW, + .FlushD, .FlushE, .FlushM, .FlushW); + + // privileged unit + if (`ZICSR_SUPPORTED) begin:priv + privileged priv( + .clk, .reset, + .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, + .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F, + .InstrM, .CSRReadValW, .UnalignedPCNextF, + .RetM, .TrapM, .sfencevmaM, + .InstrValidM, .CommittedM, .CommittedF, + .FRegWriteM, .LoadStallD, + .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM, + .RASPredPCWrongM, .PredictionInstrClassWrongM, + .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, + .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, + .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, + .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, + .MTimerInt, .MExtInt, .SExtInt, .MSwInt, + .MTIME_CLINT, .IEUAdrM, .SetFflagsM, + .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, + .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW, + .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, + .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM); + end else begin + assign CSRReadValW = 0; + assign UnalignedPCNextF = PCNext2F; + assign RetM = 0; + assign TrapM = 0; + assign WFIStallM = 0; + assign sfencevmaM = 0; + assign BigEndianM = 0; + end + + // multiply/divide unit + if (`M_SUPPORTED) begin:mdu + mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW, + .ForwardedSrcAE, .ForwardedSrcBE, + .Funct3E, .Funct3M, .IntDivE, .W64E, + .MDUResultW, .DivBusyE); + end else begin // no M instructions supported + assign MDUResultW = 0; + assign DivBusyE = 0; + end + + // floating point unit + if (`F_SUPPORTED) begin:fpu + fpu fpu( + .clk, .reset, + .FRM_REGW, // Rounding mode from CSR + .InstrD, // instruction from IFU + .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory + .ForwardedSrcAE, // Integer input being processed (from IEU) + .StallE, .StallM, .StallW, // stall signals from HZU + .FlushE, .FlushM, .FlushW, // flush signals from HZU + .RdE, .RdM, .RdW, // which FP register to write to (from IEU) + .STATUS_FS, // is floating-point enabled? + .FRegWriteM, // FP register write enable + .FpLoadStoreM, + .ForwardedSrcBE, // Integer input for intdiv + .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions + .FPUStallD, // Stall the decode stage + .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation + .FWriteDataM, // Data to be written to memory + .FIntResM, // data to be written to integer register + .FCvtIntResW, // fp -> int conversion result to be stored in int register + .FCvtIntW, // fpu result selection + .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) + .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction + .SetFflagsM, // FPU flags (to privileged unit) + .FIntDivResultW); + end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low + assign FPUStallD = 0; + assign FWriteIntE = 0; + assign FCvtIntE = 0; + assign FIntResM = 0; + assign FCvtIntW = 0; + assign FDivBusyE = 0; + assign IllegalFPUInstrM = 1; + assign SetFflagsM = 0; + assign FpLoadStoreM = 0; + end + +endmodule diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv new file mode 100644 index 000000000..e4c461571 --- /dev/null +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -0,0 +1,93 @@ +/////////////////////////////////////////// +// wally-pipelinedsoc.sv +// +// Written: David_Harris@hmc.edu 6 November 2020 +// Modified: +// +// Purpose: System on chip including pipelined processor and uncore memories/peripherals +// +// Documentation: RISC-V System on Chip Design (Figure 6.20) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +//import cvw::*; // global CORE-V-Wally parameters +`include "wally-config.vh" + +module wallypipelinedsoc ( + input logic clk, + input logic reset_ext, // external asynchronous reset pin + output logic reset, // reset synchronized to clk to prevent races on release + // AHB Interface + input logic [`AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + output logic HSELEXT, + // outputs to external memory, shared with uncore memory + output logic HCLK, HRESETn, + output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, + output logic HREADY, + // I/O Interface + input logic TIMECLK, // optional for CLINT MTIME counter + input logic [31:0] GPIOPinsIn, // inputs from GPIO + output logic [31:0] GPIOPinsOut, // output values for GPIO + output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic UARTSin, // UART serial data input + output logic UARTSout, // UART serial data output + input logic SDCCmdIn, // SDC Command input + output logic SDCCmdOut, // SDC Command output + output logic SDCCmdOE, // SDC Command output enable + input logic [3:0] SDCDatIn, // SDC data input + output logic SDCCLK // SDC clock +); + + // Uncore signals + logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore + logic HRESP; // response from AHB + logic MTimerInt, MSwInt; // timer and software interrupts from CLINT + logic [63:0] MTIME_CLINT; // from CLINT to CSRs + logic MExtInt,SExtInt; // from PLIC + + // synchronize reset to SOC clock domain + synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); + + // instantiate processor and internal memories + wallypipelinedcore core(.clk, .reset, + .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, + .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, + .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK + ); + + // instantiate uncore if a bus interface exists + if (`BUS_SUPPORTED) begin : uncore + uncore uncore(.HCLK, .HRESETn, .TIMECLK, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, + .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, + .UARTSout, .MTIME_CLINT, + .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); + end + +endmodule From 0e29a5f9c2ad644b7b81db25e5d11a8e9c77d180 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 30 Jan 2023 18:13:12 -0600 Subject: [PATCH 182/294] Minor gshare optimization. --- pipelined/src/ifu/bpred/speculativegshare.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 62608f0bb..f257d7537 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -109,7 +109,7 @@ module speculativegshare #(parameter int k = 10 ) ( always_comb begin if(FlushD | DirPredictionWrongE) begin - GHRNextF = GHRNextD[k-1:0]; + GHRNextF = GHRNextE[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; end From 57ab5a74889b56e1011c8b25ce1fd90bf80abc53 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 30 Jan 2023 19:27:18 -0600 Subject: [PATCH 183/294] Simplified gshare. --- pipelined/src/ifu/bpred/speculativegshare.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index f257d7537..fc497be7f 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -103,7 +103,7 @@ module speculativegshare #(parameter int k = 10 ) ( // GHR pipeline // this version fails the regression test do to pessimistic x propagation. - // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] : + // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextE[k-1:0] : // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : // GHRF; From 165b4858d79846d6b8278067b04aebf8bb3ce09b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 30 Jan 2023 23:37:34 -0600 Subject: [PATCH 184/294] Major cleanup of branch predictor. --- pipelined/src/ifu/bpred/speculativegshare.sv | 61 ++++++++------------ 1 file changed, 24 insertions(+), 37 deletions(-) diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index fc497be7f..5fc5b7122 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -48,17 +48,13 @@ module speculativegshare #(parameter int k = 10 ) ( logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; - logic [k-1:0] GHRF; - logic GHRExtraF; - logic [k-1:0] GHRD, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k-1:0] GHRNextD; - logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; - logic [k-1:0] IndexNextF, IndexF; - logic [k-1:0] IndexD, IndexE; - - + logic [k-1:0] GHRF, GHRD, GHRE; + logic GHRLastF; + logic [k-1:0] GHRNextF, GHRNextD, GHRNextE; + logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; + + logic FlushDOrDirWrong; assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; @@ -102,41 +98,32 @@ module speculativegshare #(parameter int k = 10 ) ( satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline - // this version fails the regression test do to pessimistic x propagation. - // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextE[k-1:0] : - // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - // GHRF; - always_comb begin - if(FlushD | DirPredictionWrongE) begin - GHRNextF = GHRNextE[k-1:0]; - end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; - else GHRNextF = GHRF; - end + // If Fetch has a branch, speculatively insert prediction into the GHR + // If the front end is flushed or the direction prediction is wrong, reset to + // most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in. + // For FlushE this is GHRE. GHRNextE is both. + assign FlushDOrDirWrong = FlushD | DirPredictionWrongE; + mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], + {FlushDOrDirWrong, BranchInstrF}, GHRNextF); + // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift. flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF); + flopenr #(1) GHRFLastReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRLastF); - // use with out instruction class prediction - //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; - // with instruction class prediction - assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : - WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left - GHRF[k-1:0]; + // With instruction class prediction, the class could be wrong and is checked in Decode. + // If it is wrong and branch does exist then shift right and insert the prediction. + // If the branch does not exist then shift left and use GHRLastF to restore the LSB. + logic [k-1:0] GHRClassWrong; + mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, BranchInstrD, GHRClassWrong); + // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. + mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed - FlushE ? GHRE : // branch is flushed - GHRD; + mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {BranchInstrE & ~FlushM, FlushE}, GHRNextE); + flopenr #(k) GHREReg(clk, reset, (BranchInstrE & ~StallE) | FlushE, GHRNextE, GHRE); - - //assign GHRNextM = FlushM ? GHRM : GHRE; - //flopenr #(k) GHRMReg(clk, reset, (BranchInstrM & ~StallM) | FlushM, GHRNextM, GHRM); - - //assign GHRNextW = FlushW ? GHRW : GHRM; - //flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; From 61759af9dc433caeab7700eb35136a7924c0bf38 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 30 Jan 2023 23:51:04 -0600 Subject: [PATCH 185/294] Improved signal names. --- pipelined/src/ifu/bpred/bpred.sv | 3 +- pipelined/src/ifu/bpred/speculativegshare.sv | 40 ++++++++++---------- 2 files changed, 21 insertions(+), 22 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index cccbe29f0..0f2b4bf6c 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -117,8 +117,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), - .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); + .InstrClassF(PredInstrClassF), .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor // *** Fix me diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 5fc5b7122..2d0c9b90e 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -29,17 +29,17 @@ `include "wally-config.vh" module speculativegshare #(parameter int k = 10 ) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, // update input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic [3:0] WrongPredInstrClassD, - input logic PCSrcE + input logic [3:0] InstrClassF, InstrClassD, InstrClassE, + input logic [3:0] WrongPredInstrClassD, + input logic PCSrcE ); logic MatchF, MatchD, MatchE; @@ -67,14 +67,14 @@ module speculativegshare #(parameter int k = 10 ) ( .rd1(TableDirPredictionF), .wa2(IndexE), .wd2(NewDirPredictionE), - .we2(BranchInstrE & ~StallM & ~FlushM), + .we2(InstrClassE[0]), .bwe2(1'b1)); // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage // and then register for use in the Fetch stage. - assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); - assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); - assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); + assign MatchF = InstrClassF[0] & ~FlushD & (IndexNextF == IndexF); + assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD); + assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE); assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); @@ -105,26 +105,26 @@ module speculativegshare #(parameter int k = 10 ) ( // For FlushE this is GHRE. GHRNextE is both. assign FlushDOrDirWrong = FlushD | DirPredictionWrongE; mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], - {FlushDOrDirWrong, BranchInstrF}, GHRNextF); + {FlushDOrDirWrong, InstrClassF[0]}, GHRNextF); // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift. - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - flopenr #(1) GHRFLastReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRLastF); + flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushD, GHRNextF, GHRF); + flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushD, GHRF[0], GHRLastF); // With instruction class prediction, the class could be wrong and is checked in Decode. // If it is wrong and branch does exist then shift right and insert the prediction. // If the branch does not exist then shift left and use GHRLastF to restore the LSB. logic [k-1:0] GHRClassWrong; - mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, BranchInstrD, GHRClassWrong); + mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong); // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {BranchInstrE & ~FlushM, FlushE}, GHRNextE); + mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); - flopenr #(k) GHREReg(clk, reset, (BranchInstrE & ~StallE) | FlushE, GHRNextE, GHRE); + flopenr #(k) GHREReg(clk, reset, (InstrClassE[0] & ~StallE) | FlushE, GHRNextE, GHRE); - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; + assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; endmodule From 22ef051603231b05dde8b526c2757e7b9f76d76d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 30 Jan 2023 23:55:52 -0600 Subject: [PATCH 186/294] More branch predictor cleanup. --- pipelined/src/ifu/bpred/bpred.sv | 18 ++++++++---------- pipelined/src/ifu/bpred/speculativegshare.sv | 6 +++--- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 0f2b4bf6c..048aa1125 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -117,7 +117,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, - .InstrClassF(PredInstrClassF), .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); + .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor // *** Fix me @@ -151,15 +151,6 @@ module bpred ( .IEUAdrE, .InstrClassE); - // Part 3 RAS - // *** need to add the logic to restore RAS on flushes. We will use incr for this. - // *** needs to include flushX - RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PredInstrClassF, .InstrClassD, .InstrClassE, - .WrongPredInstrClassD, .RASPCF, .PCLinkE); - - assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; - // the branch predictor needs a compact decoding of the instruction class. if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode logic [4:0] CompressedOpcF; @@ -196,12 +187,19 @@ module bpred ( (PredInstrClassF[1] & PredValidF) ; end + // Part 3 RAS + RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .PredInstrClassF, .InstrClassD, .InstrClassE, + .WrongPredInstrClassD, .RASPCF, .PCLinkE); + + assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch + flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW); diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 2d0c9b90e..09c1863b6 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -37,7 +37,7 @@ module speculativegshare #(parameter int k = 10 ) ( output logic DirPredictionWrongE, // update input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic [3:0] InstrClassF, InstrClassD, InstrClassE, + input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, input logic [3:0] WrongPredInstrClassD, input logic PCSrcE ); @@ -72,7 +72,7 @@ module speculativegshare #(parameter int k = 10 ) ( // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage // and then register for use in the Fetch stage. - assign MatchF = InstrClassF[0] & ~FlushD & (IndexNextF == IndexF); + assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF); assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD); assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE); assign MatchNextX = MatchF | MatchD | MatchE; @@ -105,7 +105,7 @@ module speculativegshare #(parameter int k = 10 ) ( // For FlushE this is GHRE. GHRNextE is both. assign FlushDOrDirWrong = FlushD | DirPredictionWrongE; mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], - {FlushDOrDirWrong, InstrClassF[0]}, GHRNextF); + {FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF); // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift. flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushD, GHRNextF, GHRF); From b64b3016e2ac742265bacfd70f71bdaaa47b7757 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 00:08:11 -0600 Subject: [PATCH 187/294] Parameterized testbench branch predictor preload. --- pipelined/src/ifu/bpred/speculativegshare.sv | 9 +++------ pipelined/testbench/testbench.sv | 2 +- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 09c1863b6..1c7ec6092 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -46,7 +46,7 @@ module speculativegshare #(parameter int k = 10 ) ( logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; + logic [1:0] NewDirPredictionE; logic [k-1:0] GHRF, GHRD, GHRE; logic GHRLastF; @@ -79,8 +79,8 @@ module speculativegshare #(parameter int k = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : - MatchD ? NewDirPredictionD : + assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} : + MatchD ? {2{DirPredictionD[1]}} : NewDirPredictionE ; flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); @@ -91,10 +91,7 @@ module speculativegshare #(parameter int k = 10 ) ( flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - // New prediction pipeline - assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]}; - flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 0696367da..0f25935f3 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -471,7 +471,7 @@ logic [3:0] dummy; genvar adrindex; // Initializing all zeroes into the branch predictor memory. - for(adrindex = 0; adrindex < 1024; adrindex++) begin + for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin initial begin force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; From 20e99dce7349219fd2e4ccf274edeee67186e584 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 00:11:01 -0600 Subject: [PATCH 188/294] Fixed parameterization in testbench. --- pipelined/testbench/testbench.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 0f25935f3..affb12128 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -471,13 +471,18 @@ logic [3:0] dummy; genvar adrindex; // Initializing all zeroes into the branch predictor memory. + for(adrindex = 0; adrindex < 2**10; adrindex++) begin + initial begin + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + #1; + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + end for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin initial begin force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; - force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; #1; release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; - release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; end end From b4854d8e94a9e899c9fa5c0b515789531b159c49 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 00:17:49 -0600 Subject: [PATCH 189/294] Found small bug in gshare. --- pipelined/src/ifu/bpred/speculativegshare.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 1c7ec6092..8ce431f6c 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -116,11 +116,11 @@ module speculativegshare #(parameter int k = 10 ) ( // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); - flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushD, GHRNextD, GHRD); mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); - flopenr #(k) GHREReg(clk, reset, (InstrClassE[0] & ~StallE) | FlushE, GHRNextE, GHRE); + flopenr #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; From a8f268e2a48214f4303dd3a9ccc6508390f6aa65 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 31 Jan 2023 04:37:23 -0800 Subject: [PATCH 190/294] Removed output delay in synthesis --- synthDC/scripts/synth.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 1d7281fcb..9fd86eccc 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -134,8 +134,8 @@ if {$tech == "sky130"} { # Set input/output delay if {$drive == "FLOP"} { - set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk - set_output_delay 0.1 -max -clock $my_clk [all_outputs] + set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk + set_output_delay 0.0 -max -clock $my_clk [all_outputs] } else { set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_output_delay 0.0 -max -clock $my_clk [all_outputs] From e7b91d5934c320ba8e3ad12c816bff3a401663ba Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 10:44:11 -0600 Subject: [PATCH 191/294] Renamed signals in RAS. --- pipelined/src/ifu/bpred/RAsPredictor.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/src/ifu/bpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RAsPredictor.sv index d345a5b0c..0c47aed99 100644 --- a/pipelined/src/ifu/bpred/RAsPredictor.sv +++ b/pipelined/src/ifu/bpred/RAsPredictor.sv @@ -42,7 +42,7 @@ module RASPredictor #(parameter int StackSize = 16 )( logic CounterEn; localparam Depth = $clog2(StackSize); - logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; + logic [Depth-1:0] NextPtr, CurrPtr, PtrP1, PtrM1; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; @@ -70,12 +70,12 @@ module RASPredictor #(parameter int StackSize = 16 )( assign CounterEn = PopF | PushE | RepairD; assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD; - mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD); + mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, NextPtr); - assign PtrM1 = PtrQ - 1'b1; - assign PtrP1 = PtrQ + 1'b1; + assign PtrM1 = CurrPtr - 1'b1; + assign PtrP1 = CurrPtr + 1'b1; - flopenr #(Depth) PTR(clk, reset, CounterEn, PtrD, PtrQ); + flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, CurrPtr); // RAS must be reset. always_ff @ (posedge clk) begin @@ -87,7 +87,7 @@ module RASPredictor #(parameter int StackSize = 16 )( end end - assign RASPCF = memory[PtrQ]; + assign RASPCF = memory[CurrPtr]; endmodule From 52bdf3257518e297b0804c8e08a562d10c1aa8c8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 10:45:32 -0600 Subject: [PATCH 192/294] Minor bug fix in gshare. --- pipelined/src/ifu/bpred/speculativegshare.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 8ce431f6c..23a49eac3 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -105,8 +105,8 @@ module speculativegshare #(parameter int k = 10 ) ( {FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF); // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift. - flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushD, GHRNextF, GHRF); - flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushD, GHRF[0], GHRLastF); + flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF); + flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF); // With instruction class prediction, the class could be wrong and is checked in Decode. // If it is wrong and branch does exist then shift right and insert the prediction. @@ -116,7 +116,7 @@ module speculativegshare #(parameter int k = 10 ) ( // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); - flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushD, GHRNextD, GHRD); + flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD); mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); From eededd1ba9502bc53c93cd4a4ce0492f4793e96c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 13:04:26 -0600 Subject: [PATCH 193/294] Fixed remaining bugs in the imperas merge. --- pipelined/testbench/common/wallyTracer.sv | 14 +++++++------- pipelined/testbench/testbench_imperas.sv | 20 ++++++++++---------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/pipelined/testbench/common/wallyTracer.sv b/pipelined/testbench/common/wallyTracer.sv index 23aaebd10..14b229685 100644 --- a/pipelined/testbench/common/wallyTracer.sv +++ b/pipelined/testbench/common/wallyTracer.sv @@ -98,20 +98,20 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; // supervisor CSRs - CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.SSTATUS_REGW; + CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; - CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.STVEC_REGW; - CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.SEPC_REGW; - CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.SCOUNTEREN_REGW; - CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.SATP_REGW; + CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; + CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; + CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; + CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // user CSRs CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; - CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.FRM_REGW; - CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; + CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; + CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; end else begin // hold the old value if the pipeline is stalled. CSRArray[12'h300] = CSRArrayOld[12'h300]; CSRArray[12'h310] = CSRArrayOld[12'h310]; diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv index c8f036b1c..65c92eb33 100644 --- a/pipelined/testbench/testbench_imperas.sv +++ b/pipelined/testbench/testbench_imperas.sv @@ -111,7 +111,7 @@ module testbench; $error("Must specify test directory using plusarg testDir"); end - if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); else $error("Imperas test bench requires BUS."); ProgramAddrMapFile = {testDir, "/ref/ref.elf.objdump.addr"}; @@ -231,7 +231,7 @@ module testbench; // Track names of instructions instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.FinalInstrRawF[31:0], + dut.core.ifu.InstrRawF[31:0], dut.core.ifu.InstrD, dut.core.ifu.InstrE, dut.core.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); @@ -339,17 +339,17 @@ module riscvassertions; assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); + assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACH_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); @@ -360,7 +360,7 @@ module riscvassertions; assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); @@ -383,7 +383,7 @@ module DCacheFlushFSM logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; - if(`DCACHE) begin + if(`DCACHE_SUPPORTED) begin localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; From bfbf5348300771c3a0f80f0ac36f057a680bc405 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 13:51:05 -0600 Subject: [PATCH 194/294] Created scripts to install imperas and run a single test using imperas. --- bin/imperas-one-time.sh | 54 ++++++++++++++++++++++++++++++++ pipelined/regression/sim-imperas | 32 +++++++++++++++++++ 2 files changed, 86 insertions(+) create mode 100755 bin/imperas-one-time.sh create mode 100755 pipelined/regression/sim-imperas diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh new file mode 100755 index 000000000..474bccea3 --- /dev/null +++ b/bin/imperas-one-time.sh @@ -0,0 +1,54 @@ +#!/bin/bash +########################################### +## imperas-one-time.sh +## +## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com) +## Created: 31 January 2023 +## Modified: 31 January 2023 +## +## Purpose: One time setup script for running imperas. +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https://solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + + +IMP_HASH=56b1479 + +# clone the Imperas repo +cd $WALY +if [ ! -d external ]; then + mkdir -p external +fi +pushd external + if [ ! -d ImperasDV-HMC ]; then + git clone git@github.com:Imperas/ImperasDV-HMC.git + fi + pushd ImperasDV-HMC + git checkout $IMP_HASH + popd +popd + +# Setup Imperas +source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh +setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas +export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC + +# setup QUESTA (Imperas only command, YMMV) +#svsetup -questa + + diff --git a/pipelined/regression/sim-imperas b/pipelined/regression/sim-imperas new file mode 100755 index 000000000..d696f18e5 --- /dev/null +++ b/pipelined/regression/sim-imperas @@ -0,0 +1,32 @@ +#!/bin/bash + +########################################### +## imperas-one-time.sh +## +## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com) +## Created: 31 January 2023 +## Modified: 31 January 2023 +## +## Purpose: Run wally with imperas +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https://solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ +IMPERAS_TOOLS=$(pwd)/imperas.ic \ +OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ +TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ +vsim -c -do "do wally-pipelined-imperas.do rv64gc" From 122809b2b27a21f4959f05dad3b4d3ee58819ab9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 14:35:05 -0600 Subject: [PATCH 195/294] RAS file name was spelled wrong. --- pipelined/src/ifu/bpred/{RAsPredictor.sv => RASPredictor.sv} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/ifu/bpred/{RAsPredictor.sv => RASPredictor.sv} (100%) diff --git a/pipelined/src/ifu/bpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RASPredictor.sv similarity index 100% rename from pipelined/src/ifu/bpred/RAsPredictor.sv rename to pipelined/src/ifu/bpred/RASPredictor.sv From dd556e8763da2d7c3961ed9c2ea977df16e94bfc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 14:54:05 -0600 Subject: [PATCH 196/294] Simplified RAS. --- pipelined/src/ifu/bpred/RASPredictor.sv | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/pipelined/src/ifu/bpred/RASPredictor.sv b/pipelined/src/ifu/bpred/RASPredictor.sv index 0c47aed99..6b2bdae4d 100644 --- a/pipelined/src/ifu/bpred/RASPredictor.sv +++ b/pipelined/src/ifu/bpred/RASPredictor.sv @@ -52,20 +52,21 @@ module RASPredictor #(parameter int StackSize = 16 )( logic IncrRepairD, DecRepairD; logic DecrementPtr; + logic FlushedRetDE; + logic WrongPredRetD; + assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - - assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) | // Wrong class undo increment or decrement. - (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed - (~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed - - assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed - (~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed - (WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not - - assign DecRepairD = (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret. - assign PushE = InstrClassE[3] & ~StallM & ~FlushM; + + assign WrongPredRetD = (WrongPredInstrClassD[2]) & ~StallE & ~FlushE; + assign FlushedRetDE = (~StallE & FlushE & InstrClassD[2]) | (~StallM & FlushM & InstrClassE[2]); + + assign RepairD = WrongPredRetD | FlushedRetDE ; + + assign IncrRepairD = FlushedRetDE | (WrongPredRetD & ~InstrClassD[2]); // Guessed it was a ret, but its not + + assign DecRepairD = WrongPredRetD & InstrClassD[2]; // Guessed non ret but is a ret. assign CounterEn = PopF | PushE | RepairD; From 7166fcd4d2fd9bd30c65543c753837cf54ca8bdd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 15:17:32 -0600 Subject: [PATCH 197/294] Updates to RAS. --- pipelined/src/ifu/bpred/RASPredictor.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/bpred/RASPredictor.sv b/pipelined/src/ifu/bpred/RASPredictor.sv index 6b2bdae4d..f71cb48f4 100644 --- a/pipelined/src/ifu/bpred/RASPredictor.sv +++ b/pipelined/src/ifu/bpred/RASPredictor.sv @@ -60,7 +60,7 @@ module RASPredictor #(parameter int StackSize = 16 )( assign PushE = InstrClassE[3] & ~StallM & ~FlushM; assign WrongPredRetD = (WrongPredInstrClassD[2]) & ~StallE & ~FlushE; - assign FlushedRetDE = (~StallE & FlushE & InstrClassD[2]) | (~StallM & FlushM & InstrClassE[2]); + assign FlushedRetDE = (~StallE & FlushE & InstrClassD[2]) | (~StallM & FlushM & InstrClassE[2]); // flushed ret assign RepairD = WrongPredRetD | FlushedRetDE ; From 625ca64474f0d5b618cfe511fdfc0c7c4bb031fa Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 31 Jan 2023 14:40:12 -0800 Subject: [PATCH 198/294] Removed student solution to fir --- examples/C/fir/fir.S | 35 ----------------------------------- 1 file changed, 35 deletions(-) delete mode 100644 examples/C/fir/fir.S diff --git a/examples/C/fir/fir.S b/examples/C/fir/fir.S deleted file mode 100644 index a96339ba7..000000000 --- a/examples/C/fir/fir.S +++ /dev/null @@ -1,35 +0,0 @@ -// fir.s -// mmasserfrye@hmc.edu 30 January 2022 -// FIR filter - -// a0 = N, a1 = M, a2 = &X, a3 = &c, a4 = &Y - -.global fir - -fir: - li t0, 0 # n = 0 = t0 - slli t6, a0, 3 # N*8 - slli t5, a1, 3 # M*8 - addi t4, t5, -8 # (M-1)*8 -for1: - bge t0, t6, end # exit outer for if n >= N - fmv.d.x f3, zero # sum = 0 = f3 - li t2, 0 # i = 0 = t2 - add t1, t4, t0 # [(M-1) + n]*8 -for2: - bge t2, t5, for1end # exit inner for if i >= M - sub t3, t1, t2 # [(M-1) + n - i]*8 - add t3, t3, a2 # t3 = offset + &X - fld f0, 0(t3) # X[n-i+(M-1)] - add t3, t2, a3 # t3 = offset + &c - fld f1, 0(t3) # c[i] - fmadd.d f3, f0, f1, f3 # sum += c[i]*X[n-i+(M-1)] - addi t2, t2, 8 # i++ - j for2 -for1end: - add t3, t0, a4 # t3 = offset + &Y - fsd f3, 0(t3) # Y[n] = sum - addi t0, t0, 8 # n++ - j for1 -end: - ret \ No newline at end of file From d5c1ac4e110f05274e61b6f81e96f0ff98d98985 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 22:03:51 -0600 Subject: [PATCH 199/294] Minor optimization to btb. --- pipelined/src/ifu/bpred/bpred.sv | 1 + pipelined/src/ifu/bpred/btb.sv | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 048aa1125..9889607a4 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -149,6 +149,7 @@ module bpred ( .PredValidF, .PredictionInstrClassWrongE, .IEUAdrE, + .InstrClassD, .InstrClassE); // the branch predictor needs a compact decoding of the instruction class. diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index 02c77fab9..dc32d9145 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -41,6 +41,7 @@ module btb #(parameter int Depth = 10 ) ( // update input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassD, // Instruction class to insert into btb input logic [3:0] InstrClassE // Instruction class to insert into btb ); @@ -71,7 +72,7 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex; + assign MatchF = PCNextFIndex == PCFIndex & PredValidF; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; @@ -79,7 +80,7 @@ module btb #(parameter int Depth = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {PredInstrClassD, PredPCD} : + MatchD ? {InstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); @@ -104,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); + flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); endmodule From d734f7af92cd0ba54560c56032b7edded9a0022e Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Wed, 1 Feb 2023 05:40:35 +0000 Subject: [PATCH 200/294] updated synth makefile to change all relevant ram ranges to 1FF --- synthDC/Makefile | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index ec024984e..0f791feae 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -66,9 +66,15 @@ $(CONFIG): sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh ifneq ($(filter $ $(CONFIG), $(DIRS32)),) - sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh else ifneq ($(filter $ $(CONFIG), $(DIRS64)),) - sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh else $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) @echo "Config not in list, RAM_RANGE will be unmodified" @@ -106,7 +112,6 @@ endif freqs: @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) -mkdirecs: mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) @@ -116,17 +121,12 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -synth: mkdirecs configs rundc clean - -rundc: synth: mkdirecs configs rundc clean rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out -clean: - rm -rf $(OUTPUTDIR)/hdl clean: rm -rf $(OUTPUTDIR)/hdl From a81d569e1a103b1a09da7c4170cecc2b424599a0 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Wed, 1 Feb 2023 05:51:31 +0000 Subject: [PATCH 201/294] increased bpred size to (2^) 5 --- synthDC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 0f791feae..0f64f0966 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -63,7 +63,7 @@ $(CONFIG): cp -r $(OLDCONFIGDIR)/$(CONFIG) $(CONFIGDIR)/$(CONFIG)_orig sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh ifneq ($(filter $ $(CONFIG), $(DIRS32)),) sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh From 57b35c293d609678af8e5e0a843d210dd2a8d47e Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Wed, 1 Feb 2023 06:08:27 +0000 Subject: [PATCH 202/294] added memories (not tested) --- pipelined/config/shared/wally-shared.vh | 2 +- pipelined/src/generic/mem/ram1p1rwbe.sv | 2 +- synthDC/.synopsys_dc.setup | 4 ++++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 4e43c7217..c8f1a667d 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -34,7 +34,7 @@ `define ZBS_SUPPORTED 0 // Memory synthesis configuration -`define USE_SRAM 0 +`define USE_SRAM 1 // shared constants `include "wally-constants.vh" diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 47b3f1fe7..0dffb2a70 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -55,7 +55,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index ddb62533e..8b0ba0309 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -48,6 +48,10 @@ set cache_read $cache_write lappend search_path ./scripts lappend search_path ./hdl lappend search_path ./mapped +set memory /home/jstine/WallyMem/rv64gc/ +lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db +lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db +lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db # Set up User Information set company "Oklahoma State University" From 6fb624950ec1da1f4cc83d8b943907583b6cd684 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 00:24:54 -0600 Subject: [PATCH 203/294] Minor change to btb. --- pipelined/src/ifu/bpred/btb.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index dc32d9145..7cf9ed993 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -50,12 +50,12 @@ module btb #(parameter int Depth = 10 ) ( logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; - logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; - logic TablePredValidF; + logic TablePredValidF, PredValidD; // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. @@ -72,20 +72,20 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex & PredValidF; + assign MatchF = PCNextFIndex == PCFIndex; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {InstrClassD, PredPCD} : - {InstrClassE, IEUAdrE} ; + assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} : + MatchD ? {PredValidD, InstrClassD, PredPCD} : + {1'b1, InstrClassE, IEUAdrE} ; - flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF}; always_ff @ (posedge clk) begin if (reset) begin @@ -96,7 +96,7 @@ module btb #(parameter int Depth = 10 ) ( if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex]; end - assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; + //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; @@ -105,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD}); endmodule From e820d1938ac7d21c8cbb7eddfc7e7c75c40c5fac Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 1 Feb 2023 05:06:56 -0800 Subject: [PATCH 204/294] Only add memory libraries when targeting 28nm --- synthDC/.synopsys_dc.setup | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 8b0ba0309..492256568 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -48,10 +48,12 @@ set cache_read $cache_write lappend search_path ./scripts lappend search_path ./hdl lappend search_path ./mapped -set memory /home/jstine/WallyMem/rv64gc/ -lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db -lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db -lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db +if {$tech="tsmc28"} {} + set memory /home/jstine/WallyMem/rv64gc/ + lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db + lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db + lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db +} # Set up User Information set company "Oklahoma State University" From 8601f0439766508dda9a2d137fd4bf599ef64e4a Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 1 Feb 2023 05:49:30 -0800 Subject: [PATCH 205/294] Fixed typo in DC setup for memories --- synthDC/.synopsys_dc.setup | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 492256568..2fdc11c27 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -48,7 +48,7 @@ set cache_read $cache_write lappend search_path ./scripts lappend search_path ./hdl lappend search_path ./mapped -if {$tech="tsmc28"} {} +if {$tech == "tsmc28"} { set memory /home/jstine/WallyMem/rv64gc/ lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db From 51a2a71410e5a069047f3bc2113c0f7e8dd0481d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:27:58 -0600 Subject: [PATCH 206/294] Removed unused signal. --- pipelined/src/ifu/bpred/bpred.sv | 2 +- pipelined/src/ifu/bpred/speculativegshare.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 9889607a4..c72e90148 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -116,7 +116,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 23a49eac3..1eb888a90 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -36,7 +36,7 @@ module speculativegshare #(parameter int k = 10 ) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, input logic [3:0] WrongPredInstrClassD, input logic PCSrcE From 3276353b8c466c03f9f7aac8bf61a822f47801e8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:59:38 -0600 Subject: [PATCH 207/294] Minor branch predictor bug fix. --- pipelined/src/ifu/bpred/bpred.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index c72e90148..664149652 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -180,12 +180,14 @@ module bpred ( assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | PredInstrClassF[2] | - (PredInstrClassF[1]) ; + PredInstrClassF[1] | + PredInstrClassF[3]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) ; + (PredInstrClassF[1] & PredValidF) | + (PredInstrClassF[3] & PredValidF); end // Part 3 RAS From fc5692629a9213f0af243eadb6d7cbed667f7657 Mon Sep 17 00:00:00 2001 From: James Stine Date: Wed, 1 Feb 2023 17:03:48 -0600 Subject: [PATCH 208/294] Update ram2 and other memories and associated wrappers --- pipelined/src/generic/mem/ram2p1r1wbe.sv | 92 +++++++++--- ...1wbe_1024x69.sv => ram2p1r1wbe_1024x68.sv} | 18 +-- .../src/generic/mem/ram2p1r1wbe_64x32.sv | 48 ++++++ pipelined/src/generic/mem/rom1p1r.sv | 137 +++++++++--------- pipelined/src/generic/mem/rom1p1r_128x32.sv | 2 +- pipelined/src/generic/mem/rom1p1r_128x64.sv | 37 +++++ 6 files changed, 234 insertions(+), 100 deletions(-) rename pipelined/src/generic/mem/{ram2p1r1wbe_1024x69.sv => ram2p1r1wbe_1024x68.sv} (83%) create mode 100755 pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv create mode 100755 pipelined/src/generic/mem/rom1p1r_128x64.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/pipelined/src/generic/mem/ram2p1r1wbe.sv index 49354075b..3c93ce868 100644 --- a/pipelined/src/generic/mem/ram2p1r1wbe.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe.sv @@ -5,7 +5,9 @@ // Two port SRAM 1 read port and 1 write port. // When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. -// Write +// Write +// Modified: james.stine@okstate.edu Feb 1, 2023 +// Integration of memories // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // @@ -42,31 +44,79 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( output logic [WIDTH-1:0] rd1 ); - logic [WIDTH-1:0] mem[DEPTH-1:0]; + logic [WIDTH-1:0] mem[DEPTH-1:0]; + localparam SRAMWIDTH = 32; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; // *************************************************************************** // TRUE Smem macro // *************************************************************************** - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** - integer i; + if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin + + ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); - // Read - always_ff @(posedge clk) - if(ce1) rd1 <= #1 mem[ra1]; - - // Write divided into part for bytes and part for extra msbs - if(WIDTH >= 8) - always @(posedge clk) - if (ce2 & we2) - for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; - - if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always @(posedge clk) - if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin + logic [SRAMWIDTH-1:0] SRAMReadData; + logic [SRAMWIDTH-1:0] SRAMWriteData; + logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; + logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; + logic [SRAMWIDTH-1:0] SRAMBitMask; + logic [$clog2(DEPTH)-1:0] RA1Q; + + + onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); + genvar index; + for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux + assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; + assign SRAMWriteData[index*2+1:index*2] = wd2; + assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; + end + flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); + assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; + ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .DA('0), + .DB(SRAMWriteData), + .BWEBA('0), .BWEBB(SRAMBitMask), + .QA(SRAMReadData), + .QB()); + + end else begin + + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** + integer i; + + // Read + always_ff @(posedge clk) + if(ce1) rd1 <= #1 mem[ra1]; + + // Write divided into part for bytes and part for extra msbs + if(WIDTH >= 8) + always @(posedge clk) + if (ce2 & we2) + for(i = 0; i < WIDTH/8; i++) + if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; + + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 + always @(posedge clk) + if (ce2 & we2 & bwe2[WIDTH/8]) + mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; + + end + endmodule diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv similarity index 83% rename from pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv rename to pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv index 4437c09bf..11eacd5ae 100755 --- a/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// ram2p1rwbe_1024x69.sv +// ram2p1rwbe_1024x68.sv // // Written: james.stine@okstate.edu 28 January 2023 // Modified: @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ram2p1r1wbe_1024x69( +module ram2p1r1wbe_1024x68( input logic CLKA, input logic CLKB, input logic CEBA, @@ -33,16 +33,16 @@ module ram2p1r1wbe_1024x69( input logic WEBB, input logic [9:0] AA, input logic [9:0] AB, - input logic [68:0] DA, - input logic [68:0] DB, - input logic [68:0] BWEBA, - input logic [68:0] BWEBB, - output logic [68:0] QA, - output logic [68:0] QB + input logic [67:0] DA, + input logic [67:0] DB, + input logic [67:0] BWEBA, + input logic [67:0] BWEBB, + output logic [67:0] QA, + output logic [67:0] QB ); // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor - generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv b/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv new file mode 100755 index 000000000..8bc19637d --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// ram2p1rwbe_64x32.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1r1wbe_64x32( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [5:0] AA, + input logic [5:0] AB, + input logic [31:0] DA, + input logic [31:0] DB, + input logic [31:0] BWEBA, + input logic [31:0] BWEBB, + output logic [31:0] QA, + output logic [31:0] QB +); + + // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor + generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 90bb87f9e..4669cadb8 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -27,74 +27,73 @@ `include "wally-config.vh" -module rom1p1r - #( - //-------------------------------------------------------------------------- - parameter ADDR_WIDTH = 8, - // Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth - parameter DATA_WIDTH = 32, // Data Width in bits - parameter PRELOAD_ENABLED = 0 - //---------------------------------------------------------------------- - ) ( - input logic clk, - input logic ce, - input logic [ADDR_WIDTH-1:0] addr, - output logic [DATA_WIDTH-1:0] dout - ); - // Core Memory - logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; +module rom1p1r #(parameter ADDR_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter PRELOAD_ENABLED = 0) + (input logic clk, + input logic ce, + input logic [ADDR_WIDTH-1:0] addr, + output logic [DATA_WIDTH-1:0] dout +); - always @ (posedge clk) begin - if(ce) dout <= ROM[addr]; - end + // Core Memory + logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; + if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin + rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); - // for FPGA, initialize with zero-stage bootloader - if(PRELOAD_ENABLED) begin - initial begin - ROM[0] = 64'h9581819300002197; - ROM[1] = 64'h4281420141014081; - ROM[2] = 64'h4481440143814301; - ROM[3] = 64'h4681460145814501; - ROM[4] = 64'h4881480147814701; - ROM[5] = 64'h4a814a0149814901; - ROM[6] = 64'h4c814c014b814b01; - ROM[7] = 64'h4e814e014d814d01; - ROM[8] = 64'h0110011b4f814f01; - ROM[9] = 64'h059b45011161016e; - ROM[10] = 64'h0004063705fe0010; - ROM[11] = 64'h05a000ef8006061b; - ROM[12] = 64'h0ff003930000100f; - ROM[13] = 64'h4e952e3110060e37; - ROM[14] = 64'hc602829b0053f2b7; - ROM[15] = 64'h2023fe02dfe312fd; - ROM[16] = 64'h829b0053f2b7007e; - ROM[17] = 64'hfe02dfe312fdc602; - ROM[18] = 64'h4de31efd000e2023; - ROM[19] = 64'h059bf1402573fdd0; - ROM[20] = 64'h0000061705e20870; - ROM[21] = 64'h0010029b01260613; - ROM[22] = 64'h11010002806702fe; - ROM[23] = 64'h84b2842ae426e822; - ROM[24] = 64'h892ee04aec064511; - ROM[25] = 64'h06e000ef07e000ef; - ROM[26] = 64'h979334fd02905563; - ROM[27] = 64'h07930177d4930204; - ROM[28] = 64'h4089093394be2004; - ROM[29] = 64'h04138522008905b3; - ROM[30] = 64'h19e3014000ef2004; - ROM[31] = 64'h64a2644260e2fe94; - ROM[32] = 64'h6749808261056902; - ROM[33] = 64'hdfed8b8510472783; - ROM[34] = 64'h2423479110a73823; - ROM[35] = 64'h10472783674910f7; - ROM[36] = 64'h20058693ffed8b89; - ROM[37] = 64'h05a1118737836749; - ROM[38] = 64'hfed59be3fef5bc23; - ROM[39] = 64'h1047278367498082; - ROM[40] = 64'h47858082dfed8b85; - ROM[41] = 64'h40a7853b4015551b; - ROM[42] = 64'h808210a7a02367c9; - end -end - -endmodule // bytewrite_tdp_ram_rf + end else begin + always @ (posedge clk) begin + if(ce) dout <= ROM[addr]; + end + + // for FPGA, initialize with zero-stage bootloader + if(PRELOAD_ENABLED) begin + initial begin + ROM[0] = 64'h9581819300002197; + ROM[1] = 64'h4281420141014081; + ROM[2] = 64'h4481440143814301; + ROM[3] = 64'h4681460145814501; + ROM[4] = 64'h4881480147814701; + ROM[5] = 64'h4a814a0149814901; + ROM[6] = 64'h4c814c014b814b01; + ROM[7] = 64'h4e814e014d814d01; + ROM[8] = 64'h0110011b4f814f01; + ROM[9] = 64'h059b45011161016e; + ROM[10] = 64'h0004063705fe0010; + ROM[11] = 64'h05a000ef8006061b; + ROM[12] = 64'h0ff003930000100f; + ROM[13] = 64'h4e952e3110060e37; + ROM[14] = 64'hc602829b0053f2b7; + ROM[15] = 64'h2023fe02dfe312fd; + ROM[16] = 64'h829b0053f2b7007e; + ROM[17] = 64'hfe02dfe312fdc602; + ROM[18] = 64'h4de31efd000e2023; + ROM[19] = 64'h059bf1402573fdd0; + ROM[20] = 64'h0000061705e20870; + ROM[21] = 64'h0010029b01260613; + ROM[22] = 64'h11010002806702fe; + ROM[23] = 64'h84b2842ae426e822; + ROM[24] = 64'h892ee04aec064511; + ROM[25] = 64'h06e000ef07e000ef; + ROM[26] = 64'h979334fd02905563; + ROM[27] = 64'h07930177d4930204; + ROM[28] = 64'h4089093394be2004; + ROM[29] = 64'h04138522008905b3; + ROM[30] = 64'h19e3014000ef2004; + ROM[31] = 64'h64a2644260e2fe94; + ROM[32] = 64'h6749808261056902; + ROM[33] = 64'hdfed8b8510472783; + ROM[34] = 64'h2423479110a73823; + ROM[35] = 64'h10472783674910f7; + ROM[36] = 64'h20058693ffed8b89; + ROM[37] = 64'h05a1118737836749; + ROM[38] = 64'hfed59be3fef5bc23; + ROM[39] = 64'h1047278367498082; + ROM[40] = 64'h47858082dfed8b85; + ROM[41] = 64'h40a7853b4015551b; + ROM[42] = 64'h808210a7a02367c9; + end + end + end + +endmodule diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/pipelined/src/generic/mem/rom1p1r_128x32.sv index 89d46b8f1..bc16a76dc 100755 --- a/pipelined/src/generic/mem/rom1p1r_128x32.sv +++ b/pipelined/src/generic/mem/rom1p1r_128x32.sv @@ -4,7 +4,7 @@ // Written: james.stine@okstate.edu 28 January 2023 // Modified: // -// Purpose: RAM wrapper for instantiating RAM IP +// Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/generic/mem/rom1p1r_128x64.sv b/pipelined/src/generic/mem/rom1p1r_128x64.sv new file mode 100755 index 000000000..14e83f5f5 --- /dev/null +++ b/pipelined/src/generic/mem/rom1p1r_128x64.sv @@ -0,0 +1,37 @@ +/////////////////////////////////////////// +// rom1p1r_128x64.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: ROM wrapper for instantiating ROM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rom1p1r_128x64( + input logic CLK, + input logic CEB, + input logic [6:0] A, + output logic [63:0] Q +); + + // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor + generic64x128ROM romIP (.CLK, .CEB, .A, .Q); + +endmodule From 0a540495f62ae178ff10ff199f0bad8c94090ac0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 1 Feb 2023 15:43:52 -0800 Subject: [PATCH 209/294] Removed O2 from fir Makefile to be consistent with lab. --- examples/C/fir/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile index c27e423a5..4e3991e46 100644 --- a/examples/C/fir/Makefile +++ b/examples/C/fir/Makefile @@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET) spike $(TARGET) $(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\ + riscv64-unknown-elf-gcc -o $(TARGET) -g\ -march=rv64gc -mabi=lp64d -mcmodel=medany \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ -T../common/test.ld -I../common \ From 3838ab232bd663e883e06fb73c253a4141741c8f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 2 Feb 2023 08:52:06 -0600 Subject: [PATCH 210/294] Fixed bug #47 discovered by Lee Moore. ECALL and EBREAK do not commit their results. --- pipelined/src/hazard/hazard.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 9dd3c0e4b..650e8367d 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -68,7 +68,7 @@ module hazard ( assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE; assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE)); assign FlushMCause = TrapM | RetM | CSRWriteFenceM; - assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM); + assign FlushWCause = TrapM; // Stall causes // Most data depenency stalls are identified in the decode stage From 9a5023a17e28fa26ec43326d46372fd598a6511d Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 2 Feb 2023 13:28:18 -0600 Subject: [PATCH 211/294] Modify generic/mem for rv32gc ram2 --- pipelined/src/generic/mem/ram2p1r1wbe.sv | 12 +++++ .../src/generic/mem/ram2p1r1wbe_1024x36.sv | 48 +++++++++++++++++++ .../src/generic/mem/ram2p1r1wbe_1024x68.sv | 2 +- pipelined/src/generic/mem/rom1p1r.sv | 5 +- 4 files changed, 65 insertions(+), 2 deletions(-) create mode 100755 pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/pipelined/src/generic/mem/ram2p1r1wbe.sv index 3c93ce868..08c232bba 100644 --- a/pipelined/src/generic/mem/ram2p1r1wbe.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe.sv @@ -64,6 +64,18 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); + end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + + ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin logic [SRAMWIDTH-1:0] SRAMReadData; diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv new file mode 100755 index 000000000..0aad7db4a --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// ram2p1rwbe_1024x36.sv +// +// Written: james.stine@okstate.edu 2 February 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1r1wbe_1024x36( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [9:0] AA, + input logic [9:0] AB, + input logic [35:0] DA, + input logic [35:0] DB, + input logic [35:0] BWEBA, + input logic [35:0] BWEBB, + output logic [35:0] QA, + output logic [35:0] QB +); + + // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor + generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv index 11eacd5ae..e6a6b6257 100755 --- a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -41,7 +41,7 @@ module ram2p1r1wbe_1024x68( output logic [67:0] QB ); - // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor + // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 4669cadb8..64cb9224b 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -38,9 +38,12 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // Core Memory logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; - if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin + if (`USE_SRAM == 1 && DATA_WIDTH == 64) begin rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); + end if (`USE_SRAM == 1 && DATA_WIDTH == 32) begin + rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); + end else begin always @ (posedge clk) begin if(ce) dout <= ROM[addr]; From 924e55325c33a12cc7e17a528b5150403bb31e60 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 2 Feb 2023 13:54:25 -0600 Subject: [PATCH 212/294] Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 --- pipelined/src/generic/mem/ram1p1rwbe.sv | 20 ++++++++++ pipelined/src/generic/mem/ram1p1rwbe_64x22.sv | 40 +++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100755 pipelined/src/generic/mem/ram1p1rwbe_64x22.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 028f928cd..e33e708a3 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -68,6 +68,26 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); + + end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin + genvar index; + // 64 x 128-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); + + end else if (`USE_SRAM == 1 && WIDTH == 22 && DEPTH == 32) begin + genvar index; + // 64 x 22-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); // *************************************************************************** // READ first SRAM model diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv new file mode 100755 index 000000000..84c8d1b75 --- /dev/null +++ b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// ram1p1rwbe_64x22.sv +// +// Written: james.stine@okstate.edu 2 Feburary 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram1p1rwbe_64x22( + input logic CLK, + input logic CEB, + input logic WEB, + input logic [5:0] A, + input logic [127:0] D, + input logic [127:0] BWEB, + output logic [127:0] Q +); + + // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor + generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + +endmodule From 3531afa5cfa46a566db93dd0a41bd61bb993329a Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 2 Feb 2023 12:59:28 -0800 Subject: [PATCH 213/294] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 12d7fe1f6..1fec92868 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ Wally is a 5-stage pipelined processor configurable to support all the standard ![Wally block diagram](wallyriscvTopAll.png) -Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. +Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. # New User Setup From 78eb90715c7819bd8b524c2197f67f5e3ccbe549 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 2 Feb 2023 14:14:11 -0800 Subject: [PATCH 214/294] Removed pipelined level of hierarchy --- .gitignore | 23 ++++++++----------- Install | 2 +- Makefile | 4 ++-- README.md | 2 +- benchmarks/coremark/Makefile | 2 +- benchmarks/embench/Makefile | 2 +- .../buildroot/wally-config.vh | 0 .../config => config}/fpga/wally-config.vh | 0 .../config => config}/rv32e/wally-config.vh | 0 .../config => config}/rv32gc/wally-config.vh | 0 .../config => config}/rv32i/wally-config.vh | 0 .../config => config}/rv32imc/wally-config.vh | 0 .../rv64fpquad/wally-config.vh | 0 .../config => config}/rv64gc/wally-config.vh | 0 .../config => config}/rv64i/wally-config.vh | 0 {pipelined/config => config}/shared/README | 0 .../config => config}/shared/wally-shared.vh | 0 fpga/README.md | 2 +- fpga/generator/Makefile | 2 +- fpga/generator/wally.tcl | 2 +- {pipelined/regression => regression}/Makefile | 0 .../buildrootBugFinder.py | 0 .../regression => regression}/fpga-wave.do | 0 .../regression => regression}/imperas.ic | 0 .../regression => regression}/lint-wally | 0 .../regression => regression}/linux-wave.do | 0 .../regression => regression}/make-tests.sh | 2 +- .../makefile-memfile | 0 .../regression-wally | 0 .../run-imperasdv-tests.bash | 0 .../regression => regression}/sim-buildroot | 0 .../sim-buildroot-batch | 0 .../regression => regression}/sim-imperas | 0 .../regression => regression}/sim-testfloat | 0 .../sim-testfloat-batch | 0 .../regression => regression}/sim-wally | 0 .../regression => regression}/sim-wally-batch | 0 .../slack-notifier/slack-notifier.py | 0 {pipelined/regression => regression}/test | 0 .../regression => regression}/testfloat.do | 0 .../wally-pipelined-batch.do | 0 .../wally-pipelined-imperas-no-idv.do | 0 .../wally-pipelined-imperas.do | 0 .../wally-pipelined.do | 0 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testbench}/testbench-linux.sv (100%) rename {pipelined/testbench => testbench}/testbench.sv (99%) rename {pipelined/testbench => testbench}/testbench_imperas.sv (100%) rename {pipelined/testbench => testbench}/tests-fp.vh (100%) rename {pipelined/testbench => testbench}/tests.vh (99%) diff --git a/.gitignore b/.gitignore index 1e651e68e..b389dd1dd 100644 --- a/.gitignore +++ b/.gitignore @@ -15,7 +15,7 @@ benchmarks/embench/wally*.json #vsim work files to ignore transcript vsim.wlf -pipelined/wlft* +wlft* wlft* /imperas-riscv-tests/FunctionRadix_32.addr /imperas-riscv-tests/FunctionRadix_64.addr @@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output tests/linux-testgen/buildroot-config-src/main.config.old tests/linux-testgen/buildroot-config-src/linux.config.old tests/linux-testgen/buildroot-config-src/busybox.config.old -pipelined/regression/slack-notifier/slack-webhook-url.txt -pipelined/regression/logs +regression/slack-notifier/slack-webhook-url.txt +regression/logs fpga/generator/IP fpga/generator/vivado.* fpga/generator/.Xil/* @@ -59,7 +59,7 @@ examples/C/sum/sum examples/C/fir/fir examples/fp/softfloat_demo/softfloat_demo examples/fp/fpcalc/fpcalc -pipelined/src/fma/fma16_testgen +src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh linux/testvector-generation/genCheckpoint.gdb @@ -79,29 +79,24 @@ synthDC/ppa/plots synthDC/wallyplots/ synthDC/runArchive synthDC/hdl -/pipelined/regression/power.saif +regression/power.saif tests/fp/vectors/*.tv synthDC/Summary.csv -pipelined/srt/exptestgen -pipelined/srt/testgen -pipelined/srt/qslc_r4a2 -pipelined/srt/qslc_r4a2.sv -pipelined/srt/testvectors -pipelined/regression/wkdir +regression/wkdir tests/custom/work tests/custom/*/*/*.list tests/custom/*/*/*.elf tests/custom/*/*/*.map tests/custom/*/*/*.memfile tests/custom/crt0/*.a -/pipelined/regression/sd_model.log +regression/sd_model.log fpga/src/sdc/* fpga/src/sdc.tar.gz fpga/src/CopiedFiles_do_not_add_to_repo/* -/pipelined/regression/branch.log +regression/branch.log /fpga/generator/sim/imp-funcsim.v /fpga/generator/sim/imp-timesim.sdf /fpga/generator/sim/imp-timesim.v /fpga/generator/sim/syn-funcsim.v external -pipelined/regression/results +regression/results diff --git a/Install b/Install index 7e509197d..46f4d78ec 100644 --- a/Install +++ b/Install @@ -328,6 +328,6 @@ source ./setup.sh # may require some modification for your system. Always cd make - cd pipelined/regression + cd regression ./regression-wally #(depends on having Questa installed) diff --git a/Makefile b/Makefile index b3a054e49..24ba57e57 100644 --- a/Makefile +++ b/Makefile @@ -15,8 +15,8 @@ install: ##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe regression: - make -C pipelined/regression + make -C regression clean: - make clean -C pipelined/regression + make clean -C regression diff --git a/README.md b/README.md index 12d7fe1f6..824c7c176 100644 --- a/README.md +++ b/README.md @@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se Run a regression simulation with Questa to prove everything is installed. - $ cd pipelined/regression + $ cd regression $ ./regression-wally (depends on having Questa installed) # Toolchain Installation (Sys Admin) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index 8c467d581..b8235ea94 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -21,7 +21,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: - (cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) + (cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) cd ../../benchmarks/coremark/ # KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test python3 coremark-postprocess.py diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 21c30cf6e..b5030d119 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed # launches modelsim to simulate tests on wally modelsim_run: - (cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") + (cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") cd ../../benchmarks/embench/ # builds the objdump based on the compiled c elf files diff --git a/pipelined/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh similarity index 100% rename from pipelined/config/buildroot/wally-config.vh rename to config/buildroot/wally-config.vh diff --git a/pipelined/config/fpga/wally-config.vh b/config/fpga/wally-config.vh similarity index 100% rename from pipelined/config/fpga/wally-config.vh rename to config/fpga/wally-config.vh diff --git a/pipelined/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh similarity index 100% rename from pipelined/config/rv32e/wally-config.vh rename to config/rv32e/wally-config.vh diff --git a/pipelined/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh similarity index 100% rename from pipelined/config/rv32gc/wally-config.vh rename to config/rv32gc/wally-config.vh diff --git a/pipelined/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh similarity index 100% rename from pipelined/config/rv32i/wally-config.vh rename to config/rv32i/wally-config.vh diff --git a/pipelined/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh similarity index 100% rename from pipelined/config/rv32imc/wally-config.vh rename to config/rv32imc/wally-config.vh diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh similarity index 100% rename from pipelined/config/rv64fpquad/wally-config.vh rename to config/rv64fpquad/wally-config.vh diff --git a/pipelined/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh similarity index 100% rename from pipelined/config/rv64gc/wally-config.vh rename to config/rv64gc/wally-config.vh diff --git a/pipelined/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh similarity index 100% rename from pipelined/config/rv64i/wally-config.vh rename to config/rv64i/wally-config.vh diff --git a/pipelined/config/shared/README b/config/shared/README similarity index 100% rename from pipelined/config/shared/README rename to config/shared/README diff --git a/pipelined/config/shared/wally-shared.vh b/config/shared/wally-shared.vh similarity index 100% rename from pipelined/config/shared/wally-shared.vh rename to config/shared/wally-shared.vh diff --git a/fpga/README.md b/fpga/README.md index 3f9853c72..dfa27479e 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -16,7 +16,7 @@ a large number of debuging signals. * Programming the flash card You'll need to write the linux image to the flash card. Use the convert2bin.py -script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt +script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt file from QEMU's preload to generate the binary. Then to copy sudo dd if=ram.bin of=. diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 3ab35b34b..1d07305fb 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -27,7 +27,7 @@ SDC: PreProcessFiles: rm -rf ../src/CopiedFiles_do_not_add_to_repo/ - cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/ + cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/ ./insert_debug_comment.sh $(dst)/%.log: %.tcl diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 45444d577..c93abed78 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -19,7 +19,7 @@ read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../s read_verilog {../src/fpgaTop.v} read_verilog -sv [glob -type f ../src/sdc/*.sv] -set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset] +set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset] add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc diff --git a/pipelined/regression/Makefile b/regression/Makefile similarity index 100% rename from pipelined/regression/Makefile rename to regression/Makefile diff --git a/pipelined/regression/buildrootBugFinder.py b/regression/buildrootBugFinder.py similarity index 100% rename from pipelined/regression/buildrootBugFinder.py rename to regression/buildrootBugFinder.py diff --git a/pipelined/regression/fpga-wave.do b/regression/fpga-wave.do similarity index 100% rename from pipelined/regression/fpga-wave.do rename to regression/fpga-wave.do diff --git a/pipelined/regression/imperas.ic b/regression/imperas.ic similarity index 100% rename from pipelined/regression/imperas.ic rename to regression/imperas.ic diff --git a/pipelined/regression/lint-wally b/regression/lint-wally similarity index 100% rename from pipelined/regression/lint-wally rename to regression/lint-wally diff --git a/pipelined/regression/linux-wave.do b/regression/linux-wave.do similarity index 100% rename from pipelined/regression/linux-wave.do rename to regression/linux-wave.do diff --git a/pipelined/regression/make-tests.sh b/regression/make-tests.sh similarity index 88% rename from pipelined/regression/make-tests.sh rename to regression/make-tests.sh index fe4555ff2..de7765086 100755 --- a/pipelined/regression/make-tests.sh +++ b/regression/make-tests.sh @@ -13,4 +13,4 @@ make # exe2memfile.pl work/*/*/*.elf # cd ../linux-testgen/linux-testvectors # ./tvLinker.sh -# cd ../../../pipelined/regression +# cd ../../../regression diff --git a/pipelined/regression/makefile-memfile b/regression/makefile-memfile similarity index 100% rename from pipelined/regression/makefile-memfile rename to regression/makefile-memfile diff --git a/pipelined/regression/regression-wally b/regression/regression-wally similarity index 100% rename from pipelined/regression/regression-wally rename to regression/regression-wally diff --git a/pipelined/regression/run-imperasdv-tests.bash b/regression/run-imperasdv-tests.bash similarity index 100% rename from pipelined/regression/run-imperasdv-tests.bash rename to regression/run-imperasdv-tests.bash diff --git a/pipelined/regression/sim-buildroot b/regression/sim-buildroot similarity index 100% rename from pipelined/regression/sim-buildroot rename to regression/sim-buildroot diff --git a/pipelined/regression/sim-buildroot-batch b/regression/sim-buildroot-batch similarity index 100% rename from pipelined/regression/sim-buildroot-batch rename to regression/sim-buildroot-batch diff --git a/pipelined/regression/sim-imperas b/regression/sim-imperas similarity index 100% rename from pipelined/regression/sim-imperas rename to regression/sim-imperas diff --git a/pipelined/regression/sim-testfloat b/regression/sim-testfloat similarity index 100% rename from pipelined/regression/sim-testfloat rename to regression/sim-testfloat diff --git a/pipelined/regression/sim-testfloat-batch b/regression/sim-testfloat-batch similarity index 100% rename from pipelined/regression/sim-testfloat-batch rename to regression/sim-testfloat-batch diff --git a/pipelined/regression/sim-wally b/regression/sim-wally similarity index 100% rename from pipelined/regression/sim-wally rename to regression/sim-wally diff --git a/pipelined/regression/sim-wally-batch b/regression/sim-wally-batch similarity index 100% rename from pipelined/regression/sim-wally-batch rename to regression/sim-wally-batch diff --git a/pipelined/regression/slack-notifier/slack-notifier.py b/regression/slack-notifier/slack-notifier.py similarity index 100% rename from pipelined/regression/slack-notifier/slack-notifier.py rename to regression/slack-notifier/slack-notifier.py diff --git a/pipelined/regression/test b/regression/test similarity index 100% rename from pipelined/regression/test rename to regression/test diff --git a/pipelined/regression/testfloat.do b/regression/testfloat.do similarity index 100% rename from pipelined/regression/testfloat.do rename to regression/testfloat.do diff --git a/pipelined/regression/wally-pipelined-batch.do b/regression/wally-pipelined-batch.do similarity index 100% rename from pipelined/regression/wally-pipelined-batch.do rename to regression/wally-pipelined-batch.do diff --git a/pipelined/regression/wally-pipelined-imperas-no-idv.do b/regression/wally-pipelined-imperas-no-idv.do similarity index 100% rename from pipelined/regression/wally-pipelined-imperas-no-idv.do rename to regression/wally-pipelined-imperas-no-idv.do diff --git a/pipelined/regression/wally-pipelined-imperas.do b/regression/wally-pipelined-imperas.do similarity index 100% rename from pipelined/regression/wally-pipelined-imperas.do rename to regression/wally-pipelined-imperas.do diff --git a/pipelined/regression/wally-pipelined.do b/regression/wally-pipelined.do similarity index 100% rename from pipelined/regression/wally-pipelined.do rename to regression/wally-pipelined.do diff --git a/pipelined/regression/wave-all.do b/regression/wave-all.do similarity index 100% rename from pipelined/regression/wave-all.do rename to regression/wave-all.do diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/regression/wave-dos/ahb-muldiv.do similarity index 100% rename from pipelined/regression/wave-dos/ahb-muldiv.do rename to regression/wave-dos/ahb-muldiv.do diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/regression/wave-dos/ahb-waves.do similarity index 100% rename from pipelined/regression/wave-dos/ahb-waves.do rename to regression/wave-dos/ahb-waves.do diff --git a/pipelined/regression/wave-dos/cache-waves.do b/regression/wave-dos/cache-waves.do similarity index 100% rename from pipelined/regression/wave-dos/cache-waves.do rename to regression/wave-dos/cache-waves.do diff --git a/pipelined/regression/wave-dos/default-waves.do b/regression/wave-dos/default-waves.do similarity index 100% rename from pipelined/regression/wave-dos/default-waves.do rename to regression/wave-dos/default-waves.do diff --git a/pipelined/regression/wave-dos/generic.do b/regression/wave-dos/generic.do similarity index 100% rename from pipelined/regression/wave-dos/generic.do rename to regression/wave-dos/generic.do diff --git a/pipelined/regression/wave-dos/linux-waves.do b/regression/wave-dos/linux-waves.do similarity index 100% rename from pipelined/regression/wave-dos/linux-waves.do rename to regression/wave-dos/linux-waves.do diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/regression/wave-dos/peripheral-waves.do similarity index 100% rename from pipelined/regression/wave-dos/peripheral-waves.do rename to regression/wave-dos/peripheral-waves.do diff --git a/pipelined/regression/wave-fpu.do b/regression/wave-fpu.do similarity index 100% rename from pipelined/regression/wave-fpu.do rename to regression/wave-fpu.do diff --git a/pipelined/regression/wave.do b/regression/wave.do similarity index 100% rename from pipelined/regression/wave.do rename to regression/wave.do diff --git a/setup.imperas.sh b/setup.imperas.sh index e3ac447bf..4e30fb07f 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC # setup QUESTA (Imperas only command, YMMV) svsetup -questa -pushd pipelined/regression +pushd regression # With IDV IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ diff --git a/pipelined/src/cache/cache.sv b/src/cache/cache.sv similarity index 100% rename from pipelined/src/cache/cache.sv rename to src/cache/cache.sv diff --git a/pipelined/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv similarity index 100% rename from pipelined/src/cache/cacheLRU.sv rename to src/cache/cacheLRU.sv diff --git a/pipelined/src/cache/cachefsm.sv b/src/cache/cachefsm.sv similarity index 100% rename from pipelined/src/cache/cachefsm.sv rename to src/cache/cachefsm.sv diff --git a/pipelined/src/cache/cacheway.sv b/src/cache/cacheway.sv similarity index 100% rename from pipelined/src/cache/cacheway.sv rename to src/cache/cacheway.sv diff --git a/pipelined/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv similarity index 100% rename from pipelined/src/cache/subcachelineread.sv rename to src/cache/subcachelineread.sv diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv similarity index 100% rename from pipelined/src/ebu/ahbcacheinterface.sv rename to src/ebu/ahbcacheinterface.sv diff --git a/pipelined/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv similarity index 100% rename from pipelined/src/ebu/ahbinterface.sv rename to src/ebu/ahbinterface.sv diff --git a/pipelined/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv similarity index 100% rename from pipelined/src/ebu/buscachefsm.sv rename to src/ebu/buscachefsm.sv diff --git a/pipelined/src/ebu/busfsm.sv b/src/ebu/busfsm.sv similarity index 100% rename from pipelined/src/ebu/busfsm.sv rename to src/ebu/busfsm.sv diff --git a/pipelined/src/ebu/controllerinputstage.sv b/src/ebu/controllerinputstage.sv similarity index 100% rename from pipelined/src/ebu/controllerinputstage.sv rename to src/ebu/controllerinputstage.sv diff --git a/pipelined/src/ebu/ebu.sv b/src/ebu/ebu.sv similarity index 100% rename from pipelined/src/ebu/ebu.sv rename to src/ebu/ebu.sv diff --git a/pipelined/src/ebu/ebuarbfsm.sv b/src/ebu/ebuarbfsm.sv similarity index 100% rename from pipelined/src/ebu/ebuarbfsm.sv rename to src/ebu/ebuarbfsm.sv diff --git a/pipelined/src/fpu/fclassify.sv b/src/fpu/fclassify.sv similarity index 100% rename from pipelined/src/fpu/fclassify.sv rename to src/fpu/fclassify.sv diff --git a/pipelined/src/fpu/fcmp.sv b/src/fpu/fcmp.sv similarity index 100% rename from pipelined/src/fpu/fcmp.sv rename to src/fpu/fcmp.sv diff --git a/pipelined/src/fpu/fctrl.sv b/src/fpu/fctrl.sv similarity index 100% rename from pipelined/src/fpu/fctrl.sv rename to src/fpu/fctrl.sv diff --git a/pipelined/src/fpu/fcvt.sv b/src/fpu/fcvt.sv similarity index 100% rename from pipelined/src/fpu/fcvt.sv rename to src/fpu/fcvt.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrt.sv rename to src/fpu/fdivsqrt/fdivsqrt.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv rename to src/fpu/fdivsqrt/fdivsqrtexpcalc.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv rename to src/fpu/fdivsqrt/fdivsqrtfgen2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv rename to src/fpu/fdivsqrt/fdivsqrtfgen4.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv rename to src/fpu/fdivsqrt/fdivsqrtfsm.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv rename to src/fpu/fdivsqrt/fdivsqrtiter.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv rename to src/fpu/fdivsqrt/fdivsqrtpostproc.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv rename to src/fpu/fdivsqrt/fdivsqrtpreproc.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv rename to src/fpu/fdivsqrt/fdivsqrtqsel2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv rename to src/fpu/fdivsqrt/fdivsqrtqsel4.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv rename to src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv rename to src/fpu/fdivsqrt/fdivsqrtstage2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv rename to src/fpu/fdivsqrt/fdivsqrtstage4.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv rename to src/fpu/fdivsqrt/fdivsqrtuotfc2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv rename to src/fpu/fdivsqrt/fdivsqrtuotfc4.sv diff --git a/pipelined/src/fpu/fhazard.sv b/src/fpu/fhazard.sv similarity index 100% rename from pipelined/src/fpu/fhazard.sv rename to src/fpu/fhazard.sv diff --git a/pipelined/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv similarity index 100% rename from pipelined/src/fpu/fma/fma.sv rename to src/fpu/fma/fma.sv diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv similarity index 100% rename from pipelined/src/fpu/fma/fmaadd.sv rename to src/fpu/fma/fmaadd.sv diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv similarity index 100% rename from pipelined/src/fpu/fma/fmaalign.sv rename to src/fpu/fma/fmaalign.sv diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv similarity index 100% rename from pipelined/src/fpu/fma/fmaexpadd.sv rename to src/fpu/fma/fmaexpadd.sv diff --git a/pipelined/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv similarity index 100% rename from pipelined/src/fpu/fma/fmalza.sv rename to src/fpu/fma/fmalza.sv diff --git a/pipelined/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv similarity index 100% rename from pipelined/src/fpu/fma/fmamult.sv rename to src/fpu/fma/fmamult.sv diff --git a/pipelined/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv similarity index 100% rename from pipelined/src/fpu/fma/fmasign.sv rename to src/fpu/fma/fmasign.sv diff --git a/pipelined/src/fpu/fpu.sv b/src/fpu/fpu.sv similarity index 100% rename from pipelined/src/fpu/fpu.sv rename to src/fpu/fpu.sv diff --git a/pipelined/src/fpu/fregfile.sv b/src/fpu/fregfile.sv similarity index 100% rename from pipelined/src/fpu/fregfile.sv rename to src/fpu/fregfile.sv diff --git a/pipelined/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv similarity index 100% rename from pipelined/src/fpu/fsgninj.sv rename to src/fpu/fsgninj.sv diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv similarity index 100% rename from pipelined/src/fpu/postproc/cvtshiftcalc.sv rename to src/fpu/postproc/cvtshiftcalc.sv diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv similarity index 100% rename from pipelined/src/fpu/postproc/divshiftcalc.sv rename to src/fpu/postproc/divshiftcalc.sv diff --git a/pipelined/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv similarity index 100% rename from pipelined/src/fpu/postproc/flags.sv rename to src/fpu/postproc/flags.sv diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv similarity index 100% rename from pipelined/src/fpu/postproc/fmashiftcalc.sv rename to src/fpu/postproc/fmashiftcalc.sv diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv similarity index 100% rename from pipelined/src/fpu/postproc/negateintres.sv rename to src/fpu/postproc/negateintres.sv diff --git a/pipelined/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv similarity index 100% rename from pipelined/src/fpu/postproc/normshift.sv rename to src/fpu/postproc/normshift.sv diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv similarity index 100% rename from pipelined/src/fpu/postproc/postprocess.sv rename to src/fpu/postproc/postprocess.sv diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv similarity index 100% rename from pipelined/src/fpu/postproc/resultsign.sv rename to src/fpu/postproc/resultsign.sv diff --git a/pipelined/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv similarity index 100% rename from pipelined/src/fpu/postproc/round.sv rename to src/fpu/postproc/round.sv diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv similarity index 100% rename from pipelined/src/fpu/postproc/roundsign.sv rename to src/fpu/postproc/roundsign.sv diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv similarity index 100% rename from pipelined/src/fpu/postproc/shiftcorrection.sv rename to src/fpu/postproc/shiftcorrection.sv diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv similarity index 100% rename from pipelined/src/fpu/postproc/specialcase.sv rename to src/fpu/postproc/specialcase.sv diff --git a/pipelined/src/fpu/unpack.sv b/src/fpu/unpack.sv similarity index 100% rename from pipelined/src/fpu/unpack.sv rename to src/fpu/unpack.sv diff --git a/pipelined/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv similarity index 100% rename from pipelined/src/fpu/unpackinput.sv rename to src/fpu/unpackinput.sv diff --git a/pipelined/src/generic/adder.sv b/src/generic/adder.sv similarity index 100% rename from pipelined/src/generic/adder.sv rename to src/generic/adder.sv diff --git a/pipelined/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv similarity index 100% rename from pipelined/src/generic/aplusbeq0.sv rename to src/generic/aplusbeq0.sv diff --git a/pipelined/src/generic/arrs.sv b/src/generic/arrs.sv similarity index 100% rename from pipelined/src/generic/arrs.sv rename to src/generic/arrs.sv diff --git a/pipelined/src/generic/binencoder.sv b/src/generic/binencoder.sv similarity index 100% rename from pipelined/src/generic/binencoder.sv rename to src/generic/binencoder.sv diff --git a/pipelined/src/generic/clockgater.sv b/src/generic/clockgater.sv similarity index 100% rename from pipelined/src/generic/clockgater.sv rename to src/generic/clockgater.sv diff --git a/pipelined/src/generic/counter.sv b/src/generic/counter.sv similarity index 100% rename from pipelined/src/generic/counter.sv rename to src/generic/counter.sv diff --git a/pipelined/src/generic/csa.sv b/src/generic/csa.sv similarity index 100% rename from pipelined/src/generic/csa.sv rename to src/generic/csa.sv diff --git a/pipelined/src/generic/decoder.sv b/src/generic/decoder.sv similarity index 100% rename from pipelined/src/generic/decoder.sv rename to src/generic/decoder.sv diff --git a/pipelined/src/generic/flop/flop.sv b/src/generic/flop/flop.sv similarity index 100% rename from pipelined/src/generic/flop/flop.sv rename to src/generic/flop/flop.sv diff --git a/pipelined/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv similarity index 100% rename from pipelined/src/generic/flop/flopen.sv rename to src/generic/flop/flopen.sv diff --git a/pipelined/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv similarity index 100% rename from pipelined/src/generic/flop/flopenl.sv rename to src/generic/flop/flopenl.sv diff --git a/pipelined/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv similarity index 100% rename from pipelined/src/generic/flop/flopenr.sv rename to src/generic/flop/flopenr.sv diff --git a/pipelined/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv similarity index 100% rename from pipelined/src/generic/flop/flopenrc.sv rename to src/generic/flop/flopenrc.sv diff --git a/pipelined/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv similarity index 100% rename from pipelined/src/generic/flop/flopens.sv rename to src/generic/flop/flopens.sv diff --git a/pipelined/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv similarity index 100% rename from pipelined/src/generic/flop/flopr.sv rename to src/generic/flop/flopr.sv diff --git a/pipelined/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv similarity index 100% rename from pipelined/src/generic/flop/floprc.sv rename to src/generic/flop/floprc.sv diff --git a/pipelined/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv similarity index 100% rename from pipelined/src/generic/flop/synchronizer.sv rename to src/generic/flop/synchronizer.sv diff --git a/pipelined/src/generic/lzc.sv b/src/generic/lzc.sv similarity index 100% rename from pipelined/src/generic/lzc.sv rename to src/generic/lzc.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv similarity index 100% rename from pipelined/src/generic/mem/ram1p1rwbe.sv rename to src/generic/mem/ram1p1rwbe.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv similarity index 100% rename from pipelined/src/generic/mem/ram1p1rwbe_64x128.sv rename to src/generic/mem/ram1p1rwbe_64x128.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv similarity index 100% rename from pipelined/src/generic/mem/ram1p1rwbe_64x44.sv rename to src/generic/mem/ram1p1rwbe_64x44.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv similarity index 100% rename from pipelined/src/generic/mem/ram2p1r1wbe.sv rename to src/generic/mem/ram2p1r1wbe.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv similarity index 100% rename from pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv rename to src/generic/mem/ram2p1r1wbe_1024x68.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv similarity index 100% rename from pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv rename to src/generic/mem/ram2p1r1wbe_64x32.sv diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv similarity index 100% rename from pipelined/src/generic/mem/rom1p1r.sv rename to src/generic/mem/rom1p1r.sv diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv similarity index 100% rename from pipelined/src/generic/mem/rom1p1r_128x32.sv rename to src/generic/mem/rom1p1r_128x32.sv diff --git a/pipelined/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv similarity index 100% rename from pipelined/src/generic/mem/rom1p1r_128x64.sv rename to src/generic/mem/rom1p1r_128x64.sv diff --git a/pipelined/src/generic/mux.sv b/src/generic/mux.sv similarity index 100% rename from pipelined/src/generic/mux.sv rename to src/generic/mux.sv diff --git a/pipelined/src/generic/neg.sv b/src/generic/neg.sv similarity index 100% rename from pipelined/src/generic/neg.sv rename to src/generic/neg.sv diff --git a/pipelined/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv similarity index 100% rename from pipelined/src/generic/onehotdecoder.sv rename to src/generic/onehotdecoder.sv diff --git a/pipelined/src/generic/or_rows.sv b/src/generic/or_rows.sv similarity index 100% rename from pipelined/src/generic/or_rows.sv rename to src/generic/or_rows.sv diff --git a/pipelined/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv similarity index 100% rename from pipelined/src/generic/priorityonehot.sv rename to src/generic/priorityonehot.sv diff --git a/pipelined/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv similarity index 100% rename from pipelined/src/generic/prioritythermometer.sv rename to src/generic/prioritythermometer.sv diff --git a/pipelined/src/hazard/hazard.sv b/src/hazard/hazard.sv similarity index 100% rename from pipelined/src/hazard/hazard.sv rename to src/hazard/hazard.sv diff --git a/pipelined/src/ieu/alu.sv b/src/ieu/alu.sv similarity index 100% rename from pipelined/src/ieu/alu.sv rename to src/ieu/alu.sv diff --git a/pipelined/src/ieu/comparator.sv b/src/ieu/comparator.sv similarity index 100% rename from pipelined/src/ieu/comparator.sv rename to src/ieu/comparator.sv diff --git a/pipelined/src/ieu/controller.sv b/src/ieu/controller.sv similarity index 100% rename from pipelined/src/ieu/controller.sv rename to src/ieu/controller.sv diff --git a/pipelined/src/ieu/datapath.sv b/src/ieu/datapath.sv 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a/pipelined/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv similarity index 100% rename from pipelined/src/ifu/bpred/gshare.sv rename to src/ifu/bpred/gshare.sv diff --git a/pipelined/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localHistoryPredictor.sv similarity index 100% rename from pipelined/src/ifu/bpred/localHistoryPredictor.sv rename to src/ifu/bpred/localHistoryPredictor.sv diff --git a/pipelined/src/ifu/bpred/optgshare.sv b/src/ifu/bpred/optgshare.sv similarity index 100% rename from pipelined/src/ifu/bpred/optgshare.sv rename to src/ifu/bpred/optgshare.sv diff --git a/pipelined/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv similarity index 100% rename from pipelined/src/ifu/bpred/satCounter2.sv rename to src/ifu/bpred/satCounter2.sv diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv similarity index 100% rename from pipelined/src/ifu/bpred/speculativeglobalhistory.sv rename to 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a/pipelined/src/lsu/subwordread.sv b/src/lsu/subwordread.sv similarity index 100% rename from pipelined/src/lsu/subwordread.sv rename to src/lsu/subwordread.sv diff --git a/pipelined/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv similarity index 100% rename from pipelined/src/lsu/subwordwrite.sv rename to src/lsu/subwordwrite.sv diff --git a/pipelined/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv similarity index 100% rename from pipelined/src/lsu/swbytemask.sv rename to src/lsu/swbytemask.sv diff --git a/pipelined/src/mdu/intdivrestoring.sv b/src/mdu/intdivrestoring.sv similarity index 100% rename from pipelined/src/mdu/intdivrestoring.sv rename to src/mdu/intdivrestoring.sv diff --git a/pipelined/src/mdu/intdivrestoringstep.sv b/src/mdu/intdivrestoringstep.sv similarity index 100% rename from pipelined/src/mdu/intdivrestoringstep.sv rename to src/mdu/intdivrestoringstep.sv diff --git a/pipelined/src/mdu/mdu.sv b/src/mdu/mdu.sv similarity index 100% rename from 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b/src/mmu/pmpadrdec.sv similarity index 100% rename from pipelined/src/mmu/pmpadrdec.sv rename to src/mmu/pmpadrdec.sv diff --git a/pipelined/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv similarity index 100% rename from pipelined/src/mmu/pmpchecker.sv rename to src/mmu/pmpchecker.sv diff --git a/pipelined/src/mmu/tlb.sv b/src/mmu/tlb.sv similarity index 100% rename from pipelined/src/mmu/tlb.sv rename to src/mmu/tlb.sv diff --git a/pipelined/src/mmu/tlbcam.sv b/src/mmu/tlbcam.sv similarity index 100% rename from pipelined/src/mmu/tlbcam.sv rename to src/mmu/tlbcam.sv diff --git a/pipelined/src/mmu/tlbcamline.sv b/src/mmu/tlbcamline.sv similarity index 100% rename from pipelined/src/mmu/tlbcamline.sv rename to src/mmu/tlbcamline.sv diff --git a/pipelined/src/mmu/tlbcontrol.sv b/src/mmu/tlbcontrol.sv similarity index 100% rename from pipelined/src/mmu/tlbcontrol.sv rename to src/mmu/tlbcontrol.sv diff --git a/pipelined/src/mmu/tlblru.sv b/src/mmu/tlblru.sv similarity index 100% rename from pipelined/src/mmu/tlblru.sv rename to src/mmu/tlblru.sv diff --git a/pipelined/src/mmu/tlbmixer.sv b/src/mmu/tlbmixer.sv similarity index 100% rename from pipelined/src/mmu/tlbmixer.sv rename to src/mmu/tlbmixer.sv diff --git a/pipelined/src/mmu/tlbram.sv b/src/mmu/tlbram.sv similarity index 100% rename from pipelined/src/mmu/tlbram.sv rename to src/mmu/tlbram.sv diff --git a/pipelined/src/mmu/tlbramline.sv b/src/mmu/tlbramline.sv similarity index 100% rename from pipelined/src/mmu/tlbramline.sv rename to src/mmu/tlbramline.sv diff --git a/pipelined/src/mmu/vm64check.sv b/src/mmu/vm64check.sv similarity index 100% rename from pipelined/src/mmu/vm64check.sv rename to src/mmu/vm64check.sv diff --git a/pipelined/src/privileged/csr.sv b/src/privileged/csr.sv similarity index 100% rename from pipelined/src/privileged/csr.sv rename to src/privileged/csr.sv diff --git a/pipelined/src/privileged/csrc.sv b/src/privileged/csrc.sv similarity index 100% rename from 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b/src/privileged/privdec.sv similarity index 100% rename from pipelined/src/privileged/privdec.sv rename to src/privileged/privdec.sv diff --git a/pipelined/src/privileged/privileged.sv b/src/privileged/privileged.sv similarity index 100% rename from pipelined/src/privileged/privileged.sv rename to src/privileged/privileged.sv diff --git a/pipelined/src/privileged/privmode.sv b/src/privileged/privmode.sv similarity index 100% rename from pipelined/src/privileged/privmode.sv rename to src/privileged/privmode.sv diff --git a/pipelined/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv similarity index 100% rename from pipelined/src/privileged/privpiperegs.sv rename to src/privileged/privpiperegs.sv diff --git a/pipelined/src/privileged/trap.sv b/src/privileged/trap.sv similarity index 100% rename from pipelined/src/privileged/trap.sv rename to src/privileged/trap.sv diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv similarity index 100% rename from pipelined/src/uncore/ahbapbbridge.sv rename to src/uncore/ahbapbbridge.sv diff --git a/pipelined/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv similarity index 100% rename from pipelined/src/uncore/clint_apb.sv rename to src/uncore/clint_apb.sv diff --git a/pipelined/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv similarity index 100% rename from pipelined/src/uncore/gpio_apb.sv rename to src/uncore/gpio_apb.sv diff --git a/pipelined/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv similarity index 100% rename from pipelined/src/uncore/plic_apb.sv rename to src/uncore/plic_apb.sv diff --git a/pipelined/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv similarity index 100% rename from pipelined/src/uncore/ram_ahb.sv rename to src/uncore/ram_ahb.sv diff --git a/pipelined/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv similarity index 100% rename from pipelined/src/uncore/rom_ahb.sv rename to src/uncore/rom_ahb.sv diff --git a/pipelined/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv similarity index 100% rename from pipelined/src/uncore/uartPC16550D.sv rename to src/uncore/uartPC16550D.sv diff --git a/pipelined/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv similarity index 100% rename from pipelined/src/uncore/uart_apb.sv rename to src/uncore/uart_apb.sv diff --git a/pipelined/src/uncore/uncore.sv b/src/uncore/uncore.sv similarity index 100% rename from pipelined/src/uncore/uncore.sv rename to src/uncore/uncore.sv diff --git a/pipelined/src/wally/cvw.sv b/src/wally/cvw.sv similarity index 100% rename from pipelined/src/wally/cvw.sv rename to src/wally/cvw.sv diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv similarity index 100% rename from pipelined/src/wally/wallypipelinedcore.sv rename to src/wally/wallypipelinedcore.sv diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv similarity index 100% rename from pipelined/src/wally/wallypipelinedsoc.sv rename to src/wally/wallypipelinedsoc.sv diff --git a/synthDC/Makefile b/synthDC/Makefile index 81d37e9d2..7ef295434 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -27,7 +27,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 -OLDCONFIGDIR ?= ${WALLY}/pipelined/config +OLDCONFIGDIR ?= ${WALLY}/config export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) @@ -102,11 +102,11 @@ endif sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh ifeq ($(SAIFPOWER), 1) - cp -f ../pipelined/regression/power.saif . + cp -f ../regression/power.saif . endif ifeq ($(SAIFPOWER), 1) - cp -f ../pipelined/regression/power.saif . + cp -f ../regression/power.saif . endif freqs: diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 9fd86eccc..29a0d3a35 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -19,7 +19,7 @@ set_host_options -max_cores $::env(MAXCORES) # get outputDir and configDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh -set hdl_src "../pipelined/src" +set hdl_src "../src" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) diff --git a/pipelined/testbench/common/functionName.sv b/testbench/common/functionName.sv similarity index 100% rename from pipelined/testbench/common/functionName.sv rename to testbench/common/functionName.sv diff --git a/pipelined/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv similarity index 100% rename from pipelined/testbench/common/instrNameDecTB.sv rename to testbench/common/instrNameDecTB.sv diff --git a/pipelined/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv similarity index 100% rename from pipelined/testbench/common/instrTrackerTB.sv rename to testbench/common/instrTrackerTB.sv diff --git a/pipelined/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv similarity index 100% rename from pipelined/testbench/common/wallyTracer.sv rename to testbench/common/wallyTracer.sv diff --git a/pipelined/testbench/fp/case.sh b/testbench/fp/case.sh similarity index 100% rename from pipelined/testbench/fp/case.sh rename to testbench/fp/case.sh diff --git a/pipelined/testbench/sdc/ram2sdLoad.py b/testbench/sdc/ram2sdLoad.py similarity index 100% rename from pipelined/testbench/sdc/ram2sdLoad.py rename to testbench/sdc/ram2sdLoad.py diff --git a/pipelined/testbench/sdc/ramdisk2.hex b/testbench/sdc/ramdisk2.hex similarity index 100% rename from pipelined/testbench/sdc/ramdisk2.hex rename to testbench/sdc/ramdisk2.hex diff --git a/pipelined/testbench/sdc/run_tb.do b/testbench/sdc/run_tb.do similarity index 100% rename from pipelined/testbench/sdc/run_tb.do rename to testbench/sdc/run_tb.do diff --git a/pipelined/testbench/sdc/sdModel.sv b/testbench/sdc/sdModel.sv similarity index 100% rename from pipelined/testbench/sdc/sdModel.sv rename to testbench/sdc/sdModel.sv diff --git a/pipelined/testbench/sdc/sd_crc_16.sv b/testbench/sdc/sd_crc_16.sv similarity index 100% rename from pipelined/testbench/sdc/sd_crc_16.sv rename to testbench/sdc/sd_crc_16.sv diff --git a/pipelined/testbench/sdc/sd_crc_7.sv b/testbench/sdc/sd_crc_7.sv similarity index 100% rename from pipelined/testbench/sdc/sd_crc_7.sv rename to testbench/sdc/sd_crc_7.sv diff --git a/pipelined/testbench/sdc/sd_defines.h b/testbench/sdc/sd_defines.h similarity index 100% rename from pipelined/testbench/sdc/sd_defines.h rename to testbench/sdc/sd_defines.h diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/testbench/sdc/sd_top_tb.sv similarity index 100% rename from pipelined/testbench/sdc/sd_top_tb.sv rename to testbench/sdc/sd_top_tb.sv diff --git a/pipelined/testbench/sdc/wave.do b/testbench/sdc/wave.do similarity index 100% rename from pipelined/testbench/sdc/wave.do rename to testbench/sdc/wave.do diff --git a/pipelined/testbench/testbench-fp.sv b/testbench/testbench-fp.sv similarity index 99% rename from pipelined/testbench/testbench-fp.sv rename to testbench/testbench-fp.sv index 62a739c40..8d6826b70 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -31,7 +31,7 @@ // steps to run FMA Tests // 1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh -// 2) go to riscv-wally/pipelined/testbench/fp/Tests +// 2) go to cvw/testbench/fp/Tests // 3) run ./sim-fma-batch module testbenchfp; parameter TEST="none"; diff --git a/pipelined/testbench/testbench-linux.sv b/testbench/testbench-linux.sv similarity index 100% rename from pipelined/testbench/testbench-linux.sv rename to testbench/testbench-linux.sv diff --git a/pipelined/testbench/testbench.sv b/testbench/testbench.sv similarity index 99% rename from pipelined/testbench/testbench.sv rename to testbench/testbench.sv index 853a6e001..a3fa2c093 100644 --- a/pipelined/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -238,7 +238,7 @@ logic [3:0] dummy; else memfilename = {pathname, tests[test], ".elf.memfile"}; if (`FPGA) begin string romfilename, sdcfilename; - romfilename = {"../../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; + romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); diff --git a/pipelined/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv similarity index 100% rename from pipelined/testbench/testbench_imperas.sv rename to testbench/testbench_imperas.sv diff --git a/pipelined/testbench/tests-fp.vh b/testbench/tests-fp.vh similarity index 100% rename from pipelined/testbench/tests-fp.vh rename to testbench/tests-fp.vh diff --git a/pipelined/testbench/tests.vh b/testbench/tests.vh similarity index 99% rename from pipelined/testbench/tests.vh rename to testbench/tests.vh index 1d094254e..f119b0a4e 100644 --- a/pipelined/testbench/tests.vh +++ b/testbench/tests.vh @@ -33,13 +33,13 @@ // *** remove MYIMPERASTEST cases when ported string tvpaths[] = '{ - "../../addins/imperas-riscv-tests/work/", - "../../tests/riscof/work/riscv-arch-test/", - "../../tests/riscof/work/wally-riscv-arch-test/", - "../../tests/imperas-riscv-tests/work/", - "../../benchmarks/coremark/work/", - "../../addins/embench-iot/", - "../../tests/custom/work/" + "../addins/imperas-riscv-tests/work/", + "../tests/riscof/work/riscv-arch-test/", + "../tests/riscof/work/wally-riscv-arch-test/", + "../tests/imperas-riscv-tests/work/", + "../benchmarks/coremark/work/", + "../addins/embench-iot/", + "../tests/custom/work/" }; string coremark[] = '{ diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh index 1fa3a9d01..414f4f2d5 100755 --- a/tests/testgen/privileged/run.sh +++ b/tests/testgen/privileged/run.sh @@ -11,7 +11,7 @@ printf "\n\n#####\nStarting tests for $1\n#####\n\n" if [[ "$2" != "-simonly" ]] then - cd $WALLY/pipelined/testgen/privileged + cd $WALLY/testgen/privileged python3 "testgen-$1.py" printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n" @@ -48,7 +48,7 @@ fi if [[ "$2" == "-sim" || "$2" == "-simonly" ]] then printf "\n\n\n#####\nSimulating!\n#####\n\n" - cd $WALLY/pipelined/regression + cd $WALLY/regression vsim -do wally-privileged.do -c fi From 80f42a8638a104955c0fe826ab16b0a3ea4616c2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 2 Feb 2023 14:48:23 -0800 Subject: [PATCH 215/294] Renamed regression to sim --- .gitignore | 14 +++++++------- Install | 2 +- Makefile | 4 ++-- README.md | 2 +- benchmarks/coremark/Makefile | 4 ++-- benchmarks/embench/Makefile | 2 +- setup.imperas.sh | 2 +- {regression => sim}/Makefile | 18 +++++++++--------- {regression => sim}/buildrootBugFinder.py | 0 {regression => sim}/fpga-wave.do | 0 {regression => sim}/imperas.ic | 0 {regression => sim}/lint-wally | 0 {regression => sim}/linux-wave.do | 0 {regression => sim}/make-tests.sh | 0 {regression => sim}/makefile-memfile | 2 +- {regression => sim}/regression-wally | 0 {regression => sim}/run-imperasdv-tests.bash | 0 {regression => sim}/sim-buildroot | 0 {regression => sim}/sim-buildroot-batch | 0 {regression => sim}/sim-imperas | 0 {regression => sim}/sim-testfloat | 0 {regression => sim}/sim-testfloat-batch | 0 {regression => sim}/sim-wally | 0 {regression => sim}/sim-wally-batch | 0 .../slack-notifier/slack-notifier.py | 0 {regression => sim}/test | 0 {regression => sim}/testfloat.do | 0 {regression => sim}/wally-pipelined-batch.do | 0 .../wally-pipelined-imperas-no-idv.do | 0 {regression => sim}/wally-pipelined-imperas.do | 0 {regression => sim}/wally-pipelined.do | 0 {regression => sim}/wave-all.do | 0 {regression => sim}/wave-dos/ahb-muldiv.do | 0 {regression => sim}/wave-dos/ahb-waves.do | 0 {regression => sim}/wave-dos/cache-waves.do | 0 {regression => sim}/wave-dos/default-waves.do | 0 {regression => sim}/wave-dos/generic.do | 0 {regression => sim}/wave-dos/linux-waves.do | 0 .../wave-dos/peripheral-waves.do | 0 {regression => sim}/wave-fpu.do | 0 {regression => sim}/wave.do | 0 synthDC/Makefile | 4 ++-- tests/testgen/privileged/run.sh | 2 +- 43 files changed, 28 insertions(+), 28 deletions(-) rename {regression => sim}/Makefile (62%) rename {regression => sim}/buildrootBugFinder.py (100%) rename {regression => sim}/fpga-wave.do (100%) rename {regression => sim}/imperas.ic (100%) rename {regression => sim}/lint-wally (100%) rename {regression => sim}/linux-wave.do (100%) rename {regression => sim}/make-tests.sh (100%) rename {regression => sim}/makefile-memfile (99%) rename {regression => sim}/regression-wally (100%) rename {regression => sim}/run-imperasdv-tests.bash (100%) rename {regression => sim}/sim-buildroot (100%) rename {regression => sim}/sim-buildroot-batch (100%) rename {regression => sim}/sim-imperas (100%) rename {regression => sim}/sim-testfloat (100%) rename {regression => sim}/sim-testfloat-batch (100%) rename {regression => sim}/sim-wally (100%) rename {regression => sim}/sim-wally-batch (100%) rename {regression => sim}/slack-notifier/slack-notifier.py (100%) rename {regression => sim}/test (100%) rename {regression => sim}/testfloat.do (100%) rename {regression => sim}/wally-pipelined-batch.do (100%) rename {regression => sim}/wally-pipelined-imperas-no-idv.do (100%) rename {regression => sim}/wally-pipelined-imperas.do (100%) rename {regression => sim}/wally-pipelined.do (100%) rename {regression => sim}/wave-all.do (100%) rename {regression => sim}/wave-dos/ahb-muldiv.do (100%) rename {regression => sim}/wave-dos/ahb-waves.do (100%) rename {regression => sim}/wave-dos/cache-waves.do (100%) rename {regression => sim}/wave-dos/default-waves.do (100%) rename {regression => sim}/wave-dos/generic.do (100%) rename {regression => sim}/wave-dos/linux-waves.do (100%) rename {regression => sim}/wave-dos/peripheral-waves.do (100%) rename {regression => sim}/wave-fpu.do (100%) rename {regression => sim}/wave.do (100%) diff --git a/.gitignore b/.gitignore index b389dd1dd..5619adbff 100644 --- a/.gitignore +++ b/.gitignore @@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output tests/linux-testgen/buildroot-config-src/main.config.old tests/linux-testgen/buildroot-config-src/linux.config.old tests/linux-testgen/buildroot-config-src/busybox.config.old -regression/slack-notifier/slack-webhook-url.txt -regression/logs +sim/slack-notifier/slack-webhook-url.txt +sim/logs fpga/generator/IP fpga/generator/vivado.* fpga/generator/.Xil/* @@ -79,24 +79,24 @@ synthDC/ppa/plots synthDC/wallyplots/ synthDC/runArchive synthDC/hdl -regression/power.saif +sim/power.saif tests/fp/vectors/*.tv synthDC/Summary.csv -regression/wkdir +sim/wkdir tests/custom/work tests/custom/*/*/*.list tests/custom/*/*/*.elf tests/custom/*/*/*.map tests/custom/*/*/*.memfile tests/custom/crt0/*.a -regression/sd_model.log +sim/sd_model.log fpga/src/sdc/* fpga/src/sdc.tar.gz fpga/src/CopiedFiles_do_not_add_to_repo/* -regression/branch.log +sim/branch.log /fpga/generator/sim/imp-funcsim.v /fpga/generator/sim/imp-timesim.sdf /fpga/generator/sim/imp-timesim.v /fpga/generator/sim/syn-funcsim.v external -regression/results +sim/results diff --git a/Install b/Install index 46f4d78ec..47a91dddd 100644 --- a/Install +++ b/Install @@ -328,6 +328,6 @@ source ./setup.sh # may require some modification for your system. Always cd make - cd regression + cd sim ./regression-wally #(depends on having Questa installed) diff --git a/Makefile b/Makefile index 24ba57e57..1f540b56c 100644 --- a/Makefile +++ b/Makefile @@ -15,8 +15,8 @@ install: ##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe regression: - make -C regression + make -C sim clean: - make clean -C regression + make clean -C sim diff --git a/README.md b/README.md index 824c7c176..ce92151ed 100644 --- a/README.md +++ b/README.md @@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se Run a regression simulation with Questa to prove everything is installed. - $ cd regression + $ cd sim $ ./regression-wally (depends on having Questa installed) # Toolchain Installation (Sys Admin) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index b8235ea94..e0aa6661d 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -21,8 +21,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: - (cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) - cd ../../benchmarks/coremark/ + (cd ../../sim && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) + cd ../benchmarks/coremark/ # KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test python3 coremark-postprocess.py diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index b5030d119..0d619c90b 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed # launches modelsim to simulate tests on wally modelsim_run: - (cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") + (cd ../../sim/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") cd ../../benchmarks/embench/ # builds the objdump based on the compiled c elf files diff --git a/setup.imperas.sh b/setup.imperas.sh index 4e30fb07f..755a298b5 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC # setup QUESTA (Imperas only command, YMMV) svsetup -questa -pushd regression +pushd sim # With IDV IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ diff --git a/regression/Makefile b/sim/Makefile similarity index 62% rename from regression/Makefile rename to sim/Makefile index adc7bc718..6a917bcda 100644 --- a/regression/Makefile +++ b/sim/Makefile @@ -2,27 +2,27 @@ all: riscoftests memfiles # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired - #make -C ../../tests/imperas-riscv-tests --jobs - #make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs + #make -C ../tests/imperas-riscv-tests --jobs + #make -C ../tests/imperas-riscv-tests XLEN=64 --jobs # Only compile Imperas tests if they are installed locally. # They are usually a symlink to $RISCV/imperas-riscv-tests and only # get compiled there manually during installation - #make -C ../../addins/imperas-riscv-tests - #make -C ../../addins/imperas-riscv-tests XLEN=64 - #cd ../../addins/imperas-riscv-tests; elf2hex.sh - #cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump + #make -C ../addins/imperas-riscv-tests + #make -C ../addins/imperas-riscv-tests XLEN=64 + #cd ../addins/imperas-riscv-tests; elf2hex.sh + #cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump # Link Linux test vectors - #cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh + #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh allclean: clean all clean: - make clean -C ../../tests/riscof + make clean -C ../tests/riscof # make clean -C ../../tests/wally-riscv-arch-test # make allclean -C ../../tests/imperas-riscv-tests riscoftests: # Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions - make -C ../../tests/riscof/ + make -C ../tests/riscof/ memfiles: make -f makefile-memfile wally-sim-files --jobs diff --git a/regression/buildrootBugFinder.py b/sim/buildrootBugFinder.py similarity index 100% rename from regression/buildrootBugFinder.py rename to sim/buildrootBugFinder.py diff --git a/regression/fpga-wave.do b/sim/fpga-wave.do similarity index 100% rename from regression/fpga-wave.do rename to sim/fpga-wave.do diff --git a/regression/imperas.ic b/sim/imperas.ic similarity index 100% rename from regression/imperas.ic rename to sim/imperas.ic diff --git a/regression/lint-wally b/sim/lint-wally similarity index 100% rename from regression/lint-wally rename to sim/lint-wally diff --git a/regression/linux-wave.do b/sim/linux-wave.do similarity index 100% rename from regression/linux-wave.do rename to sim/linux-wave.do diff --git a/regression/make-tests.sh b/sim/make-tests.sh similarity index 100% rename from regression/make-tests.sh rename to sim/make-tests.sh diff --git a/regression/makefile-memfile b/sim/makefile-memfile similarity index 99% rename from regression/makefile-memfile rename to sim/makefile-memfile index 646da5ac3..6c2da42fa 100644 --- a/regression/makefile-memfile +++ b/sim/makefile-memfile @@ -1,4 +1,4 @@ -ROOT := ../.. +ROOT := .. SUFFIX := work ARCHDIR := $(ROOT)/tests/riscof WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test diff --git a/regression/regression-wally b/sim/regression-wally similarity index 100% rename from regression/regression-wally rename to sim/regression-wally diff --git a/regression/run-imperasdv-tests.bash b/sim/run-imperasdv-tests.bash similarity index 100% rename from regression/run-imperasdv-tests.bash rename to sim/run-imperasdv-tests.bash diff --git a/regression/sim-buildroot b/sim/sim-buildroot similarity index 100% rename from regression/sim-buildroot rename to sim/sim-buildroot diff --git a/regression/sim-buildroot-batch b/sim/sim-buildroot-batch similarity index 100% rename from regression/sim-buildroot-batch rename to sim/sim-buildroot-batch diff --git a/regression/sim-imperas b/sim/sim-imperas similarity index 100% rename from regression/sim-imperas rename to sim/sim-imperas diff --git a/regression/sim-testfloat b/sim/sim-testfloat similarity index 100% rename from regression/sim-testfloat rename to sim/sim-testfloat diff --git a/regression/sim-testfloat-batch b/sim/sim-testfloat-batch similarity index 100% rename from regression/sim-testfloat-batch rename to sim/sim-testfloat-batch diff --git a/regression/sim-wally b/sim/sim-wally similarity index 100% rename from regression/sim-wally rename to sim/sim-wally diff --git a/regression/sim-wally-batch b/sim/sim-wally-batch similarity index 100% rename from regression/sim-wally-batch rename to sim/sim-wally-batch diff --git a/regression/slack-notifier/slack-notifier.py b/sim/slack-notifier/slack-notifier.py similarity index 100% rename from regression/slack-notifier/slack-notifier.py rename to sim/slack-notifier/slack-notifier.py diff --git a/regression/test b/sim/test similarity index 100% rename from regression/test rename to sim/test diff --git a/regression/testfloat.do b/sim/testfloat.do similarity index 100% rename from regression/testfloat.do rename to sim/testfloat.do diff --git a/regression/wally-pipelined-batch.do b/sim/wally-pipelined-batch.do similarity index 100% rename from regression/wally-pipelined-batch.do rename to sim/wally-pipelined-batch.do diff --git a/regression/wally-pipelined-imperas-no-idv.do b/sim/wally-pipelined-imperas-no-idv.do similarity index 100% rename from regression/wally-pipelined-imperas-no-idv.do rename to sim/wally-pipelined-imperas-no-idv.do diff --git a/regression/wally-pipelined-imperas.do b/sim/wally-pipelined-imperas.do similarity index 100% rename from regression/wally-pipelined-imperas.do rename to sim/wally-pipelined-imperas.do diff --git a/regression/wally-pipelined.do b/sim/wally-pipelined.do similarity index 100% rename from regression/wally-pipelined.do rename to sim/wally-pipelined.do diff --git a/regression/wave-all.do b/sim/wave-all.do similarity index 100% rename from regression/wave-all.do rename to sim/wave-all.do diff --git a/regression/wave-dos/ahb-muldiv.do b/sim/wave-dos/ahb-muldiv.do similarity index 100% rename from regression/wave-dos/ahb-muldiv.do rename to sim/wave-dos/ahb-muldiv.do diff --git a/regression/wave-dos/ahb-waves.do b/sim/wave-dos/ahb-waves.do similarity index 100% rename from regression/wave-dos/ahb-waves.do rename to sim/wave-dos/ahb-waves.do diff --git a/regression/wave-dos/cache-waves.do b/sim/wave-dos/cache-waves.do similarity index 100% rename from regression/wave-dos/cache-waves.do rename to sim/wave-dos/cache-waves.do diff --git a/regression/wave-dos/default-waves.do b/sim/wave-dos/default-waves.do similarity index 100% rename from regression/wave-dos/default-waves.do rename to sim/wave-dos/default-waves.do diff --git a/regression/wave-dos/generic.do b/sim/wave-dos/generic.do similarity index 100% rename from regression/wave-dos/generic.do rename to sim/wave-dos/generic.do diff --git a/regression/wave-dos/linux-waves.do b/sim/wave-dos/linux-waves.do similarity index 100% rename from regression/wave-dos/linux-waves.do rename to sim/wave-dos/linux-waves.do diff --git a/regression/wave-dos/peripheral-waves.do b/sim/wave-dos/peripheral-waves.do similarity index 100% rename from regression/wave-dos/peripheral-waves.do rename to sim/wave-dos/peripheral-waves.do diff --git a/regression/wave-fpu.do b/sim/wave-fpu.do similarity index 100% rename from regression/wave-fpu.do rename to sim/wave-fpu.do diff --git a/regression/wave.do b/sim/wave.do similarity index 100% rename from regression/wave.do rename to sim/wave.do diff --git a/synthDC/Makefile b/synthDC/Makefile index 7ef295434..f13b38ab6 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -102,11 +102,11 @@ endif sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh ifeq ($(SAIFPOWER), 1) - cp -f ../regression/power.saif . + cp -f ../sim/power.saif . endif ifeq ($(SAIFPOWER), 1) - cp -f ../regression/power.saif . + cp -f ../sim/power.saif . endif freqs: diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh index 414f4f2d5..d1afb4e89 100755 --- a/tests/testgen/privileged/run.sh +++ b/tests/testgen/privileged/run.sh @@ -48,7 +48,7 @@ fi if [[ "$2" == "-sim" || "$2" == "-simonly" ]] then printf "\n\n\n#####\nSimulating!\n#####\n\n" - cd $WALLY/regression + cd $WALLY/sim vsim -do wally-privileged.do -c fi From 644dfe7463fb617c34e97399e5076410970b0a0e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 2 Feb 2023 19:40:41 -0800 Subject: [PATCH 216/294] Removed lab1matrix solutions --- examples/C/lab1matrix/Makefile | 33 ------------ examples/C/lab1matrix/matMult | Bin 43352 -> 0 bytes examples/C/lab1matrix/matMult.c | 87 -------------------------------- 3 files changed, 120 deletions(-) delete mode 100644 examples/C/lab1matrix/Makefile delete mode 100755 examples/C/lab1matrix/matMult delete mode 100644 examples/C/lab1matrix/matMult.c diff --git a/examples/C/lab1matrix/Makefile b/examples/C/lab1matrix/Makefile deleted file mode 100644 index 18c011f4f..000000000 --- a/examples/C/lab1matrix/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -TARGET = matMult - -$(TARGET).objdump: $(TARGET) - riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump - spike $(TARGET) - -$(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ - -march=rv64gc -mabi=lp64d -mcmodel=medany \ - -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ - -T../common/test.ld -I../common \ - $(TARGET).c ../common/crt.S ../common/syscalls.c -# Compiler flags: -# -o $(TARGET) defines the name of the output file -# -g generates debugging symbols for gdb -# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization -# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits -# -static forces static linking (no dynamic shared libraries on bare metal) -# -lm links the math library if necessary (when #include math.h) -# -nostdlib avoids inserting standard startup files and default libraries -# because we are using crt.s on bare metal -# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library -# -T specifies the linker file -# -I specifies the include path (e.g. for util.h) -# The last line defines the C files to compile. -# crt.S is needed as our startup file to initialize the processor -# syscalls.c implements printf through the HTIF for Spike -# other flags from riscv-tests makefiles that don't seem to be important -# -ffast-math -DPREALLOCATE=1 -std=gnu99 \ -# -fno-common -fno-builtin-printf -nostartfiles -lgcc \ - -clean: - rm -f $(TARGET) $(TARGET).objdump diff --git a/examples/C/lab1matrix/matMult b/examples/C/lab1matrix/matMult deleted file mode 100755 index e3d3b25dd44f3d863bf10fb093a7f51972edf99a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 43352 zcmeHwd3;nwwtrRM?!M{lq(j0IAq2uEgjL)SArKZtbU+;lNJu&h4cSbZO|}F`0^)|5 zF@r=woI&LI{5bdoM;&#Ths!uRjx*13e2yC`jN^ieiVl$9_f*xny#$^2-tV6`pO^dj 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b/examples/C/lab1matrix/matMult.c deleted file mode 100644 index b794819f9..000000000 --- a/examples/C/lab1matrix/matMult.c +++ /dev/null @@ -1,87 +0,0 @@ -// matMult.c -// mmasserfrye@hmc.edu 30 January 2022 - -#include // supports printf -#include // supports fabs -#include "util.h" // supports verify - -// puts the indicated row of length n from matrix mat into array arr -void getRow(int n, int row, double *mat, double *arr){ - int ind; - for (int i=0; i Date: Thu, 2 Feb 2023 23:52:21 -0600 Subject: [PATCH 217/294] Lee Moore found another bug using imperas. An ITLB miss concurrent with a d cache flush did not interlock. The LSU should suppress the d cache flush until the hptw fills the missing tlb entry. --- bugs.txt | 5 +- pipelined/regression/wave.do | 460 +++++++++++++++++++---------------- pipelined/src/lsu/lsu.sv | 8 +- 3 files changed, 251 insertions(+), 222 deletions(-) diff --git a/bugs.txt b/bugs.txt index 95d68b0d4..4c5a15a3c 100644 --- a/bugs.txt +++ b/bugs.txt @@ -1,5 +1,2 @@ -1. [X] Cache is suppressing d cache flush if there is a dtlb miss. - 1. Fixed by disabling mmu's address translation on flush. +1. [ ] AMO should always generate store faults never load faults. We are generating both. - -2. Test commit. diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index d6d7b695c..b62c31227 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -6,28 +6,28 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM @@ -42,11 +42,12 @@ add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/core/PCE -add wave -noupdate -group PCS /testbench/dut/core/PCM -add wave -noupdate -group PCS /testbench/PCW +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/core/PCE +add wave -noupdate -expand -group PCS /testbench/dut/core/PCM +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -55,11 +56,11 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName @@ -96,6 +97,7 @@ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F @@ -183,151 +185,153 @@ add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE @@ -365,6 +369,9 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testb add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF @@ -456,14 +463,21 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group ifu -expand -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/InstrDAPageFaultF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF +add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -expand -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr @@ -525,22 +539,49 @@ add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group w add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/VAdr add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Key2} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Key3} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Query2} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Query3} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Key2} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Key3} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Query2} +add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Query3} +add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} +add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} +add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer @@ -571,7 +612,6 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF @@ -597,25 +637,15 @@ add wave -noupdate -expand -group {branch direction} -expand -group {branch outc add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextW -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM @@ -626,12 +656,12 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBP add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW +add wave -noupdate /testbench/dut/core/ifu/CSRWriteFenceM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {1211181 ns} 1} {{Cursor 5} {158657 ns} 0} -quietly wave cursor active 5 +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {1151457 ns} 0} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {1156601 ns} 1} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -646,4 +676,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {158482 ns} {158818 ns} +WaveRestoreZoom {1151311 ns} {1151571 ns} diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 9a8226a5e..e01de3128 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -251,20 +251,22 @@ module lsu ( logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface - logic [1:0] BusRW; // Uncached bus memory access + logic [1:0] BusRW; // Uncached bus memory access logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11) - logic [1:0] CacheAtomicM; // Cache AMO + logic [1:0] CacheAtomicM; // Cache AMO + logic FlushDCache; // Suppress d cache flush if there is an ITLB miss. assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; assign CacheRWM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0; + assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW); cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), - .FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), + .FlushCache(FlushDCache), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataM), .SelHPTW, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), From 4547da80ea143d020a48897dbfaaa04fc7fc44ad Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 3 Feb 2023 00:39:26 -0600 Subject: [PATCH 218/294] Fixed bug #49. FFLAGS was updated while the pipeline was stalled. Also I found serveral performance counters which had similar issues. --- pipelined/src/privileged/csrc.sv | 10 +++++----- pipelined/src/privileged/csru.sv | 8 +++++--- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 94dbcaf48..ad9475d32 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -85,7 +85,7 @@ module csrc #(parameter if(`QEMU) begin: cevent // No other performance counters in QEMU assign CounterEvent[`COUNTERS-1:3] = 0; end else begin: cevent // User-defined counters - assign CounterEvent[3] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. + assign CounterEvent[3] = LoadStallM & InstrValidNotFlushedM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM; // branch predictor wrong target @@ -93,10 +93,10 @@ module csrc #(parameter assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong - assign CounterEvent[11] = DCacheAccess; // data cache access - assign CounterEvent[12] = DCacheMiss; // data cache miss - assign CounterEvent[13] = ICacheAccess; // instruction cache access - assign CounterEvent[14] = ICacheMiss; // instruction cache miss + assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM; // data cache access + assign CounterEvent[12] = DCacheMiss & InstrValidNotFlushedM; // data cache miss + assign CounterEvent[13] = ICacheAccess & InstrValidNotFlushedM; // instruction cache access + assign CounterEvent[14] = ICacheMiss & InstrValidNotFlushedM; // instruction cache miss assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM; // branch predictor wrong assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 08e2035d9..94b0683d2 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -48,19 +48,21 @@ module csru #(parameter logic [4:0] FFLAGS_REGW; logic [2:0] NextFRMM; logic [4:0] NextFFLAGSM; - + logic SetOrWriteFFLAGSM; + // Write enables //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM; assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM; - assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; + assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; // Write Values assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0]; assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM; + assign SetOrWriteFFLAGSM = WriteFFLAGSM | (|SetFflagsM & InstrValidNotFlushedM); // CSRs flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW); - flopr #(5) FFLAGSreg(clk, reset, NextFFLAGSM, FFLAGS_REGW); + flopenr #(5) FFLAGSreg(clk, reset, SetOrWriteFFLAGSM, NextFFLAGSM, FFLAGS_REGW); // CSR Reads always_comb begin From 4dca69f20537049a8a52f0c191744866b1692dee Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 3 Feb 2023 08:36:03 -0800 Subject: [PATCH 219/294] Updated division radix test script with paths, but script is out of date for files it manipulates --- bin/radixcopiesmultiregression.sh | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh index 1953b1da4..f701dada2 100755 --- a/bin/radixcopiesmultiregression.sh +++ b/bin/radixcopiesmultiregression.sh @@ -10,39 +10,39 @@ currCopies="define DIVCOPIES 32'h1" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h2" currCopies="define DIVCOPIES 32'h2" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h2" currCopies="define DIVCOPIES 32'h4" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h4" currCopies="define DIVCOPIES 32'h1" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h4" currCopies="define DIVCOPIES 32'h2" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h4" currCopies="define DIVCOPIES 32'h4" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally \ No newline at end of file +./sim/regression-wally \ No newline at end of file From 34fbfeb5cdaea5a514f577177452866696a649f0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 3 Feb 2023 08:36:51 -0800 Subject: [PATCH 220/294] Removed redundant line from synthesis makefile --- synthDC/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index f13b38ab6..c715a88b4 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -24,7 +24,6 @@ export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) -export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/config From 583d87afc7c07b9137b3d412cb67c328c6513a73 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 3 Feb 2023 17:40:20 -0600 Subject: [PATCH 221/294] Change CurrPtr to Ptr in RAS. --- pipelined/src/ifu/bpred/RASPredictor.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/pipelined/src/ifu/bpred/RASPredictor.sv b/pipelined/src/ifu/bpred/RASPredictor.sv index f71cb48f4..624d8e641 100644 --- a/pipelined/src/ifu/bpred/RASPredictor.sv +++ b/pipelined/src/ifu/bpred/RASPredictor.sv @@ -42,7 +42,7 @@ module RASPredictor #(parameter int StackSize = 16 )( logic CounterEn; localparam Depth = $clog2(StackSize); - logic [Depth-1:0] NextPtr, CurrPtr, PtrP1, PtrM1; + logic [Depth-1:0] NextPtr, Ptr, PtrP1, PtrM1; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; @@ -73,10 +73,10 @@ module RASPredictor #(parameter int StackSize = 16 )( assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD; mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, NextPtr); - assign PtrM1 = CurrPtr - 1'b1; - assign PtrP1 = CurrPtr + 1'b1; + assign PtrM1 = Ptr - 1'b1; + assign PtrP1 = Ptr + 1'b1; - flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, CurrPtr); + flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr); // RAS must be reset. always_ff @ (posedge clk) begin @@ -88,7 +88,7 @@ module RASPredictor #(parameter int StackSize = 16 )( end end - assign RASPCF = memory[CurrPtr]; + assign RASPCF = memory[Ptr]; endmodule From f5468ebd7ac8a689db528af2225764fe4ef61e34 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 3 Feb 2023 18:19:47 -0600 Subject: [PATCH 222/294] Replaced PCLinkX registers with a +2/4 adder in the execution stage. David and I estimate this is lower hardware cost. --- pipelined/src/ifu/ifu.sv | 20 ++++++++++---------- pipelined/src/ifu/spill.sv | 5 ++++- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c64049909..956144de2 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -109,6 +109,8 @@ module ifu ( logic [31:0] ICacheInstrF; // Instruction from the I$ logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus logic CompressedF; // The fetched instruction is compressed + logic CompressedD; // The decoded instruction is compressed + logic CompressedE; // The execution instruction is compressed logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage @@ -297,18 +299,11 @@ module ifu ( // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 + // *** consider using PCPlus2or4F = PCF + CompressedF ? 2 : 4; assign PCPlus4F = PCF[`XLEN-1:2] + 1; // add 4 to PC // choose PC+2 or PC+4 based on CompressedF, which arrives later. // Speeds up critical path as compared to selecting adder input based on CompressedF // *** consider gating PCPlus4F to provide the reset. -/* -----\/----- EXCLUDED -----\/----- - assign PCPlus2or4F[0] = '0; - assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]); - assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlus4F; - -----/\----- EXCLUDED -----/\----- */ -/* -----\/----- EXCLUDED -----\/----- - assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0]; - -----/\----- EXCLUDED -----/\----- */ // *** There is actually a bug in the regression test. We fetched an address which returns data with // an X. This version of the code does not die because if CompressedF is an X it just defaults to the last @@ -377,6 +372,11 @@ module ifu ( flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM); flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); - flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD); - flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE); + //flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD); + //flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE); + + flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD); + flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE); + assign PCLinkE = PCE + (CompressedE ? 2 : 4); + endmodule diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv index aa93c4397..4bb677cab 100644 --- a/pipelined/src/ifu/spill.sv +++ b/pipelined/src/ifu/spill.sv @@ -107,6 +107,9 @@ module spill #( // merge together mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalf}, SpillF, PostSpillInstrRawF); - assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11; + // Need to use always comb to avoid pessimistic x propagation if PostSpillInstrRawF is x + always_comb + if (PostSpillInstrRawF[1:0] != 2'b11) CompressedF = 1'b1; + else CompressedF = 1'b0; endmodule From b78ce62748f80a870bf11ec079c9d6037e3923a5 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Sat, 4 Feb 2023 09:50:36 +0000 Subject: [PATCH 223/294] added use sram parameter, cleaned up config writing, added single synth functionality to wallySynth --- synthDC/Makefile | 79 +++++++++++++++++---------------------- synthDC/scripts/synth.tcl | 3 +- synthDC/wallySynth.py | 17 ++++++--- 3 files changed, 47 insertions(+), 52 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 81d37e9d2..fdfc9e488 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -12,7 +12,7 @@ export MOD ?= orig # title to add a note in the synth's directory name TITLE = # tsmc28, sky130, and sky90 presently supported -export TECH ?= sky90 +export TECH ?= tsmc28 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient # Avoid when doing sweeps of many optimization points in parallel export MAXCORES ?= 1 @@ -20,6 +20,7 @@ export MAXCORES ?= 1 # The output netlist is hard to interpret, but significantly better PPA export MAXOPT ?= 0 export DRIVE ?= FLOP +export USESRAM ?= 0 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) @@ -29,13 +30,7 @@ export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/pipelined/config export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config -CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) -CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) -print: - @echo $(FREQS) - @echo $(CONFIG) - @echo $(CONFIGFILESTRIM) default: @@ -46,8 +41,6 @@ default: DIRS32 = rv32e rv32gc rv32imc rv32i DIRS64 = rv64i rv64gc -DIRS32 = rv32e rv32gc rv32ic rv32i -DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) # k = 3 6 @@ -60,57 +53,55 @@ DIRS = $(DIRS32) $(DIRS64) configs: $(CONFIG) $(CONFIG): @echo $(CONFIG) - cp -r $(OLDCONFIGDIR)/$(CONFIG) $(CONFIGDIR)/$(CONFIG)_orig - sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh + cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR) + cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR) -ifneq ($(filter $ $(CONFIG), $(DIRS32)),) - sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh -else ifneq ($(filter $ $(CONFIG), $(DIRS64)),) - sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh - sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh +ifeq ($(USESRAM), 1) + sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh + +else + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh + sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh + +ifneq ($(filter $(CONFIG), $(DIRS32)),) + sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh +else ifneq ($(filter $(CONFIG), $(DIRS64)),) + sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh else $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) @echo "Config not in list, RAM_RANGE will be unmodified" endif +endif +ifeq ($(MOD), FPUoff) # turn off FPU - cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff - sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh - sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh - + sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh + sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/wally-config.vh +else ifeq ($(MOD), PMP16) # PMP 16 - cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh - + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/wally-config.vh +else ifeq ($(MOD), PMP0) # PMP 0 - cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh - + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh +else ifeq ($(MOD), noMulDiv) # no muldiv - cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv - sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - + sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh +else ifeq ($(MOD), noPriv) # no priv - cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv - sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh - -ifeq ($(SAIFPOWER), 1) - cp -f ../pipelined/regression/power.saif . + sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh endif ifeq ($(SAIFPOWER), 1) cp -f ../pipelined/regression/power.saif . endif -freqs: - @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) mkdirecs: @echo "DC Synthesis" @@ -129,7 +120,7 @@ rundc: clean: - rm -rf $(OUTPUTDIR)/hdl + rm -rf $(OUTPUTDIR)/hdl/*.sv rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/alib-52 rm -f default.svf diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 9fd86eccc..d7e792569 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -18,7 +18,7 @@ set_host_options -max_cores $::env(MAXCORES) # get outputDir and configDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) -set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh +set cfg $::env(CONFIGDIR)/wally-config.vh set hdl_src "../pipelined/src" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) @@ -26,7 +26,6 @@ set drive $::env(DRIVE) eval file copy -force $cfg {$outputDir/hdl/} eval file copy -force $cfg {$outputDir/} -eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 9ac3a995d..5015b8ca7 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -5,9 +5,9 @@ import subprocess from multiprocessing import Pool import argparse -def runSynth(config, mod, tech, freq, maxopt): +def runSynth(config, mod, tech, freq, maxopt, usesram): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram) pool.map(mask, [command]) def mask(command): @@ -32,6 +32,7 @@ if __name__ == '__main__': parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy") parser.add_argument("-e", "--tech", choices=techs, help = "Technology") parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT") + parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM (not flops)") args = parser.parse_args() @@ -39,17 +40,21 @@ if __name__ == '__main__': defaultfreq = 3000 if tech == 'sky90' else 10000 freq = args.targetfreq if args.targetfreq else defaultfreq maxopt = int(args.maxopt) - mod = 'orig' # until memory integrated + usesram = int(args.usesram) + mod = 'orig' if args.freqsweep: sc = args.freqsweep config = args.version if args.version else 'rv32e' for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep - runSynth(config, mod, tech, freq, maxopt) + runSynth(config, mod, tech, freq, maxopt, usesram) if args.configsweep: for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs - runSynth(config, mod, tech, freq, maxopt) + runSynth(config, mod, tech, freq, maxopt, usesram) if args.featuresweep: config = args.version if args.version else 'rv64gc' for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', - runSynth(config, mod, tech, freq, maxopt) + runSynth(config, mod, tech, freq, maxopt, usesram) + else: + config = args.version if args.version else 'rv64gc' + runSynth(config, mod, tech, freq, maxopt, usesram) \ No newline at end of file From 4be41ae25c0ba64901c8cbd4c2f89e78407c3f2f Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Sat, 4 Feb 2023 10:24:01 +0000 Subject: [PATCH 224/294] finishing the job of the last commit --- synthDC/Makefile | 8 ++++---- synthDC/scripts/synth.tcl | 5 ++--- synthDC/wallySynth.py | 4 ++-- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index fdfc9e488..fd9667942 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -29,7 +29,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/pipelined/config -export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config +export CONFIGDIR ?= $(OUTPUTDIR)/config @@ -106,8 +106,8 @@ endif mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) - @mkdir -p $(OUTPUTDIR)/hdl/config - @mkdir -p $(OUTPUTDIR)/hdl/config + @mkdir -p $(OUTPUTDIR)/hdl + @mkdir -p $(OUTPUTDIR)/config @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped @@ -120,7 +120,7 @@ rundc: clean: - rm -rf $(OUTPUTDIR)/hdl/*.sv + rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/alib-52 rm -f default.svf diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index d7e792569..ba6e4bb96 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -18,14 +18,13 @@ set_host_options -max_cores $::env(MAXCORES) # get outputDir and configDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) -set cfg $::env(CONFIGDIR)/wally-config.vh +set cfg $::env(CONFIGDIR) set hdl_src "../pipelined/src" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) -eval file copy -force $cfg {$outputDir/hdl/} -eval file copy -force $cfg {$outputDir/} +eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 5015b8ca7..3c96c38ee 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -1,5 +1,5 @@ #!/usr/bin/python3 -# Madeleine Masser-Frye mmasserfrye@hmc.edu 6/22 +# Madeleine Masser-Frye mmasserfrye@hmc.edu 1/2023 import subprocess from multiprocessing import Pool @@ -32,7 +32,7 @@ if __name__ == '__main__': parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy") parser.add_argument("-e", "--tech", choices=techs, help = "Technology") parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT") - parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM (not flops)") + parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules") args = parser.parse_args() From e831baf335ee375386685a297623fb731d06a395 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 03:42:20 -0800 Subject: [PATCH 225/294] Improved illegal NaN-box detection and formatted fsgninj --- src/fpu/fsgninj.sv | 18 +++++++++--------- src/fpu/unpack.sv | 11 +++++------ src/fpu/unpackinput.sv | 25 ++++++++++++++----------- 3 files changed, 28 insertions(+), 26 deletions(-) diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index d5568cabe..0db7dc2f3 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -29,11 +29,11 @@ `include "wally-config.vh" module fsgninj ( - input logic Xs, Ys, // X and Y sign bits - input logic [`FLEN-1:0] X, // X - input logic [`FMTBITS-1:0] Fmt, // format - input logic [1:0] OpCtrl, // operation control - output logic [`FLEN-1:0] SgnRes // result + input logic Xs, Ys, // X and Y sign bits + input logic [`FLEN-1:0] X, // X + input logic [`FMTBITS-1:0] Fmt, // format + input logic [1:0] OpCtrl, // operation control + output logic [`FLEN-1:0] SgnRes // result ); logic ResSgn; // result sign @@ -54,13 +54,13 @@ module fsgninj ( assign SgnRes = {ResSgn, X[`FLEN-2:0]}; else if (`FPSIZES == 2) assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; - else if (`FPSIZES == 3) begin + else if (`FPSIZES == 3) begin logic [2:0] SgnBits; always_comb case (Fmt) - `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; - `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; - `FMT2: SgnBits = {2'b11, ResSgn}; + `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; + `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; + `FMT2: SgnBits = {2'b11, ResSgn}; default: SgnBits = {3{1'bx}}; endcase assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 13addc2e3..356d7e897 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -48,15 +48,14 @@ module unpack ( unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero), - .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero)); + .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), .Subnorm(XSubnorm)); unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero), - .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero)); + .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), .Subnorm()); unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero), - .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero)); - // is the input subnormal - assign XSubnorm = ~XExpNonZero & ~XFracZero; -endmodule \ No newline at end of file + .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), .Subnorm()); + + endmodule \ No newline at end of file diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index 34663bd8c..b85077d20 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -31,16 +31,17 @@ module unpackinput ( input logic [`FLEN-1:0] In, // inputs from register file input logic En, // enable the input input logic [`FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half - output logic Sgn, // sign bits of XYZ - output logic [`NE-1:0] Exp, // exponents of XYZ (converted to largest supported precision) - output logic [`NF:0] Man, // mantissas of XYZ (converted to largest supported precision) - output logic NaN, // is XYZ a NaN - output logic SNaN, // is XYZ a signaling NaN - output logic Zero, // is XYZ zero - output logic Inf, // is XYZ infinity + output logic Sgn, // sign bits of the number + output logic [`NE-1:0] Exp, // exponent of the number (converted to largest supported precision) + output logic [`NF:0] Man, // mantissa of the number (converted to largest supported precision) + output logic NaN, // is the number a NaN + output logic SNaN, // is the number a signaling NaN + output logic Zero, // is the number zero + output logic Inf, // is the number infinity output logic ExpNonZero, // is the exponent not zero output logic FracZero, // is the fraction zero - output logic ExpMax // does In have the maximum exponent (NaN or Inf) + output logic ExpMax, // does In have the maximum exponent (NaN or Inf) + output logic Subnorm // is the number subnormal ); logic [`NF-1:0] Frac; // Fraction of XYZ @@ -261,10 +262,12 @@ module unpackinput ( end // Output logic - assign FracZero = ~|Frac; // is the fraction zero? + assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero? assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN? assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN? - assign Inf = ExpMax & FracZero &En; // is the input infinity? - assign Zero = ~ExpNonZero & FracZero; // is the input zero? + assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity? + assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero? + assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal + endmodule \ No newline at end of file From f89e64231215292296e3cf449db931eb34c4d03e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 04:19:09 -0800 Subject: [PATCH 226/294] ../synthDC/Makefile --- synthDC/Makefile | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 4d39e7c87..613ca49af 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -57,27 +57,17 @@ $(CONFIG): ifeq ($(USESRAM), 1) sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh - else sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh - @echo "match32" - @echo $(filter $(CONFIG), $(DIRS32)) - @echo "match64" - @echo $(filter $(CONFIG), $(DIRS64)) - ifneq ($(filter $(CONFIG), $(DIRS32)),) sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh - sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh - sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh else ifneq ($(filter $(CONFIG), $(DIRS64)),) sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh - sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh - sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh else $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) @echo "Config not in list, RAM_RANGE will be unmodified" From be08523ba0f60087e65c43160c4f5a26608fd873 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 04:29:27 -0800 Subject: [PATCH 227/294] Added license headers --- Makefile | 4 + benchmarks/coremark/Makefile | 1 + benchmarks/coremark/coremark-postprocess.py | 12 +- benchmarks/graphGen.py | 3 + bin/radixcopiesmultiregression.sh | 2 + setup.sh | 1 + wallypipelinedcore.sv | 360 -------------------- wallypipelinedsoc.sv | 92 ----- 8 files changed, 12 insertions(+), 463 deletions(-) delete mode 100644 wallypipelinedcore.sv delete mode 100644 wallypipelinedsoc.sv diff --git a/Makefile b/Makefile index 1f540b56c..518bcd2dd 100644 --- a/Makefile +++ b/Makefile @@ -1,3 +1,7 @@ +# David_Harris@hmc.edu 2023 +# Top-level Makefile for CORE-V-Wally +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + all: make install make regression diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index e0aa6661d..bb0f20f5a 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -1,5 +1,6 @@ # Wally Coremark Makefile # Daniel Torres & David Harris 28 July 2022 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 PORT_DIR = $(CURDIR)/riscv64-baremetal cmbase=../../addins/coremark diff --git a/benchmarks/coremark/coremark-postprocess.py b/benchmarks/coremark/coremark-postprocess.py index d069e8744..f77f2ef8b 100644 --- a/benchmarks/coremark/coremark-postprocess.py +++ b/benchmarks/coremark/coremark-postprocess.py @@ -9,17 +9,7 @@ # # Copyright (C) 2021 Harvey Mudd College & Oklahoma State University # -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -# is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ################################################## logFile = "../../benchmarks/coremark/work/coremark.sim.log" diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py index de8b70ce9..dd7b3a204 100755 --- a/benchmarks/graphGen.py +++ b/benchmarks/graphGen.py @@ -1,4 +1,7 @@ #!/usr/bin/env python +# Daniel Torres 2022 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + import subprocess import sys import json diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh index f701dada2..5d4f3f653 100755 --- a/bin/radixcopiesmultiregression.sh +++ b/bin/radixcopiesmultiregression.sh @@ -1,4 +1,6 @@ #!/bin/bash +# Alessandro Maiuolo 2022 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 configFile=config/shared/wally-shared.vh diff --git a/setup.sh b/setup.sh index d54ae7bd4..af4bac3b5 100755 --- a/setup.sh +++ b/setup.sh @@ -3,6 +3,7 @@ # setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 # Set up tools for rvw +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 echo "Executing Wally setup.sh" diff --git a/wallypipelinedcore.sv b/wallypipelinedcore.sv deleted file mode 100644 index 7013d0309..000000000 --- a/wallypipelinedcore.sv +++ /dev/null @@ -1,360 +0,0 @@ -/////////////////////////////////////////// -// wallypipelinedcore.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: Pipelined RISC-V Processor -// -// Documentation: RISC-V System on Chip Design (Figure 4.1) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -import cvw::*; // global CORE-V-Wally parameters - -module wallypipelinedcore ( - input logic clk, reset, - // Privileged - input logic MTimerInt, MExtInt, SExtInt, MSwInt, - input logic [63:0] MTIME_CLINT, - // Bus Interface - input logic [AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK -); - - logic StallF, StallD, StallE, StallM, StallW; - logic FlushD, FlushE, FlushM, FlushW; - logic RetM; - logic TrapM; - - // signals that must connect through DP - logic IntDivE, W64E; - logic CSRReadM, CSRWriteM, PrivilegedM; - logic [1:0] AtomicM; - logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; - logic [XLEN-1:0] SrcAM; - logic [2:0] Funct3E; - logic [31:0] InstrD; - logic [31:0] InstrM; - logic [XLEN-1:0] PCFSpill, PCE, PCLinkE; - logic [XLEN-1:0] PCM; - logic [XLEN-1:0] CSRReadValW, MDUResultW; - logic [XLEN-1:0] UnalignedPCNextF, PCNext2F; - logic [1:0] MemRWM; - logic InstrValidM; - logic InstrMisalignedFaultM; - logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; - logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; - logic LoadMisalignedFaultM, LoadAccessFaultM; - logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; - logic InvalidateICacheM, FlushDCacheM; - logic PCSrcE; - logic CSRWriteFenceM; - logic DivBusyE; - logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; - logic SquashSCW; - - // floating point unit signals - logic [2:0] FRM_REGW; - logic [4:0] RdE, RdM, RdW; - logic FPUStallD; - logic FWriteIntE; - logic [FLEN-1:0] FWriteDataM; - logic [XLEN-1:0] FIntResM; - logic [XLEN-1:0] FCvtIntResW; - logic FCvtIntW; - logic FDivBusyE; - logic IllegalFPUInstrM; - logic FRegWriteM; - logic FCvtIntStallD; - logic FpLoadStoreM; - logic [4:0] SetFflagsM; - logic [XLEN-1:0] FIntDivResultW; - - // memory management unit signals - logic ITLBWriteF; - logic ITLBMissF; - logic [XLEN-1:0] SATP_REGW; - logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; - logic [1:0] STATUS_MPP, STATUS_FS; - logic [1:0] PrivilegeModeW; - logic [XLEN-1:0] PTE; - logic [1:0] PageType; - logic sfencevmaM, WFIStallM; - logic SelHPTW; - - // PMA checker signals - var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0]; - var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0]; - - // IMem stalls - logic IFUStallF; - logic LSUStallM; - - // cpu lsu interface - logic [2:0] Funct3M; - logic [XLEN-1:0] IEUAdrE; - logic [XLEN-1:0] WriteDataM; - logic [XLEN-1:0] IEUAdrM; - logic [LLEN-1:0] ReadDataW; - logic CommittedM; - - // AHB ifu interface - logic [PA_BITS-1:0] IFUHADDR; - logic [2:0] IFUHBURST; - logic [1:0] IFUHTRANS; - logic [2:0] IFUHSIZE; - logic IFUHWRITE; - logic IFUHREADY; - - // AHB LSU interface - logic [PA_BITS-1:0] LSUHADDR; - logic [XLEN-1:0] LSUHWDATA; - logic [XLEN/8-1:0] LSUHWSTRB; - logic LSUHWRITE; - logic LSUHREADY; - - logic BPPredWrongE, BPPredWrongM; - logic DirPredictionWrongM; - logic BTBPredPCWrongM; - logic RASPredPCWrongM; - logic PredictionInstrClassWrongM; - logic [3:0] InstrClassM; - logic InstrAccessFaultF, HPTWInstrAccessFaultM; - logic [2:0] LSUHSIZE; - logic [2:0] LSUHBURST; - logic [1:0] LSUHTRANS; - - logic DCacheMiss; - logic DCacheAccess; - logic ICacheMiss; - logic ICacheAccess; - logic BreakpointFaultM, EcallFaultM; - logic InstrDAPageFaultF; - logic BigEndianM; - logic FCvtIntE; - logic CommittedF; - logic JumpOrTakenBranchM; - - // instruction fetch unit: PC, branch prediction, instruction cache - ifu ifu(.clk, .reset, - .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - // Fetch - .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, - .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, - .ICacheAccess, .ICacheMiss, - // Execute - .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM, - // Mem - .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, - .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, - // Faults out - .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, - // mmu management - .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, - .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF, - // pmp/pma (inside mmu) signals. - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); - - // integer execution unit: integer register file, datapath and controller - ieu ieu(.clk, .reset, - // Decode Stage interface - .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, - // Execute Stage interface - .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, - // Memory stage interface - .SquashSCW, // from LSU - .MemRWM, // read/write control goes to LSU - .AtomicM, // atomic control goes to LSU - .WriteDataM, // Write data to LSU - .Funct3M, // size and signedness to LSU - .SrcAM, // to privilege and fpu - .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, - // Writeback stage - .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]), - .InstrValidM, .FCvtIntResW, .FCvtIntW, - // hazards - .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE, - .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD); - - lsu lsu( - .clk, .reset, .StallM, .FlushM, .StallW, .FlushW, - // CPU interface - .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM, - .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, - .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM, - .ReadDataW, .FlushDCacheM, - // connected to ahb (all stay the same) - .LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, - .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY, - // connect to csr or privilege and stay the same. - .PrivilegeModeW, .BigEndianM, // connects to csr - .PMPCFG_ARRAY_REGW, // connects to csr - .PMPADDR_ARRAY_REGW, // connects to csr - // hptw keep i/o - .SATP_REGW, // from csr - .STATUS_MXR, // from csr - .STATUS_SUM, // from csr - .STATUS_MPRV, // from csr - .STATUS_MPP, // from csr - .sfencevmaM, // connects to privilege - .LoadPageFaultM, // connects to privilege - .StoreAmoPageFaultM, // connects to privilege - .LoadMisalignedFaultM, // connects to privilege - .LoadAccessFaultM, // connects to privilege - .HPTWInstrAccessFaultM, // connects to privilege - .StoreAmoMisalignedFaultM, // connects to privilege - .StoreAmoAccessFaultM, // connects to privilege - .InstrDAPageFaultF, - .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, - .LSUStallM); - - if(BUS_SUPPORTED) begin : ebu - ebu ebu(// IFU connections - .clk, .reset, - // IFU interface - .IFUHADDR, - .IFUHBURST, - .IFUHTRANS, - .IFUHREADY, - .IFUHSIZE, - // LSU interface - .LSUHADDR, - .LSUHWDATA, - .LSUHWSTRB, - .LSUHSIZE, - .LSUHBURST, - .LSUHTRANS, - .LSUHWRITE, - .LSUHREADY, - // BUS interface - .HREADY, .HRESP, .HCLK, .HRESETn, - .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, - .HPROT, .HTRANS, .HMASTLOCK); - end - - // global stall and flush control - hazard hzu( - .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM, - .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, - .LSUStallM, .IFUStallF, - .FCvtIntStallD, .FPUStallD, - .DivBusyE, .FDivBusyE, - .EcallFaultM, .BreakpointFaultM, - .WFIStallM, - // Stall & flush outputs - .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushD, .FlushE, .FlushM, .FlushW); - - // privileged unit - if (ZICSR_SUPPORTED) begin:priv - privileged priv( - .clk, .reset, - .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, - .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F, - .InstrM, .CSRReadValW, .UnalignedPCNextF, - .RetM, .TrapM, .sfencevmaM, - .InstrValidM, .CommittedM, .CommittedF, - .FRegWriteM, .LoadStallD, - .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM, - .RASPredPCWrongM, .PredictionInstrClassWrongM, - .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, - .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, - .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, - .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, - .MTimerInt, .MExtInt, .SExtInt, .MSwInt, - .MTIME_CLINT, .IEUAdrM, .SetFflagsM, - .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, - .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW, - .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM); - end else begin - assign CSRReadValW = 0; - assign UnalignedPCNextF = PCNext2F; - assign RetM = 0; - assign TrapM = 0; - assign WFIStallM = 0; - assign sfencevmaM = 0; - assign BigEndianM = 0; - end - - // multiply/divide unit - if (M_SUPPORTED) begin:mdu - mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW, - .ForwardedSrcAE, .ForwardedSrcBE, - .Funct3E, .Funct3M, .IntDivE, .W64E, - .MDUResultW, .DivBusyE); - end else begin // no M instructions supported - assign MDUResultW = 0; - assign DivBusyE = 0; - end - - // floating point unit - if (F_SUPPORTED) begin:fpu - fpu fpu( - .clk, .reset, - .FRM_REGW, // Rounding mode from CSR - .InstrD, // instruction from IFU - .ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory - .ForwardedSrcAE, // Integer input being processed (from IEU) - .StallE, .StallM, .StallW, // stall signals from HZU - .FlushE, .FlushM, .FlushW, // flush signals from HZU - .RdE, .RdM, .RdW, // which FP register to write to (from IEU) - .STATUS_FS, // is floating-point enabled? - .FRegWriteM, // FP register write enable - .FpLoadStoreM, - .ForwardedSrcBE, // Integer input for intdiv - .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions - .FPUStallD, // Stall the decode stage - .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation - .FWriteDataM, // Data to be written to memory - .FIntResM, // data to be written to integer register - .FCvtIntResW, // fp -> int conversion result to be stored in int register - .FCvtIntW, // fpu result selection - .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) - .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction - .SetFflagsM, // FPU flags (to privileged unit) - .FIntDivResultW); - end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low - assign FPUStallD = 0; - assign FWriteIntE = 0; - assign FCvtIntE = 0; - assign FIntResM = 0; - assign FCvtIntW = 0; - assign FDivBusyE = 0; - assign IllegalFPUInstrM = 1; - assign SetFflagsM = 0; - assign FpLoadStoreM = 0; - end - -endmodule diff --git a/wallypipelinedsoc.sv b/wallypipelinedsoc.sv deleted file mode 100644 index e792f6f89..000000000 --- a/wallypipelinedsoc.sv +++ /dev/null @@ -1,92 +0,0 @@ -/////////////////////////////////////////// -// wally-pipelinedsoc.sv -// -// Written: David_Harris@hmc.edu 6 November 2020 -// Modified: -// -// Purpose: System on chip including pipelined processor and uncore memories/peripherals -// -// Documentation: RISC-V System on Chip Design (Figure 6.20) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -import cvw::*; // global CORE-V-Wally parameters - -module wallypipelinedsoc ( - input logic clk, - input logic reset_ext, // external asynchronous reset pin - output logic reset, // reset synchronized to clk to prevent races on release - // AHB Interface - input logic [AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic HSELEXT, - // outputs to external memory, shared with uncore memory - output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, - output logic HREADY, - // I/O Interface - input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO - input logic UARTSin, // UART serial data input - output logic UARTSout, // UART serial data output - input logic SDCCmdIn, // SDC Command input - output logic SDCCmdOut, // SDC Command output - output logic SDCCmdOE, // SDC Command output enable - input logic [3:0] SDCDatIn, // SDC data input - output logic SDCCLK // SDC clock -); - - // Uncore signals - logic [AHBW-1:0] HRDATA; // from AHB mux in uncore - logic HRESP; // response from AHB - logic MTimerInt, MSwInt; // timer and software interrupts from CLINT - logic [63:0] MTIME_CLINT; // from CLINT to CSRs - logic MExtInt,SExtInt; // from PLIC - - // synchronize reset to SOC clock domain - synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); - - // instantiate processor and internal memories - wallypipelinedcore core(.clk, .reset, - .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, - .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, - .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK - ); - - // instantiate uncore if a bus interface exists - if (BUS_SUPPORTED) begin : uncore - uncore uncore(.HCLK, .HRESETn, .TIMECLK, - .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, - .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, - .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, - .UARTSout, .MTIME_CLINT, - .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); - end - -endmodule From ae548608050285651dbc4138c3675f06cc6fed59 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 04:38:41 -0800 Subject: [PATCH 228/294] Renamed wally-piplined.do to wally.do --- benchmarks/coremark/Makefile | 2 +- benchmarks/embench/Makefile | 2 +- setup.imperas.sh | 4 ++-- sim/buildrootBugFinder.py | 2 +- sim/regression-wally | 20 +++++++++---------- sim/run-imperasdv-tests.bash | 2 +- sim/sim-buildroot | 2 +- sim/sim-buildroot-batch | 2 +- sim/sim-imperas | 2 +- sim/sim-wally | 2 +- sim/sim-wally-batch | 2 +- sim/testfloat.do | 11 ++-------- ...ally-pipelined-batch.do => wally-batch.do} | 17 ++++++++-------- ...eras-no-idv.do => wally-imperas-no-idv.do} | 12 ++--------- ...-pipelined-imperas.do => wally-imperas.do} | 12 ++--------- sim/{wally-pipelined.do => wally.do} | 7 ++++--- 16 files changed, 40 insertions(+), 61 deletions(-) rename sim/{wally-pipelined-batch.do => wally-batch.do} (89%) rename sim/{wally-pipelined-imperas-no-idv.do => wally-imperas-no-idv.do} (73%) rename sim/{wally-pipelined-imperas.do => wally-imperas.do} (79%) rename sim/{wally-pipelined.do => wally.do} (95%) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index bb0f20f5a..b412c36ef 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -22,7 +22,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: - (cd ../../sim && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) + (cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) cd ../benchmarks/coremark/ # KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test python3 coremark-postprocess.py diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 0d619c90b..538fb64f9 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed # launches modelsim to simulate tests on wally modelsim_run: - (cd ../../sim/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") + (cd ../../sim/ && vsim -c -do "do wally-batch.do rv32gc embench") cd ../../benchmarks/embench/ # builds the objdump based on the compiled c elf files diff --git a/setup.imperas.sh b/setup.imperas.sh index 755a298b5..71d5dcfd5 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -36,7 +36,7 @@ pushd sim IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ - vsim -c -do "do wally-pipelined-imperas.do rv64gc" + vsim -c -do "do wally-imperas.do rv64gc" popd # notes @@ -50,7 +50,7 @@ popd IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ -vsim -c -do "do wally-pipelined-imperas.do rv64gc" +vsim -c -do "do wally-imperas.do rv64gc" # getting library issue. diff --git a/sim/buildrootBugFinder.py b/sim/buildrootBugFinder.py index 89a838d2f..af6324596 100755 --- a/sim/buildrootBugFinder.py +++ b/sim/buildrootBugFinder.py @@ -22,7 +22,7 @@ def main(): break checkpoint = checkpointList[0] logFile = logDir+"checkpoint"+str(checkpoint)+".log" - runCommand="{\nvsim -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < ${OUTDIR} :: ${OUTLOG}" mkdir -p ${OUTDIR} - vsim -c -do "do wally-pipelined-imperas.do rv64gc" + vsim -c -do "do wally-imperas.do rv64gc" mv transcript ${OUTLOG} done diff --git a/sim/sim-buildroot b/sim/sim-buildroot index 938bff866..530e33386 100755 --- a/sim/sim-buildroot +++ b/sim/sim-buildroot @@ -30,4 +30,4 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}" echo "INSTR_WAVEON = ${INSTR_WAVEON}" echo "CHECKPOINT = ${CHECKPOINT}" -vsim -do "do ./wally-pipelined.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT" +vsim -do "do ./wally.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT" diff --git a/sim/sim-buildroot-batch b/sim/sim-buildroot-batch index a8d4038ef..81a6fac1e 100755 --- a/sim/sim-buildroot-batch +++ b/sim/sim-buildroot-batch @@ -32,5 +32,5 @@ echo "CHECKPOINT = ${CHECKPOINT}" # *** change config from buildroot to rv64gc vsim -c <" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) +# run with vsim -do "do wally.do rv64ic riscvarchtest-64m" onbreak {resume} diff --git a/sim/wally-pipelined-batch.do b/sim/wally-batch.do similarity index 89% rename from sim/wally-pipelined-batch.do rename to sim/wally-batch.do index 4bd153ce7..064f503b2 100644 --- a/sim/wally-pipelined-batch.do +++ b/sim/wally-batch.do @@ -1,4 +1,5 @@ -# wally-pipelined-batch.do +# wally-batch.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -7,14 +8,14 @@ # # Takes 1:10 to run RV64IC tests using gui -# Usage: do wally-pipelined-batch.do -# Example: do wally-pipelined-batch.do rv32imc imperas-32i +# Usage: do wally-batch.do +# Example: do wally-batch.do rv32imc imperas-32i -# Use this wally-pipelined-batch.do file to run this example. +# Use this wally-batch.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined-batch.do +# do wally-batch.do # or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined-batch.do -c +# vsim -do wally-batch.do -c # (omit the "-c" to see the GUI while running from the shell) onbreak {resume} @@ -91,9 +92,9 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { # power off -r /dut/core/* } -#coverage report -file wally-pipelined-coverage.txt +#coverage report -file wally-coverage.txt # These aren't doing anything helpful #coverage report -memory -#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 +#profile report -calltree -file wally-calltree.rpt -cutoff 2 #power report -all -bsaif power.saif quit diff --git a/sim/wally-pipelined-imperas-no-idv.do b/sim/wally-imperas-no-idv.do similarity index 73% rename from sim/wally-pipelined-imperas-no-idv.do rename to sim/wally-imperas-no-idv.do index 646c41c72..5f300250c 100644 --- a/sim/wally-pipelined-imperas-no-idv.do +++ b/sim/wally-imperas-no-idv.do @@ -1,4 +1,5 @@ -# wally-pipelined.do +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -7,15 +8,6 @@ # # Takes 1:10 to run RV64IC tests using gui -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - onbreak {resume} # create library diff --git a/sim/wally-pipelined-imperas.do b/sim/wally-imperas.do similarity index 79% rename from sim/wally-pipelined-imperas.do rename to sim/wally-imperas.do index 21ed71420..d08361e8c 100644 --- a/sim/wally-pipelined-imperas.do +++ b/sim/wally-imperas.do @@ -1,4 +1,5 @@ -# wally-pipelined.do +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -7,15 +8,6 @@ # # Takes 1:10 to run RV64IC tests using gui -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - onbreak {resume} # create library diff --git a/sim/wally-pipelined.do b/sim/wally.do similarity index 95% rename from sim/wally-pipelined.do rename to sim/wally.do index 9d61511b7..895b10b95 100644 --- a/sim/wally-pipelined.do +++ b/sim/wally.do @@ -1,4 +1,5 @@ -# wally-pipelined.do +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -11,9 +12,9 @@ # Use this wally-pipelined.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do +# do wally.do # or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c +# vsim -do wally.do -c # (omit the "-c" to see the GUI while running from the shell) onbreak {resume} From 2c69adc5f7864a51a4e5532ab4340e0a68ac0c0c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 08:18:55 -0800 Subject: [PATCH 229/294] Started making debug testcase --- tests/custom/debug/Makefile | 27 ++++++++++++++++++++++++ tests/custom/debug/debug.S | 42 +++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 tests/custom/debug/Makefile create mode 100644 tests/custom/debug/debug.S diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile new file mode 100644 index 000000000..a63fb3b11 --- /dev/null +++ b/tests/custom/debug/Makefile @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +TARGET = debug + +%.elf.memfile: %.elf %.elf.objdump.adr + riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@ + +%.elf.objdump.addr: %.elf.objdump + extractFunctionRadix.sh $< + +$(TARGET).objdump: $(TARGET).elf + riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump + +$(TARGET): $(TARGET).S Makefile + riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ + -nostartfiles -T../../link/link.ld $(TARGET).S + +sim: + spike +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET) + diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit + echo "Signature matches! Success!" + +clean: + rm -f $(TARGET).elf $(TARGET).objdump $(TARGET).objdump.adr %(TARGET).elf.memfile $(TARGET).signature.output + + + diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S new file mode 100644 index 000000000..aadbcac64 --- /dev/null +++ b/tests/custom/debug/debug.S @@ -0,0 +1,42 @@ +// debug.S +// David_Harris@hmc.edu 4 February 2023 +// Small code snippets for the purpose of debugging issues +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# openhwgroup/cvw Issue #55 +li x1, 0x7ff0000000000001 +fmv.w.x f4, x1 +li x1, 7ff8000000000000 +fmv.w.x f9, x1 +fsgnjx.s f12,f9,f4 # expected f 0xffffffff7fc00000 + + +######################### +# HTIF and signature +######################### + +write_tohost: + la t1, tohost + li t0, 1 # 1 for success, 3 for failure + sd t0, 0(t1) # send success code + +self_loop: + j self_loop # wait + +.section .tohost +tohost: # write to HTIF + .dword 0 +fromhost: + .dword 0 + +.data + +.EQU XLEN,64 +begin_signature: + .fill 2*(XLEN/32),4,0xdeadbeef # +end_signature: + +# Initialize stack with room for 512 bytes +.bss + .space 512 +topofstack: \ No newline at end of file From b09002c71d4b22bd66442370e524ada8a18ac07e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 08:19:20 -0800 Subject: [PATCH 230/294] Fixed license on testbench files --- testbench/testbench-fp.sv | 24 ++++++++++-------------- testbench/testbench-linux.sv | 23 +++++++++++------------ testbench/testbench.sv | 24 ++++++++++-------------- testbench/testbench_imperas.sv | 24 ++++++++++-------------- testbench/tests-fp.vh | 26 ++++++++++++++++++++++++++ testbench/tests.vh | 22 ++++++++++++---------- 6 files changed, 79 insertions(+), 64 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 8d6826b70..3359090ac 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -9,22 +9,18 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" `include "tests-fp.vh" diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index da369250e..1705b36fd 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -10,20 +10,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -// When letting Wally go for it, let wally make own interrupts -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" diff --git a/testbench/testbench.sv b/testbench/testbench.sv index a3fa2c093..329d4c605 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -11,22 +11,18 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 65c92eb33..ce4b16de1 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -11,22 +11,18 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" diff --git a/testbench/tests-fp.vh b/testbench/tests-fp.vh index ff5cf2fb8..1d4cfdc60 100644 --- a/testbench/tests-fp.vh +++ b/testbench/tests-fp.vh @@ -1,3 +1,29 @@ +/////////////////////////////////////////// +// tests0fo.vh +// +// Written: Katherine Parry 2022 +// Modified: +// +// Purpose: List of floating-point tests to apply +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-3 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + `define PATH "../../tests/fp/vectors/" `define ADD_OPCTRL 3'b110 `define MUL_OPCTRL 3'b100 diff --git a/testbench/tests.vh b/testbench/tests.vh index f119b0a4e..397c66a0d 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -10,18 +10,19 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// `define IMPERASTEST "0" `define RISCVARCHTEST "1" @@ -1883,6 +1884,7 @@ string imperas32f[] = '{ string custom[] = '{ `CUSTOM, + "debug", "simple", "cacheTest" }; From 43668a3fc573fb8b77a3cc6cf817f601faabe57c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 08:31:47 -0800 Subject: [PATCH 231/294] Developing debug test --- src/fpu/unpackinput.sv | 4 +--- tests/custom/debug/Makefile | 2 +- tests/custom/debug/debug.S | 2 +- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index b85077d20..68f98e900 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -56,7 +56,6 @@ module unpackinput ( assign ExpMax = &In[`FLEN-2:`NF]; // is the exponent all 1's end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported - //***need better names for these constants // largest format | smaller format //---------------------------------- // `FLEN | `LEN1 length of floating point number @@ -104,7 +103,6 @@ module unpackinput ( end else if (`FPSIZES == 3) begin // three floating point precsions supported - //***need better names for these constants // largest format | larger format | smallest format //--------------------------------------------------- // `FLEN | `LEN1 | `LEN2 length of floating point number @@ -196,7 +194,7 @@ module unpackinput ( // Check NaN boxing always_comb case (Fmt) - 2'b11: BadNaNBox = 0; + 2'b11: BadNaNBox = 0; 2'b01: BadNaNBox = ~&In[`Q_LEN-1:`D_LEN]; 2'b00: BadNaNBox = ~&In[`Q_LEN-1:`S_LEN]; 2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN]; diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile index a63fb3b11..900f5b5e3 100644 --- a/tests/custom/debug/Makefile +++ b/tests/custom/debug/Makefile @@ -11,7 +11,7 @@ TARGET = debug $(TARGET).objdump: $(TARGET).elf riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump -$(TARGET): $(TARGET).S Makefile +$(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../link/link.ld $(TARGET).S diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S index aadbcac64..e493cab74 100644 --- a/tests/custom/debug/debug.S +++ b/tests/custom/debug/debug.S @@ -6,7 +6,7 @@ # openhwgroup/cvw Issue #55 li x1, 0x7ff0000000000001 fmv.w.x f4, x1 -li x1, 7ff8000000000000 +li x1, 0x7ff8000000000000 fmv.w.x f9, x1 fsgnjx.s f12,f9,f4 # expected f 0xffffffff7fc00000 From d7a65b2576368dfc7116e3b863c9a6ad398c514a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 4 Feb 2023 11:28:23 -0600 Subject: [PATCH 232/294] Updates to imperas test bench. --- pipelined/regression/imperas.ic | 1 + pipelined/regression/sim-imperas | 6 +- pipelined/regression/wave.do | 762 ++++++++++++++++--------------- 3 files changed, 388 insertions(+), 381 deletions(-) diff --git a/pipelined/regression/imperas.ic b/pipelined/regression/imperas.ic index 164cec228..930b6d3e2 100644 --- a/pipelined/regression/imperas.ic +++ b/pipelined/regression/imperas.ic @@ -2,6 +2,7 @@ --override cpu/show_c_prefix=T --override cpu/unaligned=F --override cpu/mstatus_FS=1 +--override cpu/ignore_non_leaf_DAU=1 # Enable the Imperas instruction coverage -extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 diff --git a/pipelined/regression/sim-imperas b/pipelined/regression/sim-imperas index d696f18e5..da1d5a919 100755 --- a/pipelined/regression/sim-imperas +++ b/pipelined/regression/sim-imperas @@ -28,5 +28,7 @@ ################################################################################################ IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ -TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ -vsim -c -do "do wally-pipelined-imperas.do rv64gc" +TESTDIR=${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/Lee.S/ \ +vsim -do "do wally-pipelined-imperas.do rv64gc" + +#TESTDIR=${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/FCVT-S-L-RTZ-01.S/ \ diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index b62c31227..7ccb27fb8 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -6,37 +6,37 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -68,23 +68,26 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE @@ -178,209 +181,209 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM +add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData +add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk +add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt @@ -461,112 +464,104 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/InstrDAPageFaultF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -expand -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Key2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Key3} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Query2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Query3} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Key2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Key3} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Query2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Query3} +add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/InstrDAPageFaultF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} @@ -631,25 +626,25 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF -add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE -add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF @@ -659,9 +654,18 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW add wave -noupdate /testbench/dut/core/ifu/CSRWriteFenceM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/NextFFLAGSM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/WriteFFLAGSM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/InstrValidNotFlushedM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRUWriteM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRAdrM +add wave -noupdate /testbench/dut/core/ifu/MatchCopy +add wave -noupdate /testbench/dut/core/ifu/PCLinkECopy +add wave -noupdate /testbench/dut/core/ifu/PCLinkE TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {1151457 ns} 0} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {1156601 ns} 1} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {353781 ns} 0} +quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -676,4 +680,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1151311 ns} {1151571 ns} +WaveRestoreZoom {348453 ns} {359109 ns} From 5256d3a625f42641f208eefecfaef221a10de6d2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 09:59:22 -0800 Subject: [PATCH 233/294] More progress on debug.S, but it crashes in Spike --- .gitignore | 1 + tests/custom/debug/Makefile | 14 +++++++------- tests/custom/debug/debug.S | 27 +++++++++++++++++++++------ 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/.gitignore b/.gitignore index 5619adbff..2d1454e3c 100644 --- a/.gitignore +++ b/.gitignore @@ -89,6 +89,7 @@ tests/custom/*/*/*.elf tests/custom/*/*/*.map tests/custom/*/*/*.memfile tests/custom/crt0/*.a +tests/custom/*/*.elf* sim/sd_model.log fpga/src/sdc/* fpga/src/sdc.tar.gz diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile index 900f5b5e3..9ee0b2e7b 100644 --- a/tests/custom/debug/Makefile +++ b/tests/custom/debug/Makefile @@ -2,26 +2,26 @@ TARGET = debug -%.elf.memfile: %.elf %.elf.objdump.adr +$(TARGET).elf.memfile:$(TARGET).elf $(TARGET).elf.objdump.addr riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@ -%.elf.objdump.addr: %.elf.objdump +$(TARGET).elf.objdump.addr: $(TARGET).elf.objdump extractFunctionRadix.sh $< -$(TARGET).objdump: $(TARGET).elf - riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump +$(TARGET).elf.objdump: $(TARGET).elf + riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).elf.objdump $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ - -nostartfiles -T../../link/link.ld $(TARGET).S + -nostartfiles -T$(WALLY)/examples/link/link.ld $(TARGET).S sim: - spike +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET) + spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET).elf diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit echo "Signature matches! Success!" clean: - rm -f $(TARGET).elf $(TARGET).objdump $(TARGET).objdump.adr %(TARGET).elf.memfile $(TARGET).signature.output + rm -f $(TARGET).elf $(TARGET).elf.* diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S index e493cab74..431a261e5 100644 --- a/tests/custom/debug/debug.S +++ b/tests/custom/debug/debug.S @@ -3,13 +3,22 @@ // Small code snippets for the purpose of debugging issues // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# openhwgroup/cvw Issue #55 -li x1, 0x7ff0000000000001 -fmv.w.x f4, x1 -li x1, 0x7ff8000000000000 -fmv.w.x f9, x1 -fsgnjx.s f12,f9,f4 # expected f 0xffffffff7fc00000 +.global rvtest_entry_point +rvtest_entry_point: + # openhwgroup/cvw Issue #55 + la a6, begin_signature + la a7, rvtest_data + fadd.d ft0, ft1, ft2 + fld f4, 0(a7) + fld f9, 8(a7) +# li x1, 0x7ff0000000000001 +# sd x1, 0(a6) +# fmv.w.x f4, x1 +# li x1, 0x7ff8000000000000 + # fmv.w.x f9, x1 + fsgnjx.s f12,f9,f4 # expected f 0xffffffff7fc00000 + fsd f12, 0(a6) ######################### # HTIF and signature @@ -23,14 +32,20 @@ write_tohost: self_loop: j self_loop # wait +.align 6 .section .tohost tohost: # write to HTIF .dword 0 fromhost: .dword 0 +.align 6 .data +rvtest_data: +.dword 0x7ff0000000000001 +.dword 0x7ff8000000000000 + .EQU XLEN,64 begin_signature: .fill 2*(XLEN/32),4,0xdeadbeef # From 9454eb921de5f2e8b6f805532c612e05d2be20ee Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Sun, 5 Feb 2023 00:02:50 +0000 Subject: [PATCH 234/294] Now modifying dtim and irom even when USESRAM=1 --- synthDC/Makefile | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 613ca49af..e9f4ac171 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -6,8 +6,8 @@ NAME := synth # defaults export DESIGN ?= wallypipelinedcore -export FREQ ?= 3000 -export CONFIG ?= rv32e +export FREQ ?= 10000 +export CONFIG ?= rv64gc export MOD ?= orig # title to add a note in the synth's directory name TITLE = @@ -20,7 +20,7 @@ export MAXCORES ?= 1 # The output netlist is hard to interpret, but significantly better PPA export MAXOPT ?= 0 export DRIVE ?= FLOP -export USESRAM ?= 0 +export USESRAM ?= 1 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) @@ -55,25 +55,35 @@ $(CONFIG): cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR) cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR) +# adjust DTIM and IROM to reasonable values depending on config +ifneq ($(filter $(CONFIG), $(DIRS32)),) + sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh +else ifneq ($(filter $(CONFIG), $(DIRS64)),) + sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh +else + $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) + @echo "Config not in list, RAM_RANGE will be unmodified" +endif + +# if USESRAM = 1, set that in the config file, otherwise reduce sizes ifeq ($(USESRAM), 1) sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh else sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh - - ifneq ($(filter $(CONFIG), $(DIRS32)),) - sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh - sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh - else ifneq ($(filter $(CONFIG), $(DIRS64)),) - sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh - sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh - else - $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) - @echo "Config not in list, RAM_RANGE will be unmodified" - endif +ifneq ($(filter $(CONFIG), $(DIRS32)),) + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh +else ifneq ($(filter $(CONFIG), $(DIRS64)),) + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh +endif endif +# adjust config if synthesizing with any modifications ifeq ($(MOD), FPUoff) # turn off FPU sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh From 66fa1e67bb4e584a194a074dcf1d2e15f4d6769c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 18:49:25 -0800 Subject: [PATCH 235/294] Removed redundant USE_SRAM from wally-shared.vh (already in wally-config.vh) --- config/shared/wally-shared.vh | 3 --- 1 file changed, 3 deletions(-) diff --git a/config/shared/wally-shared.vh b/config/shared/wally-shared.vh index 5d60fdce3..507388f7f 100644 --- a/config/shared/wally-shared.vh +++ b/config/shared/wally-shared.vh @@ -135,9 +135,6 @@ `define DIVBLEN ($clog2(`DIVb+1)-1) `define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu -// Memory synthesis configuration -`define USE_SRAM 0 - // Disable spurious Verilator warnings /* verilator lint_off STMTDLY */ From 7cf98811f39b80aad074b746cd306a6c6b66d661 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 18:49:47 -0800 Subject: [PATCH 236/294] Parenthesized reduction operators to avoid DC lint --- src/ebu/buscachefsm.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 8467f3029..2f3e99228 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -116,7 +116,7 @@ module buscachefsm #( assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY); assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; - assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) | + assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW))) | //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. (CurrState == DATA_PHASE) | (CurrState == CACHE_FETCH & ~HREADY) | @@ -124,7 +124,7 @@ module buscachefsm #( assign BusCommitted = CurrState != ADR_PHASE; // AHB bus interface - assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) | + assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) | (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; From 077edbf78dbef5b247aa935c418e008d33f5dd0e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 20:13:24 -0800 Subject: [PATCH 237/294] changed USE_SRAM to modify wally-config rather than wally-shared --- synthDC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index e9f4ac171..974626706 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -69,7 +69,7 @@ endif # if USESRAM = 1, set that in the config file, otherwise reduce sizes ifeq ($(USESRAM), 1) - sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh + sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-config.vh else sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh From 232bfbcfd02558c5bcec557f4a017daa8c615c1a Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Mon, 6 Feb 2023 13:43:12 +0000 Subject: [PATCH 238/294] remerge changes --- sim/imperas.ic | 18 ++++++++++++++---- sim/wally-imperas.do | 6 ++++-- testbench/testbench_imperas.sv | 7 ++++--- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index 164cec228..2f400b24a 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,20 +1,23 @@ -#--showoverrides --override cpu/show_c_prefix=T --override cpu/unaligned=F --override cpu/mstatus_FS=1 # Enable the Imperas instruction coverage --extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 --override refRoot/cpu/cv/cover=basic --override refRoot/cpu/cv/extensions=RV32I +#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 +#-override refRoot/cpu/cv/cover=basic +#-override refRoot/cpu/cv/extensions=RV32I # Add Imperas simulator application instruction tracing --trace --tracechange --traceshowicount --tracemode +--tracemem ASX --monitornetschange +# Exceptions and pagetables debug +--override cpu/debugflags=6 + # Turn on verbose output for Imperas simulator --verbose @@ -24,3 +27,10 @@ # Store simulator output to logfile --output imperas.log +--override cpu/PMP_registers=0 +#--showoverrides +#--mpdconsole + +# ignore settings of bits DAU for non leaf page table walks +--override cpu/ignore_non_leaf_DAU=1 + diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index d08361e8c..4164b7bdb 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -46,10 +46,12 @@ vsim workopt +nowarn3829 -fatal 7 \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) view wave #-- display input and output signals as hexidecimal values -add log -recursive /* -do wave.do +# add log -recursive /* +# do wave.do run -all noview ../testbench/testbench_imperas.sv view wave + +quit -f diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index ce4b16de1..759787299 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -142,9 +142,10 @@ module testbench; if (!rvviVersionCheck(RVVI_API_VERSION)) begin msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); end - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); - void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 39)); if (!rvviRefInit(elffilename)) begin msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); end From d88b56eebc1b66be5d782d3cc89f30adf7349a3b Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Mon, 6 Feb 2023 14:01:05 +0000 Subject: [PATCH 239/294] remove leading space --- sim/imperas.ic | 1 - 1 file changed, 1 deletion(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index 2f400b24a..016fdf505 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -33,4 +33,3 @@ # ignore settings of bits DAU for non leaf page table walks --override cpu/ignore_non_leaf_DAU=1 - From ae3ac025563331431456581bfa5fd321c54394fc Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Mon, 6 Feb 2023 15:53:29 +0000 Subject: [PATCH 240/294] remove dead code for ignoring fflags/fcsr --- testbench/testbench_imperas.sv | 5 ----- 1 file changed, 5 deletions(-) diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 759787299..e52a79c2e 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -164,11 +164,6 @@ module testbench; void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH end - // // Temporary fix for inexact difference -// void'(rvviRefCsrSetVolatile(0, 32'h001)); // fflags -// void'(rvviRefCsrSetVolatile(0, 32'h003)); // fcsr - - // Enable the trace2log module if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE)); From a07684914bec3b3cbac2b1f70c37b3f83a90e8b6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 6 Feb 2023 16:35:03 -0600 Subject: [PATCH 241/294] Updated imperas git repo to use a different hash. --- bin/imperas-one-time.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh index 474bccea3..404636d7c 100755 --- a/bin/imperas-one-time.sh +++ b/bin/imperas-one-time.sh @@ -27,7 +27,7 @@ ################################################################################################ -IMP_HASH=56b1479 +IMP_HASH=355a055ff7e36bc897e942e41f06e1baf96e34d5 # clone the Imperas repo cd $WALY From 4e8ef4a0ac014bdbae067fe2c92ee6560d20221f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 6 Feb 2023 16:42:07 -0600 Subject: [PATCH 242/294] Removed unreachable if branch in hptw next state logic. --- src/mmu/hptw.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 5cf58ffdf..78975e38e 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -255,7 +255,6 @@ module hptw ( L2_RD: if (DCacheStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32 - else if (ValidNonLeafPTE) NextWalkerState = L1_RD; else NextWalkerState = LEAF; L1_RD: if (DCacheStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; From c33230d1c1995c78fcda438ea71618b79c63e1e2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 6 Feb 2023 17:32:28 -0600 Subject: [PATCH 243/294] Fixed Bug 66. If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish. --- src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 78975e38e..c0b7ad933 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -245,7 +245,7 @@ module hptw ( flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) - IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; + IDLE: if (TLBMiss & ~DCacheStallM) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // first access in SV48 L3_RD: if (DCacheStallM) NextWalkerState = L3_RD; From 4c219de13d4791788d834d5d8988b0fc569124ce Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 6 Feb 2023 15:38:57 -0800 Subject: [PATCH 244/294] Fixed floating point crash in debug.S --- tests/custom/debug/Makefile | 8 +++++--- tests/custom/debug/debug.S | 2 ++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile index 9ee0b2e7b..4616dde67 100644 --- a/tests/custom/debug/Makefile +++ b/tests/custom/debug/Makefile @@ -17,11 +17,13 @@ $(TARGET).elf: $(TARGET).S Makefile sim: spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET).elf - diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit - echo "Signature matches! Success!" +# diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit +# echo "Signature matches! Success!" + mkdir -p ../work + cp -f * ../work clean: - rm -f $(TARGET).elf $(TARGET).elf.* + rm -f $(TARGET).elf $(TARGET).elf.* *.signature.output diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S index 431a261e5..5be3c2012 100644 --- a/tests/custom/debug/debug.S +++ b/tests/custom/debug/debug.S @@ -5,6 +5,8 @@ .global rvtest_entry_point rvtest_entry_point: + lui t0, 0x1e # turn on Floating point and XS + csrs mstatus, t0 # openhwgroup/cvw Issue #55 la a6, begin_signature From 44fef2f2a169be60b91736f4b5619114a2eaa1a4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 6 Feb 2023 16:47:56 -0800 Subject: [PATCH 245/294] debug simulating, produing discrepancy --- tests/custom/debug/Makefile | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile index 4616dde67..ddabe4e31 100644 --- a/tests/custom/debug/Makefile +++ b/tests/custom/debug/Makefile @@ -2,8 +2,15 @@ TARGET = debug +$(TARGET).signature.output: $(TARGET).elf.memfile $(TARGET).elf + spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=4 $(TARGET).elf +# diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit +# echo "Signature matches! Success!" + mkdir -p ../work + cp -f * ../work + $(TARGET).elf.memfile:$(TARGET).elf $(TARGET).elf.objdump.addr - riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@ + riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@ $(TARGET).elf.objdump.addr: $(TARGET).elf.objdump extractFunctionRadix.sh $< @@ -15,12 +22,6 @@ $(TARGET).elf: $(TARGET).S Makefile riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ -nostartfiles -T$(WALLY)/examples/link/link.ld $(TARGET).S -sim: - spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET).elf -# diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit -# echo "Signature matches! Success!" - mkdir -p ../work - cp -f * ../work clean: rm -f $(TARGET).elf $(TARGET).elf.* *.signature.output From e92605e2deaa57dd8eebb5c3094cf7a0b01f58c3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 7 Feb 2023 06:31:14 -0800 Subject: [PATCH 246/294] Disabled STATUS_FS at reset, fixing issue #71 --- src/privileged/csrsr.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index c5d5e7a1f..92f0f5045 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -145,7 +145,7 @@ module csrsr ( STATUS_MXR_INT <= #1 0; STATUS_SUM_INT <= #1 0; STATUS_MPRV_INT <= #1 0; // Per Priv 3.3 - STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b01 : 2'b00; + STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b00 : 2'b00; // leave floating-point off until activated, even if F_SUPPORTED STATUS_MPP <= #1 0; STATUS_SPP <= #1 0; STATUS_MPIE <= #1 0; From 755c795f919e3d4a55cd0d5b2998d5ce01d7a156 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 7 Feb 2023 06:55:42 -0800 Subject: [PATCH 247/294] Moved STATUS_FS_INT write to if statement to properly prioritize --- src/privileged/csrsr.sv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 92f0f5045..1fa1fe8e7 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -156,8 +156,6 @@ module csrsr ( STATUS_SBE <= #1 0; STATUS_UBE <= #1 0; end else if (~StallW) begin - if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else; - if (TrapM) begin // Update interrupt enables per Privileged Spec p. 21 // y = PrivilegeModeW @@ -211,6 +209,6 @@ module csrsr ( STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5]; STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1]; STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED; - end + end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; end endmodule From 0678f3f2b71a735b842e0ca70e595a19be7edc4e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 7 Feb 2023 14:01:59 -0600 Subject: [PATCH 248/294] Branch predictor cleanup. --- sim/wave.do | 559 ++++++++++++++++++++--------------------- src/ifu/bpred/bpred.sv | 56 ++--- testbench/tests.vh | 1 + 3 files changed, 305 insertions(+), 311 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index 7ccb27fb8..5faf74f35 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -6,37 +6,37 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -68,26 +68,26 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW -add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW -add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW -add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW -add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW +add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW +add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW +add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE @@ -181,209 +181,210 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -expand -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt @@ -540,28 +541,28 @@ add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} @@ -660,11 +661,9 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/InstrValidNotFlus add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRUWriteM add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRAdrM -add wave -noupdate /testbench/dut/core/ifu/MatchCopy -add wave -noupdate /testbench/dut/core/ifu/PCLinkECopy add wave -noupdate /testbench/dut/core/ifu/PCLinkE TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {353781 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {497341 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -680,4 +679,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {348453 ns} {359109 ns} +WaveRestoreZoom {497212 ns} {497470 ns} diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 664149652..700ec4092 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -71,8 +71,6 @@ module bpred ( logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; logic [`XLEN-1:0] PredPCF, RASPCF; - logic TargetWrongE; - logic FallThroughWrongE; logic PredictionPCWrongE; logic PredictionInstrClassWrongE; logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; @@ -219,27 +217,37 @@ module bpred ( flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE); // Check the prediction - // first check if the target or fallthrough address matches what was predicted. - assign TargetWrongE = IEUAdrE != PCD; - assign FallThroughWrongE = PCLinkE != PCD; - // If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected - // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi - // it must have selected the fall through. - assign PredictionPCWrongE = (PCSrcE & (|InstrClassE) ? TargetWrongE : FallThroughWrongE); + // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address. + // if the class prediction is wrong a regular instruction may have been predicted as a taken branch + // this will result in PCD not being equal to the fall through address PCLinkE (PCE+4). + // The next instruction is always valid as no other flush would occur at the same time as the branch and not + // also flush the branch. This will change in a superscaler cpu. + assign PredictionPCWrongE = PCCorrectE != PCD; + assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | BPPredClassNonCFIWrongE); - // The branch direction also need to checked. - // However if the direction is wrong then the pc will be wrong. This is only relavent to checking the - // accuracy of the direciton prediction. - //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0]; + // The branch direction is checked inside each branch predictor, but does not actually matter for + // branch miss prediction recovery. If the class or direction is wrong, but the target is correct + // we an ignore the branch miss-prediction. + + // Output the predicted PC or corrected PC on miss-predict. + // Selects the BP or PC+2/4. + mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); + // If the prediction is wrong select the correct address. + mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F); + // Correct branch/jump target. + mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); + // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. + // Effectively this is PCM+4 or the non-existant PCLinkM + if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); + else assign NextValidPCE = PCE; + // Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated. // Also we want to track this in a performance counter. assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE; + // The remaining checks are used for performance counters. + - // We want to output to the instruction fetch if the PC fetched was wrong. If by chance the predictor was wrong about - // the direction or class, but correct about the target we don't have the flush the pipeline. However we still - // need this information to verify the accuracy of the predictors. - assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE; // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; @@ -255,20 +263,6 @@ module bpred ( // branch class prediction wrong. assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; - // Selects the BP or PC+2/4. - mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); - // If the prediction is wrong select the correct address. - mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F); - // Correct branch/jump target. - mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); - - // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. - // Effectively this is PCM+4 or the non-existant PCLinkM - // if(`BPCLASS) begin - mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); - // end else begin - // assign NextValidPCE = PCE; - // end // performance counters // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now diff --git a/testbench/tests.vh b/testbench/tests.vh index 397c66a0d..1e1065cf1 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1747,6 +1747,7 @@ string imperas32f[] = '{ string wally64priv[] = '{ `WALLYTEST, +// "rv64i_m/privilege/src/BUG66", "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S", "rv64i_m/privilege/src/WALLY-mie-01.S", From b9f05c02e3189af222c1b7f02483378dc4b46077 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Tue, 7 Feb 2023 20:07:43 +0000 Subject: [PATCH 249/294] for feature sweep now adding feature modifications on top of each other --- synthDC/Makefile | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 974626706..76531d950 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -84,22 +84,22 @@ endif endif # adjust config if synthesizing with any modifications -ifeq ($(MOD), FPUoff) +ifneq ($(MOD), orig) + # PMP 0 + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh +ifneq ($(MOD), PMP0) + # no priv + sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh +ifneq ($(MOD), noPriv) # turn off FPU sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), PMP16) - # PMP 16 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), PMP0) - # PMP 0 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), noMulDiv) +ifneq ($(MOD), noFPU) # no muldiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), noPriv) - # no priv - sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh +endif +endif +endif endif ifeq ($(SAIFPOWER), 1) From 0cbf50ed805077de75a128e2505b29e19f916a10 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Tue, 7 Feb 2023 21:18:39 +0000 Subject: [PATCH 250/294] changed default freqs for synth sweeps updated plotting to not overlap labels --- synthDC/extractSummary.py | 12 ++++++------ synthDC/wallySynth.py | 10 +++++++--- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 430f86178..3d939644a 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -8,6 +8,7 @@ from matplotlib.cbook import flatten import matplotlib.pyplot as plt import matplotlib.lines as lines import numpy as np +from adjustText import adjust_text from ppa.ppaAnalyze import noOutliers from matplotlib import ticker import argparse @@ -149,9 +150,8 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): ax.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) - for i in range(len(labels)): - plt.annotate(labels[i], (delays[i], areas[i]), textcoords="offset points", xytext=(0,10), ha='center') - + texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))] + adjust_text(texts) return fig @@ -169,7 +169,7 @@ def plotFeatures(tech, width, config): fig = areaDelay(tech, delays, areas, labels, fig, ax) - titlestr = tech+'_'+width+config + titlestr = tech+'_'+width+config+'_'+str(freq)+'MHz' plt.title(titlestr) plt.savefig(final_directory + '/features_'+titlestr+'.png') @@ -240,8 +240,8 @@ def addFO4axis(fig, ax, tech): if __name__ == '__main__': parser = argparse.ArgumentParser() - parser.add_argument("-s", "--skyfreq", type=int, default=3000, help = "Target frequency used for sky90 syntheses") - parser.add_argument("-t", "--tsmcfreq", type=int, default=10000, help = "Target frequency used for tsmc28 syntheses") + parser.add_argument("-s", "--skyfreq", type=int, default=1500, help = "Target frequency used for sky90 syntheses") + parser.add_argument("-t", "--tsmcfreq", type=int, default=5000, help = "Target frequency used for tsmc28 syntheses") args = parser.parse_args() TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy") diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 3c96c38ee..3253607d5 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -37,8 +37,6 @@ if __name__ == '__main__': args = parser.parse_args() tech = args.tech if args.tech else 'sky90' - defaultfreq = 3000 if tech == 'sky90' else 10000 - freq = args.targetfreq if args.targetfreq else defaultfreq maxopt = int(args.maxopt) usesram = int(args.usesram) mod = 'orig' @@ -49,12 +47,18 @@ if __name__ == '__main__': for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep runSynth(config, mod, tech, freq, maxopt, usesram) if args.configsweep: + defaultfreq = 1500 if tech == 'sky90' else 5000 + freq = args.targetfreq if args.targetfreq else defaultfreq for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs runSynth(config, mod, tech, freq, maxopt, usesram) if args.featuresweep: + defaultfreq = 500 if tech == 'sky90' else 1500 + freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' - for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', + for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: runSynth(config, mod, tech, freq, maxopt, usesram) else: + defaultfreq = 500 if tech == 'sky90' else 1500 + freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' runSynth(config, mod, tech, freq, maxopt, usesram) \ No newline at end of file From ff7dc4f34ae1cf53ae3ffbddd65d5b1046ad2a6d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 7 Feb 2023 15:22:14 -0600 Subject: [PATCH 251/294] fpga constraints updates --- fpga/constraints/debug2.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 8b0b7c448..7ea5bf6bd 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -281,7 +281,7 @@ connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/Re create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55] From f41a8f9e624c0bc22da8b856cc0a62f037032a02 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Tue, 7 Feb 2023 16:35:44 -0800 Subject: [PATCH 252/294] Update README.md gcc seems to have changed its path to executables --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 400df6b3b..32e363569 100644 --- a/README.md +++ b/README.md @@ -125,7 +125,7 @@ Note: make --jobs will reduce compile time by compiling in parallel. However, a We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: $ cd $RISCV - $ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH + $ export PATH=$RISCV/bin:$PATH $ git clone https://github.com/sifive/elf2hex.git $ cd elf2hex $ autoreconf -i From 76332cac064176397d436225475cd1bec1af4f23 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 7 Feb 2023 16:49:50 -0800 Subject: [PATCH 253/294] Paths changed in latest GCC --- README.md | 6 +++--- bin/wally-tool-chain-install.sh | 6 ++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 400df6b3b..a7e2b99d0 100644 --- a/README.md +++ b/README.md @@ -110,11 +110,11 @@ Ubuntu users may need to install and update various tools. Beware when cutting ### Install RISC-V GCC Cross-Compiler -To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. +To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. $ git clone https://github.com/riscv/riscv-gnu-toolchain $ cd riscv-gnu-toolchain - $ git checkout 2022.09.21 + $ git checkout 2023.01.31 $ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" $ make --jobs @@ -143,7 +143,7 @@ Spike also takes a while to install and compile, but this can be done concurrent $ git clone https://github.com/riscv-software-src/riscv-isa-sim $ mkdir riscv-isa-sim/build $ cd riscv-isa-sim/build - $ ../configure --prefix=$RISCV --enable-commitlog + $ ../configure --prefix=$RISCV $ make --jobs $ make install $ cd ../arch_test_target/spike/device diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2b45d8e77..c4d9ed741 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -54,13 +54,15 @@ fi cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain +git checkout 2023.01.31 ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} make install # elf2hex cd $RISCV -export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +#export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +gexport PATH=$RISCV/bin:$PATH git clone https://github.com/sifive/elf2hex.git cd elf2hex autoreconf -i @@ -87,7 +89,7 @@ cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir -p riscv-isa-sim/build cd riscv-isa-sim/build -../configure --prefix=$RISCV --enable-commitlog +../configure --prefix=$RISCV make -j ${NUM_THREADS} make install cd ../arch_test_target/spike/device From 7f062cff8b0ee5f4b4a9469d70f8a83d5a3dd4e9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 8 Feb 2023 13:02:21 -0800 Subject: [PATCH 254/294] Removed unnecessary --enable-multilib from gcc build commands because --with-multilib-generator implies it --- README.md | 2 +- bin/wally-tool-chain-install.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index efd7e26cf..d8c2432d4 100644 --- a/README.md +++ b/README.md @@ -115,7 +115,7 @@ To install GCC from source can take hours to compile. This configuration enables $ git clone https://github.com/riscv/riscv-gnu-toolchain $ cd riscv-gnu-toolchain $ git checkout 2023.01.31 - $ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + $ ./configure --prefix=$RISCV --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" $ make --jobs Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index c4d9ed741..331ca13d6 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -55,7 +55,7 @@ cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain git checkout 2023.01.31 -./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} make install From 962c0189914fe2116fa3ce2522eb8da4d7067107 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 8 Feb 2023 18:24:38 -0600 Subject: [PATCH 255/294] Simplified branch predictor. --- src/ifu/bpred/bpred.sv | 62 ++++++++++++++---------------------------- src/ifu/bpred/btb.sv | 4 +-- 2 files changed, 23 insertions(+), 43 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 700ec4092..2d4dfe5c2 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -69,12 +69,12 @@ module bpred ( logic PredValidF; logic [1:0] DirPredictionF; - logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; + logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD; logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; - logic PredictionInstrClassWrongE; + logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; - logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; + logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; @@ -82,7 +82,6 @@ module bpred ( logic [`XLEN-1:0] PCCorrectE; logic [3:0] WrongPredInstrClassD; - logic BTBTargetWrongE; logic RASTargetWrongE; logic JumpOrTakenBranchE; @@ -132,20 +131,15 @@ module bpred ( -----/\----- EXCLUDED -----/\----- */ end - // this predictor will have two pieces of data, - // 1) A direction (1 = Taken, 0 = Not Taken) - // 2) Any information which is necessary for the predictor to build its next state. - // For a 2 bit table this is the prediction count. - // Part 2 Branch target address prediction - // *** For now the BTB will house the direct and indirect targets + // BTB contains target address for all CFI btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, .PCNextF, .PCF, .PCD, .PCE, .PredPCF, .BTBPredInstrClassF, .PredValidF, - .PredictionInstrClassWrongE, + .AnyWrongPredInstrClassE, .IEUAdrE, .InstrClassD, .InstrClassE); @@ -205,16 +199,15 @@ module bpred ( flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); - flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); // branch predictor flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE}, + {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, AnyWrongPredInstrClassE}, {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); // pipeline the class flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); - flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE); + flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE); // Check the prediction // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address. @@ -223,11 +216,13 @@ module bpred ( // The next instruction is always valid as no other flush would occur at the same time as the branch and not // also flush the branch. This will change in a superscaler cpu. assign PredictionPCWrongE = PCCorrectE != PCD; - assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | BPPredClassNonCFIWrongE); - // The branch direction is checked inside each branch predictor, but does not actually matter for - // branch miss prediction recovery. If the class or direction is wrong, but the target is correct - // we an ignore the branch miss-prediction. + // branch class prediction wrong. + assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; + assign AnyWrongPredInstrClassD = |WrongPredInstrClassD; + + // Finally indicate if the branch predictor was wrong + assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | AnyWrongPredInstrClassE); // Output the predicted PC or corrected PC on miss-predict. // Selects the BP or PC+2/4. @@ -242,27 +237,6 @@ module bpred ( if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); else assign NextValidPCE = PCE; - // Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated. - // Also we want to track this in a performance counter. - assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE; - // The remaining checks are used for performance counters. - - - - // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. - //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; - //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE; - assign BTBPredPCWrongE = BTBTargetWrongE; - - // similar with RAS. Over counts ras if the class prediction was wrong. - //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE; - assign RASPredPCWrongE = RASTargetWrongE; - // Finally if the real instruction class is non CFI but the predictor said it was we need to count. - assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; - - // branch class prediction wrong. - assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; - // performance counters // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now @@ -270,11 +244,17 @@ module bpred ( // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) - assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; - assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; + // Unforuantely we can't relay on PCD to infer the correctness of the BTB or RAS because the class prediction + // could be wrong or the fall through address selected for branch predict not taken. + // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of + // both without the above inaccuracies. + assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; + flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); + flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE); diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 7cf9ed993..c538636df 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -39,7 +39,7 @@ module btb #(parameter int Depth = 10 ) ( output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class output logic PredValidF, // BTB's guess is valid // update - input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong + input logic AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb input logic [3:0] InstrClassD, // Instruction class to insert into btb input logic [3:0] InstrClassE // Instruction class to insert into btb @@ -98,7 +98,7 @@ module btb #(parameter int Depth = 10 ) ( //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; - assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; + assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE; // An optimization may be using a PC relative address. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( From 2d7749db7fb9c150977fd32a5bb7fb8b147a604d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 9 Feb 2023 14:48:02 -0600 Subject: [PATCH 256/294] Updated globalhistory predictor. --- src/ifu/bpred/bpred.sv | 3 +- src/ifu/bpred/speculativeglobalhistory.sv | 102 +++++++++------------- 2 files changed, 44 insertions(+), 61 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 2d4dfe5c2..fd9e8a923 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -103,8 +103,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), - .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); + .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv index 3ed9ba3e5..51dbb422b 100644 --- a/src/ifu/bpred/speculativeglobalhistory.sv +++ b/src/ifu/bpred/speculativeglobalhistory.sv @@ -29,35 +29,31 @@ `include "wally-config.vh" module speculativeglobalhistory #(parameter int k = 10 ) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, // update - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic [3:0] WrongPredInstrClassD, - input logic PCSrcE + input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, + input logic [3:0] WrongPredInstrClassD, + input logic PCSrcE ); logic MatchF, MatchD, MatchE; logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; - - logic [k-1:0] GHRF; - logic GHRExtraF; - logic [k-1:0] GHRD, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k-1:0] GHRNextD; - logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; - logic [k-1:0] IndexNextF, IndexF; - logic [k-1:0] IndexD, IndexE; - + logic [1:0] NewDirPredictionE; + logic [k-1:0] GHRF, GHRD, GHRE; + logic GHRLastF; + logic [k-1:0] GHRNextF, GHRNextD, GHRNextE; + logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; + + logic FlushDOrDirWrong; assign IndexNextF = GHRNextF; assign IndexF = GHRF; @@ -70,20 +66,20 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( .rd1(TableDirPredictionF), .wa2(IndexE), .wd2(NewDirPredictionE), - .we2(BranchInstrE & ~StallM & ~FlushM), + .we2(InstrClassE[0]), .bwe2(1'b1)); // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage // and then register for use in the Fetch stage. - assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); - assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); - assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); + assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF); + assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD); + assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE); assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : - MatchD ? NewDirPredictionD : + assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} : + MatchD ? {2{DirPredictionD[1]}} : NewDirPredictionE ; flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); @@ -94,49 +90,37 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - // New prediction pipeline - assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]}; - flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline - // this version fails the regression test do to pessimistic x propagation. - // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] : - // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - // GHRF; - always_comb begin - if(FlushD | DirPredictionWrongE) begin - GHRNextF = GHRNextD[k-1:0]; - end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; - else GHRNextF = GHRF; - end + // If Fetch has a branch, speculatively insert prediction into the GHR + // If the front end is flushed or the direction prediction is wrong, reset to + // most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in. + // For FlushE this is GHRE. GHRNextE is both. + assign FlushDOrDirWrong = FlushD | DirPredictionWrongE; + mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], + {FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF); - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF); + // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift. + flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF); + flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF); - // use with out instruction class prediction - //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; - // with instruction class prediction - assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : - WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left - GHRF[k-1:0]; + // With instruction class prediction, the class could be wrong and is checked in Decode. + // If it is wrong and branch does exist then shift right and insert the prediction. + // If the branch does not exist then shift left and use GHRLastF to restore the LSB. + logic [k-1:0] GHRClassWrong; + mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong); + // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. + mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); - flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD); - assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed - FlushE ? GHRNextM : // branch is flushed - GHRD; - flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); + mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); - assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); - - assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); + flopenr #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE); - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; + assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; endmodule From edbf962b5f16c1081df762da49a4d5af85f893b7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 9 Feb 2023 18:14:26 -0800 Subject: [PATCH 257/294] Test gen header --- tests/testgen/testgen_header.S | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S index 4129782f6..44a74f5d1 100644 --- a/tests/testgen/testgen_header.S +++ b/tests/testgen/testgen_header.S @@ -1,21 +1,12 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 /////////////////////////////////////////// #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point From 8fb513ad35389beadbdf3fed72310818c59a4f55 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 9 Feb 2023 18:24:48 -0800 Subject: [PATCH 258/294] Moved test generators --- .../testgen}/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py | 0 .../testgen}/testgen-ADDI-XORI-ORI-ANDI-SLTI.py | 0 .../testgen}/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py | 0 .../testgen}/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-BRANCH.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-CSR.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-JAL-JALR.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-LOAD.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-PIPELINE.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-SLL-SRL-SRA.py | 0 .../testgen/imperas => studies/testgen}/testgen-SLLI-SRLI-SRAI.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-SLTIU.py | 0 {tests/testgen/imperas => studies/testgen}/testgen-STORE.py | 0 .../testgen/imperas => studies/testgen}/testgen-VIRTUALMEMORY.py | 0 14 files changed, 0 insertions(+), 0 deletions(-) rename {tests/testgen/imperas => studies/testgen}/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-ADDI-XORI-ORI-ANDI-SLTI.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-BRANCH.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-CSR.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-JAL-JALR.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-LOAD.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-PIPELINE.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-SLL-SRL-SRA.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-SLLI-SRLI-SRAI.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-SLTIU.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-STORE.py (100%) rename {tests/testgen/imperas => studies/testgen}/testgen-VIRTUALMEMORY.py (100%) diff --git a/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py similarity index 100% rename from tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py rename to studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py diff --git a/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py similarity index 100% rename from tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py rename to studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py diff --git a/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py similarity index 100% rename from tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py rename to studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py diff --git a/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py similarity index 100% rename from tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py rename to studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py diff --git a/tests/testgen/imperas/testgen-BRANCH.py b/studies/testgen/testgen-BRANCH.py similarity index 100% rename from tests/testgen/imperas/testgen-BRANCH.py rename to studies/testgen/testgen-BRANCH.py diff --git a/tests/testgen/imperas/testgen-CSR.py b/studies/testgen/testgen-CSR.py similarity index 100% rename from tests/testgen/imperas/testgen-CSR.py rename to studies/testgen/testgen-CSR.py diff --git a/tests/testgen/imperas/testgen-JAL-JALR.py b/studies/testgen/testgen-JAL-JALR.py similarity index 100% rename from tests/testgen/imperas/testgen-JAL-JALR.py rename to studies/testgen/testgen-JAL-JALR.py diff --git a/tests/testgen/imperas/testgen-LOAD.py b/studies/testgen/testgen-LOAD.py similarity index 100% rename from tests/testgen/imperas/testgen-LOAD.py rename to studies/testgen/testgen-LOAD.py diff --git a/tests/testgen/imperas/testgen-PIPELINE.py b/studies/testgen/testgen-PIPELINE.py similarity index 100% rename from tests/testgen/imperas/testgen-PIPELINE.py rename to studies/testgen/testgen-PIPELINE.py diff --git a/tests/testgen/imperas/testgen-SLL-SRL-SRA.py b/studies/testgen/testgen-SLL-SRL-SRA.py similarity index 100% rename from tests/testgen/imperas/testgen-SLL-SRL-SRA.py rename to studies/testgen/testgen-SLL-SRL-SRA.py diff --git a/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py b/studies/testgen/testgen-SLLI-SRLI-SRAI.py similarity index 100% rename from tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py rename to studies/testgen/testgen-SLLI-SRLI-SRAI.py diff --git a/tests/testgen/imperas/testgen-SLTIU.py b/studies/testgen/testgen-SLTIU.py similarity index 100% rename from tests/testgen/imperas/testgen-SLTIU.py rename to studies/testgen/testgen-SLTIU.py diff --git a/tests/testgen/imperas/testgen-STORE.py b/studies/testgen/testgen-STORE.py similarity index 100% rename from tests/testgen/imperas/testgen-STORE.py rename to studies/testgen/testgen-STORE.py diff --git a/tests/testgen/imperas/testgen-VIRTUALMEMORY.py b/studies/testgen/testgen-VIRTUALMEMORY.py similarity index 100% rename from tests/testgen/imperas/testgen-VIRTUALMEMORY.py rename to studies/testgen/testgen-VIRTUALMEMORY.py From 9a6d7bb16ddf94362397213120fd3de637dce396 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 9 Feb 2023 18:25:24 -0800 Subject: [PATCH 259/294] Added RVTEST_CASE to testgen header --- tests/testgen/testgen_header.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S index 44a74f5d1..a93e5af10 100644 --- a/tests/testgen/testgen_header.S +++ b/tests/testgen/testgen_header.S @@ -14,4 +14,7 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp) + + RVTEST_SIGBASE( x6, wally_signature) From 91427ed72dfed67f42c89f57dd8b68ebbe9b91c1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 10 Feb 2023 09:06:51 -0600 Subject: [PATCH 260/294] RAS and RAS documentation now consistent. --- src/ifu/bpred/RASPredictor.sv | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 624d8e641..0a841ae11 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -42,7 +42,7 @@ module RASPredictor #(parameter int StackSize = 16 )( logic CounterEn; localparam Depth = $clog2(StackSize); - logic [Depth-1:0] NextPtr, Ptr, PtrP1, PtrM1; + logic [Depth-1:0] NextPtr, Ptr, P1, M1, IncDecPtr; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; @@ -71,10 +71,11 @@ module RASPredictor #(parameter int StackSize = 16 )( assign CounterEn = PopF | PushE | RepairD; assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD; - mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, NextPtr); - assign PtrM1 = Ptr - 1'b1; - assign PtrP1 = Ptr + 1'b1; + assign P1 = 1; + assign M1 = '1; // -1 + mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr); + assign NextPtr = Ptr + IncDecPtr; flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr); @@ -84,7 +85,7 @@ module RASPredictor #(parameter int StackSize = 16 )( for(index=0; index Date: Fri, 10 Feb 2023 09:07:06 -0600 Subject: [PATCH 261/294] Added new features to branch predictor analysis script. --- bin/parseHPMC.py | 62 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 50 insertions(+), 12 deletions(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 35bb9c82e..5b5ce522d 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -28,6 +28,7 @@ import os import sys import matplotlib.pyplot as plt +import re def ComputeCPI(benchmark): 'Computes and inserts CPI into benchmark stats.' @@ -145,6 +146,11 @@ def FormatToPlot(currBenchmark): if(sys.argv[1] == '-b'): configList = [] + summery = 0 + if(sys.argv[2] == '-s'): + summery = 1 + sys.argv = sys.argv[1::] + print('summery = %d' % summery) for config in sys.argv[2::]: benchmarks = ProcessFile(config) ComputeAverage(benchmarks) @@ -171,18 +177,50 @@ if(sys.argv[1] == '-b'): size = len(benchmarkDict) index = 1 - print('Number of plots', size) - for benchmarkName in benchmarkDict: - currBenchmark = benchmarkDict[benchmarkName] - (names, values) = FormatToPlot(currBenchmark) - print(names, values) - plt.subplot(6, 7, index) - plt.bar(names, values) - plt.title(benchmarkName) - plt.ylabel('BR Dir Miss Rate (%)') - #plt.xlabel('Predictor') - index += 1 - #plt.tight_layout() + print('summery = %d' % summery) + if(summery == 0): + print('Number of plots', size) + for benchmarkName in benchmarkDict: + currBenchmark = benchmarkDict[benchmarkName] + (names, values) = FormatToPlot(currBenchmark) + print(names, values) + plt.subplot(6, 7, index) + plt.bar(names, values) + plt.title(benchmarkName) + plt.ylabel('BR Dir Miss Rate (%)') + #plt.xlabel('Predictor') + index += 1 + else: + combined = benchmarkDict['All_'] + (name, value) = FormatToPlot(combined) + lst = [] + dct = {} + category = [] + length = [] + accuracy = [] + for index in range(0, len(name)): + match = re.match(r"([a-z]+)([0-9]+)", name[index], re.I) + percent = 100 -value[index] + if match: + (PredType, size) = match.groups() + category.append(PredType) + length.append(size) + accuracy.append(percent) + if(PredType not in dct): + dct[PredType] = ([size], [percent]) + else: + (currSize, currPercent) = dct[PredType] + currSize.append(size) + currPercent.append(percent) + dct[PredType] = (currSize, currPercent) + print(dct) + for cat in dct: + (x, y) = dct[cat] + plt.scatter(x, y, label=cat) + plt.plot(x, y) + plt.ylabel('Prediction Accuracy') + plt.xlabel('Size (b or k)') + plt.legend(loc='upper left') plt.show() From ca0eb5a5912c788988bbb4927ff29cd6f058cb66 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 10 Feb 2023 10:33:10 -0600 Subject: [PATCH 262/294] Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic. --- src/ieu/controller.sv | 4 ++-- src/ieu/ieu.sv | 4 ++-- src/ifu/bpred/bpred.sv | 6 +++--- src/ifu/ifu.sv | 3 ++- src/wally/wallypipelinedcore.sv | 5 +++-- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 1819de17c..108b0bb1e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -62,7 +62,8 @@ module controller( output logic [2:0] Funct3M, // Instruction's funct3 field output logic RegWriteM, // Instruction writes a register (needed for Hazard unit) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ - output logic InstrValidM, // Instruction is valid + output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid + output logic FWriteIntM, // FPU controller writes integer register file // Writeback stage control signals input logic StallW, FlushW, // Stall, flush Writeback stage @@ -96,7 +97,6 @@ module controller( logic FenceXD; // Fence instruction logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$ logic CSRWriteD, CSRWriteE; // CSR write - logic InstrValidD, InstrValidE; // Instruction is valid logic PrivilegedD, PrivilegedE; // Privileged instruction logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 681bd9826..9df95040d 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -54,7 +54,7 @@ module ieu ( output logic [4:0] RdM, // Destination register input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ - output logic InstrValidM, // Instruction is valid + output logic InstrValidD, InstrValidE, InstrValidM,// Instruction is valid // Writeback stage signals input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) input logic [`XLEN-1:0] CSRReadValW, // CSR read value, @@ -97,7 +97,7 @@ module ieu ( .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, - .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM, + .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); datapath dp( diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index fd9e8a923..c2ad9ac91 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -51,6 +51,7 @@ module bpred ( input logic [31:0] PostSpillInstrRawF, // Instruction // Branch and jump outcome + input logic InstrValidD, InstrValidE, input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) @@ -220,8 +221,8 @@ module bpred ( assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; assign AnyWrongPredInstrClassD = |WrongPredInstrClassD; - // Finally indicate if the branch predictor was wrong - assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | AnyWrongPredInstrClassE); + // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. + assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; // Output the predicted PC or corrected PC on miss-predict. // Selects the BP or PC+2/4. @@ -236,7 +237,6 @@ module bpred ( if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); else assign NextValidPCE = PCE; - // performance counters // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 956144de2..68350bac5 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -35,6 +35,7 @@ module ifu ( // Command from CPU input logic InvalidateICacheM, // Clears all instruction cache valid bits input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE) + input logic InstrValidD, InstrValidE, InstrValidM, // Bus interface output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU @@ -322,7 +323,7 @@ module ifu ( if (`BPRED_SUPPORTED) begin : bpred bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushD, .FlushE, .FlushM, .FlushW, + .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 2df96d1fb..3a57b9aed 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -68,7 +68,7 @@ module wallypipelinedcore ( logic [`XLEN-1:0] CSRReadValW, MDUResultW; logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; logic [1:0] MemRWM; - logic InstrValidM; + logic InstrValidD, InstrValidE, InstrValidM; logic InstrMisalignedFaultM; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; @@ -166,6 +166,7 @@ module wallypipelinedcore ( // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .InstrValidM, .InstrValidE, .InstrValidD, // Fetch .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, @@ -201,7 +202,7 @@ module wallypipelinedcore ( .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), - .InstrValidM, .FCvtIntResW, .FCvtIntW, + .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW, // hazards .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE, From 6fbca64eb7a3cd6b86d7732b55d46ba8b95b4c10 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 10 Feb 2023 15:45:56 -0600 Subject: [PATCH 263/294] Experimental branch prediction optimization. --- src/ieu/controller.sv | 4 ++-- src/ieu/ieu.sv | 5 +++-- src/ifu/bpred/bpred.sv | 23 ++++++++++++++++------- src/ifu/ifu.sv | 5 ++++- src/wally/wallypipelinedcore.sv | 3 +++ 5 files changed, 28 insertions(+), 12 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 108b0bb1e..d66425343 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -63,6 +63,8 @@ module controller( output logic RegWriteM, // Instruction writes a register (needed for Hazard unit) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, output logic FWriteIntM, // FPU controller writes integer register file // Writeback stage control signals @@ -85,8 +87,6 @@ module controller( logic RegWriteD, RegWriteE; // RegWrite (register will be written) logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) - logic JumpD; // Jump instruction - logic BranchD, BranchE; // Branch instruction logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic [2:0] ALUControlD; // Determines ALU operation logic ALUSrcAD, ALUSrcBD; // ALU inputs diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 9df95040d..9d3a833e9 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -55,6 +55,8 @@ module ieu ( input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidD, InstrValidE, InstrValidM,// Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, JumpE, // Writeback stage signals input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) input logic [`XLEN-1:0] CSRReadValW, // CSR read value, @@ -87,7 +89,6 @@ module ieu ( logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages logic MemReadE, CSRReadE; // Load, CSRRead instruction - logic JumpE; // Jump instruction logic BranchSignedE; // Branch does signed comparison on operands logic MDUE; // Multiply/divide instruction @@ -95,7 +96,7 @@ module ieu ( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index c2ad9ac91..82bc5323d 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -52,6 +52,8 @@ module bpred ( // Branch and jump outcome input logic InstrValidD, InstrValidE, + input logic BranchD, BranchE, + input logic JumpD, JumpE, input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) @@ -189,11 +191,17 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; - assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 - assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 - assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 - assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch + //assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 + //assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 + //assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + // (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 + //assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch + assign InstrClassD[0] = BranchD; + assign InstrClassD[1] = JumpD ; + assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5 + assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 + + flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); @@ -247,10 +255,11 @@ module bpred ( // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + //assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; - assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; + assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1]; flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 68350bac5..51317e0b0 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -36,6 +36,8 @@ module ifu ( input logic InvalidateICacheM, // Clears all instruction cache valid bits input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE) input logic InstrValidD, InstrValidE, InstrValidM, + input logic BranchD, BranchE, + input logic JumpD, JumpE, // Bus interface output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU @@ -323,7 +325,8 @@ module ifu ( if (`BPRED_SUPPORTED) begin : bpred bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, + .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, + .BranchD, .BranchE, .JumpD, .JumpE, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 3a57b9aed..a03caea15 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -162,11 +162,13 @@ module wallypipelinedcore ( logic FCvtIntE; logic CommittedF; logic JumpOrTakenBranchM; + logic BranchD, BranchE, JumpD, JumpE; // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidM, .InstrValidE, .InstrValidD, + .BranchD, .BranchE, .JumpD, .JumpE, // Fetch .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, @@ -200,6 +202,7 @@ module wallypipelinedcore ( .Funct3M, // size and signedness to LSU .SrcAM, // to privilege and fpu .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, + .BranchD, .BranchE, .JumpD, .JumpE, // Writeback stage .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW, From 91fc883f6a1706ecb28d4d0660a83bac74c5a657 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 10 Feb 2023 17:09:35 -0600 Subject: [PATCH 264/294] More simplifications to the BP. --- src/ifu/bpred/bpred.sv | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 82bc5323d..0a01469d2 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -76,7 +76,7 @@ module bpred ( logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; - logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; + logic [3:0] InstrClassF, InstrClassD, InstrClassE; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; logic SelBPPredF; @@ -154,6 +154,7 @@ module bpred ( assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; +// *** still need to update to use inclusive jump assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; assign cj = CompressedOpcF == 5'h0d; assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; @@ -162,9 +163,10 @@ module bpred ( assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); - assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 - (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); + //assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + // (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 + // (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); + assign InstrClassF[1] = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F | (`C_SUPPORTED & (cjal | cj | cj | cjalr)); assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); @@ -173,15 +175,11 @@ module bpred ( (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | - PredInstrClassF[2] | - PredInstrClassF[1] | - PredInstrClassF[3]; + PredInstrClassF[1]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | - PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) | - (PredInstrClassF[3] & PredValidF); + PredInstrClassF[1] & PredValidF; end // Part 3 RAS @@ -191,11 +189,6 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; - //assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 - //assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 - //assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - // (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 - //assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch assign InstrClassD[0] = BranchD; assign InstrClassD[1] = JumpD ; assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5 @@ -205,7 +198,6 @@ module bpred ( flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); - flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); // branch predictor From 2dfbf15ff9169485927d43bf6d49806aa0093fa8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 19:59:03 -0800 Subject: [PATCH 265/294] fixed typo in LZC --- src/generic/lzc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index 60719c494..ecfd6796a 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -33,6 +33,6 @@ module lzc #(parameter WIDTH = 1) ( always_comb begin i = 0; while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one - ZeroCnt = i[$clog2(WIDTH)-1:0]; + ZeroCnt = i[$clog2(WIDTH+1)-1:0]; end endmodule From 51158e94bafddc7cde3557190b87ec7f51d33d9b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 12 Feb 2023 11:33:43 -0600 Subject: [PATCH 266/294] Removed another bit from btb class. --- src/ifu/bpred/RASPredictor.sv | 6 ++- src/ifu/bpred/bpred.sv | 47 ++++++++++++----------- src/ifu/bpred/btb.sv | 19 ++++----- src/ifu/bpred/speculativeglobalhistory.sv | 4 +- src/ifu/bpred/speculativegshare.sv | 5 ++- 5 files changed, 42 insertions(+), 39 deletions(-) diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 0a841ae11..40fb5bb15 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -33,8 +33,10 @@ module RASPredictor #(parameter int StackSize = 16 )( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, - input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong - input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class + input logic [2:0] WrongPredInstrClassD, // Prediction class is wrong + input logic [3:0] InstrClassD, + input logic [3:0] InstrClassE, // Instr class + input logic [2:0] PredInstrClassF, input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal output logic [`XLEN-1:0] RASPCF // Top of the stack ); diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 0a01469d2..8a1eb801b 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -72,22 +72,24 @@ module bpred ( logic PredValidF; logic [1:0] DirPredictionF; - logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD; + logic [2:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD; logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; - logic [3:0] InstrClassF, InstrClassD, InstrClassE; + logic [2:0] InstrClassF; + logic [3:0] InstrClassD; + logic [3:0] InstrClassE; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; logic [`XLEN-1:0] PCNext0F; logic [`XLEN-1:0] PCCorrectE; - logic [3:0] WrongPredInstrClassD; + logic [2:0] WrongPredInstrClassD; - logic BTBTargetWrongE; - logic RASTargetWrongE; - logic JumpOrTakenBranchE; + logic BTBTargetWrongE; + logic RASTargetWrongE; + logic JumpOrTakenBranchE; logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; @@ -149,30 +151,31 @@ module bpred ( // the branch predictor needs a compact decoding of the instruction class. if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode logic [4:0] CompressedOpcF; - logic [3:0] InstrClassF; - logic cjal, cj, cjr, cjalr; + logic [2:0] InstrClassF; + logic cjal, cj, cjr, cjalr, CJumpF, CBranchF; + logic JumpF, BranchF; assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; -// *** still need to update to use inclusive jump assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; assign cj = CompressedOpcF == 5'h0d; assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign CJumpF = cjal | cj | cjr | cjalr; + assign CBranchF = CompressedOpcF[4:1] == 4'h7; + + assign JumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; + assign BranchF = PostSpillInstrRawF[6:0] == 7'h63; - assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | - (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); - - //assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - // (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 - // (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); - assign InstrClassF[1] = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F | (`C_SUPPORTED & (cjal | cj | cj | cjalr)); - - assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + assign InstrClassF[0] = BranchF | (`C_SUPPORTED & CBranchF); + assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (cjal | cj | cj | cjalr)); + assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5 (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); - assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 - (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + //assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + // (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + + assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | PredInstrClassF[1]; @@ -206,7 +209,7 @@ module bpred ( {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); // pipeline the class - flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); + flopenrc #(3) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE); // Check the prediction @@ -218,7 +221,7 @@ module bpred ( assign PredictionPCWrongE = PCCorrectE != PCD; // branch class prediction wrong. - assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; + assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[2:0]; assign AnyWrongPredInstrClassD = |WrongPredInstrClassD; // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index c538636df..2100eb352 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -36,7 +36,7 @@ module btb #(parameter int Depth = 10 ) ( input logic StallF, StallD, StallM, FlushD, FlushM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC - output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class + output logic [2:0] BTBPredInstrClassF, // BTB's guess at instruction class output logic PredValidF, // BTB's guess is valid // update input logic AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong @@ -50,10 +50,9 @@ module btb #(parameter int Depth = 10 ) ( logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; - logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF; - logic [`XLEN+3:0] TableBTBPredictionF; + logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+2:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; - logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; logic TablePredValidF, PredValidD; @@ -80,10 +79,10 @@ module btb #(parameter int Depth = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} : - MatchD ? {PredValidD, InstrClassD, PredPCD} : - {1'b1, InstrClassE, IEUAdrE} ; + MatchD ? {PredValidD, InstrClassD[2:0], PredPCD} : + {1'b1, InstrClassE[2:0], IEUAdrE} ; - flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF}; @@ -96,14 +95,12 @@ module btb #(parameter int Depth = 10 ) ( if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex]; end - //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; - assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE; // An optimization may be using a PC relative address. - ram2p1r1wbe #(2**Depth, `XLEN+4) memory( + ram2p1r1wbe #(2**Depth, `XLEN+3) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), - .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); + .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE[2:0], IEUAdrE}), .we2(UpdateEn), .bwe2('1)); flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD}); diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv index 51dbb422b..645ac99e6 100644 --- a/src/ifu/bpred/speculativeglobalhistory.sv +++ b/src/ifu/bpred/speculativeglobalhistory.sv @@ -36,8 +36,8 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, - input logic [3:0] WrongPredInstrClassD, + input logic [3:0] InstrClassD, InstrClassE, + input logic [2:0] PredInstrClassF, WrongPredInstrClassD, input logic PCSrcE ); diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv index 1eb888a90..9d55dc874 100644 --- a/src/ifu/bpred/speculativegshare.sv +++ b/src/ifu/bpred/speculativegshare.sv @@ -37,8 +37,9 @@ module speculativegshare #(parameter int k = 10 ) ( output logic DirPredictionWrongE, // update input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, - input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, - input logic [3:0] WrongPredInstrClassD, + input logic [2:0] PredInstrClassF, + input logic [3:0] InstrClassD, InstrClassE, + input logic [2:0] WrongPredInstrClassD, input logic PCSrcE ); From 716fbca2b1009e7a6f66977da9564adb94240dd4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 11:57:25 -0600 Subject: [PATCH 267/294] Partial fix for gshare bugs from the last two weeks. --- src/ifu/bpred/bpred.sv | 2 +- src/ifu/bpred/speculativegshare.sv | 15 +++++++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 8a1eb801b..0976275bc 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -118,7 +118,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); + .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor // *** Fix me diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv index 9d55dc874..bfbd1bbd1 100644 --- a/src/ifu/bpred/speculativegshare.sv +++ b/src/ifu/bpred/speculativegshare.sv @@ -38,7 +38,7 @@ module speculativegshare #(parameter int k = 10 ) ( // update input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, input logic [2:0] PredInstrClassF, - input logic [3:0] InstrClassD, InstrClassE, + input logic [3:0] InstrClassD, InstrClassE, InstrClassM, input logic [2:0] WrongPredInstrClassD, input logic PCSrcE ); @@ -49,9 +49,9 @@ module speculativegshare #(parameter int k = 10 ) ( logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE; - logic [k-1:0] GHRF, GHRD, GHRE; + logic [k-1:0] GHRF, GHRD, GHRE, GHRM; logic GHRLastF; - logic [k-1:0] GHRNextF, GHRNextD, GHRNextE; + logic [k-1:0] GHRNextF, GHRNextD, GHRNextE, GHRNextM; logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -113,15 +113,18 @@ module speculativegshare #(parameter int k = 10 ) ( // If it is wrong and branch does exist then shift right and insert the prediction. // If the branch does not exist then shift left and use GHRLastF to restore the LSB. logic [k-1:0] GHRClassWrong; - mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong); + mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong); // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD); - mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); + mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); - flopenr #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE); + flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); + + assign GHRNextM = FlushM ? GHRM : GHRE; + flopenr #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; From 0165fd54b4a5b764073017201ecf109c57f27c23 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 16:14:17 -0600 Subject: [PATCH 268/294] Hacked commit. Fixes the gshare bugs introduced last week. Need to recover the good changes in the next commit. --- src/ifu/bpred/RASPredictor.sv | 7 +- src/ifu/bpred/bpred.sv | 363 ++++++++++++++++++++++++++++- src/ifu/bpred/btb.sv | 16 +- src/ifu/bpred/speculativegshare.sv | 4 +- 4 files changed, 368 insertions(+), 22 deletions(-) diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 40fb5bb15..330607af4 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -33,10 +33,10 @@ module RASPredictor #(parameter int StackSize = 16 )( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, - input logic [2:0] WrongPredInstrClassD, // Prediction class is wrong + input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong input logic [3:0] InstrClassD, input logic [3:0] InstrClassE, // Instr class - input logic [2:0] PredInstrClassF, + input logic [3:0] PredInstrClassF, input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal output logic [`XLEN-1:0] RASPCF // Top of the stack ); @@ -95,6 +95,3 @@ module RASPredictor #(parameter int StackSize = 16 )( endmodule - - - diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 0976275bc..b833f99ea 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -72,11 +72,11 @@ module bpred ( logic PredValidF; logic [1:0] DirPredictionF; - logic [2:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD; + logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; - logic [2:0] InstrClassF; + logic [3:0] InstrClassF; logic [3:0] InstrClassD; logic [3:0] InstrClassE; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; @@ -85,7 +85,7 @@ module bpred ( logic [`XLEN-1:0] BPPredPCF; logic [`XLEN-1:0] PCNext0F; logic [`XLEN-1:0] PCCorrectE; - logic [2:0] WrongPredInstrClassD; + logic [3:0] WrongPredInstrClassD; logic BTBTargetWrongE; logic RASTargetWrongE; @@ -149,6 +149,8 @@ module bpred ( .InstrClassE); // the branch predictor needs a compact decoding of the instruction class. + ///// ********* THIS IS NOT THE ISSUE. +/* -----\/----- EXCLUDED -----\/----- if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode logic [4:0] CompressedOpcF; logic [2:0] InstrClassF; @@ -184,6 +186,44 @@ module bpred ( assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | PredInstrClassF[1] & PredValidF; end + -----/\----- EXCLUDED -----/\----- */ + // the branch predictor needs a compact decoding of the instruction class. + if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode + logic [4:0] CompressedOpcF; + logic [3:0] InstrClassF; + logic cjal, cj, cjr, cjalr; + + assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; + + assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; + assign cj = CompressedOpcF == 5'h0d; + assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + + assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | + (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); + + assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 + (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); + + assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); + + assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + assign PredInstrClassF = InstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | + PredInstrClassF[2] | + PredInstrClassF[1] | + PredInstrClassF[3]; + end else begin + assign PredInstrClassF = BTBPredInstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | + PredInstrClassF[2] | + (PredInstrClassF[1] & PredValidF) | + (PredInstrClassF[3] & PredValidF); + end // Part 3 RAS RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, @@ -192,10 +232,17 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; +/* -----\/----- EXCLUDED -----\/----- assign InstrClassD[0] = BranchD; assign InstrClassD[1] = JumpD ; assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5 assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 + -----/\----- EXCLUDED -----/\----- */ + assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 + assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 + assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 + assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch @@ -209,8 +256,10 @@ module bpred ( {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); // pipeline the class - flopenrc #(3) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); - flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE); + flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); + //flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE); + flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE); + assign AnyWrongPredInstrClassE = InstrClassE != PredInstrClassE; // Check the prediction // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address. @@ -221,11 +270,12 @@ module bpred ( assign PredictionPCWrongE = PCCorrectE != PCD; // branch class prediction wrong. - assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[2:0]; + assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[3:0]; assign AnyWrongPredInstrClassD = |WrongPredInstrClassD; // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. - assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; + assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | (AnyWrongPredInstrClassE & ~|InstrClassE); + //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; // Output the predicted PC or corrected PC on miss-predict. // Selects the BP or PC+2/4. @@ -265,3 +315,302 @@ module bpred ( flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); endmodule +/* -----\/----- EXCLUDED -----\/----- +/////////////////////////////////////////// +// bpred.sv +// +// Written: Ross Thomposn ross1728@gmail.com +// Created: 12 February 2021 +// Modified: 19 January 2023 +// +// Purpose: Branch direction prediction and jump/branch target prediction. +// Prediction made during the fetch stage and corrected in the execution stage. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +`define INSTR_CLASS_PRED 1 + +module bpred ( + input logic clk, reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, + // Fetch stage + // the prediction + input logic InstrValidD, InstrValidE, + input logic BranchD, BranchE, + input logic JumpD, JumpE, + input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class + input logic [`XLEN-1:0] PCNextF, // Next Fetch Address + input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 + output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction + output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage + + // Update Predictor + input logic [`XLEN-1:0] PCF, // Fetch stage instruction address + input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took + input logic [`XLEN-1:0] PCE, // Execution stage instruction address + input logic [`XLEN-1:0] PCM, // Memory stage instruction address + + input logic [31:0] PostSpillInstrRawF, // Instruction + + // Branch and jump outcome + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) + output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + + // Report branch prediction status + output logic BPPredWrongE, // Prediction is wrong + output logic BPPredWrongM, // Prediction is wrong + output logic DirPredictionWrongM, // Prediction direction is wrong + output logic BTBPredPCWrongM, // Prediction target wrong + output logic RASPredPCWrongM, // RAS prediction is wrong + output logic PredictionInstrClassWrongM // Class prediction is wrong + ); + + logic PredValidF; + logic [1:0] DirPredictionF; + + logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; + logic [`XLEN-1:0] PredPCF, RASPCF; + logic TargetWrongE; + logic FallThroughWrongE; + logic PredictionPCWrongE; + logic PredictionInstrClassWrongE; + logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; + logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; + + logic SelBPPredF; + logic [`XLEN-1:0] BPPredPCF; + logic [`XLEN-1:0] PCNext0F; + logic [`XLEN-1:0] PCCorrectE; + logic [3:0] WrongPredInstrClassD; + + + logic BTBTargetWrongE; + logic RASTargetWrongE; + logic JumpOrTakenBranchE; + + logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; + + // Part 1 branch direction prediction + // look into the 2 port Sram model. something is wrong. + if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor + twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, + .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); + + end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor + globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, + .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); + +/-* -----\/----- EXCLUDED -----\/----- + end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor + speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .DirPredictionF, .DirPredictionWrongE, + .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), + .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); + + end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor + gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, + .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); + -----/\----- EXCLUDED -----/\----- *-/ + + end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor + speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, + .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE); + + end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor + // *** Fix me +/-* -----\/----- EXCLUDED -----\/----- + localHistoryPredictor DirPredictor(.clk, + .reset, .StallF, .StallE, + .LookUpPC(PCNextF), + .Prediction(DirPredictionF), + // update + .UpdatePC(PCE), + .UpdateEN(InstrClassE[0] & ~StallE), + .PCSrcE, + .UpdatePrediction(InstrClassE[0])); + -----/\----- EXCLUDED -----/\----- *-/ + end + + // this predictor will have two pieces of data, + // 1) A direction (1 = Taken, 0 = Not Taken) + // 2) Any information which is necessary for the predictor to build its next state. + // For a 2 bit table this is the prediction count. + + // Part 2 Branch target address prediction + // *** For now the BTB will house the direct and indirect targets + + btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, + .PCNextF, .PCF, .PCD, .PCE, + .PredPCF, + .BTBPredInstrClassF, + .PredValidF, + .AnyWrongPredInstrClassE(PredictionInstrClassWrongE), + .IEUAdrE, + .InstrClassD, + .InstrClassE); + + // the branch predictor needs a compact decoding of the instruction class. + if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode + logic [4:0] CompressedOpcF; + logic [3:0] InstrClassF; + logic cjal, cj, cjr, cjalr; + + assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; + + assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; + assign cj = CompressedOpcF == 5'h0d; + assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + + assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | + (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); + + assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 + (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); + + assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); + + assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + assign PredInstrClassF = InstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | + PredInstrClassF[2] | + PredInstrClassF[1] | + PredInstrClassF[3]; + end else begin + assign PredInstrClassF = BTBPredInstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | + PredInstrClassF[2] | + (PredInstrClassF[1] & PredValidF) | + (PredInstrClassF[3] & PredValidF); + end + + // Part 3 RAS + RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .PredInstrClassF, .InstrClassD, .InstrClassE, + .WrongPredInstrClassD, .RASPCF, .PCLinkE); + + assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; + + assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 + assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 + assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 + assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch + + flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); + flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); + flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); + flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); + + // branch predictor + flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, + {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE}, + {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); + + // pipeline the class + flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); + flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE); + + // Check the prediction + // first check if the target or fallthrough address matches what was predicted. + assign TargetWrongE = IEUAdrE != PCD; + assign FallThroughWrongE = PCLinkE != PCD; + // If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected + // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi + // it must have selected the fall through. + assign PredictionPCWrongE = PCCorrectE != PCD; + +// assign PredictionPCWrongE = (PCSrcE & (|InstrClassE) ? TargetWrongE : FallThroughWrongE); + + // The branch direction also need to checked. + // However if the direction is wrong then the pc will be wrong. This is only relavent to checking the + // accuracy of the direciton prediction. + //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0]; + + // Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated. + // Also we want to track this in a performance counter. + assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE; + + // We want to output to the instruction fetch if the PC fetched was wrong. If by chance the predictor was wrong about + // the direction or class, but correct about the target we don't have the flush the pipeline. However we still + // need this information to verify the accuracy of the predictors. + assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE; +// assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; + + // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. + //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; + //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE; + assign BTBPredPCWrongE = BTBTargetWrongE; + + // similar with RAS. Over counts ras if the class prediction was wrong. + //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE; + assign RASPredPCWrongE = RASTargetWrongE; + // Finally if the real instruction class is non CFI but the predictor said it was we need to count. + assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; + + // branch class prediction wrong. + assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; + + // Selects the BP or PC+2/4. + mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); + // If the prediction is wrong select the correct address. + mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F); + // Correct branch/jump target. + mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); + + // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. + // Effectively this is PCM+4 or the non-existant PCLinkM + // if(`BPCLASS) begin + mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); + // end else begin + // assign NextValidPCE = PCE; + // end + + // performance counters + // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now + // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) + // 3. target ras (ras target wrong / class[2]) + // 4. direction (br dir wrong / class[0]) + + assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; + + assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; + + flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE); + + flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); + flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); + +endmodule + -----/\----- EXCLUDED -----/\----- */ diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 2100eb352..7893ace5f 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -36,7 +36,7 @@ module btb #(parameter int Depth = 10 ) ( input logic StallF, StallD, StallM, FlushD, FlushM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC - output logic [2:0] BTBPredInstrClassF, // BTB's guess at instruction class + output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class output logic PredValidF, // BTB's guess is valid // update input logic AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong @@ -50,8 +50,8 @@ module btb #(parameter int Depth = 10 ) ( logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; - logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; - logic [`XLEN+2:0] TableBTBPredictionF; + logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; logic UpdateEn; logic TablePredValidF, PredValidD; @@ -79,10 +79,10 @@ module btb #(parameter int Depth = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} : - MatchD ? {PredValidD, InstrClassD[2:0], PredPCD} : - {1'b1, InstrClassE[2:0], IEUAdrE} ; + MatchD ? {PredValidD, InstrClassD, PredPCD} : + {1'b1, InstrClassE, IEUAdrE} ; - flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF}; @@ -98,9 +98,9 @@ module btb #(parameter int Depth = 10 ) ( assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE; // An optimization may be using a PC relative address. - ram2p1r1wbe #(2**Depth, `XLEN+3) memory( + ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), - .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE[2:0], IEUAdrE}), .we2(UpdateEn), .bwe2('1)); + .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD}); diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv index bfbd1bbd1..1dd7d4cdb 100644 --- a/src/ifu/bpred/speculativegshare.sv +++ b/src/ifu/bpred/speculativegshare.sv @@ -37,9 +37,9 @@ module speculativegshare #(parameter int k = 10 ) ( output logic DirPredictionWrongE, // update input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, - input logic [2:0] PredInstrClassF, + input logic [3:0] PredInstrClassF, input logic [3:0] InstrClassD, InstrClassE, InstrClassM, - input logic [2:0] WrongPredInstrClassD, + input logic [3:0] WrongPredInstrClassD, input logic PCSrcE ); From 1cfdd201a5fd358afd389bbbd85cb6f72f6f7d57 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 17:10:24 -0600 Subject: [PATCH 269/294] Partial improvement. --- src/ifu/bpred/bpred.sv | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index b833f99ea..a6cb0ccb2 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -220,9 +220,7 @@ module bpred ( end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | - PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) | - (PredInstrClassF[3] & PredValidF); + PredInstrClassF[1] & PredValidF; end // Part 3 RAS @@ -232,17 +230,18 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; -/* -----\/----- EXCLUDED -----\/----- assign InstrClassD[0] = BranchD; assign InstrClassD[1] = JumpD ; assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5 assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 - -----/\----- EXCLUDED -----/\----- */ + +/* -----\/----- EXCLUDED -----\/----- assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch + -----/\----- EXCLUDED -----/\----- */ @@ -274,7 +273,7 @@ module bpred ( assign AnyWrongPredInstrClassD = |WrongPredInstrClassD; // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. - assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | (AnyWrongPredInstrClassE & ~|InstrClassE); + assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE)); //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; // Output the predicted PC or corrected PC on miss-predict. From 10b45ed6c7c217d4cf551eedd0cf295195b49ffe Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 17:23:56 -0600 Subject: [PATCH 270/294] Further branch predictor improvements. --- src/ifu/bpred/bpred.sv | 59 +++--------------------------------------- 1 file changed, 4 insertions(+), 55 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index a6cb0ccb2..c86c09790 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -149,11 +149,9 @@ module bpred ( .InstrClassE); // the branch predictor needs a compact decoding of the instruction class. - ///// ********* THIS IS NOT THE ISSUE. -/* -----\/----- EXCLUDED -----\/----- if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode logic [4:0] CompressedOpcF; - logic [2:0] InstrClassF; + logic [3:0] InstrClassF; logic cjal, cj, cjr, cjalr, CJumpF, CBranchF; logic JumpF, BranchF; @@ -174,49 +172,12 @@ module bpred ( assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5 (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); - //assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 - // (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); - - - assign PredInstrClassF = InstrClassF; - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | - PredInstrClassF[1]; - end else begin - assign PredInstrClassF = BTBPredInstrClassF; - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | - PredInstrClassF[1] & PredValidF; - end - -----/\----- EXCLUDED -----/\----- */ - // the branch predictor needs a compact decoding of the instruction class. - if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode - logic [4:0] CompressedOpcF; - logic [3:0] InstrClassF; - logic cjal, cj, cjr, cjalr; - - assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; - - assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; - assign cj = CompressedOpcF == 5'h0d; - assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - - assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | - (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); - - assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 - (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); - - assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 - (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); - - assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | - PredInstrClassF[2] | PredInstrClassF[1] | - PredInstrClassF[3]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | @@ -235,16 +196,6 @@ module bpred ( assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5 assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 -/* -----\/----- EXCLUDED -----\/----- - assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 - assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 - assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 - assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch - -----/\----- EXCLUDED -----/\----- */ - - - flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); @@ -256,9 +207,8 @@ module bpred ( // pipeline the class flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); - //flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE); + flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE); flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE); - assign AnyWrongPredInstrClassE = InstrClassE != PredInstrClassE; // Check the prediction // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address. @@ -299,7 +249,6 @@ module bpred ( // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - //assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; From c18ac35332d361260562050f7dc8abe46cf21d96 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 17:29:51 -0600 Subject: [PATCH 271/294] Created copy of gshare. I think there may be a simpler implementation. --- src/ifu/bpred/bpred.sv | 304 +---------------------------------- src/ifu/bpred/gshare_copy.sv | 80 +++++++++ testbench/tests.vh | 2 +- 3 files changed, 83 insertions(+), 303 deletions(-) create mode 100644 src/ifu/bpred/gshare_copy.sv diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index c86c09790..69bec3e73 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -76,7 +76,6 @@ module bpred ( logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; - logic [3:0] InstrClassF; logic [3:0] InstrClassD; logic [3:0] InstrClassE; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; @@ -177,7 +176,7 @@ module bpred ( assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | - PredInstrClassF[1] | + PredInstrClassF[1]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | @@ -224,7 +223,7 @@ module bpred ( // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE)); - //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; + //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark // Output the predicted PC or corrected PC on miss-predict. // Selects the BP or PC+2/4. @@ -263,302 +262,3 @@ module bpred ( flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); endmodule -/* -----\/----- EXCLUDED -----\/----- -/////////////////////////////////////////// -// bpred.sv -// -// Written: Ross Thomposn ross1728@gmail.com -// Created: 12 February 2021 -// Modified: 19 January 2023 -// -// Purpose: Branch direction prediction and jump/branch target prediction. -// Prediction made during the fetch stage and corrected in the execution stage. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -`define INSTR_CLASS_PRED 1 - -module bpred ( - input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - // Fetch stage - // the prediction - input logic InstrValidD, InstrValidE, - input logic BranchD, BranchE, - input logic JumpD, JumpE, - input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class - input logic [`XLEN-1:0] PCNextF, // Next Fetch Address - input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 - output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction - output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage - - // Update Predictor - input logic [`XLEN-1:0] PCF, // Fetch stage instruction address - input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took - input logic [`XLEN-1:0] PCE, // Execution stage instruction address - input logic [`XLEN-1:0] PCM, // Memory stage instruction address - - input logic [31:0] PostSpillInstrRawF, // Instruction - - // Branch and jump outcome - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) - output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br - output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br - - // Report branch prediction status - output logic BPPredWrongE, // Prediction is wrong - output logic BPPredWrongM, // Prediction is wrong - output logic DirPredictionWrongM, // Prediction direction is wrong - output logic BTBPredPCWrongM, // Prediction target wrong - output logic RASPredPCWrongM, // RAS prediction is wrong - output logic PredictionInstrClassWrongM // Class prediction is wrong - ); - - logic PredValidF; - logic [1:0] DirPredictionF; - - logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; - logic [`XLEN-1:0] PredPCF, RASPCF; - logic TargetWrongE; - logic FallThroughWrongE; - logic PredictionPCWrongE; - logic PredictionInstrClassWrongE; - logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; - logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; - - logic SelBPPredF; - logic [`XLEN-1:0] BPPredPCF; - logic [`XLEN-1:0] PCNext0F; - logic [`XLEN-1:0] PCCorrectE; - logic [3:0] WrongPredInstrClassD; - - - logic BTBTargetWrongE; - logic RASTargetWrongE; - logic JumpOrTakenBranchE; - - logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; - - // Part 1 branch direction prediction - // look into the 2 port Sram model. something is wrong. - if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor - twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - - end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor - globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - -/-* -----\/----- EXCLUDED -----\/----- - end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor - speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .DirPredictionF, .DirPredictionWrongE, - .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), - .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); - - end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor - gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - -----/\----- EXCLUDED -----/\----- *-/ - - end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor - speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE); - - end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor - // *** Fix me -/-* -----\/----- EXCLUDED -----\/----- - localHistoryPredictor DirPredictor(.clk, - .reset, .StallF, .StallE, - .LookUpPC(PCNextF), - .Prediction(DirPredictionF), - // update - .UpdatePC(PCE), - .UpdateEN(InstrClassE[0] & ~StallE), - .PCSrcE, - .UpdatePrediction(InstrClassE[0])); - -----/\----- EXCLUDED -----/\----- *-/ - end - - // this predictor will have two pieces of data, - // 1) A direction (1 = Taken, 0 = Not Taken) - // 2) Any information which is necessary for the predictor to build its next state. - // For a 2 bit table this is the prediction count. - - // Part 2 Branch target address prediction - // *** For now the BTB will house the direct and indirect targets - - btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, - .PCNextF, .PCF, .PCD, .PCE, - .PredPCF, - .BTBPredInstrClassF, - .PredValidF, - .AnyWrongPredInstrClassE(PredictionInstrClassWrongE), - .IEUAdrE, - .InstrClassD, - .InstrClassE); - - // the branch predictor needs a compact decoding of the instruction class. - if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode - logic [4:0] CompressedOpcF; - logic [3:0] InstrClassF; - logic cjal, cj, cjr, cjalr; - - assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; - - assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; - assign cj = CompressedOpcF == 5'h0d; - assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - - assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | - (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); - - assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 - (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); - - assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 - (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); - - assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 - (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); - assign PredInstrClassF = InstrClassF; - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | - PredInstrClassF[2] | - PredInstrClassF[1] | - PredInstrClassF[3]; - end else begin - assign PredInstrClassF = BTBPredInstrClassF; - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | - PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) | - (PredInstrClassF[3] & PredValidF); - end - - // Part 3 RAS - RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PredInstrClassF, .InstrClassD, .InstrClassE, - .WrongPredInstrClassD, .RASPCF, .PCLinkE); - - assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; - - assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 - assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 - assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 - assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch - - flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); - flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); - flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); - flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); - - // branch predictor - flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE}, - {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); - - // pipeline the class - flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); - flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE); - - // Check the prediction - // first check if the target or fallthrough address matches what was predicted. - assign TargetWrongE = IEUAdrE != PCD; - assign FallThroughWrongE = PCLinkE != PCD; - // If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected - // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi - // it must have selected the fall through. - assign PredictionPCWrongE = PCCorrectE != PCD; - -// assign PredictionPCWrongE = (PCSrcE & (|InstrClassE) ? TargetWrongE : FallThroughWrongE); - - // The branch direction also need to checked. - // However if the direction is wrong then the pc will be wrong. This is only relavent to checking the - // accuracy of the direciton prediction. - //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0]; - - // Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated. - // Also we want to track this in a performance counter. - assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE; - - // We want to output to the instruction fetch if the PC fetched was wrong. If by chance the predictor was wrong about - // the direction or class, but correct about the target we don't have the flush the pipeline. However we still - // need this information to verify the accuracy of the predictors. - assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE; -// assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; - - // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. - //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; - //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE; - assign BTBPredPCWrongE = BTBTargetWrongE; - - // similar with RAS. Over counts ras if the class prediction was wrong. - //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE; - assign RASPredPCWrongE = RASTargetWrongE; - // Finally if the real instruction class is non CFI but the predictor said it was we need to count. - assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; - - // branch class prediction wrong. - assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; - - // Selects the BP or PC+2/4. - mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); - // If the prediction is wrong select the correct address. - mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F); - // Correct branch/jump target. - mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); - - // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. - // Effectively this is PCM+4 or the non-existant PCLinkM - // if(`BPCLASS) begin - mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); - // end else begin - // assign NextValidPCE = PCE; - // end - - // performance counters - // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now - // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) - // 3. target ras (ras target wrong / class[2]) - // 4. direction (br dir wrong / class[0]) - - assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; - assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; - - assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; - - flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); - flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE); - - flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); - flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); - -endmodule - -----/\----- EXCLUDED -----/\----- */ diff --git a/src/ifu/bpred/gshare_copy.sv b/src/ifu/bpred/gshare_copy.sv new file mode 100644 index 000000000..119056c83 --- /dev/null +++ b/src/ifu/bpred/gshare_copy.sv @@ -0,0 +1,80 @@ +/////////////////////////////////////////// +// globalHistoryPredictor.sv +// +// Written: Shreya Sanghai +// Email: ssanghai@hmc.edu +// Created: March 16, 2021 +// Modified: +// +// Purpose: Global History Branch predictor with parameterized global history register +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module gshare_copy #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCE, + input logic BranchInstrE, BranchInstrM, PCSrcE +); + + logic [k-1:0] IndexNextF, IndexE; + logic [1:0] DirPredictionD, DirPredictionE; + logic [1:0] NewDirPredictionE, NewDirPredictionM; + + logic [k-1:0] GHRF, GHRD, GHRE, GHR; + logic [k-1:0] GHRNext; + logic PCSrcM; + + assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; + + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + .ce1(~StallF), .ce2(~StallM & ~FlushM), + .ra1(IndexNextF), + .rd1(DirPredictionF), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), + .bwe2(1'b1)); + + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE); + + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM); + + assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; + + assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR; + flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR); + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); + + flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); + flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); + flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); + + +endmodule diff --git a/testbench/tests.vh b/testbench/tests.vh index 1e1065cf1..ec6f04f43 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -50,9 +50,9 @@ string tvpaths[] = '{ string embench[] = '{ `EMBENCH, + "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/aha-mont64/aha-mont64", "bd_speedopt_speed/src/crc32/crc32", - "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/edn/edn", "bd_speedopt_speed/src/huffbench/huffbench", "bd_speedopt_speed/src/matmult-int/matmult-int", From 1ab2d0d19bcd27af5f8ec7a44b45dcc7f5974680 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 17:57:05 -0600 Subject: [PATCH 272/294] Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now. --- src/ifu/bpred/gshare.sv | 4 ++-- src/ifu/bpred/gshare_copy.sv | 20 +++++++++++--------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index fde1a0825..4cffbf93d 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -48,8 +48,8 @@ module gshare #(parameter k = 10) ( logic [k-1:0] GHRNext; logic PCSrcM; - assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; + assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), diff --git a/src/ifu/bpred/gshare_copy.sv b/src/ifu/bpred/gshare_copy.sv index 119056c83..d73bce20b 100644 --- a/src/ifu/bpred/gshare_copy.sv +++ b/src/ifu/bpred/gshare_copy.sv @@ -31,16 +31,16 @@ module gshare_copy #(parameter k = 10) ( input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCE, + input logic [`XLEN-1:0] PCNextF, PCM, input logic BranchInstrE, BranchInstrM, PCSrcE ); - logic [k-1:0] IndexNextF, IndexE; + logic [k-1:0] IndexNextF, IndexM; logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; @@ -48,16 +48,16 @@ module gshare_copy #(parameter k = 10) ( logic [k-1:0] GHRNext; logic PCSrcM; - assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; + assign IndexNextF = GHRNext ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexM = GHR ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), - .wa2(IndexE), - .wd2(NewDirPredictionE), - .we2(BranchInstrE & ~StallM & ~FlushM), + .wa2(IndexM), + .wd2(NewDirPredictionM), + .we2(BranchInstrM & ~StallW & ~FlushW), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -72,9 +72,11 @@ module gshare_copy #(parameter k = 10) ( flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); +/* -----\/----- EXCLUDED -----\/----- flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); + -----/\----- EXCLUDED -----/\----- */ endmodule From 3847d9e39a91fcf49d27fc3cf9fe939303450186 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 18:07:32 -0600 Subject: [PATCH 273/294] Updated global history predictor. --- src/ifu/bpred/speculativeglobalhistory.sv | 25 ++++++++++++++--------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv index 645ac99e6..1ddd3dfe4 100644 --- a/src/ifu/bpred/speculativeglobalhistory.sv +++ b/src/ifu/bpred/speculativeglobalhistory.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// speculativeglobalhistory.sv +// gsharePredictor.sv // // Written: Shreya Sanghai // Email: ssanghai@hmc.edu @@ -36,8 +36,10 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [3:0] InstrClassD, InstrClassE, - input logic [2:0] PredInstrClassF, WrongPredInstrClassD, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, + input logic [3:0] PredInstrClassF, + input logic [3:0] InstrClassD, InstrClassE, InstrClassM, + input logic [3:0] WrongPredInstrClassD, input logic PCSrcE ); @@ -47,9 +49,9 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE; - logic [k-1:0] GHRF, GHRD, GHRE; + logic [k-1:0] GHRF, GHRD, GHRE, GHRM; logic GHRLastF; - logic [k-1:0] GHRNextF, GHRNextD, GHRNextE; + logic [k-1:0] GHRNextF, GHRNextD, GHRNextE, GHRNextM; logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -57,8 +59,8 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( assign IndexNextF = GHRNextF; assign IndexF = GHRF; - assign IndexD = GHRD[k-1:0]; - assign IndexE = GHRE[k-1:0]; + assign IndexD = GHRD; + assign IndexE = GHRE; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), @@ -111,15 +113,18 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( // If it is wrong and branch does exist then shift right and insert the prediction. // If the branch does not exist then shift left and use GHRLastF to restore the LSB. logic [k-1:0] GHRClassWrong; - mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong); + mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong); // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD); - mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); + mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); - flopenr #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE); + flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); + + assign GHRNextM = FlushM ? GHRM : GHRE; + flopenr #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; From 6ea830cf44a9d9aa1b5d9a0a656e2c8a34e6f7aa Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 18:08:13 -0600 Subject: [PATCH 274/294] Fixed global history predictor. --- src/ifu/bpred/speculativeglobalhistory.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv index 1ddd3dfe4..8ebda61c5 100644 --- a/src/ifu/bpred/speculativeglobalhistory.sv +++ b/src/ifu/bpred/speculativeglobalhistory.sv @@ -36,7 +36,6 @@ module speculativeglobalhistory #(parameter int k = 10 ) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, input logic [3:0] PredInstrClassF, input logic [3:0] InstrClassD, InstrClassE, InstrClassM, input logic [3:0] WrongPredInstrClassD, From f3c8c6e60a7c4998dbdbf65daef96e91e1e876fd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 18:08:51 -0600 Subject: [PATCH 275/294] More fixeds to global history. --- src/ifu/bpred/bpred.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 69bec3e73..a88845efb 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -107,7 +107,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); + .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, From fc3baa684684e8ad23f9a07a2dae05367f8edca5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 13 Feb 2023 18:52:52 -0600 Subject: [PATCH 276/294] Updated gshare (no speculation) to have better performance. --- src/ifu/bpred/bpred.sv | 4 +- src/ifu/bpred/gshare.sv | 17 ++++---- src/ifu/bpred/gshare_copy.sv | 80 ------------------------------------ 3 files changed, 11 insertions(+), 90 deletions(-) delete mode 100644 src/ifu/bpred/gshare_copy.sv diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 69bec3e73..6ed6c8c86 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -110,8 +110,8 @@ module bpred ( .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor - gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, + gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index fde1a0825..35a73fb04 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -31,12 +31,12 @@ module gshare #(parameter k = 10) ( input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCE, + input logic [`XLEN-1:0] PCNextF, PCM, input logic BranchInstrE, BranchInstrM, PCSrcE ); @@ -44,20 +44,20 @@ module gshare #(parameter k = 10) ( logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHR; + logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; logic [k-1:0] GHRNext; logic PCSrcM; - assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; + assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), .wa2(IndexE), - .wd2(NewDirPredictionE), - .we2(BranchInstrE & ~StallM & ~FlushM), + .wd2(NewDirPredictionM), + .we2(BranchInstrM & ~StallW & ~FlushW), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -75,6 +75,7 @@ module gshare #(parameter k = 10) ( flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); + flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); endmodule diff --git a/src/ifu/bpred/gshare_copy.sv b/src/ifu/bpred/gshare_copy.sv deleted file mode 100644 index 119056c83..000000000 --- a/src/ifu/bpred/gshare_copy.sv +++ /dev/null @@ -1,80 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module gshare_copy #(parameter k = 10) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCE, - input logic BranchInstrE, BranchInstrM, PCSrcE -); - - logic [k-1:0] IndexNextF, IndexE; - logic [1:0] DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE, NewDirPredictionM; - - logic [k-1:0] GHRF, GHRD, GHRE, GHR; - logic [k-1:0] GHRNext; - logic PCSrcM; - - assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; - - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF), .ce2(~StallM & ~FlushM), - .ra1(IndexNextF), - .rd1(DirPredictionF), - .wa2(IndexE), - .wd2(NewDirPredictionE), - .we2(BranchInstrE & ~StallM & ~FlushM), - .bwe2(1'b1)); - - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE); - - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - - assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR; - flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR); - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - - flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); - flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); - flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - - -endmodule From 237a1153770dbee3feb459177dbc2817a69b31db Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 15 Feb 2023 11:12:30 +0000 Subject: [PATCH 277/294] add files to support coverage --- sim/imperas.ic | 1 - sim/wally-imperas-cov.do | 68 ++++++++++++++++++++++++++++++++++ sim/wally-imperas.do | 1 + testbench/testbench_imperas.sv | 1 + 4 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 sim/wally-imperas-cov.do diff --git a/sim/imperas.ic b/sim/imperas.ic index 302773d0e..d28234bbc 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,6 +1,5 @@ --override cpu/show_c_prefix=T --override cpu/unaligned=F ---override cpu/mstatus_FS=1 --override cpu/ignore_non_leaf_DAU=1 # Enable the Imperas instruction coverage diff --git a/sim/wally-imperas-cov.do b/sim/wally-imperas-cov.do new file mode 100644 index 000000000..9ac7a39e4 --- /dev/null +++ b/sim/wally-imperas-cov.do @@ -0,0 +1,68 @@ +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals + # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. +vlog +incdir+../config/$1 \ + +incdir+../config/shared \ + +define+USE_IMPERAS_DV \ + +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ + +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + \ + +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \ + +define+COVER_RV64I \ + +define+COVER_RV64C \ + +define+COVER_RV64M \ + +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ + \ + ../testbench/testbench_imperas.sv \ + ../testbench/common/*.sv \ + ../src/*/*.sv \ + ../src/*/*/*.sv \ + -suppress 2583 \ + -suppress 7063 \ + +acc +vopt +acc work.testbench -G DEBUG=1 -o workopt +vsim workopt +nowarn3829 -fatal 7 \ + -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ + +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \ + -do "coverage save -onexit ./riscv.ucdb" + +view wave +#-- display input and output signals as hexidecimal values +# add log -recursive /* +# do wave.do + +run -all + +noview ../testbench/testbench_imperas.sv +view wave + +quit -f diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index 4164b7bdb..d10c57d57 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -34,6 +34,7 @@ vlog +incdir+../config/$1 \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ ../testbench/testbench_imperas.sv \ ../testbench/common/*.sv \ ../src/*/*.sv \ diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index e52a79c2e..c7d987b83 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -125,6 +125,7 @@ module testbench; `ifdef USE_IMPERAS_DV trace2log idv_trace2log(rvvi); + trace2cov idv_trace2cov(rvvi); // enabling of comparison types trace2api #(.CMP_PC (1), From a3aeff2703e33e1328fb87b666d1f182b2475fd3 Mon Sep 17 00:00:00 2001 From: James Stine Date: Wed, 15 Feb 2023 18:12:12 -0600 Subject: [PATCH 278/294] Update if-then-else for ram items --- src/generic/mem/ram1p1rwbe.sv | 14 +++++++------- src/generic/mem/ram2p1r1wbe.sv | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index e33e708a3..f1e784c13 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -55,10 +55,10 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - + end else if (`USE_SRAM == 1 && WIDTH == 44 && DEPTH == 64) begin genvar index; // 64 x 44-bit SRAM @@ -69,15 +69,15 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin + end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + ram1p1rwbe_128x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); end else if (`USE_SRAM == 1 && WIDTH == 22 && DEPTH == 32) begin genvar index; @@ -85,7 +85,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 08c232bba..da099cdc7 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), From 9e83b0bfafd4a02eccc46e7fdf98e41ced59962f Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 16 Feb 2023 08:07:17 -0600 Subject: [PATCH 279/294] Update topo psyn stuff --- synthDC/.synopsys_dc.setup | 20 ++++++++++++++++++++ synthDC/Makefile | 4 +++- synthDC/scripts/synth.tcl | 30 ++++++++++++++++++++++++++++++ synthDC/wallySynth.py | 4 ++-- 4 files changed, 55 insertions(+), 3 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 2fdc11c27..1310c4dd7 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -21,6 +21,21 @@ if {$tech == "sky130"} { set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a lappend search_path $s10lib } +elseif {$tech == "tsmc28psyn"} { + set TLU /home/jstine/TLU+ + set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a + lappend search_path $s10lib + set TLUPLUS true + set mw_logic1_net VDD + set mw_logic0_net VSS + set TLU_PDK /import/yukari1/jstine/TLU+/ + set CAPTABLE $TLU/1p8m/ + set MW_REFERENCE_LIBRARY /home/jstine/MW + set MW_TECH_FILE tcbn28hpcplusbwp7t30p140 + set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_typical.tluplus + set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus + set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map +} # Synthetic libraries set synthetic_library [list dw_foundation.sldb] @@ -36,6 +51,11 @@ if {$tech == "sky130"} { } elseif {$tech == "tsmc28"} { lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db } +} elseif {$tech == "tsmc28psyn"} { + set mw_reference_library [list ] + lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db + lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp7t30p140 +} # Set Link Library set link_library "$target_library $synthetic_library" diff --git a/synthDC/Makefile b/synthDC/Makefile index 76531d950..d7fb2b914 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -122,6 +122,8 @@ synth: mkdirecs configs rundc clean rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out +rundctopo: + dc_shell-xg-t -64bit -topographical_mode -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out clean: rm -rf $(OUTPUTDIR)/hdl @@ -132,4 +134,4 @@ clean: rm -f filenames*.log rm -f power.saif rm -f Synopsys_stack_trace_*.txt - rm -f crte_*.txt \ No newline at end of file + rm -f crte_*.txt diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 1040f35ce..830203520 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -49,6 +49,36 @@ set report_default_significant_digits 6 set verilogout_show_unconnected_pins "true" set vhdlout_show_unconnected_pins "true" +# Set up MW List +set MY_LIB_NAME $my_toplevel +# Create MW +if { [shell_is_in_topographical_mode] } { + echo "In Topographical Mode...processing\n" + if {[file isdirectory $MY_LIB_NAME]} { + echo "MW directory already here, deleting/readdding." + [exec rm -rf $my_toplevel] + create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ + -mw_reference_library $mw_reference_library $MY_LIB_NAME + } else { + create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ + -mw_reference_library $mw_reference_library $MY_LIB_NAME + } + + # Open MW + open_mw_lib $MY_LIB_NAME + + # TLU+ + set_tlu_plus_files -max_tluplus $MAX_TLU_FILE -min_tluplus $MIN_TLU_FILE \ + -tech2itf_map $PRS_MAP_FILE + +} else { + if {[file isdirectory $MY_LIB_NAME]} { + [exec rm -rf $my_toplevel] + echo "MW directory already here, deleting." + } + echo "In normal DC mode...processing\n" +} + # Due to parameterized Verilog must use analyze/elaborate and not # read_verilog/vhdl (change to pull in Verilog and/or VHDL) # diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 3253607d5..cfcfde788 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -16,7 +16,7 @@ def mask(command): if __name__ == '__main__': - techs = ['sky90', 'tsmc28'] + techs = ['sky90', 'tsmc28', 'tsmc28psyn'] allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] @@ -61,4 +61,4 @@ if __name__ == '__main__': defaultfreq = 500 if tech == 'sky90' else 1500 freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' - runSynth(config, mod, tech, freq, maxopt, usesram) \ No newline at end of file + runSynth(config, mod, tech, freq, maxopt, usesram) From 14c6cfb24d514b794bca7468c177b21e860f7d71 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 16 Feb 2023 13:38:26 -0600 Subject: [PATCH 280/294] Fix bugs in scripts for synthesis and tsmc28 psyn --- synthDC/.synopsys_dc.setup | 13 +++++++------ synthDC/wallySynth.py | 14 ++++++++------ 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 1310c4dd7..6942e58e6 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -18,20 +18,22 @@ if {$tech == "sky130"} { set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib lappend search_path $s9lib } elseif {$tech == "tsmc28"} { - set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a + set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/ + set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a lappend search_path $s10lib } elseif {$tech == "tsmc28psyn"} { set TLU /home/jstine/TLU+ - set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a + set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/ + set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a lappend search_path $s10lib set TLUPLUS true set mw_logic1_net VDD set mw_logic0_net VSS - set TLU_PDK /import/yukari1/jstine/TLU+/ + set TLU_PDK /home/jstine/TLU+/ set CAPTABLE $TLU/1p8m/ set MW_REFERENCE_LIBRARY /home/jstine/MW - set MW_TECH_FILE tcbn28hpcplusbwp7t30p140 + set MW_TECH_FILE tcbn28hpcplusbwp30p140 set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_typical.tluplus set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map @@ -50,11 +52,10 @@ if {$tech == "sky130"} { lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db } elseif {$tech == "tsmc28"} { lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db -} } elseif {$tech == "tsmc28psyn"} { set mw_reference_library [list ] lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db - lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp7t30p140 + lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140 } # Set Link Library diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index cfcfde788..876a482d9 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -5,9 +5,9 @@ import subprocess from multiprocessing import Pool import argparse -def runSynth(config, mod, tech, freq, maxopt, usesram): +def runSynth(config, mod, tech, freq, maxopt, usesram, usetopo): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} USETOPO={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram, usetopo) pool.map(mask, [command]) def mask(command): @@ -33,32 +33,34 @@ if __name__ == '__main__': parser.add_argument("-e", "--tech", choices=techs, help = "Technology") parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT") parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules") + parser.add_argument("-topo", "--usetopo", action='store_true', help = "Run physical synthesis") args = parser.parse_args() tech = args.tech if args.tech else 'sky90' maxopt = int(args.maxopt) usesram = int(args.usesram) + usetopo = int(args.usetopop) mod = 'orig' if args.freqsweep: sc = args.freqsweep config = args.version if args.version else 'rv32e' for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep - runSynth(config, mod, tech, freq, maxopt, usesram) + runSynth(config, mod, tech, freq, maxopt, usesram, usetopo) if args.configsweep: defaultfreq = 1500 if tech == 'sky90' else 5000 freq = args.targetfreq if args.targetfreq else defaultfreq for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs - runSynth(config, mod, tech, freq, maxopt, usesram) + runSynth(config, mod, tech, freq, maxopt, usesram, usetopo) if args.featuresweep: defaultfreq = 500 if tech == 'sky90' else 1500 freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: - runSynth(config, mod, tech, freq, maxopt, usesram) + runSynth(config, mod, tech, freq, maxopt, usesram, usetopo) else: defaultfreq = 500 if tech == 'sky90' else 1500 freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' - runSynth(config, mod, tech, freq, maxopt, usesram) + runSynth(config, mod, tech, freq, maxopt, usesram, usetopo) From 64eeb07c6bbf15e8054d62730a3b277c952e96cf Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 16 Feb 2023 15:01:52 -0600 Subject: [PATCH 281/294] Get rid of extra CR/LF in .synopsys_dc.setup file --- synthDC/.synopsys_dc.setup | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 6942e58e6..ac93f6592 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -21,8 +21,7 @@ if {$tech == "sky130"} { set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/ set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a lappend search_path $s10lib -} -elseif {$tech == "tsmc28psyn"} { +} elseif {$tech == "tsmc28psyn"} { set TLU /home/jstine/TLU+ set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/ set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a From 8e9cf8f3e4d755a7468ce6dc97918473ed4a7e51 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 16 Feb 2023 15:16:32 -0600 Subject: [PATCH 282/294] Update bug in Makefile --- synthDC/Makefile | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index d7fb2b914..9dd2b0aba 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -21,6 +21,7 @@ export MAXCORES ?= 1 export MAXOPT ?= 0 export DRIVE ?= FLOP export USESRAM ?= 1 +export USETOPO ?= 0 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) @@ -30,8 +31,6 @@ export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/config export CONFIGDIR ?= $(OUTPUTDIR)/config - - default: @echo " Basic synthesis procedure for Wally:" @echo " Invoke with make synth" @@ -51,6 +50,18 @@ DIRS = $(DIRS32) $(DIRS64) configs: $(CONFIG) $(CONFIG): +ifeq ($(USETOPO), 0)) +ifeq ($(TECH), tsmc28psyn)) + @echo "Bad configuration: you cannot use physical synthesis without tsmc28psyn and usetopo (i.e., -topo)" + exit 1 +endif +endif +ifeq ($(USETOPO), 1)) +ifneq ($(TECH), tsmc28psyn)) + @echo "Bad configuration: you cannot use usetopo (i.e., -topo) without tsmc28psyn" + exit 1 +endif +endif @echo $(CONFIG) cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR) cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR) @@ -116,15 +127,17 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped - synth: mkdirecs configs rundc clean rundc: +ifeq ($(USETOPO), 0) dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out +else -rundctopo: dc_shell-xg-t -64bit -topographical_mode -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out - +endif + + clean: rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK From 3347aa7fe8fa3ee06d73451f73b808ee8bc82afd Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 16 Feb 2023 15:50:31 -0600 Subject: [PATCH 283/294] fix typo - remove extra p at end of script --- synthDC/.synopsys_dc.setup | 1 - synthDC/wallySynth.py | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index ac93f6592..ccc0c67c8 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -29,7 +29,6 @@ if {$tech == "sky130"} { set TLUPLUS true set mw_logic1_net VDD set mw_logic0_net VSS - set TLU_PDK /home/jstine/TLU+/ set CAPTABLE $TLU/1p8m/ set MW_REFERENCE_LIBRARY /home/jstine/MW set MW_TECH_FILE tcbn28hpcplusbwp30p140 diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 876a482d9..d89964c10 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -40,7 +40,7 @@ if __name__ == '__main__': tech = args.tech if args.tech else 'sky90' maxopt = int(args.maxopt) usesram = int(args.usesram) - usetopo = int(args.usetopop) + usetopo = int(args.usetopo) mod = 'orig' if args.freqsweep: From f2e4274c9cea73f2e4e75cd76d7e796e345c5b93 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 16 Feb 2023 17:33:21 -0600 Subject: [PATCH 284/294] Fixed debug signal names. Builds on the fpga. Bug in the crossbar. --- bin/wally-tool-chain-install.sh | 2 +- fpga/constraints/debug2.xdc | 2 +- fpga/constraints/marked_debug.txt | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2b45d8e77..08d63554f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -31,7 +31,7 @@ export PATH=$PATH:$RISCV/bin set -e # break on error -NUM_THREADS=1 # for low memory machines > 16GiB +NUM_THREADS=32 # for low memory machines > 16GiB #NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 8b0b7c448..ecb3b8e73 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -281,7 +281,7 @@ connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/Re create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/StallFCause ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index ff0fb325c..9e51d15ad 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -14,7 +14,6 @@ ieu/regfile.sv: logic rf ieu/datapath.sv: logic RegWriteW hazard/hazard.sv: logic BPPredWrongE hazard/hazard.sv: logic LoadStallD -hazard/hazard.sv: logic LSUStallM hazard/hazard.sv: logic FCvtIntStallD hazard/hazard.sv: logic DivBusyE hazard/hazard.sv: logic EcallFaultM From 85d789a7e06b9155319f50af89b75fcee7efb9b9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 22 Feb 2023 15:13:16 -0600 Subject: [PATCH 285/294] AXI Crossbar is working. Fixed address width in generator script. --- fpga/constraints/debug2.xdc | 407 +++++++++++++-------------- fpga/generator/xlnx_axi_crossbar.tcl | 3 +- fpga/src/fpgaTop.v | 155 +++++----- 3 files changed, 283 insertions(+), 282 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index ecb3b8e73..71e45611e 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -717,430 +717,421 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] -# UART Signals ------------------------------------------------------- - create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe139] +set_property port_width 4 [get_debug_ports u_ila_0/probe139] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] -connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]] +connect_debug_port u_ila_0/probe139 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe140] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] -connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]] +connect_debug_port u_ila_0/probe140 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]] + create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe141] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] -connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]] +connect_debug_port u_ila_0/probe141 [get_nets [list {m_axi_awsize[0]} {m_axi_awsize[1]} {m_axi_awsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe142] +set_property port_width 2 [get_debug_ports u_ila_0/probe142] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] -connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]] +connect_debug_port u_ila_0/probe142 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe143] +set_property port_width 4 [get_debug_ports u_ila_0/probe143] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] -connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]] +connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe144] +set_property port_width 31 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]] +connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe145] +set_property port_width 3 [get_debug_ports u_ila_0/probe145] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] -connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]] +connect_debug_port u_ila_0/probe145 [get_nets [list {m_axi_awprot[0]} {m_axi_awprot[1]} {m_axi_awprot[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe146] +set_property port_width 1 [get_debug_ports u_ila_0/probe146] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] -connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]] +connect_debug_port u_ila_0/probe146 [get_nets [list {m_axi_awvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe147] +set_property port_width 1 [get_debug_ports u_ila_0/probe147] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] -connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]] +connect_debug_port u_ila_0/probe147 [get_nets [list {m_axi_awready}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe148] +set_property port_width 1 [get_debug_ports u_ila_0/probe148] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] -connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]] +connect_debug_port u_ila_0/probe148 [get_nets [list {m_axi_awlock}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe149] +set_property port_width 64 [get_debug_ports u_ila_0/probe149] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149] -connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]] +connect_debug_port u_ila_0/probe149 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]] + create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe150] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150] -connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]] +connect_debug_port u_ila_0/probe150 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe151] +set_property port_width 1 [get_debug_ports u_ila_0/probe151] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151] -connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]] +connect_debug_port u_ila_0/probe151 [get_nets [list {m_axi_wlast}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe152] +set_property port_width 1 [get_debug_ports u_ila_0/probe152] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152] -connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]] +connect_debug_port u_ila_0/probe152 [get_nets [list {m_axi_wvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe153] +set_property port_width 1 [get_debug_ports u_ila_0/probe153] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153] -connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]] +connect_debug_port u_ila_0/probe153 [get_nets [list {m_axi_wready}]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe154] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] -connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]] +connect_debug_port u_ila_0/probe154 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe155] +set_property port_width 2 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] -connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]] +connect_debug_port u_ila_0/probe155 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe156] +set_property port_width 1 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]] +connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_bvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe157] +set_property port_width 1 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]] +connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_bready}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe158] +set_property port_width 4 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]] +connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]] +connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe160] +set_property port_width 3 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]] +connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe161] +set_property port_width 2 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]] +connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe162] +set_property port_width 3 [get_debug_ports u_ila_0/probe162] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] -connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]] +connect_debug_port u_ila_0/probe162 [get_nets [list {m_axi_arprot[0]} {m_axi_arprot[1]} {m_axi_arprot[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe163] +set_property port_width 4 [get_debug_ports u_ila_0/probe163] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] -connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]] +connect_debug_port u_ila_0/probe163 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe164] +set_property port_width 1 [get_debug_ports u_ila_0/probe164] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] -connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]] +connect_debug_port u_ila_0/probe164 [get_nets [list {m_axi_arvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe165] +set_property port_width 31 [get_debug_ports u_ila_0/probe165] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] -connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]] +connect_debug_port u_ila_0/probe165 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe166] +set_property port_width 1 [get_debug_ports u_ila_0/probe166] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] -connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]] +connect_debug_port u_ila_0/probe166 [get_nets [list {m_axi_arlock}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe167] +set_property port_width 1 [get_debug_ports u_ila_0/probe167] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] -connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]] +connect_debug_port u_ila_0/probe167 [get_nets [list {m_axi_arready}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe168] +set_property port_width 4 [get_debug_ports u_ila_0/probe168] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] -connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]] +connect_debug_port u_ila_0/probe168 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe169] +set_property port_width 64 [get_debug_ports u_ila_0/probe169] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] -connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]] +connect_debug_port u_ila_0/probe169 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe170] +set_property port_width 2 [get_debug_ports u_ila_0/probe170] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] -connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]] +connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe171] +set_property port_width 1 [get_debug_ports u_ila_0/probe171] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] -connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]] +connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_rvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe172] +set_property port_width 1 [get_debug_ports u_ila_0/probe172] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] -connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]] +connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_rlast}]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] -connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]] +connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe174] +set_property port_width 4 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]] +connect_debug_port u_ila_0/probe174 [get_nets [list {BUS_axi_awid[0]} {BUS_axi_awid[1]} {BUS_axi_awid[2]} {BUS_axi_awid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe175] +set_property port_width 8 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]] +connect_debug_port u_ila_0/probe175 [get_nets [list {BUS_axi_awlen[0]} {BUS_axi_awlen[1]} {BUS_axi_awlen[2]} {BUS_axi_awlen[3]} {BUS_axi_awlen[4]} {BUS_axi_awlen[5]} {BUS_axi_awlen[6]} {BUS_axi_awlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe176] +set_property port_width 3 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]] +connect_debug_port u_ila_0/probe176 [get_nets [list {BUS_axi_awsize[0]} {BUS_axi_awsize[1]} {BUS_axi_awsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe177] +set_property port_width 2 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]] +connect_debug_port u_ila_0/probe177 [get_nets [list {BUS_axi_awburst[0]} {BUS_axi_awburst[1]} ]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]] +connect_debug_port u_ila_0/probe178 [get_nets [list {BUS_axi_awcache[0]} {BUS_axi_awcache[1]} {BUS_axi_awcache[2]} {BUS_axi_awcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe179] +set_property port_width 31 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]] +connect_debug_port u_ila_0/probe179 [get_nets [list {BUS_axi_awaddr[0]} {BUS_axi_awaddr[1]} {BUS_axi_awaddr[2]} {BUS_axi_awaddr[3]} {BUS_axi_awaddr[4]} {BUS_axi_awaddr[5]} {BUS_axi_awaddr[6]} {BUS_axi_awaddr[7]} {BUS_axi_awaddr[8]} {BUS_axi_awaddr[9]} {BUS_axi_awaddr[10]} {BUS_axi_awaddr[11]} {BUS_axi_awaddr[12]} {BUS_axi_awaddr[13]} {BUS_axi_awaddr[14]} {BUS_axi_awaddr[15]} {BUS_axi_awaddr[16]} {BUS_axi_awaddr[17]} {BUS_axi_awaddr[18]} {BUS_axi_awaddr[19]} {BUS_axi_awaddr[20]} {BUS_axi_awaddr[21]} {BUS_axi_awaddr[22]} {BUS_axi_awaddr[23]} {BUS_axi_awaddr[24]} {BUS_axi_awaddr[25]} {BUS_axi_awaddr[26]} {BUS_axi_awaddr[27]} {BUS_axi_awaddr[28]} {BUS_axi_awaddr[29]} {BUS_axi_awaddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 7 [get_debug_ports u_ila_0/probe180] +set_property port_width 3 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]] +connect_debug_port u_ila_0/probe180 [get_nets [list {BUS_axi_awprot[0]} {BUS_axi_awprot[1]} {BUS_axi_awprot[2]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]] +connect_debug_port u_ila_0/probe181 [get_nets [list {BUS_axi_awvalid}]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]] +connect_debug_port u_ila_0/probe182 [get_nets [list {BUS_axi_awready}]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]] +connect_debug_port u_ila_0/probe183 [get_nets [list {BUS_axi_awlock}]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe184] +set_property port_width 64 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]] +connect_debug_port u_ila_0/probe184 [get_nets [list {BUS_axi_wdata[0]} {BUS_axi_wdata[1]} {BUS_axi_wdata[2]} {BUS_axi_wdata[3]} {BUS_axi_wdata[4]} {BUS_axi_wdata[5]} {BUS_axi_wdata[6]} {BUS_axi_wdata[7]} {BUS_axi_wdata[8]} {BUS_axi_wdata[9]} {BUS_axi_wdata[10]} {BUS_axi_wdata[11]} {BUS_axi_wdata[12]} {BUS_axi_wdata[13]} {BUS_axi_wdata[14]} {BUS_axi_wdata[15]} {BUS_axi_wdata[16]} {BUS_axi_wdata[17]} {BUS_axi_wdata[18]} {BUS_axi_wdata[19]} {BUS_axi_wdata[20]} {BUS_axi_wdata[21]} {BUS_axi_wdata[22]} {BUS_axi_wdata[23]} {BUS_axi_wdata[24]} {BUS_axi_wdata[25]} {BUS_axi_wdata[26]} {BUS_axi_wdata[27]} {BUS_axi_wdata[28]} {BUS_axi_wdata[29]} {BUS_axi_wdata[30]} {BUS_axi_wdata[31]} {BUS_axi_wdata[32]} {BUS_axi_wdata[33]} {BUS_axi_wdata[34]} {BUS_axi_wdata[35]} {BUS_axi_wdata[36]} {BUS_axi_wdata[37]} {BUS_axi_wdata[38]} {BUS_axi_wdata[39]} {BUS_axi_wdata[40]} {BUS_axi_wdata[41]} {BUS_axi_wdata[42]} {BUS_axi_wdata[43]} {BUS_axi_wdata[44]} {BUS_axi_wdata[45]} {BUS_axi_wdata[46]} {BUS_axi_wdata[47]} {BUS_axi_wdata[48]} {BUS_axi_wdata[49]} {BUS_axi_wdata[50]} {BUS_axi_wdata[51]} {BUS_axi_wdata[52]} {BUS_axi_wdata[53]} {BUS_axi_wdata[54]} {BUS_axi_wdata[55]} {BUS_axi_wdata[56]} {BUS_axi_wdata[57]} {BUS_axi_wdata[58]} {BUS_axi_wdata[59]} {BUS_axi_wdata[60]} {BUS_axi_wdata[61]} {BUS_axi_wdata[62]} {BUS_axi_wdata[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe185] +set_property port_width 8 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]] +connect_debug_port u_ila_0/probe185 [get_nets [list {BUS_axi_wstrb[0]} {BUS_axi_wstrb[1]} {BUS_axi_wstrb[2]} {BUS_axi_wstrb[3]} {BUS_axi_wstrb[4]} {BUS_axi_wstrb[5]} {BUS_axi_wstrb[6]} {BUS_axi_wstrb[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe186] +set_property port_width 1 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]] +connect_debug_port u_ila_0/probe186 [get_nets [list {BUS_axi_wlast}]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe187] +set_property port_width 1 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]] +connect_debug_port u_ila_0/probe187 [get_nets [list {BUS_axi_wvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe188] +set_property port_width 1 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]] +connect_debug_port u_ila_0/probe188 [get_nets [list {BUS_axi_wready}]] + create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe189] +set_property port_width 4 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]] +connect_debug_port u_ila_0/probe189 [get_nets [list {BUS_axi_bid[0]} {BUS_axi_bid[1]} {BUS_axi_bid[2]} {BUS_axi_bid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 16 [get_debug_ports u_ila_0/probe190] +set_property port_width 2 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]] +connect_debug_port u_ila_0/probe190 [get_nets [list {BUS_axi_bresp[0]} {BUS_axi_bresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 16 [get_debug_ports u_ila_0/probe191] +set_property port_width 1 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]] +connect_debug_port u_ila_0/probe191 [get_nets [list {BUS_axi_bvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe192] +set_property port_width 1 [get_debug_ports u_ila_0/probe192] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]] +connect_debug_port u_ila_0/probe192 [get_nets [list {BUS_axi_bready}]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe193] +set_property port_width 4 [get_debug_ports u_ila_0/probe193] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] +connect_debug_port u_ila_0/probe193 [get_nets [list {BUS_axi_arid[0]} {BUS_axi_arid[1]} {BUS_axi_arid[2]} {BUS_axi_arid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe194] +set_property port_width 8 [get_debug_ports u_ila_0/probe194] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] +connect_debug_port u_ila_0/probe194 [get_nets [list {BUS_axi_arlen[0]} {BUS_axi_arlen[1]} {BUS_axi_arlen[2]} {BUS_axi_arlen[3]} {BUS_axi_arlen[4]} {BUS_axi_arlen[5]} {BUS_axi_arlen[6]} {BUS_axi_arlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe195] +set_property port_width 3 [get_debug_ports u_ila_0/probe195] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]] +connect_debug_port u_ila_0/probe195 [get_nets [list {BUS_axi_arsize[0]} {BUS_axi_arsize[1]} {BUS_axi_arsize[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe196] +set_property port_width 2 [get_debug_ports u_ila_0/probe196] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]] +connect_debug_port u_ila_0/probe196 [get_nets [list {BUS_axi_arburst[0]} {BUS_axi_arburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe197] +set_property port_width 3 [get_debug_ports u_ila_0/probe197] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]] +connect_debug_port u_ila_0/probe197 [get_nets [list {BUS_axi_arprot[0]} {BUS_axi_arprot[1]} {BUS_axi_arprot[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe198] +set_property port_width 4 [get_debug_ports u_ila_0/probe198] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]] +connect_debug_port u_ila_0/probe198 [get_nets [list {BUS_axi_arcache[0]} {BUS_axi_arcache[1]} {BUS_axi_arcache[2]} {BUS_axi_arcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe199] +set_property port_width 1 [get_debug_ports u_ila_0/probe199] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]] +connect_debug_port u_ila_0/probe199 [get_nets [list {BUS_axi_arvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe200] +set_property port_width 31 [get_debug_ports u_ila_0/probe200] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]] +connect_debug_port u_ila_0/probe200 [get_nets [list {BUS_axi_araddr[0]} {BUS_axi_araddr[1]} {BUS_axi_araddr[2]} {BUS_axi_araddr[3]} {BUS_axi_araddr[4]} {BUS_axi_araddr[5]} {BUS_axi_araddr[6]} {BUS_axi_araddr[7]} {BUS_axi_araddr[8]} {BUS_axi_araddr[9]} {BUS_axi_araddr[10]} {BUS_axi_araddr[11]} {BUS_axi_araddr[12]} {BUS_axi_araddr[13]} {BUS_axi_araddr[14]} {BUS_axi_araddr[15]} {BUS_axi_araddr[16]} {BUS_axi_araddr[17]} {BUS_axi_araddr[18]} {BUS_axi_araddr[19]} {BUS_axi_araddr[20]} {BUS_axi_araddr[21]} {BUS_axi_araddr[22]} {BUS_axi_araddr[23]} {BUS_axi_araddr[24]} {BUS_axi_araddr[25]} {BUS_axi_araddr[26]} {BUS_axi_araddr[27]} {BUS_axi_araddr[28]} {BUS_axi_araddr[29]} {BUS_axi_araddr[30]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe201] +set_property port_width 1 [get_debug_ports u_ila_0/probe201] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]] +connect_debug_port u_ila_0/probe201 [get_nets [list {BUS_axi_arlock}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe202] +set_property port_width 1 [get_debug_ports u_ila_0/probe202] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]] +connect_debug_port u_ila_0/probe202 [get_nets [list {BUS_axi_arready}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe203] +set_property port_width 4 [get_debug_ports u_ila_0/probe203] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]] +connect_debug_port u_ila_0/probe203 [get_nets [list {BUS_axi_rid[0]} {BUS_axi_rid[1]} {BUS_axi_rid[2]} {BUS_axi_rid[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe204] +set_property port_width 64 [get_debug_ports u_ila_0/probe204] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]] +connect_debug_port u_ila_0/probe204 [get_nets [list {BUS_axi_rdata[0]} {BUS_axi_rdata[1]} {BUS_axi_rdata[2]} {BUS_axi_rdata[3]} {BUS_axi_rdata[4]} {BUS_axi_rdata[5]} {BUS_axi_rdata[6]} {BUS_axi_rdata[7]} {BUS_axi_rdata[8]} {BUS_axi_rdata[9]} {BUS_axi_rdata[10]} {BUS_axi_rdata[11]} {BUS_axi_rdata[12]} {BUS_axi_rdata[13]} {BUS_axi_rdata[14]} {BUS_axi_rdata[15]} {BUS_axi_rdata[16]} {BUS_axi_rdata[17]} {BUS_axi_rdata[18]} {BUS_axi_rdata[19]} {BUS_axi_rdata[20]} {BUS_axi_rdata[21]} {BUS_axi_rdata[22]} {BUS_axi_rdata[23]} {BUS_axi_rdata[24]} {BUS_axi_rdata[25]} {BUS_axi_rdata[26]} {BUS_axi_rdata[27]} {BUS_axi_rdata[28]} {BUS_axi_rdata[29]} {BUS_axi_rdata[30]} {BUS_axi_rdata[31]} {BUS_axi_rdata[32]} {BUS_axi_rdata[33]} {BUS_axi_rdata[34]} {BUS_axi_rdata[35]} {BUS_axi_rdata[36]} {BUS_axi_rdata[37]} {BUS_axi_rdata[38]} {BUS_axi_rdata[39]} {BUS_axi_rdata[40]} {BUS_axi_rdata[41]} {BUS_axi_rdata[42]} {BUS_axi_rdata[43]} {BUS_axi_rdata[44]} {BUS_axi_rdata[45]} {BUS_axi_rdata[46]} {BUS_axi_rdata[47]} {BUS_axi_rdata[48]} {BUS_axi_rdata[49]} {BUS_axi_rdata[50]} {BUS_axi_rdata[51]} {BUS_axi_rdata[52]} {BUS_axi_rdata[53]} {BUS_axi_rdata[54]} {BUS_axi_rdata[55]} {BUS_axi_rdata[56]} {BUS_axi_rdata[57]} {BUS_axi_rdata[58]} {BUS_axi_rdata[59]} {BUS_axi_rdata[60]} {BUS_axi_rdata[61]} {BUS_axi_rdata[62]} {BUS_axi_rdata[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe205] +set_property port_width 2 [get_debug_ports u_ila_0/probe205] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]] +connect_debug_port u_ila_0/probe205 [get_nets [list {BUS_axi_rresp[0]} {BUS_axi_rresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe206] +set_property port_width 1 [get_debug_ports u_ila_0/probe206] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]] +connect_debug_port u_ila_0/probe206 [get_nets [list {BUS_axi_rvalid}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe207] +set_property port_width 1 [get_debug_ports u_ila_0/probe207] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]] +connect_debug_port u_ila_0/probe207 [get_nets [list {BUS_axi_rlast}]] + create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe208] +set_property port_width 1 [get_debug_ports u_ila_0/probe208] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe209] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] -connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe210] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] -connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]] - -create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe211] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] -connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]] - -create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe212] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] -connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]] - -create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe213] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] -connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]] - -create_debug_port u_ila_0 probe -set_property port_width 70 [get_debug_ports u_ila_0/probe214] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] -connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe215] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] -connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 10 [get_debug_ports u_ila_0/probe216] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe217] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] -connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe218] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218] -connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 7 [get_debug_ports u_ila_0/probe219] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219] -connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 7 [get_debug_ports u_ila_0/probe220] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220] -connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe221] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] -connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe222] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] -connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 53 [get_debug_ports u_ila_0/probe223] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223] -connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]] - +connect_debug_port u_ila_0/probe208 [get_nets [list {BUS_axi_rready}]] diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl index ba867a640..1d9eb4e78 100644 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -22,7 +22,8 @@ set_property -dict [list CONFIG.NUM_SI {2} \ CONFIG.M01_S01_READ_CONNECTIVITY {0} \ CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ - CONFIG.M01_A00_BASE_ADDR {0x0000000000013000}] [get_ips $ipName] + CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ + CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index bf910257d..4e5958875 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -94,41 +94,41 @@ module fpgaTop wire SDCCmdOE; wire SDCCmdOut; - wire [3:0] m_axi_awid; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire [3:0] m_axi_awcache; - wire [31:0] m_axi_awaddr; - wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - wire m_axi_awlock; - wire [63:0] m_axi_wdata; - wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; - wire [3:0] m_axi_bid; - wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - wire m_axi_bready; - wire [3:0] m_axi_arid; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; - wire [2:0] m_axi_arprot; - wire [3:0] m_axi_arcache; - wire m_axi_arvalid; - wire [31:0] m_axi_araddr; - wire m_axi_arlock; - wire m_axi_arready; - wire [3:0] m_axi_rid; - wire [63:0] m_axi_rdata; - wire [1:0] m_axi_rresp; - wire m_axi_rvalid; - wire m_axi_rlast; - wire m_axi_rready; + (* mark_debug = "true" *) wire [3:0] m_axi_awid; + (* mark_debug = "true" *) wire [7:0] m_axi_awlen; + (* mark_debug = "true" *) wire [2:0] m_axi_awsize; + (* mark_debug = "true" *) wire [1:0] m_axi_awburst; + (* mark_debug = "true" *) wire [3:0] m_axi_awcache; + (* mark_debug = "true" *) wire [31:0] m_axi_awaddr; + (* mark_debug = "true" *) wire [2:0] m_axi_awprot; + (* mark_debug = "true" *) wire m_axi_awvalid; + (* mark_debug = "true" *) wire m_axi_awready; + (* mark_debug = "true" *) wire m_axi_awlock; + (* mark_debug = "true" *) wire [63:0] m_axi_wdata; + (* mark_debug = "true" *) wire [7:0] m_axi_wstrb; + (* mark_debug = "true" *) wire m_axi_wlast; + (* mark_debug = "true" *) wire m_axi_wvalid; + (* mark_debug = "true" *) wire m_axi_wready; + (* mark_debug = "true" *) wire [3:0] m_axi_bid; + (* mark_debug = "true" *) wire [1:0] m_axi_bresp; + (* mark_debug = "true" *) wire m_axi_bvalid; + (* mark_debug = "true" *) wire m_axi_bready; + (* mark_debug = "true" *) wire [3:0] m_axi_arid; + (* mark_debug = "true" *) wire [7:0] m_axi_arlen; + (* mark_debug = "true" *) wire [2:0] m_axi_arsize; + (* mark_debug = "true" *) wire [1:0] m_axi_arburst; + (* mark_debug = "true" *) wire [2:0] m_axi_arprot; + (* mark_debug = "true" *) wire [3:0] m_axi_arcache; + (* mark_debug = "true" *) wire m_axi_arvalid; + (* mark_debug = "true" *) wire [31:0] m_axi_araddr; + (* mark_debug = "true" *) wire m_axi_arlock; + (* mark_debug = "true" *) wire m_axi_arready; + (* mark_debug = "true" *) wire [3:0] m_axi_rid; + (* mark_debug = "true" *) wire [63:0] m_axi_rdata; + (* mark_debug = "true" *) wire [1:0] m_axi_rresp; + (* mark_debug = "true" *) wire m_axi_rvalid; + (* mark_debug = "true" *) wire m_axi_rlast; + (* mark_debug = "true" *) wire m_axi_rready; // Extra Bus signals wire [3:0] BUS_axi_arregion; @@ -137,41 +137,41 @@ module fpgaTop wire [3:0] BUS_axi_awqos; // Bus signals - wire [3:0] BUS_axi_awid; - wire [7:0] BUS_axi_awlen; - wire [2:0] BUS_axi_awsize; - wire [1:0] BUS_axi_awburst; - wire [3:0] BUS_axi_awcache; - wire [30:0] BUS_axi_awaddr; - wire [2:0] BUS_axi_awprot; - wire BUS_axi_awvalid; - wire BUS_axi_awready; - wire BUS_axi_awlock; - wire [63:0] BUS_axi_wdata; - wire [7:0] BUS_axi_wstrb; - wire BUS_axi_wlast; - wire BUS_axi_wvalid; - wire BUS_axi_wready; - wire [3:0] BUS_axi_bid; - wire [1:0] BUS_axi_bresp; - wire BUS_axi_bvalid; - wire BUS_axi_bready; - wire [3:0] BUS_axi_arid; - wire [7:0] BUS_axi_arlen; - wire [2:0] BUS_axi_arsize; - wire [1:0] BUS_axi_arburst; - wire [2:0] BUS_axi_arprot; - wire [3:0] BUS_axi_arcache; - wire BUS_axi_arvalid; - wire [30:0] BUS_axi_araddr; - wire BUS_axi_arlock; - wire BUS_axi_arready; - wire [3:0] BUS_axi_rid; - wire [63:0] BUS_axi_rdata; - wire [1:0] BUS_axi_rresp; - wire BUS_axi_rvalid; - wire BUS_axi_rlast; - wire BUS_axi_rready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_awid; + (* mark_debug = "true" *) wire [7:0] BUS_axi_awlen; + (* mark_debug = "true" *) wire [2:0] BUS_axi_awsize; + (* mark_debug = "true" *) wire [1:0] BUS_axi_awburst; + (* mark_debug = "true" *) wire [3:0] BUS_axi_awcache; + (* mark_debug = "true" *) wire [30:0] BUS_axi_awaddr; + (* mark_debug = "true" *) wire [2:0] BUS_axi_awprot; + (* mark_debug = "true" *) wire BUS_axi_awvalid; + (* mark_debug = "true" *) wire BUS_axi_awready; + (* mark_debug = "true" *) wire BUS_axi_awlock; + (* mark_debug = "true" *) wire [63:0] BUS_axi_wdata; + (* mark_debug = "true" *) wire [7:0] BUS_axi_wstrb; + (* mark_debug = "true" *) wire BUS_axi_wlast; + (* mark_debug = "true" *) wire BUS_axi_wvalid; + (* mark_debug = "true" *) wire BUS_axi_wready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_bid; + (* mark_debug = "true" *) wire [1:0] BUS_axi_bresp; + (* mark_debug = "true" *) wire BUS_axi_bvalid; + (* mark_debug = "true" *) wire BUS_axi_bready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_arid; + (* mark_debug = "true" *) wire [7:0] BUS_axi_arlen; + (* mark_debug = "true" *) wire [2:0] BUS_axi_arsize; + (* mark_debug = "true" *) wire [1:0] BUS_axi_arburst; + (* mark_debug = "true" *) wire [2:0] BUS_axi_arprot; + (* mark_debug = "true" *) wire [3:0] BUS_axi_arcache; + (* mark_debug = "true" *) wire BUS_axi_arvalid; + (* mark_debug = "true" *) wire [30:0] BUS_axi_araddr; + (* mark_debug = "true" *) wire BUS_axi_arlock; + (* mark_debug = "true" *) wire BUS_axi_arready; + (* mark_debug = "true" *) wire [3:0] BUS_axi_rid; + (* mark_debug = "true" *) wire [63:0] BUS_axi_rdata; + (* mark_debug = "true" *) wire [1:0] BUS_axi_rresp; + (* mark_debug = "true" *) wire BUS_axi_rvalid; + (* mark_debug = "true" *) wire BUS_axi_rlast; + (* mark_debug = "true" *) wire BUS_axi_rready; wire BUSCLK; @@ -404,14 +404,19 @@ module fpgaTop wire m01_axi_rready; wire [3:0] SDCDatIn; - + + reg sd_cmd_reg_o; + reg sd_cmd_reg_t; + wire [3:0] sd_dat_i; + assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; assign calib = c0_init_calib_complete; - + + // SD Card Tristate IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low .I(SDCCmdOut), @@ -825,10 +830,14 @@ module fpgaTop //.sdio_dat(4'b0), //.sdio_cd(1'b0) + //.sd_dat_reg_t(), + //.sd_dat_reg_o(), .sd_dat_i(4'b0), + + //.sd_cmd_reg_t(), + //.sd_cmd_reg_o(), .sd_cmd_i(1'b0) - ); xlnx_axi_dwidth_conv_32to64 axi_conv_up From b7571a349d17d88ad30188ea4f704340e39c4c83 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Sat, 25 Feb 2023 16:32:20 -0600 Subject: [PATCH 286/294] Preliminary work on new bootloader using new SD peripheral. Rewrote copyflash to take advantage of the new peripheral. The new peripheral has the neat ability to use CMD18 in the SD card specification, allowing us to load multiple blocks in succession, ending the chain of CMD18 commands with a CMD17. --- tests/custom/boot/boot.c | 50 ++++++++++++++++++---------------------- tests/custom/boot/boot.h | 12 ++++++++++ 2 files changed, 34 insertions(+), 28 deletions(-) create mode 100644 tests/custom/boot/boot.h diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 8546861f9..7f04c1514 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -1,4 +1,4 @@ - +#include "boot.h" /* Card type flags (card_type) */ #define CT_MMC 0x01 /* MMC ver 3 */ @@ -72,6 +72,7 @@ #define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error #define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun + #define ERR_EOF 30 #define ERR_NOT_ELF 31 #define ERR_ELF_BITS 32 @@ -116,12 +117,7 @@ static int errno __attribute__((section(".bss"))); static DSTATUS drv_status __attribute__((section(".bss"))); static BYTE card_type __attribute__((section(".bss"))); static uint32_t response[4] __attribute__((section(".bss"))); -static FATFS fatfs __attribute__((section(".bss"))); static int alt_mem __attribute__((section(".bss"))); -static FIL fd __attribute__((section(".bss"))); - -extern unsigned char _fbss[]; -extern unsigned char _ebss[]; static const char * errno_to_str(void) { switch (errno) { @@ -252,7 +248,7 @@ static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks case CMD2: case CMD9: case CMD10: - // R2 + // R2 command |= 2; // 136 bits command |= 1 << 3; // resp CRC break; @@ -305,6 +301,9 @@ static int ini_sd(void) { /* Reset controller */ regs->software_reset = 1; while ((regs->software_reset & 1) == 0) {} + + // This clock divider is meant to initialize the card at + // 400kHz regs->clock_divider = 0x7c; regs->software_reset = 0; while (regs->software_reset) {} @@ -369,10 +368,16 @@ static int ini_sd(void) { return 0; } -DRESULT disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { +int disk_read(BYTE * buf, LBA_t sector, UINT count) { - if (!count) return RES_PARERR; - if (drv_status & STA_NOINIT) return RES_NOTRDY; + /* This is not needed. This has everything to do with the FAT + filesystem stuff that I'm not including. All I need to do is + initialize the SD card and read from it. Anything in here that is + checking for potential errors, I'm going to have to temporarily + do without. + */ + // if (!count) return RES_PARERR; + /* if (drv_status & STA_NOINIT) return RES_NOTRDY; */ /* Convert LBA to byte address if needed */ if (!(card_type & CT_BLOCK)) sector *= 512; @@ -389,30 +394,19 @@ DRESULT disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { return RES_OK; } -void disk_read(BYTE drv, BYTE * buf, LBA_t sector, UINT count) { +void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { + ini_sd(); - if (!count) return RES_PARERR; - if (drv_status & STA_NOINIT) return RES_NOTRDY; - - /* Convert LBA to byte address if needed */ - if (!(card_type & CT_BLOCK)) sector *= 512; - while (count > 0) { - UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; - unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; - if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; - sector += (card_type & CT_BLOCK) ? bcnt : bytes; - count -= bcnt; - buf += bytes; - } - - return RES_OK; + BYTE * buf = (BYTE *)Dst; + + if (disk_read(buf, (LBA_t)address, (UINT)numBlocks) < 0) /* UART Print function?*/; } +/* int main() { ini_sd(); - return 0; } +*/ diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h new file mode 100644 index 000000000..ef620cda0 --- /dev/null +++ b/tests/custom/boot/boot.h @@ -0,0 +1,12 @@ +#ifndef WALLYBOOT +#define WALLYBOOT 10000 + +#include +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef uint16_t WORD; /* 16-bit unsigned integer */ +typedef uint32_t DWORD; /* 32-bit unsigned integer */ +typedef uint64_t QWORD; /* 64-bit unsigned integer */ +typedef WORD WCHAR; + +#endif // WALLYBOOT From a7b547008a5dc6d0f75bfe96dae40ae968d9bac9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 28 Feb 2023 12:18:13 -0600 Subject: [PATCH 287/294] Commented out some fat filesystem error checks. --- tests/custom/boot/boot.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 7f04c1514..9f4eaa6f9 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -114,7 +114,7 @@ struct sdc_regs { static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013100; static int errno __attribute__((section(".bss"))); -static DSTATUS drv_status __attribute__((section(".bss"))); +// static DSTATUS drv_status __attribute__((section(".bss"))); static BYTE card_type __attribute__((section(".bss"))); static uint32_t response[4] __attribute__((section(".bss"))); static int alt_mem __attribute__((section(".bss"))); @@ -310,7 +310,7 @@ static int ini_sd(void) { usleep(5000); card_type = 0; - drv_status = STA_NOINIT; + // drv_status = STA_NOINIT; if (regs->capability & SDC_CAPABILITY_SD_RESET) { /* Power cycle SD card */ @@ -364,7 +364,7 @@ static int ini_sd(void) { /* Set R/W block length to 512 */ if (send_cmd(CMD16, 512) < 0) return -1; - drv_status &= ~STA_NOINIT; + // drv_status &= ~STA_NOINIT; return 0; } @@ -385,13 +385,13 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; unsigned bytes = bcnt * 512; if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; - if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return RES_ERROR; + if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1; sector += (card_type & CT_BLOCK) ? bcnt : bytes; count -= bcnt; buf += bytes; } - return RES_OK; + return 0;; } void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { From 449b835fcd2499609e30603fbdeaca8860212a47 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 28 Feb 2023 12:20:46 -0600 Subject: [PATCH 288/294] Disabled old SD card and attached IOBUF's to new SD peripheral. --- config/fpga/wally-config.vh | 2 +- fpga/src/fpgaTop.v | 47 ++++++++++++++++++++++++++----------- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index de25e1b43..007562a17 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -117,7 +117,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 4e5958875..13f61c03f 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -90,9 +90,10 @@ module fpgaTop wire [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; - wire SDCCmdIn; - wire SDCCmdOE; - wire SDCCmdOut; + // Old SDC connections + // wire SDCCmdIn; + // wire SDCCmdOE; + // wire SDCCmdOut; (* mark_debug = "true" *) wire [3:0] m_axi_awid; (* mark_debug = "true" *) wire [7:0] m_axi_awlen; @@ -403,11 +404,18 @@ module fpgaTop wire m01_axi_rvalid; wire m01_axi_rready; - wire [3:0] SDCDatIn; + // Old SDC input + // wire [3:0] SDCDatIn; + // New SDC Command IOBUF connections + wire sd_cmd_i; reg sd_cmd_reg_o; reg sd_cmd_reg_t; + + // New SDC Data IOBUF connections wire [3:0] sd_dat_i; + reg [3:0] sd_dat_reg_o; + reg sd_dat_reg_t; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -418,12 +426,12 @@ module fpgaTop // SD Card Tristate + /* IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low .I(SDCCmdOut), .O(SDCCmdIn), .IO(SDCCmd)); - genvar i; generate for (i = 0; i < 4; i = i + 1) begin @@ -433,8 +441,20 @@ module fpgaTop .IO(SDCDat[i])); end endgenerate - - // IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(sdio_cmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + */ + + // IOBUFS for new SDC peripheral + IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCcmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + genvar i; + generate + for (i = 0; i < 4; i = i + 1) begin + IOBUF iobufSDCDat(.T(sd_dat_reg_t), + .I(sd_dat_reg_o[i]), + .O(sd_dat_i[i]), + .IO(SDCDat[i]) ); + end + endgenerate + // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); @@ -830,14 +850,13 @@ module fpgaTop //.sdio_dat(4'b0), //.sdio_cd(1'b0) - //.sd_dat_reg_t(), - //.sd_dat_reg_o(), - .sd_dat_i(4'b0), + .sd_dat_reg_t(sd_dat_reg_t), + .sd_dat_reg_o(sd_dat_reg_o), + .sd_dat_i(sd_dat_i), - //.sd_cmd_reg_t(), - //.sd_cmd_reg_o(), - .sd_cmd_i(1'b0) - + .sd_cmd_reg_t(sd_cmd_reg_t), + .sd_cmd_reg_o(sd_cmd_reg_o), + .sd_cmd_i(sd_cmd_i) ); xlnx_axi_dwidth_conv_32to64 axi_conv_up From 2d0199a35475ad8254bdeb6c2825e6dbb5c593e8 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 24 Mar 2023 17:01:27 -0500 Subject: [PATCH 289/294] Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore --- fpga/constraints/constraints-vcu108.xdc | 48 ++++++----- fpga/src/fpgaTop.v | 66 ++++++++-------- src/uncore/uncore.sv | 8 +- src/wally/wallypipelinedsoc.sv | 6 +- tests/custom/boot/bios.s | 101 ++++++++++++++++++++++++ tests/custom/boot/boot.c | 19 ----- 6 files changed, 171 insertions(+), 77 deletions(-) create mode 100644 tests/custom/boot/bios.s diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index cbb70db92..8d59509be 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -3,7 +3,8 @@ # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] ##### GPI #### set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] @@ -16,7 +17,7 @@ set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] -set_max_delay -from [get_ports {GPI[*]}] 10.000 +set_max_delay -from [get_ports {GPI[*]}] 10.000n ##### GPO #### set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] @@ -92,23 +93,32 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### -set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] -set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] -set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] -set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] -set_property PACKAGE_PIN BB16 [get_ports SDCCLK] -set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] -set_property PULLUP true [get_ports {SDCDat[3]}] -set_property PULLUP true [get_ports {SDCDat[2]}] -set_property PULLUP true [get_ports {SDCDat[1]}] -set_property PULLUP true [get_ports {SDCDat[0]}] -set_property PULLUP true [get_ports {SDCCmd}] + +# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] +# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] +# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] +# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] +# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] +# set_property PACKAGE_PIN BB16 [get_ports SDCCLK] +# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] +# set_property PULLUP true [get_ports {SDCDat[3]}] +# set_property PULLUP true [get_ports {SDCDat[2]}] +# set_property PULLUP true [get_ports {SDCDat[1]}] +# set_property PULLUP true [get_ports {SDCDat[0]}] +# set_property PULLUP true [get_ports {SDCCmd}] + +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}] +set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}] +set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}] +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}] +set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}] +set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}] +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK] set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 13f61c03f..e2eb8441e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -28,23 +28,24 @@ module fpgaTop (input default_250mhz_clk1_0_n, - input default_250mhz_clk1_0_p, - input reset, - input south_rst, + input default_250mhz_clk1_0_p, + input reset, + input south_rst, - input [3:0] GPI, + input [3:0] GPI, output [4:0] GPO, - input UARTSin, - output UARTSout, + input UARTSin, + output UARTSout, - inout [3:0] SDCDat, - output SDCCLK, - inout SDCCmd, + inout [3:0] SDCDat, + output SDCCLK, + inout SDCCmd, + input SDCCD, - output calib, - output cpu_reset, - output ahblite_resetn, + output calib, + output cpu_reset, + output ahblite_resetn, output [16 : 0] c0_ddr4_adr, output [1 : 0] c0_ddr4_ba, @@ -56,8 +57,8 @@ module fpgaTop inout [7 : 0] c0_ddr4_dqs_t, output [0 : 0] c0_ddr4_odt, output [0 : 0] c0_ddr4_bg, - output c0_ddr4_reset_n, - output c0_ddr4_act_n, + output c0_ddr4_reset_n, + output c0_ddr4_act_n, output [0 : 0] c0_ddr4_ck_c, output [0 : 0] c0_ddr4_ck_t ); @@ -188,6 +189,7 @@ module fpgaTop wire s00_axi_aclk; wire s00_axi_aresetn; + wire [3:0] s00_axi_awid; wire [31:0]s00_axi_awaddr; wire [7:0]s00_axi_awlen; wire [2:0]s00_axi_awsize; @@ -244,11 +246,9 @@ module fpgaTop wire s01_axi_wlast; wire s01_axi_wvalid; wire s01_axi_wready; - wire [3:0]m01_axi_bid; wire [1:0]s01_axi_bresp; wire s01_axi_bvalid; wire s01_axi_bready; - wire [3:0]m01_axi_bid; wire [31:0]s01_axi_araddr; wire [7:0]s01_axi_arlen; wire [2:0]s01_axi_arsize; @@ -260,7 +260,6 @@ module fpgaTop wire [3:0]s01_axi_arqos; // wire s01_axi_arvalid; wire s01_axi_arready; - wire [3:0]m01_axi_rid; wire [63:0]s01_axi_rdata; wire [1:0]s01_axi_rresp; wire s01_axi_rlast; @@ -376,7 +375,7 @@ module fpgaTop wire [3:0]m01_axi_awqos; wire m01_axi_awvalid; wire m01_axi_awready; - wire [31:0]m01_axi_wdata; + wire [63:0]m01_axi_wdata; wire [3:0]m01_axi_wstrb; wire m01_axi_wlast; wire m01_axi_wvalid; @@ -398,7 +397,7 @@ module fpgaTop wire m01_axi_arvalid; wire m01_axi_arready; wire [3:0] m01_axi_rid; - wire [31:0]m01_axi_rdata; + wire [63:0]m01_axi_rdata; wire [1:0]m01_axi_rresp; wire m01_axi_rlast; wire m01_axi_rvalid; @@ -409,13 +408,13 @@ module fpgaTop // New SDC Command IOBUF connections wire sd_cmd_i; - reg sd_cmd_reg_o; - reg sd_cmd_reg_t; + wire sd_cmd_reg_o; + wire sd_cmd_reg_t; // New SDC Data IOBUF connections wire [3:0] sd_dat_i; - reg [3:0] sd_dat_reg_o; - reg sd_dat_reg_t; + wire [3:0] sd_dat_reg_o; + wire sd_dat_reg_t; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -444,7 +443,7 @@ module fpgaTop */ // IOBUFS for new SDC peripheral - IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCcmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); genvar i; generate for (i = 0; i < 4; i = i + 1) begin @@ -502,13 +501,13 @@ module fpgaTop .GPIOPinsEn(GPIOPinsEn), // UART .UARTSin(UARTSin), - .UARTSout(UARTSout), + .UARTSout(UARTSout) // SD Card - .SDCDatIn(SDCDatIn), + /*.SDCDatIn(SDCDatIn), .SDCCmdIn(SDCCmdIn), .SDCCmdOut(SDCCmdOut), .SDCCmdOE(SDCCmdOE), - .SDCCLK(SDCCLK)); + .SDCCLK(SDCCLK));*/ // ahb lite to axi bridge xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 @@ -568,7 +567,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({8'b0, m_axi_awid}), + .s_axi_awid({4'b0, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -588,7 +587,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({8'b0, m_axi_arid}), + .s_axi_arid({4'b0, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -624,7 +623,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({8'b0, s00_axi_bid}), + .m_axi_bid({4'b0, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -640,7 +639,7 @@ module fpgaTop .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({8'b0, s00_axi_rid}), + .m_axi_rid({4'b0, s00_axi_rid}), .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), @@ -856,7 +855,10 @@ module fpgaTop .sd_cmd_reg_t(sd_cmd_reg_t), .sd_cmd_reg_o(sd_cmd_reg_o), - .sd_cmd_i(sd_cmd_i) + .sd_cmd_i(sd_cmd_i), + + .sdio_clk(SDCCLK), + .sdio_cd(SDCCD) ); xlnx_axi_dwidth_conv_32to64 axi_conv_up diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 532efe069..845a96c14 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -57,11 +57,11 @@ module uncore ( output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input output logic UARTSout, // UART serial output - output logic SDCCmdOut, // SD Card command output + /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input input logic [3:0] SDCDatIn, // SD Card data input - output logic SDCCLK // SD Card clock + output logic SDCCLK // SD Card clock*/ ); logic [`XLEN-1:0] HREADRam, HREADSDC; @@ -158,10 +158,10 @@ module uncore ( // interrupt to PLIC .SDCIntM ); - end else begin : sdc + /*end else begin : sdc assign SDCCLK = 0; assign SDCCmdOut = 0; - assign SDCCmdOE = 0; + assign SDCCmdOE = 0;*/ end // AHB Read Multiplexer diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index e4c461571..92dded7ad 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -56,11 +56,11 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output - input logic SDCCmdIn, // SDC Command input + /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable input logic [3:0] SDCDatIn, // SDC data input - output logic SDCCLK // SDC clock + output logic SDCCLK // SDC clock*/ ); // Uncore signals @@ -87,7 +87,7 @@ module wallypipelinedsoc ( .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, - .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); + /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end endmodule diff --git a/tests/custom/boot/bios.s b/tests/custom/boot/bios.s new file mode 100644 index 000000000..8057a277d --- /dev/null +++ b/tests/custom/boot/bios.s @@ -0,0 +1,101 @@ +PERIOD = 11000000 +#PERIOD = 20 + +.section .init +.global _start +.type _start, @function + + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, 0x87FFFFF8 + + li a0, 0x00000000 + li a1, 0x80000000 + #li a2, 128*1024*1024/512 # copy 128MB + li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) + #li a2, 800 # copy 400KB + jal ra, copyFlash + + fence.i + # now toggle led so we know the copy completed. + + # write to gpio + li t2, 0xFF + la t3, 0x1006000C + li t4, 5 + +loop: + + # delay + li t0, PERIOD/2 +delay1: + addi t0, t0, -1 + bge t0, x0, delay1 + sw t2, 0x0(t3) + + li t0, PERIOD/2 +delay2: + addi t0, t0, -1 + bge t0, x0, delay2 + sw x0, 0x0(t3) + + addi t4, t4, -1 + bgt t4, x0, loop + + + # now that the card is copied and the led toggled we + # jump to the copied contents of the sd card. + +jumpToLinux: + csrrs a0, 0xF14, x0 # copy hard ID to a0 + li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB + la a2, end_of_bios + li t0, 0x80000000 # start of code + + jalr x0, t0, 0 + +end_of_bios: + + + + diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 9f4eaa6f9..f9fa2c0fe 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -121,25 +121,6 @@ static int alt_mem __attribute__((section(".bss"))); static const char * errno_to_str(void) { switch (errno) { - case FR_OK: return "No error"; - case FR_DISK_ERR: return "Disk I/O error"; - case FR_INT_ERR: return "Assertion failed"; - case FR_NOT_READY: return "Disk not ready"; - case FR_NO_FILE: return "File not found"; - case FR_NO_PATH: return "Path not found"; - case FR_INVALID_NAME: return "Invalid path"; - case FR_DENIED: return "Access denied"; - case FR_EXIST: return "Already exist"; - case FR_INVALID_OBJECT: return "The FS object is invalid"; - case FR_WRITE_PROTECTED: return "The drive is write protected"; - case FR_INVALID_DRIVE: return "The drive number is invalid"; - case FR_NOT_ENABLED: return "The volume has no work area"; - case FR_NO_FILESYSTEM: return "Not a valid FAT volume"; - case FR_MKFS_ABORTED: return "The f_mkfs() aborted"; - case FR_TIMEOUT: return "Timeout"; - case FR_LOCKED: return "Locked"; - case FR_NOT_ENOUGH_CORE: return "Not enough memory"; - case FR_TOO_MANY_OPEN_FILES: return "Too many open files"; case ERR_EOF: return "Unexpected EOF"; case ERR_NOT_ELF: return "Not an ELF file"; case ERR_ELF_BITS: return "Wrong ELF word size"; From b796b1b4929786558a1ae3e58108ea7f1c9004b9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 6 Apr 2023 16:01:58 -0500 Subject: [PATCH 290/294] Build doesn't work. AXI Crossbar has problems. --- fpga/constraints/debug2.xdc | 193 +----- fpga/src/fpgaTop.v | 84 +-- .../src/uncore/newsdc/axi_sdc_controller.v | 40 +- src/generic/mem/rom1p1r.sv | 646 +++++++++++++++++- src/uncore/uncore.sv | 10 +- src/wally/wallypipelinedsoc.sv | 4 +- tests/custom/boot/Makefile | 4 +- tests/custom/boot/boot.c | 18 +- tests/custom/boot/boot.h | 5 +- 9 files changed, 773 insertions(+), 231 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 71e45611e..13733e579 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -926,212 +926,93 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] - +# ============== AXI SDC STUFF ================ create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe174] +set_property port_width 1 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {BUS_axi_awid[0]} {BUS_axi_awid[1]} {BUS_axi_awid[2]} {BUS_axi_awid[3]} ]] - +connect_debug_port u_ila_0/probe174 [get_nets [list {axiSDC/clock_posedge}]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe175] +set_property port_width 32 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {BUS_axi_awlen[0]} {BUS_axi_awlen[1]} {BUS_axi_awlen[2]} {BUS_axi_awlen[3]} {BUS_axi_awlen[4]} {BUS_axi_awlen[5]} {BUS_axi_awlen[6]} {BUS_axi_awlen[7]} ]] - +connect_debug_port u_ila_0/probe175 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe176] +set_property port_width 25 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {BUS_axi_awsize[0]} {BUS_axi_awsize[1]} {BUS_axi_awsize[2]} ]] - +connect_debug_port u_ila_0/probe176 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe177] +set_property port_width 28 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {BUS_axi_awburst[0]} {BUS_axi_awburst[1]} ]] - +connect_debug_port u_ila_0/probe177 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe178] +set_property port_width 1 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {BUS_axi_awcache[0]} {BUS_axi_awcache[1]} {BUS_axi_awcache[2]} {BUS_axi_awcache[3]} ]] - +connect_debug_port u_ila_0/probe178 [get_nets [list {axiSDC/software_reset_reg}]] create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe179] +set_property port_width 32 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {BUS_axi_awaddr[0]} {BUS_axi_awaddr[1]} {BUS_axi_awaddr[2]} {BUS_axi_awaddr[3]} {BUS_axi_awaddr[4]} {BUS_axi_awaddr[5]} {BUS_axi_awaddr[6]} {BUS_axi_awaddr[7]} {BUS_axi_awaddr[8]} {BUS_axi_awaddr[9]} {BUS_axi_awaddr[10]} {BUS_axi_awaddr[11]} {BUS_axi_awaddr[12]} {BUS_axi_awaddr[13]} {BUS_axi_awaddr[14]} {BUS_axi_awaddr[15]} {BUS_axi_awaddr[16]} {BUS_axi_awaddr[17]} {BUS_axi_awaddr[18]} {BUS_axi_awaddr[19]} {BUS_axi_awaddr[20]} {BUS_axi_awaddr[21]} {BUS_axi_awaddr[22]} {BUS_axi_awaddr[23]} {BUS_axi_awaddr[24]} {BUS_axi_awaddr[25]} {BUS_axi_awaddr[26]} {BUS_axi_awaddr[27]} {BUS_axi_awaddr[28]} {BUS_axi_awaddr[29]} {BUS_axi_awaddr[30]} ]] - +connect_debug_port u_ila_0/probe179 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe180] +set_property port_width 32 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {BUS_axi_awprot[0]} {BUS_axi_awprot[1]} {BUS_axi_awprot[2]} ]] - +connect_debug_port u_ila_0/probe180 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe181] +set_property port_width 32 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {BUS_axi_awvalid}]] - +connect_debug_port u_ila_0/probe181 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe182] +set_property port_width 32 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {BUS_axi_awready}]] - +connect_debug_port u_ila_0/probe182 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe183] +set_property port_width 12 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {BUS_axi_awlock}]] - +connect_debug_port u_ila_0/probe183 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe184] +set_property port_width 2 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {BUS_axi_wdata[0]} {BUS_axi_wdata[1]} {BUS_axi_wdata[2]} {BUS_axi_wdata[3]} {BUS_axi_wdata[4]} {BUS_axi_wdata[5]} {BUS_axi_wdata[6]} {BUS_axi_wdata[7]} {BUS_axi_wdata[8]} {BUS_axi_wdata[9]} {BUS_axi_wdata[10]} {BUS_axi_wdata[11]} {BUS_axi_wdata[12]} {BUS_axi_wdata[13]} {BUS_axi_wdata[14]} {BUS_axi_wdata[15]} {BUS_axi_wdata[16]} {BUS_axi_wdata[17]} {BUS_axi_wdata[18]} {BUS_axi_wdata[19]} {BUS_axi_wdata[20]} {BUS_axi_wdata[21]} {BUS_axi_wdata[22]} {BUS_axi_wdata[23]} {BUS_axi_wdata[24]} {BUS_axi_wdata[25]} {BUS_axi_wdata[26]} {BUS_axi_wdata[27]} {BUS_axi_wdata[28]} {BUS_axi_wdata[29]} {BUS_axi_wdata[30]} {BUS_axi_wdata[31]} {BUS_axi_wdata[32]} {BUS_axi_wdata[33]} {BUS_axi_wdata[34]} {BUS_axi_wdata[35]} {BUS_axi_wdata[36]} {BUS_axi_wdata[37]} {BUS_axi_wdata[38]} {BUS_axi_wdata[39]} {BUS_axi_wdata[40]} {BUS_axi_wdata[41]} {BUS_axi_wdata[42]} {BUS_axi_wdata[43]} {BUS_axi_wdata[44]} {BUS_axi_wdata[45]} {BUS_axi_wdata[46]} {BUS_axi_wdata[47]} {BUS_axi_wdata[48]} {BUS_axi_wdata[49]} {BUS_axi_wdata[50]} {BUS_axi_wdata[51]} {BUS_axi_wdata[52]} {BUS_axi_wdata[53]} {BUS_axi_wdata[54]} {BUS_axi_wdata[55]} {BUS_axi_wdata[56]} {BUS_axi_wdata[57]} {BUS_axi_wdata[58]} {BUS_axi_wdata[59]} {BUS_axi_wdata[60]} {BUS_axi_wdata[61]} {BUS_axi_wdata[62]} {BUS_axi_wdata[63]} ]] - +connect_debug_port u_ila_0/probe184 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe185] +set_property port_width 5 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {BUS_axi_wstrb[0]} {BUS_axi_wstrb[1]} {BUS_axi_wstrb[2]} {BUS_axi_wstrb[3]} {BUS_axi_wstrb[4]} {BUS_axi_wstrb[5]} {BUS_axi_wstrb[6]} {BUS_axi_wstrb[7]} ]] - +connect_debug_port u_ila_0/probe185 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe186] +set_property port_width 6 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {BUS_axi_wlast}]] - +connect_debug_port u_ila_0/probe186 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe187] +set_property port_width 6 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {BUS_axi_wvalid}]] - +connect_debug_port u_ila_0/probe187 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe188] +set_property port_width 5 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {BUS_axi_wready}]] - +connect_debug_port u_ila_0/probe188 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe189] +set_property port_width 6 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {BUS_axi_bid[0]} {BUS_axi_bid[1]} {BUS_axi_bid[2]} {BUS_axi_bid[3]} ]] - +connect_debug_port u_ila_0/probe189 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe190] +set_property port_width 16 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {BUS_axi_bresp[0]} {BUS_axi_bresp[1]} ]] - +connect_debug_port u_ila_0/probe190 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe191] +set_property port_width 8 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {BUS_axi_bvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe192] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {BUS_axi_bready}]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe193] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {BUS_axi_arid[0]} {BUS_axi_arid[1]} {BUS_axi_arid[2]} {BUS_axi_arid[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe194] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {BUS_axi_arlen[0]} {BUS_axi_arlen[1]} {BUS_axi_arlen[2]} {BUS_axi_arlen[3]} {BUS_axi_arlen[4]} {BUS_axi_arlen[5]} {BUS_axi_arlen[6]} {BUS_axi_arlen[7]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe195] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {BUS_axi_arsize[0]} {BUS_axi_arsize[1]} {BUS_axi_arsize[2]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe196] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {BUS_axi_arburst[0]} {BUS_axi_arburst[1]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe197] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {BUS_axi_arprot[0]} {BUS_axi_arprot[1]} {BUS_axi_arprot[2]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe198] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {BUS_axi_arcache[0]} {BUS_axi_arcache[1]} {BUS_axi_arcache[2]} {BUS_axi_arcache[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe199] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {BUS_axi_arvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe200] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {BUS_axi_araddr[0]} {BUS_axi_araddr[1]} {BUS_axi_araddr[2]} {BUS_axi_araddr[3]} {BUS_axi_araddr[4]} {BUS_axi_araddr[5]} {BUS_axi_araddr[6]} {BUS_axi_araddr[7]} {BUS_axi_araddr[8]} {BUS_axi_araddr[9]} {BUS_axi_araddr[10]} {BUS_axi_araddr[11]} {BUS_axi_araddr[12]} {BUS_axi_araddr[13]} {BUS_axi_araddr[14]} {BUS_axi_araddr[15]} {BUS_axi_araddr[16]} {BUS_axi_araddr[17]} {BUS_axi_araddr[18]} {BUS_axi_araddr[19]} {BUS_axi_araddr[20]} {BUS_axi_araddr[21]} {BUS_axi_araddr[22]} {BUS_axi_araddr[23]} {BUS_axi_araddr[24]} {BUS_axi_araddr[25]} {BUS_axi_araddr[26]} {BUS_axi_araddr[27]} {BUS_axi_araddr[28]} {BUS_axi_araddr[29]} {BUS_axi_araddr[30]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe201] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {BUS_axi_arlock}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe202] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {BUS_axi_arready}]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe203] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {BUS_axi_rid[0]} {BUS_axi_rid[1]} {BUS_axi_rid[2]} {BUS_axi_rid[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe204] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {BUS_axi_rdata[0]} {BUS_axi_rdata[1]} {BUS_axi_rdata[2]} {BUS_axi_rdata[3]} {BUS_axi_rdata[4]} {BUS_axi_rdata[5]} {BUS_axi_rdata[6]} {BUS_axi_rdata[7]} {BUS_axi_rdata[8]} {BUS_axi_rdata[9]} {BUS_axi_rdata[10]} {BUS_axi_rdata[11]} {BUS_axi_rdata[12]} {BUS_axi_rdata[13]} {BUS_axi_rdata[14]} {BUS_axi_rdata[15]} {BUS_axi_rdata[16]} {BUS_axi_rdata[17]} {BUS_axi_rdata[18]} {BUS_axi_rdata[19]} {BUS_axi_rdata[20]} {BUS_axi_rdata[21]} {BUS_axi_rdata[22]} {BUS_axi_rdata[23]} {BUS_axi_rdata[24]} {BUS_axi_rdata[25]} {BUS_axi_rdata[26]} {BUS_axi_rdata[27]} {BUS_axi_rdata[28]} {BUS_axi_rdata[29]} {BUS_axi_rdata[30]} {BUS_axi_rdata[31]} {BUS_axi_rdata[32]} {BUS_axi_rdata[33]} {BUS_axi_rdata[34]} {BUS_axi_rdata[35]} {BUS_axi_rdata[36]} {BUS_axi_rdata[37]} {BUS_axi_rdata[38]} {BUS_axi_rdata[39]} {BUS_axi_rdata[40]} {BUS_axi_rdata[41]} {BUS_axi_rdata[42]} {BUS_axi_rdata[43]} {BUS_axi_rdata[44]} {BUS_axi_rdata[45]} {BUS_axi_rdata[46]} {BUS_axi_rdata[47]} {BUS_axi_rdata[48]} {BUS_axi_rdata[49]} {BUS_axi_rdata[50]} {BUS_axi_rdata[51]} {BUS_axi_rdata[52]} {BUS_axi_rdata[53]} {BUS_axi_rdata[54]} {BUS_axi_rdata[55]} {BUS_axi_rdata[56]} {BUS_axi_rdata[57]} {BUS_axi_rdata[58]} {BUS_axi_rdata[59]} {BUS_axi_rdata[60]} {BUS_axi_rdata[61]} {BUS_axi_rdata[62]} {BUS_axi_rdata[63]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe205] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {BUS_axi_rresp[0]} {BUS_axi_rresp[1]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe206] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {BUS_axi_rvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe207] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {BUS_axi_rlast}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe208] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {BUS_axi_rready}]] +connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index e2eb8441e..03758249e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -139,41 +139,41 @@ module fpgaTop wire [3:0] BUS_axi_awqos; // Bus signals - (* mark_debug = "true" *) wire [3:0] BUS_axi_awid; - (* mark_debug = "true" *) wire [7:0] BUS_axi_awlen; - (* mark_debug = "true" *) wire [2:0] BUS_axi_awsize; - (* mark_debug = "true" *) wire [1:0] BUS_axi_awburst; - (* mark_debug = "true" *) wire [3:0] BUS_axi_awcache; - (* mark_debug = "true" *) wire [30:0] BUS_axi_awaddr; - (* mark_debug = "true" *) wire [2:0] BUS_axi_awprot; - (* mark_debug = "true" *) wire BUS_axi_awvalid; - (* mark_debug = "true" *) wire BUS_axi_awready; - (* mark_debug = "true" *) wire BUS_axi_awlock; - (* mark_debug = "true" *) wire [63:0] BUS_axi_wdata; - (* mark_debug = "true" *) wire [7:0] BUS_axi_wstrb; - (* mark_debug = "true" *) wire BUS_axi_wlast; - (* mark_debug = "true" *) wire BUS_axi_wvalid; - (* mark_debug = "true" *) wire BUS_axi_wready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_bid; - (* mark_debug = "true" *) wire [1:0] BUS_axi_bresp; - (* mark_debug = "true" *) wire BUS_axi_bvalid; - (* mark_debug = "true" *) wire BUS_axi_bready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_arid; - (* mark_debug = "true" *) wire [7:0] BUS_axi_arlen; - (* mark_debug = "true" *) wire [2:0] BUS_axi_arsize; - (* mark_debug = "true" *) wire [1:0] BUS_axi_arburst; - (* mark_debug = "true" *) wire [2:0] BUS_axi_arprot; - (* mark_debug = "true" *) wire [3:0] BUS_axi_arcache; - (* mark_debug = "true" *) wire BUS_axi_arvalid; - (* mark_debug = "true" *) wire [30:0] BUS_axi_araddr; - (* mark_debug = "true" *) wire BUS_axi_arlock; - (* mark_debug = "true" *) wire BUS_axi_arready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_rid; - (* mark_debug = "true" *) wire [63:0] BUS_axi_rdata; - (* mark_debug = "true" *) wire [1:0] BUS_axi_rresp; - (* mark_debug = "true" *) wire BUS_axi_rvalid; - (* mark_debug = "true" *) wire BUS_axi_rlast; - (* mark_debug = "true" *) wire BUS_axi_rready; + wire [3:0] BUS_axi_awid; + wire [7:0] BUS_axi_awlen; + wire [2:0] BUS_axi_awsize; + wire [1:0] BUS_axi_awburst; + wire [3:0] BUS_axi_awcache; + wire [30:0] BUS_axi_awaddr; + wire [2:0] BUS_axi_awprot; + wire BUS_axi_awvalid; + wire BUS_axi_awready; + wire BUS_axi_awlock; + wire [63:0] BUS_axi_wdata; + wire [7:0] BUS_axi_wstrb; + wire BUS_axi_wlast; + wire BUS_axi_wvalid; + wire BUS_axi_wready; + wire [3:0] BUS_axi_bid; + wire [1:0] BUS_axi_bresp; + wire BUS_axi_bvalid; + wire BUS_axi_bready; + wire [3:0] BUS_axi_arid; + wire [7:0] BUS_axi_arlen; + wire [2:0] BUS_axi_arsize; + wire [1:0] BUS_axi_arburst; + wire [2:0] BUS_axi_arprot; + wire [3:0] BUS_axi_arcache; + wire BUS_axi_arvalid; + wire [30:0] BUS_axi_araddr; + wire BUS_axi_arlock; + wire BUS_axi_arready; + wire [3:0] BUS_axi_rid; + wire [63:0] BUS_axi_rdata; + wire [1:0] BUS_axi_rresp; + wire BUS_axi_rvalid; + wire BUS_axi_rlast; + wire BUS_axi_rready; wire BUSCLK; @@ -225,6 +225,9 @@ module fpgaTop wire s00_axi_rlast; wire s00_axi_rvalid; wire s00_axi_rready; + + wire [3:0] s00_axi_bid; + wire [3:0] s00_axi_rid; // 64to32 dwidth converter input interface------------------------- wire s01_axi_aclk; @@ -508,7 +511,8 @@ module fpgaTop .SDCCmdOut(SDCCmdOut), .SDCCmdOE(SDCCmdOE), .SDCCLK(SDCCLK));*/ - + ); + // ahb lite to axi bridge xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 (.s_ahb_hclk(CPUCLK), @@ -567,7 +571,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({4'b0, m_axi_awid}), + .s_axi_awid({4'b0001, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -587,7 +591,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b0, m_axi_arid}), + .s_axi_arid({4'b0001, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -623,7 +627,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b0, s00_axi_bid}), + .m_axi_bid({4'b0001, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -878,7 +882,7 @@ module fpgaTop .s_axi_awvalid(SDCout_axi_awvalid), .s_axi_awready(SDCout_axi_awready), .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(4'b0), + .s_axi_wstrb(8'b0), .s_axi_wlast(SDCout_axi_wlast), .s_axi_wvalid(SDCout_axi_wvalid), .s_axi_wready(SDCout_axi_wready), diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v index d900ddbbd..7e206c676 100644 --- a/pipelined/src/uncore/newsdc/axi_sdc_controller.v +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -175,25 +175,25 @@ reg data_int_rst; reg ctrl_rst; // AXI accessible registers -reg [31:0] argument_reg; -reg [`CMD_REG_SIZE-1:0] command_reg; -reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; -reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; -reg [0:0] software_reset_reg; -wire [31:0] response_0_reg; -wire [31:0] response_1_reg; -wire [31:0] response_2_reg; -wire [31:0] response_3_reg; -reg [`BLKSIZE_W-1:0] block_size_reg; -reg [1:0] controller_setting_reg; -wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; -wire [`INT_DATA_SIZE-1:0] data_int_status_reg; -wire [`INT_DATA_SIZE-1:0] data_int_status; -reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; -reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; -reg [`BLKCNT_W-1:0] block_count_reg; -reg [dma_addr_bits-1:0] dma_addr_reg; -reg [7:0] clock_divider_reg = 124; // 400KHz +(* mark_debug = "true" *) reg [31:0] argument_reg; +(* mark_debug = "true" *) reg [`CMD_REG_SIZE-1:0] command_reg; +(* mark_debug = "true" *) reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; +(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; +(* mark_debug = "true" *) reg [0:0] software_reset_reg; +(* mark_debug = "true" *) wire [31:0] response_0_reg; +(* mark_debug = "true" *) wire [31:0] response_1_reg; +(* mark_debug = "true" *) wire [31:0] response_2_reg; +(* mark_debug = "true" *) wire [31:0] response_3_reg; +(* mark_debug = "true" *) reg [`BLKSIZE_W-1:0] block_size_reg; +(* mark_debug = "true" *) reg [1:0] controller_setting_reg; +(* mark_debug = "true" *) wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; +(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status_reg; +(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status; +(* mark_debug = "true" *) reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; +(* mark_debug = "true" *) reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; +(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] block_count_reg; +(* mark_debug = "true" *) reg [dma_addr_bits-1:0] dma_addr_reg; +(* mark_debug = "true" *) reg [7:0] clock_divider_reg = 124; // 400KHz // ------ Clocks and resets @@ -206,7 +206,7 @@ always @(posedge clock) reg [7:0] clock_cnt; reg clock_state; -reg clock_posedge; +(* mark_debug = "true" *) reg clock_posedge; reg clock_data_in; wire fifo_almost_full; wire fifo_almost_empty; diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 64cb9224b..927462c78 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -52,7 +52,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // for FPGA, initialize with zero-stage bootloader if(PRELOAD_ENABLED) begin initial begin - ROM[0] = 64'h9581819300002197; + /*ROM[0] = 64'h9581819300002197; ROM[1] = 64'h4281420141014081; ROM[2] = 64'h4481440143814301; ROM[3] = 64'h4681460145814501; @@ -94,7 +94,649 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[39] = 64'h1047278367498082; ROM[40] = 64'h47858082dfed8b85; ROM[41] = 64'h40a7853b4015551b; - ROM[42] = 64'h808210a7a02367c9; + ROM[42] = 64'h808210a7a02367c9;*/ + + ROM[0] = 64'hc001819300002197; + ROM[1] = 64'h4281420141014081; + ROM[2] = 64'h4481440143814301; + ROM[3] = 64'h4681460145814501; + ROM[4] = 64'h4881480147814701; + ROM[5] = 64'h4a814a0149814901; + ROM[6] = 64'h4c814c014b814b01; + ROM[7] = 64'h4e814e014d814d01; + ROM[8] = 64'h0110011b4f814f01; + ROM[9] = 64'h059b45011161016e; + ROM[10] = 64'h0004063705fe0010; + ROM[11] = 64'h1ee000ef8006061b; + ROM[12] = 64'h0ff003930000100f; + ROM[13] = 64'h4e952e3110060e37; + ROM[14] = 64'hc602829b0053f2b7; + ROM[15] = 64'h2023fe02dfe312fd; + ROM[16] = 64'h829b0053f2b7007e; + ROM[17] = 64'hfe02dfe312fdc602; + ROM[18] = 64'h4de31efd000e2023; + ROM[19] = 64'h059bf1402573fdd0; + ROM[20] = 64'h0000061705e20870; + ROM[21] = 64'h0010029b01260613; + ROM[22] = 64'h67110002806702fe; + ROM[23] = 64'h0085179bf0070713; + ROM[24] = 64'h2781038007138ff9; + ROM[25] = 64'h7563470508a76a63; + ROM[26] = 64'h00a71733357902a7; + ROM[27] = 64'h3285350300001517; + ROM[28] = 64'h40301537e9598d79; + ROM[29] = 64'h8d7942250513051a; + ROM[30] = 64'he35d18177713e149; + ROM[31] = 64'he79300367713c295; + ROM[32] = 64'hf330674de3450207; + ROM[33] = 64'h861bc3701ff00613; + ROM[34] = 64'h01000637c730fff6; + ROM[35] = 64'hc35c674dcf10167d; + ROM[36] = 64'hd31c17fd001007b7; + ROM[37] = 64'h0007861b5b5cc30c; + ROM[38] = 64'h674d02072a23dfed; + ROM[39] = 64'h12634785fffd571c; + ROM[40] = 64'h80818793471006f6; + ROM[41] = 64'h4b10474cc3904501; + ROM[42] = 64'hc7d8c790c3cc4b58; + ROM[43] = 64'h086007138082e29d; + ROM[44] = 64'h0a90071300e50c63; + ROM[45] = 64'h0017e793f8e518e3; + ROM[46] = 64'hb74901d7e793b761; + ROM[47] = 64'h674dbfb50197e793; + ROM[48] = 64'h02072e23dffd5f5c; + ROM[49] = 64'h8513ff7d569866cd; + ROM[50] = 64'h053300a03533fff7; + ROM[51] = 64'h00a7e793808240a0; + ROM[52] = 64'h71398082557dbfa1; + ROM[53] = 64'hf8228181ca03e852; + ROM[54] = 64'hf426fc06ec4ef04a; + ROM[55] = 64'h008a7a13e05ae456; + ROM[56] = 64'h1463843289ae892a; + ROM[57] = 64'h4a8500959993000a; + ROM[58] = 64'h4549864ac4296b05; + ROM[59] = 64'h055402630009859b; + ROM[60] = 64'h008b73630004049b; + ROM[61] = 64'hecbff0ef86a66485; + ROM[62] = 64'h45814601468187aa; + ROM[63] = 64'h0207c8639c054531; + ROM[64] = 64'h0094979beb7ff0ef; + ROM[65] = 64'h0205406393811782; + ROM[66] = 64'h99ba020a1863873e; + ROM[67] = 64'ha8014501fc4d993e; + ROM[68] = 64'he93ff0ef45454685; + ROM[69] = 64'h70e24505fe055ae3; + ROM[70] = 64'h69e2790274a27442; + ROM[71] = 64'h61216b026aa26a42; + ROM[72] = 64'h9301020497138082; + ROM[73] = 64'hec26f0227179b7f9; + ROM[74] = 64'he44ef4064705e84a; + ROM[75] = 64'h842e84aad79867cd; + ROM[76] = 64'h8b85571c674d8932; + ROM[77] = 64'hd35c03600793dff5; + ROM[78] = 64'h571c674d02072423; + ROM[79] = 64'ha737b00026f3fffd; + ROM[80] = 64'h27f311f707130007; + ROM[81] = 64'hfef77de38f95b000; + ROM[82] = 64'h80018c235b1c674d; + ROM[83] = 64'he7934f5ccf9d8b89; + ROM[84] = 64'hb00026f3cf5c0027; + ROM[85] = 64'h0ff7071305f5e737; + ROM[86] = 64'h7de38f95b00027f3; + ROM[87] = 64'h9bf54f5c674dfef7; + ROM[88] = 64'h9737b00026f3cf5c; + ROM[89] = 64'h27f367f707130098; + ROM[90] = 64'hfef77de38f95b000; + ROM[91] = 64'h4501458146014681; + ROM[92] = 64'h80818993dd7ff0ef; + ROM[93] = 64'h0593460146814789; + ROM[94] = 64'h00f9882345211aa0; + ROM[95] = 64'ha783e50ddbfff0ef; + ROM[96] = 64'h17d21aa007130009; + ROM[97] = 64'h479102e79e6393d1; + ROM[98] = 64'hf0efa80900f98823; + ROM[99] = 64'ha78302054663da1f; + ROM[100]= 64'h46810207cc630009; + ROM[101]= 64'h0370051345814601; + ROM[102]= 64'h468187aad87ff0ef; + ROM[103]= 64'h0513403005b74601; + ROM[104]= 64'h8522fc07dae30a90; + ROM[105]= 64'h864a69a270a27402; + ROM[106]= 64'h614564e2694285a6; + ROM[107]= 64'hebd18b8583f9b5b9; + ROM[108]= 64'h4509458146014681; + ROM[109]= 64'hfc054de3d4fff0ef; + ROM[110]= 64'h123405b746014681; + ROM[111]= 64'h44e3d3dff0ef450d; + ROM[112]= 64'h77c10009a983fc05; + ROM[113]= 64'h460100f9f9b34681; + ROM[114]= 64'hd23ff0ef451d85ce; + ROM[115]= 64'h470567cdfa0547e3; + ROM[116]= 64'h4737b00026f3d3d8; + ROM[117]= 64'h27f323f70713000f; + ROM[118]= 64'hfef77de38f95b000; + ROM[119]= 64'h46810007ae2367cd; + ROM[120]= 64'h0370051385ce4601; + ROM[121]= 64'hf6054de3cefff0ef; + ROM[122]= 64'h0513458146014681; + ROM[123]= 64'h44e3cddff0ef0860; + ROM[124]= 64'h059346014681f605; + ROM[125]= 64'hccbff0ef45412000; + ROM[126]= 64'he7930109c783bf99; + ROM[127]= 64'hb78d00f988230087; + ROM[128]= 64'h0000000000000000; + ROM[129]= 64'h0000000000000000; + ROM[130]= 64'h0000000000000000; + ROM[131]= 64'h0000000000000000; + ROM[132]= 64'h0000000000000000; + ROM[133]= 64'h0000000000000000; + ROM[134]= 64'h0000000000000000; + ROM[135]= 64'h0000000000000000; + ROM[136]= 64'h0000000000000000; + ROM[137]= 64'h0000000000000000; + ROM[138]= 64'h0000000000000000; + ROM[139]= 64'h0000000000000000; + ROM[140]= 64'h0000000000000000; + ROM[141]= 64'h0000000000000000; + ROM[142]= 64'h0000000000000000; + ROM[143]= 64'h0000000000000000; + ROM[144]= 64'h0000000000000000; + ROM[145]= 64'h0000000000000000; + ROM[146]= 64'h0000000000000000; + ROM[147]= 64'h0000000000000000; + ROM[148]= 64'h0000000000000000; + ROM[149]= 64'h0000000000000000; + ROM[150]= 64'h0000000000000000; + ROM[151]= 64'h0000000000000000; + ROM[152]= 64'h0000000000000000; + ROM[153]= 64'h0000000000000000; + ROM[154]= 64'h0000000000000000; + ROM[155]= 64'h0000000000000000; + ROM[156]= 64'h0000000000000000; + ROM[157]= 64'h0000000000000000; + ROM[158]= 64'h0000000000000000; + ROM[159]= 64'h0000000000000000; + ROM[160]= 64'h0000000000000000; + ROM[161]= 64'h0000000000000000; + ROM[162]= 64'h0000000000000000; + ROM[163]= 64'h0000000000000000; + ROM[164]= 64'h0000000000000000; + ROM[165]= 64'h0000000000000000; + ROM[166]= 64'h0000000000000000; + ROM[167]= 64'h0000000000000000; + ROM[168]= 64'h0000000000000000; + ROM[169]= 64'h0000000000000000; + ROM[170]= 64'h0000000000000000; + ROM[171]= 64'h0000000000000000; + ROM[172]= 64'h0000000000000000; + ROM[173]= 64'h0000000000000000; + ROM[174]= 64'h0000000000000000; + ROM[175]= 64'h0000000000000000; + ROM[176]= 64'h0000000000000000; + ROM[177]= 64'h0000000000000000; + ROM[178]= 64'h0000000000000000; + ROM[179]= 64'h0000000000000000; + ROM[180]= 64'h0000000000000000; + ROM[181]= 64'h0000000000000000; + ROM[182]= 64'h0000000000000000; + ROM[183]= 64'h0000000000000000; + ROM[184]= 64'h0000000000000000; + ROM[185]= 64'h0000000000000000; + ROM[186]= 64'h0000000000000000; + ROM[187]= 64'h0000000000000000; + ROM[188]= 64'h0000000000000000; + ROM[189]= 64'h0000000000000000; + ROM[190]= 64'h0000000000000000; + ROM[191]= 64'h0000000000000000; + ROM[192]= 64'h0000000000000000; + ROM[193]= 64'h0000000000000000; + ROM[194]= 64'h0000000000000000; + ROM[195]= 64'h0000000000000000; + ROM[196]= 64'h0000000000000000; + ROM[197]= 64'h0000000000000000; + ROM[198]= 64'h0000000000000000; + ROM[199]= 64'h0000000000000000; + ROM[200]= 64'h0000000000000000; + ROM[201]= 64'h0000000000000000; + ROM[202]= 64'h0000000000000000; + ROM[203]= 64'h0000000000000000; + ROM[204]= 64'h0000000000000000; + ROM[205]= 64'h0000000000000000; + ROM[206]= 64'h0000000000000000; + ROM[207]= 64'h0000000000000000; + ROM[208]= 64'h0000000000000000; + ROM[209]= 64'h0000000000000000; + ROM[210]= 64'h0000000000000000; + ROM[211]= 64'h0000000000000000; + ROM[212]= 64'h0000000000000000; + ROM[213]= 64'h0000000000000000; + ROM[214]= 64'h0000000000000000; + ROM[215]= 64'h0000000000000000; + ROM[216]= 64'h0000000000000000; + ROM[217]= 64'h0000000000000000; + ROM[218]= 64'h0000000000000000; + ROM[219]= 64'h0000000000000000; + ROM[220]= 64'h0000000000000000; + ROM[221]= 64'h0000000000000000; + ROM[222]= 64'h0000000000000000; + ROM[223]= 64'h0000000000000000; + ROM[224]= 64'h0000000000000000; + ROM[225]= 64'h0000000000000000; + ROM[226]= 64'h0000000000000000; + ROM[227]= 64'h0000000000000000; + ROM[228]= 64'h0000000000000000; + ROM[229]= 64'h0000000000000000; + ROM[230]= 64'h0000000000000000; + ROM[231]= 64'h0000000000000000; + ROM[232]= 64'h0000000000000000; + ROM[233]= 64'h0000000000000000; + ROM[234]= 64'h0000000000000000; + ROM[235]= 64'h0000000000000000; + ROM[236]= 64'h0000000000000000; + ROM[237]= 64'h0000000000000000; + ROM[238]= 64'h0000000000000000; + ROM[239]= 64'h0000000000000000; + ROM[240]= 64'h0000000000000000; + ROM[241]= 64'h0000000000000000; + ROM[242]= 64'h0000000000000000; + ROM[243]= 64'h0000000000000000; + ROM[244]= 64'h0000000000000000; + ROM[245]= 64'h0000000000000000; + ROM[246]= 64'h0000000000000000; + ROM[247]= 64'h0000000000000000; + ROM[248]= 64'h0000000000000000; + ROM[249]= 64'h0000000000000000; + ROM[250]= 64'h0000000000000000; + ROM[251]= 64'h0000000000000000; + ROM[252]= 64'h0000000000000000; + ROM[253]= 64'h0000000000000000; + ROM[254]= 64'h0000000000000000; + ROM[255]= 64'h0000000000000000; + ROM[256]= 64'h0000000000000000; + ROM[257]= 64'h0000000000000000; + ROM[258]= 64'h0000000000000000; + ROM[259]= 64'h0000000000000000; + ROM[260]= 64'h0000000000000000; + ROM[261]= 64'h0000000000000000; + ROM[262]= 64'h0000000000000000; + ROM[263]= 64'h0000000000000000; + ROM[264]= 64'h0000000000000000; + ROM[265]= 64'h0000000000000000; + ROM[266]= 64'h0000000000000000; + ROM[267]= 64'h0000000000000000; + ROM[268]= 64'h0000000000000000; + ROM[269]= 64'h0000000000000000; + ROM[270]= 64'h0000000000000000; + ROM[271]= 64'h0000000000000000; + ROM[272]= 64'h0000000000000000; + ROM[273]= 64'h0000000000000000; + ROM[274]= 64'h0000000000000000; + ROM[275]= 64'h0000000000000000; + ROM[276]= 64'h0000000000000000; + ROM[277]= 64'h0000000000000000; + ROM[278]= 64'h0000000000000000; + ROM[279]= 64'h0000000000000000; + ROM[280]= 64'h0000000000000000; + ROM[281]= 64'h0000000000000000; + ROM[282]= 64'h0000000000000000; + ROM[283]= 64'h0000000000000000; + ROM[284]= 64'h0000000000000000; + ROM[285]= 64'h0000000000000000; + ROM[286]= 64'h0000000000000000; + ROM[287]= 64'h0000000000000000; + ROM[288]= 64'h0000000000000000; + ROM[289]= 64'h0000000000000000; + ROM[290]= 64'h0000000000000000; + ROM[291]= 64'h0000000000000000; + ROM[292]= 64'h0000000000000000; + ROM[293]= 64'h0000000000000000; + ROM[294]= 64'h0000000000000000; + ROM[295]= 64'h0000000000000000; + ROM[296]= 64'h0000000000000000; + ROM[297]= 64'h0000000000000000; + ROM[298]= 64'h0000000000000000; + ROM[299]= 64'h0000000000000000; + ROM[300]= 64'h0000000000000000; + ROM[301]= 64'h0000000000000000; + ROM[302]= 64'h0000000000000000; + ROM[303]= 64'h0000000000000000; + ROM[304]= 64'h0000000000000000; + ROM[305]= 64'h0000000000000000; + ROM[306]= 64'h0000000000000000; + ROM[307]= 64'h0000000000000000; + ROM[308]= 64'h0000000000000000; + ROM[309]= 64'h0000000000000000; + ROM[310]= 64'h0000000000000000; + ROM[311]= 64'h0000000000000000; + ROM[312]= 64'h0000000000000000; + ROM[313]= 64'h0000000000000000; + ROM[314]= 64'h0000000000000000; + ROM[315]= 64'h0000000000000000; + ROM[316]= 64'h0000000000000000; + ROM[317]= 64'h0000000000000000; + ROM[318]= 64'h0000000000000000; + ROM[319]= 64'h0000000000000000; + ROM[320]= 64'h0000000000000000; + ROM[321]= 64'h0000000000000000; + ROM[322]= 64'h0000000000000000; + ROM[323]= 64'h0000000000000000; + ROM[324]= 64'h0000000000000000; + ROM[325]= 64'h0000000000000000; + ROM[326]= 64'h0000000000000000; + ROM[327]= 64'h0000000000000000; + ROM[328]= 64'h0000000000000000; + ROM[329]= 64'h0000000000000000; + ROM[330]= 64'h0000000000000000; + ROM[331]= 64'h0000000000000000; + ROM[332]= 64'h0000000000000000; + ROM[333]= 64'h0000000000000000; + ROM[334]= 64'h0000000000000000; + ROM[335]= 64'h0000000000000000; + ROM[336]= 64'h0000000000000000; + ROM[337]= 64'h0000000000000000; + ROM[338]= 64'h0000000000000000; + ROM[339]= 64'h0000000000000000; + ROM[340]= 64'h0000000000000000; + ROM[341]= 64'h0000000000000000; + ROM[342]= 64'h0000000000000000; + ROM[343]= 64'h0000000000000000; + ROM[344]= 64'h0000000000000000; + ROM[345]= 64'h0000000000000000; + ROM[346]= 64'h0000000000000000; + ROM[347]= 64'h0000000000000000; + ROM[348]= 64'h0000000000000000; + ROM[349]= 64'h0000000000000000; + ROM[350]= 64'h0000000000000000; + ROM[351]= 64'h0000000000000000; + ROM[352]= 64'h0000000000000000; + ROM[353]= 64'h0000000000000000; + ROM[354]= 64'h0000000000000000; + ROM[355]= 64'h0000000000000000; + ROM[356]= 64'h0000000000000000; + ROM[357]= 64'h0000000000000000; + ROM[358]= 64'h0000000000000000; + ROM[359]= 64'h0000000000000000; + ROM[360]= 64'h0000000000000000; + ROM[361]= 64'h0000000000000000; + ROM[362]= 64'h0000000000000000; + ROM[363]= 64'h0000000000000000; + ROM[364]= 64'h0000000000000000; + ROM[365]= 64'h0000000000000000; + ROM[366]= 64'h0000000000000000; + ROM[367]= 64'h0000000000000000; + ROM[368]= 64'h0000000000000000; + ROM[369]= 64'h0000000000000000; + ROM[370]= 64'h0000000000000000; + ROM[371]= 64'h0000000000000000; + ROM[372]= 64'h0000000000000000; + ROM[373]= 64'h0000000000000000; + ROM[374]= 64'h0000000000000000; + ROM[375]= 64'h0000000000000000; + ROM[376]= 64'h0000000000000000; + ROM[377]= 64'h0000000000000000; + ROM[378]= 64'h0000000000000000; + ROM[379]= 64'h0000000000000000; + ROM[380]= 64'h0000000000000000; + ROM[381]= 64'h0000000000000000; + ROM[382]= 64'h0000000000000000; + ROM[383]= 64'h0000000000000000; + ROM[384]= 64'h0000000000000000; + ROM[385]= 64'h0000000000000000; + ROM[386]= 64'h0000000000000000; + ROM[387]= 64'h0000000000000000; + ROM[388]= 64'h0000000000000000; + ROM[389]= 64'h0000000000000000; + ROM[390]= 64'h0000000000000000; + ROM[391]= 64'h0000000000000000; + ROM[392]= 64'h0000000000000000; + ROM[393]= 64'h0000000000000000; + ROM[394]= 64'h0000000000000000; + ROM[395]= 64'h0000000000000000; + ROM[396]= 64'h0000000000000000; + ROM[397]= 64'h0000000000000000; + ROM[398]= 64'h0000000000000000; + ROM[399]= 64'h0000000000000000; + ROM[400]= 64'h0000000000000000; + ROM[401]= 64'h0000000000000000; + ROM[402]= 64'h0000000000000000; + ROM[403]= 64'h0000000000000000; + ROM[404]= 64'h0000000000000000; + ROM[405]= 64'h0000000000000000; + ROM[406]= 64'h0000000000000000; + ROM[407]= 64'h0000000000000000; + ROM[408]= 64'h0000000000000000; + ROM[409]= 64'h0000000000000000; + ROM[410]= 64'h0000000000000000; + ROM[411]= 64'h0000000000000000; + ROM[412]= 64'h0000000000000000; + ROM[413]= 64'h0000000000000000; + ROM[414]= 64'h0000000000000000; + ROM[415]= 64'h0000000000000000; + ROM[416]= 64'h0000000000000000; + ROM[417]= 64'h0000000000000000; + ROM[418]= 64'h0000000000000000; + ROM[419]= 64'h0000000000000000; + ROM[420]= 64'h0000000000000000; + ROM[421]= 64'h0000000000000000; + ROM[422]= 64'h0000000000000000; + ROM[423]= 64'h0000000000000000; + ROM[424]= 64'h0000000000000000; + ROM[425]= 64'h0000000000000000; + ROM[426]= 64'h0000000000000000; + ROM[427]= 64'h0000000000000000; + ROM[428]= 64'h0000000000000000; + ROM[429]= 64'h0000000000000000; + ROM[430]= 64'h0000000000000000; + ROM[431]= 64'h0000000000000000; + ROM[432]= 64'h0000000000000000; + ROM[433]= 64'h0000000000000000; + ROM[434]= 64'h0000000000000000; + ROM[435]= 64'h0000000000000000; + ROM[436]= 64'h0000000000000000; + ROM[437]= 64'h0000000000000000; + ROM[438]= 64'h0000000000000000; + ROM[439]= 64'h0000000000000000; + ROM[440]= 64'h0000000000000000; + ROM[441]= 64'h0000000000000000; + ROM[442]= 64'h0000000000000000; + ROM[443]= 64'h0000000000000000; + ROM[444]= 64'h0000000000000000; + ROM[445]= 64'h0000000000000000; + ROM[446]= 64'h0000000000000000; + ROM[447]= 64'h0000000000000000; + ROM[448]= 64'h0000000000000000; + ROM[449]= 64'h0000000000000000; + ROM[450]= 64'h0000000000000000; + ROM[451]= 64'h0000000000000000; + ROM[452]= 64'h0000000000000000; + ROM[453]= 64'h0000000000000000; + ROM[454]= 64'h0000000000000000; + ROM[455]= 64'h0000000000000000; + ROM[456]= 64'h0000000000000000; + ROM[457]= 64'h0000000000000000; + ROM[458]= 64'h0000000000000000; + ROM[459]= 64'h0000000000000000; + ROM[460]= 64'h0000000000000000; + ROM[461]= 64'h0000000000000000; + ROM[462]= 64'h0000000000000000; + ROM[463]= 64'h0000000000000000; + ROM[464]= 64'h0000000000000000; + ROM[465]= 64'h0000000000000000; + ROM[466]= 64'h0000000000000000; + ROM[467]= 64'h0000000000000000; + ROM[468]= 64'h0000000000000000; + ROM[469]= 64'h0000000000000000; + ROM[470]= 64'h0000000000000000; + ROM[471]= 64'h0000000000000000; + ROM[472]= 64'h0000000000000000; + ROM[473]= 64'h0000000000000000; + ROM[474]= 64'h0000000000000000; + ROM[475]= 64'h0000000000000000; + ROM[476]= 64'h0000000000000000; + ROM[477]= 64'h0000000000000000; + ROM[478]= 64'h0000000000000000; + ROM[479]= 64'h0000000000000000; + ROM[480]= 64'h0000000000000000; + ROM[481]= 64'h0000000000000000; + ROM[482]= 64'h0000000000000000; + ROM[483]= 64'h0000000000000000; + ROM[484]= 64'h0000000000000000; + ROM[485]= 64'h0000000000000000; + ROM[486]= 64'h0000000000000000; + ROM[487]= 64'h0000000000000000; + ROM[488]= 64'h0000000000000000; + ROM[489]= 64'h0000000000000000; + ROM[490]= 64'h0000000000000000; + ROM[491]= 64'h0000000000000000; + ROM[492]= 64'h0000000000000000; + ROM[493]= 64'h0000000000000000; + ROM[494]= 64'h0000000000000000; + ROM[495]= 64'h0000000000000000; + ROM[496]= 64'h0000000000000000; + ROM[497]= 64'h0000000000000000; + ROM[498]= 64'h0000000000000000; + ROM[499]= 64'h0000000000000000; + ROM[500]= 64'h0000000000000000; + ROM[501]= 64'h0000000000000000; + ROM[502]= 64'h0000000000000000; + ROM[503]= 64'h0000000000000000; + ROM[504]= 64'h0000000000000000; + ROM[505]= 64'h0000000000000000; + ROM[506]= 64'h0000000000000000; + ROM[507]= 64'h0000000000000000; + ROM[508]= 64'h0000000000000000; + ROM[509]= 64'h0000000000000000; + ROM[510]= 64'h0000000000000000; + ROM[511]= 64'h0000000000000000; + ROM[512]= 64'h0000000000000000; + ROM[513]= 64'h0000000000000000; + ROM[514]= 64'h0000000000000000; + ROM[515]= 64'h0000000000000000; + ROM[516]= 64'h0000000000000000; + ROM[517]= 64'h0000000000000000; + ROM[518]= 64'h0000000000000000; + ROM[519]= 64'h0000000000000000; + ROM[520]= 64'h0000000000000000; + ROM[521]= 64'h0000000000000000; + ROM[522]= 64'h0000000000000000; + ROM[523]= 64'h0000000000000000; + ROM[524]= 64'h0000000000000000; + ROM[525]= 64'h0000000000000000; + ROM[526]= 64'h0000000000000000; + ROM[527]= 64'h0000000000000000; + ROM[528]= 64'h0000000000000000; + ROM[529]= 64'h0000000000000000; + ROM[530]= 64'h0000000000000000; + ROM[531]= 64'h0000000000000000; + ROM[532]= 64'h0000000000000000; + ROM[533]= 64'h0000000000000000; + ROM[534]= 64'h0000000000000000; + ROM[535]= 64'h0000000000000000; + ROM[536]= 64'h0000000000000000; + ROM[537]= 64'h0000000000000000; + ROM[538]= 64'h0000000000000000; + ROM[539]= 64'h0000000000000000; + ROM[540]= 64'h0000000000000000; + ROM[541]= 64'h0000000000000000; + ROM[542]= 64'h0000000000000000; + ROM[543]= 64'h0000000000000000; + ROM[544]= 64'h0000000000000000; + ROM[545]= 64'h0000000000000000; + ROM[546]= 64'h0000000000000000; + ROM[547]= 64'h0000000000000000; + ROM[548]= 64'h0000000000000000; + ROM[549]= 64'h0000000000000000; + ROM[550]= 64'h0000000000000000; + ROM[551]= 64'h0000000000000000; + ROM[552]= 64'h0000000000000000; + ROM[553]= 64'h0000000000000000; + ROM[554]= 64'h0000000000000000; + ROM[555]= 64'h0000000000000000; + ROM[556]= 64'h0000000000000000; + ROM[557]= 64'h0000000000000000; + ROM[558]= 64'h0000000000000000; + ROM[559]= 64'h0000000000000000; + ROM[560]= 64'h0000000000000000; + ROM[561]= 64'h0000000000000000; + ROM[562]= 64'h0000000000000000; + ROM[563]= 64'h0000000000000000; + ROM[564]= 64'h0000000000000000; + ROM[565]= 64'h0000000000000000; + ROM[566]= 64'h0000000000000000; + ROM[567]= 64'h0000000000000000; + ROM[568]= 64'h0000000000000000; + ROM[569]= 64'h0000000000000000; + ROM[570]= 64'h0000000000000000; + ROM[571]= 64'h0000000000000000; + ROM[572]= 64'h0000000000000000; + ROM[573]= 64'h0000000000000000; + ROM[574]= 64'h0000000000000000; + ROM[575]= 64'h0000000000000000; + ROM[576]= 64'h0000000000000000; + ROM[577]= 64'h0000000000000000; + ROM[578]= 64'h0000000000000000; + ROM[579]= 64'h0000000000000000; + ROM[580]= 64'h0000000000000000; + ROM[581]= 64'h0000000000000000; + ROM[582]= 64'h0000000000000000; + ROM[583]= 64'h0000000000000000; + ROM[584]= 64'h0000000000000000; + ROM[585]= 64'h0000000000000000; + ROM[586]= 64'h0000000000000000; + ROM[587]= 64'h0000000000000000; + ROM[588]= 64'h0000000000000000; + ROM[589]= 64'h0000000000000000; + ROM[590]= 64'h0000000000000000; + ROM[591]= 64'h0000000000000000; + ROM[592]= 64'h0000000000000000; + ROM[593]= 64'h0000000000000000; + ROM[594]= 64'h0000000000000000; + ROM[595]= 64'h0000000000000000; + ROM[596]= 64'h0000000000000000; + ROM[597]= 64'h0000000000000000; + ROM[598]= 64'h0000000000000000; + ROM[599]= 64'h0000000000000000; + ROM[600]= 64'h0000000000000000; + ROM[601]= 64'h0000000000000000; + ROM[602]= 64'h0000000000000000; + ROM[603]= 64'h0000000000000000; + ROM[604]= 64'h0000000000000000; + ROM[605]= 64'h0000000000000000; + ROM[606]= 64'h0000000000000000; + ROM[607]= 64'h0000000000000000; + ROM[608]= 64'h0000000000000000; + ROM[609]= 64'h0000000000000000; + ROM[610]= 64'h0000000000000000; + ROM[611]= 64'h0000000000000000; + ROM[612]= 64'h0000000000000000; + ROM[613]= 64'h0000000000000000; + ROM[614]= 64'h0000000000000000; + ROM[615]= 64'h0000000000000000; + ROM[616]= 64'h0000000000000000; + ROM[617]= 64'h0000000000000000; + ROM[618]= 64'h0000000000000000; + ROM[619]= 64'h0000000000000000; + ROM[620]= 64'h0000000000000000; + ROM[621]= 64'h0000000000000000; + ROM[622]= 64'h0000000000000000; + ROM[623]= 64'h0000000000000000; + ROM[624]= 64'h0000000000000000; + ROM[625]= 64'h0000000000000000; + ROM[626]= 64'h0000000000000000; + ROM[627]= 64'h0000000000000000; + ROM[628]= 64'h0000000000000000; + ROM[629]= 64'h0000000000000000; + ROM[630]= 64'h0000000000000000; + ROM[631]= 64'h0000000000000000; + ROM[632]= 64'h0000000000000000; + ROM[633]= 64'h0000000000000000; + ROM[634]= 64'h0000000000000000; + ROM[635]= 64'h0000000000000000; + ROM[636]= 64'h0000000000000000; + ROM[637]= 64'h0000000000000000; + ROM[638]= 64'h0000000000000000; + ROM[639]= 64'h0000000000000000; + ROM[640]= 64'h00600100d2e3ca40; end end end diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 845a96c14..c58babb6f 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -56,7 +56,7 @@ module uncore ( input logic [31:0] GPIOPinsIn, // GPIO pin input value output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input - output logic UARTSout, // UART serial output + output logic UARTSout // UART serial output /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input @@ -150,7 +150,8 @@ module uncore ( end else begin : uart assign UARTSout = 0; assign UARTIntr = 0; end - if (`SDC_SUPPORTED == 1) begin : sdc + /*if (`SDC_SUPPORTED == 1) begin : sdc + SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, // sdc interface @@ -158,11 +159,12 @@ module uncore ( // interrupt to PLIC .SDCIntM ); - /*end else begin : sdc + end else begin : sdc assign SDCCLK = 0; assign SDCCmdOut = 0; - assign SDCCmdOE = 0;*/ + assign SDCCmdOE = 0; end + */ // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 92dded7ad..4fd50a2fe 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -55,7 +55,7 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsOut, // output values for GPIO output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input - output logic UARTSout, // UART serial data output + output logic UARTSout // UART serial data output /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable @@ -86,7 +86,7 @@ module wallypipelinedsoc ( .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, - .UARTSout, .MTIME_CLINT, + .UARTSout, .MTIME_CLINT /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile index 6dec9c797..8294f2375 100644 --- a/tests/custom/boot/Makefile +++ b/tests/custom/boot/Makefile @@ -16,7 +16,7 @@ OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) TARGETDIR := bin -TARGET := $(TARGETDIR)/fpga-test-sdc +TARGET := $(TARGETDIR)/boot ROOT := .. LIBRARY_DIRS := LIBRARY_FILES := @@ -24,7 +24,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -LINKER :=linker.x +LINKER :=$(ROOT)/linker1000.x AFLAGS =$(MARCH) $(MABI) -W diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index f9fa2c0fe..c9b2c6451 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -1,3 +1,4 @@ +#include #include "boot.h" /* Card type flags (card_type) */ @@ -82,6 +83,8 @@ #define ERR_DATA_CRC 36 #define ERR_DATA_FIFO 37 #define ERR_BUF_ALIGNMENT 38 +#define FR_DISK_ERR 39 +#define FR_TIMEOUT 40 struct sdc_regs { volatile uint32_t argument; @@ -111,7 +114,9 @@ struct sdc_regs { volatile uint64_t dma_addres; }; -static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013100; +#define MAX_BLOCK_CNT 0x1000 + +static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; static int errno __attribute__((section(".bss"))); // static DSTATUS drv_status __attribute__((section(".bss"))); @@ -130,6 +135,8 @@ static const char * errno_to_str(void) { case ERR_DATA_CRC: return "Data CRC error"; case ERR_DATA_FIFO: return "Data FIFO error"; case ERR_BUF_ALIGNMENT: return "Bad buffer alignment"; + case FR_DISK_ERR: return "Disk error"; + case FR_TIMEOUT: return "Timeout"; } return "Unknown error code"; } @@ -285,7 +292,9 @@ static int ini_sd(void) { // This clock divider is meant to initialize the card at // 400kHz - regs->clock_divider = 0x7c; + + // 22MHz/400kHz = 55 (base 10) = 0x37 - 0x01 = 0x36 + regs->clock_divider = 0x36; regs->software_reset = 0; while (regs->software_reset) {} usleep(5000); @@ -335,7 +344,8 @@ static int ini_sd(void) { if (send_cmd(CMD7, rca << 16) < 0) return -1; /* Clock 25MHz */ - regs->clock_divider = 3; + // 22Mhz/2 = 11Mhz + regs->clock_divider = 1; usleep(10000); /* Bus width 1-bit */ @@ -365,7 +375,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { while (count > 0) { UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return 1; if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1; sector += (card_type & CT_BLOCK) ? bcnt : bytes; count -= bcnt; diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h index ef620cda0..3dd7116a7 100644 --- a/tests/custom/boot/boot.h +++ b/tests/custom/boot/boot.h @@ -7,6 +7,9 @@ typedef unsigned char BYTE; /* char must be 8-bit */ typedef uint16_t WORD; /* 16-bit unsigned integer */ typedef uint32_t DWORD; /* 32-bit unsigned integer */ typedef uint64_t QWORD; /* 64-bit unsigned integer */ -typedef WORD WCHAR; +typedef WORD WCHAR; + +typedef QWORD LBA_t; #endif // WALLYBOOT + From 2839f4f41a93f9b78520428cb4e0663afb4a545d Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 18 Apr 2023 15:23:22 -0500 Subject: [PATCH 291/294] AHB triggers write, but AXI side doesn't update. --- fpga/constraints/debug2.xdc | 135 ++++++++++++++++++++++++++- fpga/generator/xlnx_axi_crossbar.tcl | 4 +- fpga/src/fpgaTop.v | 66 ++++++------- 3 files changed, 168 insertions(+), 37 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 13733e579..ec1d1d550 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -748,9 +748,9 @@ connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_aw create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe144] +set_property port_width 32 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} ]] +connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]}]] create_debug_port u_ila_0 probe @@ -1016,3 +1016,134 @@ create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe192] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] +connect_debug_port u_ila_0/probe192 [get_nets [list {SDCin_axi_awaddr[0]} {SDCin_axi_awaddr[1]} {SDCin_axi_awaddr[2]} {SDCin_axi_awaddr[3]} {SDCin_axi_awaddr[4]} {SDCin_axi_awaddr[5]} {SDCin_axi_awaddr[6]} {SDCin_axi_awaddr[7]} {SDCin_axi_awaddr[8]} {SDCin_axi_awaddr[9]} {SDCin_axi_awaddr[10]} {SDCin_axi_awaddr[11]} {SDCin_axi_awaddr[12]} {SDCin_axi_awaddr[13]} {SDCin_axi_awaddr[14]} {SDCin_axi_awaddr[15]} {SDCin_axi_awaddr[16]} {SDCin_axi_awaddr[17]} {SDCin_axi_awaddr[18]} {SDCin_axi_awaddr[19]} {SDCin_axi_awaddr[20]} {SDCin_axi_awaddr[21]} {SDCin_axi_awaddr[22]} {SDCin_axi_awaddr[23]} {SDCin_axi_awaddr[24]} {SDCin_axi_awaddr[25]} {SDCin_axi_awaddr[26]} {SDCin_axi_awaddr[27]} {SDCin_axi_awaddr[28]} {SDCin_axi_awaddr[29]} {SDCin_axi_awaddr[30]} {SDCin_axi_awaddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe193] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] +connect_debug_port u_ila_0/probe193 [get_nets [list {SDCin_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe194] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] +connect_debug_port u_ila_0/probe194 [get_nets [list {SDCin_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe195] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] +connect_debug_port u_ila_0/probe195 [get_nets [list {SDCin_axi_wdata[0]} {SDCin_axi_wdata[1]} {SDCin_axi_wdata[2]} {SDCin_axi_wdata[3]} {SDCin_axi_wdata[4]} {SDCin_axi_wdata[5]} {SDCin_axi_wdata[6]} {SDCin_axi_wdata[7]} {SDCin_axi_wdata[8]} {SDCin_axi_wdata[9]} {SDCin_axi_wdata[10]} {SDCin_axi_wdata[11]} {SDCin_axi_wdata[12]} {SDCin_axi_wdata[13]} {SDCin_axi_wdata[14]} {SDCin_axi_wdata[15]} {SDCin_axi_wdata[16]} {SDCin_axi_wdata[17]} {SDCin_axi_wdata[18]} {SDCin_axi_wdata[19]} {SDCin_axi_wdata[20]} {SDCin_axi_wdata[21]} {SDCin_axi_wdata[22]} {SDCin_axi_wdata[23]} {SDCin_axi_wdata[24]} {SDCin_axi_wdata[25]} {SDCin_axi_wdata[26]} {SDCin_axi_wdata[27]} {SDCin_axi_wdata[28]} {SDCin_axi_wdata[29]} {SDCin_axi_wdata[30]} {SDCin_axi_wdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe196] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] +connect_debug_port u_ila_0/probe196 [get_nets [list {SDCin_axi_wvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe197] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] +connect_debug_port u_ila_0/probe197 [get_nets [list {SDCin_axi_wready}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe198] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] +connect_debug_port u_ila_0/probe198 [get_nets [list {SDCin_axi_bresp[0]} {SDCin_axi_bresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe199] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] +connect_debug_port u_ila_0/probe199 [get_nets [list {SDCin_axi_bvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe200] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] +connect_debug_port u_ila_0/probe200 [get_nets [list {SDCin_axi_bready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe201] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] +connect_debug_port u_ila_0/probe201 [get_nets [list {SDCin_axi_araddr[0]} {SDCin_axi_araddr[1]} {SDCin_axi_araddr[2]} {SDCin_axi_araddr[3]} {SDCin_axi_araddr[4]} {SDCin_axi_araddr[5]} {SDCin_axi_araddr[6]} {SDCin_axi_araddr[7]} {SDCin_axi_araddr[8]} {SDCin_axi_araddr[9]} {SDCin_axi_araddr[10]} {SDCin_axi_araddr[11]} {SDCin_axi_araddr[12]} {SDCin_axi_araddr[13]} {SDCin_axi_araddr[14]} {SDCin_axi_araddr[15]} {SDCin_axi_araddr[16]} {SDCin_axi_araddr[17]} {SDCin_axi_araddr[18]} {SDCin_axi_araddr[19]} {SDCin_axi_araddr[20]} {SDCin_axi_araddr[21]} {SDCin_axi_araddr[22]} {SDCin_axi_araddr[23]} {SDCin_axi_araddr[24]} {SDCin_axi_araddr[25]} {SDCin_axi_araddr[26]} {SDCin_axi_araddr[27]} {SDCin_axi_araddr[28]} {SDCin_axi_araddr[29]} {SDCin_axi_araddr[30]} {SDCin_axi_araddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe202] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] +connect_debug_port u_ila_0/probe202 [get_nets [list {SDCin_axi_arvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe203] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] +connect_debug_port u_ila_0/probe203 [get_nets [list {SDCin_axi_arready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe204] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] +connect_debug_port u_ila_0/probe204 [get_nets [list {SDCin_axi_rdata[0]} {SDCin_axi_rdata[1]} {SDCin_axi_rdata[2]} {SDCin_axi_rdata[3]} {SDCin_axi_rdata[4]} {SDCin_axi_rdata[5]} {SDCin_axi_rdata[6]} {SDCin_axi_rdata[7]} {SDCin_axi_rdata[8]} {SDCin_axi_rdata[9]} {SDCin_axi_rdata[10]} {SDCin_axi_rdata[11]} {SDCin_axi_rdata[12]} {SDCin_axi_rdata[13]} {SDCin_axi_rdata[14]} {SDCin_axi_rdata[15]} {SDCin_axi_rdata[16]} {SDCin_axi_rdata[17]} {SDCin_axi_rdata[18]} {SDCin_axi_rdata[19]} {SDCin_axi_rdata[20]} {SDCin_axi_rdata[21]} {SDCin_axi_rdata[22]} {SDCin_axi_rdata[23]} {SDCin_axi_rdata[24]} {SDCin_axi_rdata[25]} {SDCin_axi_rdata[26]} {SDCin_axi_rdata[27]} {SDCin_axi_rdata[28]} {SDCin_axi_rdata[29]} {SDCin_axi_rdata[30]} {SDCin_axi_rdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe205] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] +connect_debug_port u_ila_0/probe205 [get_nets [list {SDCin_axi_rresp[0]} {SDCin_axi_rresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe206] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] +connect_debug_port u_ila_0/probe206 [get_nets [list {SDCin_axi_rvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe207] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] +connect_debug_port u_ila_0/probe207 [get_nets [list {SDCin_axi_rready}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe208] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] +connect_debug_port u_ila_0/probe208 [get_nets [list {s01_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe209] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] +connect_debug_port u_ila_0/probe209 [get_nets [list {s01_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe210] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] +connect_debug_port u_ila_0/probe210 [get_nets [list {s00_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe211] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] +connect_debug_port u_ila_0/probe211 [get_nets [list {s00_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe212] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] +connect_debug_port u_ila_0/probe212 [get_nets [list {axi4in_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe213] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] +connect_debug_port u_ila_0/probe213 [get_nets [list {axi4in_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe214] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] +connect_debug_port u_ila_0/probe214 [get_nets [list {SDCout_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe215] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] +connect_debug_port u_ila_0/probe215 [get_nets [list {SDCout_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe216] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] +connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe217] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] +connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_awready}]] diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl index 1d9eb4e78..ed44d9997 100644 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -19,8 +19,8 @@ create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module set_property -dict [list CONFIG.NUM_SI {2} \ CONFIG.DATA_WIDTH {64} \ CONFIG.ID_WIDTH {4} \ - CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ + # CONFIG.M01_S01_READ_CONNECTIVITY {0} \ + # CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 03758249e..42957f63b 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -199,8 +199,8 @@ module fpgaTop wire [2:0]s00_axi_awprot; wire [3:0]s00_axi_awregion; wire [3:0]s00_axi_awqos; - wire s00_axi_awvalid; - wire s00_axi_awready; + (* mark_debug = "true" *) wire s00_axi_awvalid; + (* mark_debug = "true" *) wire s00_axi_awready; wire [63:0]s00_axi_wdata; wire [7:0]s00_axi_wstrb; wire s00_axi_wlast; @@ -242,8 +242,8 @@ module fpgaTop wire [2:0]s01_axi_awprot; wire [3:0]s01_axi_awregion; wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - wire s01_axi_awvalid; - wire s01_axi_awready; + (* mark_debug = "true" *) wire s01_axi_awvalid; + (* mark_debug = "true" *) wire s01_axi_awready; wire [63:0]s01_axi_wdata; wire [7:0]s01_axi_wstrb; wire s01_axi_wlast; @@ -279,8 +279,8 @@ module fpgaTop wire [2:0]axi4in_axi_awprot; wire [3:0]axi4in_axi_awregion; wire [3:0]axi4in_axi_awqos; - wire axi4in_axi_awvalid; - wire axi4in_axi_awready; + (* mark_debug = "true" *) wire axi4in_axi_awvalid; + (* mark_debug = "true" *) wire axi4in_axi_awready; wire [31:0]axi4in_axi_wdata; wire [3:0]axi4in_axi_wstrb; wire axi4in_axi_wlast; @@ -307,25 +307,25 @@ module fpgaTop wire axi4in_axi_rready; // AXI4 to AXI4-Lite Protocol converter output - wire [31:0]SDCin_axi_awaddr; - wire [2:0]SDCin_axi_awprot; - wire SDCin_axi_awvalid; - wire SDCin_axi_awready; - wire [31:0]SDCin_axi_wdata; - wire [3:0]SDCin_axi_wstrb; - wire SDCin_axi_wvalid; - wire SDCin_axi_wready; - wire [1:0]SDCin_axi_bresp; - wire SDCin_axi_bvalid; - wire SDCin_axi_bready; - wire [31:0]SDCin_axi_araddr; - wire [2:0]SDCin_axi_arprot; - wire SDCin_axi_arvalid; - wire SDCin_axi_arready; - wire [31:0]SDCin_axi_rdata; - wire [1:0]SDCin_axi_rresp; - wire SDCin_axi_rvalid; - wire SDCin_axi_rready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; + (* mark_debug = "true" *) wire SDCin_axi_awvalid; + (* mark_debug = "true" *) wire SDCin_axi_awready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; + (* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; + (* mark_debug = "true" *) wire SDCin_axi_wvalid; + (* mark_debug = "true" *) wire SDCin_axi_wready; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; + (* mark_debug = "true" *) wire SDCin_axi_bvalid; + (* mark_debug = "true" *) wire SDCin_axi_bready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; + (* mark_debug = "true" *) wire SDCin_axi_arvalid; + (* mark_debug = "true" *) wire SDCin_axi_arready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; + (* mark_debug = "true" *) wire SDCin_axi_rvalid; + (* mark_debug = "true" *) wire SDCin_axi_rready; // ---------------------------------------------------------------- // 32to64 dwidth converter input interface ----------------------- @@ -338,8 +338,8 @@ module fpgaTop wire [2:0]SDCout_axi_awprot; wire [3:0]SDCout_axi_awregion; wire [3:0]SDCout_axi_awqos; - wire SDCout_axi_awvalid; - wire SDCout_axi_awready; + (* mark_debug = "true" *) wire SDCout_axi_awvalid; + (* mark_debug = "true" *) wire SDCout_axi_awready; wire [31:0]SDCout_axi_wdata; wire [3:0]SDCout_axi_wstrb; wire SDCout_axi_wlast; @@ -376,8 +376,8 @@ module fpgaTop wire [2:0]m01_axi_awprot; wire [3:0]m01_axi_awregion; wire [3:0]m01_axi_awqos; - wire m01_axi_awvalid; - wire m01_axi_awready; + (* mark_debug = "true" *) wire m01_axi_awvalid; + (* mark_debug = "true" *) wire m01_axi_awready; wire [63:0]m01_axi_wdata; wire [3:0]m01_axi_wstrb; wire m01_axi_wlast; @@ -571,7 +571,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({4'b0001, m_axi_awid}), + .s_axi_awid({4'b1000, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -591,7 +591,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b0001, m_axi_arid}), + .s_axi_arid({4'b1000, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -627,7 +627,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b0001, s00_axi_bid}), + .m_axi_bid({4'b1000, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -643,7 +643,7 @@ module fpgaTop .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({4'b0, s00_axi_rid}), + .m_axi_rid({4'b1000, s00_axi_rid}), .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), From 40f81d5da68202600f2f7d98fbec25643f10e5cf Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 26 May 2023 15:42:33 -0500 Subject: [PATCH 292/294] The Vivado-RISC-V SDC works. Wally is now booting through it. --- config/fpga/wally-config.vh | 6 +- fpga/constraints/debug2.xdc | 445 ++++++----- fpga/constraints/marked_debug.txt | 1 + fpga/generator/xlnx_axi_crossbar.tcl | 4 +- fpga/src/fpgaTop.v | 260 ++++--- .../src/uncore/newsdc/axi_sdc_controller.v | 2 +- pipelined/src/uncore/newsdc/sd_data_master.v | 8 +- .../src/uncore/newsdc/sd_data_serial_host.v | 2 +- src/generic/mem/ram1p1rwbe.sv | 8 +- src/generic/mem/rom1p1r.sv | 735 +++--------------- src/mmu/adrdecs.sv | 1 - src/uncore/ram_ahb.sv | 2 +- src/uncore/uncore.sv | 60 +- src/wally/wallypipelinedsoc.sv | 49 +- tests/custom/boot/boot.c | 85 +- tests/custom/linker1000.x | 1 + 16 files changed, 639 insertions(+), 1030 deletions(-) diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index 007562a17..c89d3eec8 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -93,9 +93,9 @@ `define BOOTROM_BASE 56'h00001000 `define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b0 -`define UNCORE_RAM_BASE 56'h100000000 -`define UNCORE_RAM_RANGE 56'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h000002000 +`define UNCORE_RAM_RANGE 56'h000000FFF `define EXT_MEM_SUPPORTED 1'b1 `define EXT_MEM_BASE 56'h80000000 diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index ec1d1d550..0db255fa0 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -717,433 +717,524 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] +# ============== AXI SDC STUFF ================ create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe139] +set_property port_width 1 [get_debug_ports u_ila_0/probe139] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] -connect_debug_port u_ila_0/probe139 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]] - +connect_debug_port u_ila_0/probe139 [get_nets [list {axiSDC/clock_posedge}]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe140] +set_property port_width 32 [get_debug_ports u_ila_0/probe140] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] -connect_debug_port u_ila_0/probe140 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]] - +connect_debug_port u_ila_0/probe140 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe141] +set_property port_width 25 [get_debug_ports u_ila_0/probe141] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] -connect_debug_port u_ila_0/probe141 [get_nets [list {m_axi_awsize[0]} {m_axi_awsize[1]} {m_axi_awsize[2]} ]] - +connect_debug_port u_ila_0/probe141 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe142] +set_property port_width 28 [get_debug_ports u_ila_0/probe142] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] -connect_debug_port u_ila_0/probe142 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]] - +connect_debug_port u_ila_0/probe142 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe143] +set_property port_width 1 [get_debug_ports u_ila_0/probe143] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] -connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]] - +connect_debug_port u_ila_0/probe143 [get_nets [list {axiSDC/software_reset_reg}]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]}]] - +connect_debug_port u_ila_0/probe144 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe145] +set_property port_width 32 [get_debug_ports u_ila_0/probe145] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] -connect_debug_port u_ila_0/probe145 [get_nets [list {m_axi_awprot[0]} {m_axi_awprot[1]} {m_axi_awprot[2]} ]] - +connect_debug_port u_ila_0/probe145 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe146] +set_property port_width 32 [get_debug_ports u_ila_0/probe146] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] -connect_debug_port u_ila_0/probe146 [get_nets [list {m_axi_awvalid}]] - +connect_debug_port u_ila_0/probe146 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe147] +set_property port_width 32 [get_debug_ports u_ila_0/probe147] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] -connect_debug_port u_ila_0/probe147 [get_nets [list {m_axi_awready}]] - +connect_debug_port u_ila_0/probe147 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe148] +set_property port_width 12 [get_debug_ports u_ila_0/probe148] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] -connect_debug_port u_ila_0/probe148 [get_nets [list {m_axi_awlock}]] - +connect_debug_port u_ila_0/probe148 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe149] +set_property port_width 2 [get_debug_ports u_ila_0/probe149] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149] -connect_debug_port u_ila_0/probe149 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]] - +connect_debug_port u_ila_0/probe149 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe150] +set_property port_width 5 [get_debug_ports u_ila_0/probe150] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150] -connect_debug_port u_ila_0/probe150 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]] - +connect_debug_port u_ila_0/probe150 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe151] +set_property port_width 6 [get_debug_ports u_ila_0/probe151] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151] -connect_debug_port u_ila_0/probe151 [get_nets [list {m_axi_wlast}]] - +connect_debug_port u_ila_0/probe151 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe152] +set_property port_width 6 [get_debug_ports u_ila_0/probe152] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152] -connect_debug_port u_ila_0/probe152 [get_nets [list {m_axi_wvalid}]] - +connect_debug_port u_ila_0/probe152 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe153] +set_property port_width 5 [get_debug_ports u_ila_0/probe153] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153] -connect_debug_port u_ila_0/probe153 [get_nets [list {m_axi_wready}]] - +connect_debug_port u_ila_0/probe153 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe154] +set_property port_width 6 [get_debug_ports u_ila_0/probe154] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] -connect_debug_port u_ila_0/probe154 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]] - +connect_debug_port u_ila_0/probe154 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe155] +set_property port_width 16 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] -connect_debug_port u_ila_0/probe155 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]] - +connect_debug_port u_ila_0/probe155 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe156] +set_property port_width 8 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_bvalid}]] - +connect_debug_port u_ila_0/probe156 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe157] +set_property port_width 4 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_bready}]] - +connect_debug_port u_ila_0/probe157 [get_nets [list {s00_axi_awid[0]} {s00_axi_awid[1]} {s00_axi_awid[2]} {s00_axi_awid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe158] +set_property port_width 32 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]] - +connect_debug_port u_ila_0/probe158 [get_nets [list {s00_axi_awaddr[0]} {s00_axi_awaddr[1]} {s00_axi_awaddr[2]} {s00_axi_awaddr[3]} {s00_axi_awaddr[4]} {s00_axi_awaddr[5]} {s00_axi_awaddr[6]} {s00_axi_awaddr[7]} {s00_axi_awaddr[8]} {s00_axi_awaddr[9]} {s00_axi_awaddr[10]} {s00_axi_awaddr[11]} {s00_axi_awaddr[12]} {s00_axi_awaddr[13]} {s00_axi_awaddr[14]} {s00_axi_awaddr[15]} {s00_axi_awaddr[16]} {s00_axi_awaddr[17]} {s00_axi_awaddr[18]} {s00_axi_awaddr[19]} {s00_axi_awaddr[20]} {s00_axi_awaddr[21]} {s00_axi_awaddr[22]} {s00_axi_awaddr[23]} {s00_axi_awaddr[24]} {s00_axi_awaddr[25]} {s00_axi_awaddr[26]} {s00_axi_awaddr[27]} {s00_axi_awaddr[28]} {s00_axi_awaddr[29]} {s00_axi_awaddr[30]} {s00_axi_awaddr[31]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]] - +connect_debug_port u_ila_0/probe159 [get_nets [list {s00_axi_awlen[0]} {s00_axi_awlen[1]} {s00_axi_awlen[2]} {s00_axi_awlen[3]} {s00_axi_awlen[4]} {s00_axi_awlen[5]} {s00_axi_awlen[6]} {s00_axi_awlen[7]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]] - +connect_debug_port u_ila_0/probe160 [get_nets [list {s00_axi_awsize[0]} {s00_axi_awsize[1]} {s00_axi_awsize[2]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]] - +connect_debug_port u_ila_0/probe161 [get_nets [list {s00_axi_awburst[0]} {s00_axi_awburst[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe162] +set_property port_width 1 [get_debug_ports u_ila_0/probe162] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] -connect_debug_port u_ila_0/probe162 [get_nets [list {m_axi_arprot[0]} {m_axi_arprot[1]} {m_axi_arprot[2]} ]] - +connect_debug_port u_ila_0/probe162 [get_nets [list {s00_axi_awlock}]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe163] +set_property port_width 1 [get_debug_ports u_ila_0/probe163] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] -connect_debug_port u_ila_0/probe163 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]] - +connect_debug_port u_ila_0/probe163 [get_nets [list {s00_axi_awvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe164] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] -connect_debug_port u_ila_0/probe164 [get_nets [list {m_axi_arvalid}]] - +connect_debug_port u_ila_0/probe164 [get_nets [list {s00_axi_awready}]] create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe165] +set_property port_width 64 [get_debug_ports u_ila_0/probe165] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] -connect_debug_port u_ila_0/probe165 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} ]] - +connect_debug_port u_ila_0/probe165 [get_nets [list {s00_axi_wdata[0]} {s00_axi_wdata[1]} {s00_axi_wdata[2]} {s00_axi_wdata[3]} {s00_axi_wdata[4]} {s00_axi_wdata[5]} {s00_axi_wdata[6]} {s00_axi_wdata[7]} {s00_axi_wdata[8]} {s00_axi_wdata[9]} {s00_axi_wdata[10]} {s00_axi_wdata[11]} {s00_axi_wdata[12]} {s00_axi_wdata[13]} {s00_axi_wdata[14]} {s00_axi_wdata[15]} {s00_axi_wdata[16]} {s00_axi_wdata[17]} {s00_axi_wdata[18]} {s00_axi_wdata[19]} {s00_axi_wdata[20]} {s00_axi_wdata[21]} {s00_axi_wdata[22]} {s00_axi_wdata[23]} {s00_axi_wdata[24]} {s00_axi_wdata[25]} {s00_axi_wdata[26]} {s00_axi_wdata[27]} {s00_axi_wdata[28]} {s00_axi_wdata[29]} {s00_axi_wdata[30]} {s00_axi_wdata[31]} {s00_axi_wdata[32]} {s00_axi_wdata[33]} {s00_axi_wdata[34]} {s00_axi_wdata[35]} {s00_axi_wdata[36]} {s00_axi_wdata[37]} {s00_axi_wdata[38]} {s00_axi_wdata[39]} {s00_axi_wdata[40]} {s00_axi_wdata[41]} {s00_axi_wdata[42]} {s00_axi_wdata[43]} {s00_axi_wdata[44]} {s00_axi_wdata[45]} {s00_axi_wdata[46]} {s00_axi_wdata[47]} {s00_axi_wdata[48]} {s00_axi_wdata[49]} {s00_axi_wdata[50]} {s00_axi_wdata[51]} {s00_axi_wdata[52]} {s00_axi_wdata[53]} {s00_axi_wdata[54]} {s00_axi_wdata[55]} {s00_axi_wdata[56]} {s00_axi_wdata[57]} {s00_axi_wdata[58]} {s00_axi_wdata[59]} {s00_axi_wdata[60]} {s00_axi_wdata[61]} {s00_axi_wdata[62]} {s00_axi_wdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe166] +set_property port_width 8 [get_debug_ports u_ila_0/probe166] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] -connect_debug_port u_ila_0/probe166 [get_nets [list {m_axi_arlock}]] - +connect_debug_port u_ila_0/probe166 [get_nets [list {s00_axi_wstrb[0]} {s00_axi_wstrb[1]} {s00_axi_wstrb[2]} {s00_axi_wstrb[3]} {s00_axi_wstrb[4]} {s00_axi_wstrb[5]} {s00_axi_wstrb[6]} {s00_axi_wstrb[7]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe167] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] -connect_debug_port u_ila_0/probe167 [get_nets [list {m_axi_arready}]] - +connect_debug_port u_ila_0/probe167 [get_nets [list {s00_axi_wlast}]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe168] +set_property port_width 1 [get_debug_ports u_ila_0/probe168] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] -connect_debug_port u_ila_0/probe168 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]] - +connect_debug_port u_ila_0/probe168 [get_nets [list {s00_axi_wvalid}]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe169] +set_property port_width 1 [get_debug_ports u_ila_0/probe169] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] -connect_debug_port u_ila_0/probe169 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]] - +connect_debug_port u_ila_0/probe169 [get_nets [list {s00_axi_wready}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe170] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] -connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]] - +connect_debug_port u_ila_0/probe170 [get_nets [list {s00_axi_bresp[0]} {s00_axi_bresp[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe171] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] -connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_rvalid}]] - +connect_debug_port u_ila_0/probe171 [get_nets [list {s00_axi_bvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe172] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] -connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_rlast}]] - +connect_debug_port u_ila_0/probe172 [get_nets [list {s00_axi_bready}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe173] +set_property port_width 32 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] -connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] +connect_debug_port u_ila_0/probe173 [get_nets [list {s00_axi_araddr[0]} {s00_axi_araddr[1]} {s00_axi_araddr[2]} {s00_axi_araddr[3]} {s00_axi_araddr[4]} {s00_axi_araddr[5]} {s00_axi_araddr[6]} {s00_axi_araddr[7]} {s00_axi_araddr[8]} {s00_axi_araddr[9]} {s00_axi_araddr[10]} {s00_axi_araddr[11]} {s00_axi_araddr[12]} {s00_axi_araddr[13]} {s00_axi_araddr[14]} {s00_axi_araddr[15]} {s00_axi_araddr[16]} {s00_axi_araddr[17]} {s00_axi_araddr[18]} {s00_axi_araddr[19]} {s00_axi_araddr[20]} {s00_axi_araddr[21]} {s00_axi_araddr[22]} {s00_axi_araddr[23]} {s00_axi_araddr[24]} {s00_axi_araddr[25]} {s00_axi_araddr[26]} {s00_axi_araddr[27]} {s00_axi_araddr[28]} {s00_axi_araddr[29]} {s00_axi_araddr[30]} {s00_axi_araddr[31]} ]] -# ============== AXI SDC STUFF ================ create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe174] +set_property port_width 8 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {axiSDC/clock_posedge}]] +connect_debug_port u_ila_0/probe174 [get_nets [list {s00_axi_arlen[0]} {s00_axi_arlen[1]} {s00_axi_arlen[2]} {s00_axi_arlen[3]} {s00_axi_arlen[4]} {s00_axi_arlen[5]} {s00_axi_arlen[6]} {s00_axi_arlen[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe175] +set_property port_width 3 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]] +connect_debug_port u_ila_0/probe175 [get_nets [list {s00_axi_arsize[0]} {s00_axi_arsize[1]} {s00_axi_arsize[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 25 [get_debug_ports u_ila_0/probe176] +set_property port_width 2 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]] +connect_debug_port u_ila_0/probe176 [get_nets [list {s00_axi_arburst[0]} {s00_axi_arburst[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 28 [get_debug_ports u_ila_0/probe177] +set_property port_width 1 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]] +connect_debug_port u_ila_0/probe177 [get_nets [list {s00_axi_arvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {axiSDC/software_reset_reg}]] +connect_debug_port u_ila_0/probe178 [get_nets [list {s00_axi_arready}]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe179] +set_property port_width 64 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]] +connect_debug_port u_ila_0/probe179 [get_nets [list {s00_axi_rdata[0]} {s00_axi_rdata[1]} {s00_axi_rdata[2]} {s00_axi_rdata[3]} {s00_axi_rdata[4]} {s00_axi_rdata[5]} {s00_axi_rdata[6]} {s00_axi_rdata[7]} {s00_axi_rdata[8]} {s00_axi_rdata[9]} {s00_axi_rdata[10]} {s00_axi_rdata[11]} {s00_axi_rdata[12]} {s00_axi_rdata[13]} {s00_axi_rdata[14]} {s00_axi_rdata[15]} {s00_axi_rdata[16]} {s00_axi_rdata[17]} {s00_axi_rdata[18]} {s00_axi_rdata[19]} {s00_axi_rdata[20]} {s00_axi_rdata[21]} {s00_axi_rdata[22]} {s00_axi_rdata[23]} {s00_axi_rdata[24]} {s00_axi_rdata[25]} {s00_axi_rdata[26]} {s00_axi_rdata[27]} {s00_axi_rdata[28]} {s00_axi_rdata[29]} {s00_axi_rdata[30]} {s00_axi_rdata[31]} {s00_axi_rdata[32]} {s00_axi_rdata[33]} {s00_axi_rdata[34]} {s00_axi_rdata[35]} {s00_axi_rdata[36]} {s00_axi_rdata[37]} {s00_axi_rdata[38]} {s00_axi_rdata[39]} {s00_axi_rdata[40]} {s00_axi_rdata[41]} {s00_axi_rdata[42]} {s00_axi_rdata[43]} {s00_axi_rdata[44]} {s00_axi_rdata[45]} {s00_axi_rdata[46]} {s00_axi_rdata[47]} {s00_axi_rdata[48]} {s00_axi_rdata[49]} {s00_axi_rdata[50]} {s00_axi_rdata[51]} {s00_axi_rdata[52]} {s00_axi_rdata[53]} {s00_axi_rdata[54]} {s00_axi_rdata[55]} {s00_axi_rdata[56]} {s00_axi_rdata[57]} {s00_axi_rdata[58]} {s00_axi_rdata[59]} {s00_axi_rdata[60]} {s00_axi_rdata[61]} {s00_axi_rdata[62]} {s00_axi_rdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe180] +set_property port_width 2 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]] +connect_debug_port u_ila_0/probe180 [get_nets [list {s00_axi_rresp[0]} {s00_axi_rresp[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe181] +set_property port_width 1 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]] +connect_debug_port u_ila_0/probe181 [get_nets [list {s00_axi_rlast}]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe182] +set_property port_width 1 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]] +connect_debug_port u_ila_0/probe182 [get_nets [list {s00_axi_rvalid}]] create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe183] +set_property port_width 1 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]] +connect_debug_port u_ila_0/probe183 [get_nets [list {s00_axi_rready}]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe184] +set_property port_width 4 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]] +connect_debug_port u_ila_0/probe184 [get_nets [list {s00_axi_bid[0]} {s00_axi_bid[1]} {s00_axi_bid[2]} {s00_axi_bid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe185] +set_property port_width 4 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]] +connect_debug_port u_ila_0/probe185 [get_nets [list {s00_axi_rid[0]} {s00_axi_rid[1]} {s00_axi_rid[2]} {s00_axi_rid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe186] +set_property port_width 1 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]] +connect_debug_port u_ila_0/probe186 [get_nets [list {s00_axi_awlock}]] + create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe187] +set_property port_width 4 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]] +connect_debug_port u_ila_0/probe187 [get_nets [list {m01_axi_awid[0]} {m01_axi_awid[1]} {m01_axi_awid[2]} {m01_axi_awid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe188] +set_property port_width 32 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]] +connect_debug_port u_ila_0/probe188 [get_nets [list {m01_axi_awaddr[0]} {m01_axi_awaddr[1]} {m01_axi_awaddr[2]} {m01_axi_awaddr[3]} {m01_axi_awaddr[4]} {m01_axi_awaddr[5]} {m01_axi_awaddr[6]} {m01_axi_awaddr[7]} {m01_axi_awaddr[8]} {m01_axi_awaddr[9]} {m01_axi_awaddr[10]} {m01_axi_awaddr[11]} {m01_axi_awaddr[12]} {m01_axi_awaddr[13]} {m01_axi_awaddr[14]} {m01_axi_awaddr[15]} {m01_axi_awaddr[16]} {m01_axi_awaddr[17]} {m01_axi_awaddr[18]} {m01_axi_awaddr[19]} {m01_axi_awaddr[20]} {m01_axi_awaddr[21]} {m01_axi_awaddr[22]} {m01_axi_awaddr[23]} {m01_axi_awaddr[24]} {m01_axi_awaddr[25]} {m01_axi_awaddr[26]} {m01_axi_awaddr[27]} {m01_axi_awaddr[28]} {m01_axi_awaddr[29]} {m01_axi_awaddr[30]} {m01_axi_awaddr[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 6 [get_debug_ports u_ila_0/probe189] +set_property port_width 8 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]] +connect_debug_port u_ila_0/probe189 [get_nets [list {m01_axi_awlen[0]} {m01_axi_awlen[1]} {m01_axi_awlen[2]} {m01_axi_awlen[3]} {m01_axi_awlen[4]} {m01_axi_awlen[5]} {m01_axi_awlen[6]} {m01_axi_awlen[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 16 [get_debug_ports u_ila_0/probe190] +set_property port_width 3 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]] +connect_debug_port u_ila_0/probe190 [get_nets [list {m01_axi_awsize[0]} {m01_axi_awsize[1]} {m01_axi_awsize[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe191] +set_property port_width 2 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] +connect_debug_port u_ila_0/probe191 [get_nets [list {m01_axi_awburst[0]} {m01_axi_awburst[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe192] +set_property port_width 1 [get_debug_ports u_ila_0/probe192] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {SDCin_axi_awaddr[0]} {SDCin_axi_awaddr[1]} {SDCin_axi_awaddr[2]} {SDCin_axi_awaddr[3]} {SDCin_axi_awaddr[4]} {SDCin_axi_awaddr[5]} {SDCin_axi_awaddr[6]} {SDCin_axi_awaddr[7]} {SDCin_axi_awaddr[8]} {SDCin_axi_awaddr[9]} {SDCin_axi_awaddr[10]} {SDCin_axi_awaddr[11]} {SDCin_axi_awaddr[12]} {SDCin_axi_awaddr[13]} {SDCin_axi_awaddr[14]} {SDCin_axi_awaddr[15]} {SDCin_axi_awaddr[16]} {SDCin_axi_awaddr[17]} {SDCin_axi_awaddr[18]} {SDCin_axi_awaddr[19]} {SDCin_axi_awaddr[20]} {SDCin_axi_awaddr[21]} {SDCin_axi_awaddr[22]} {SDCin_axi_awaddr[23]} {SDCin_axi_awaddr[24]} {SDCin_axi_awaddr[25]} {SDCin_axi_awaddr[26]} {SDCin_axi_awaddr[27]} {SDCin_axi_awaddr[28]} {SDCin_axi_awaddr[29]} {SDCin_axi_awaddr[30]} {SDCin_axi_awaddr[31]} ]] +connect_debug_port u_ila_0/probe192 [get_nets [list {m01_axi_awlock}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe193] +set_property port_width 4 [get_debug_ports u_ila_0/probe193] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {SDCin_axi_awvalid}]] +connect_debug_port u_ila_0/probe193 [get_nets [list {m01_axi_awcache[0]} {m01_axi_awcache[1]} {m01_axi_awcache[2]} {m01_axi_awcache[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe194] +set_property port_width 3 [get_debug_ports u_ila_0/probe194] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {SDCin_axi_awready}]] +connect_debug_port u_ila_0/probe194 [get_nets [list {m01_axi_awprot[0]} {m01_axi_awprot[1]} {m01_axi_awprot[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe195] +set_property port_width 4 [get_debug_ports u_ila_0/probe195] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {SDCin_axi_wdata[0]} {SDCin_axi_wdata[1]} {SDCin_axi_wdata[2]} {SDCin_axi_wdata[3]} {SDCin_axi_wdata[4]} {SDCin_axi_wdata[5]} {SDCin_axi_wdata[6]} {SDCin_axi_wdata[7]} {SDCin_axi_wdata[8]} {SDCin_axi_wdata[9]} {SDCin_axi_wdata[10]} {SDCin_axi_wdata[11]} {SDCin_axi_wdata[12]} {SDCin_axi_wdata[13]} {SDCin_axi_wdata[14]} {SDCin_axi_wdata[15]} {SDCin_axi_wdata[16]} {SDCin_axi_wdata[17]} {SDCin_axi_wdata[18]} {SDCin_axi_wdata[19]} {SDCin_axi_wdata[20]} {SDCin_axi_wdata[21]} {SDCin_axi_wdata[22]} {SDCin_axi_wdata[23]} {SDCin_axi_wdata[24]} {SDCin_axi_wdata[25]} {SDCin_axi_wdata[26]} {SDCin_axi_wdata[27]} {SDCin_axi_wdata[28]} {SDCin_axi_wdata[29]} {SDCin_axi_wdata[30]} {SDCin_axi_wdata[31]} ]] +connect_debug_port u_ila_0/probe195 [get_nets [list {m01_axi_awregion[0]} {m01_axi_awregion[1]} {m01_axi_awregion[2]} {m01_axi_awregion[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe196] +set_property port_width 4 [get_debug_ports u_ila_0/probe196] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {SDCin_axi_wvalid}]] +connect_debug_port u_ila_0/probe196 [get_nets [list {m01_axi_awqos[0]} {m01_axi_awqos[1]} {m01_axi_awqos[2]} {m01_axi_awqos[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe197] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {SDCin_axi_wready}]] +connect_debug_port u_ila_0/probe197 [get_nets [list {m01_axi_awvalid}]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe198] +set_property port_width 1 [get_debug_ports u_ila_0/probe198] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {SDCin_axi_bresp[0]} {SDCin_axi_bresp[1]} ]] +connect_debug_port u_ila_0/probe198 [get_nets [list {m01_axi_awready}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe199] +set_property port_width 64 [get_debug_ports u_ila_0/probe199] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {SDCin_axi_bvalid}]] +connect_debug_port u_ila_0/probe199 [get_nets [list {m01_axi_wdata[0]} {m01_axi_wdata[1]} {m01_axi_wdata[2]} {m01_axi_wdata[3]} {m01_axi_wdata[4]} {m01_axi_wdata[5]} {m01_axi_wdata[6]} {m01_axi_wdata[7]} {m01_axi_wdata[8]} {m01_axi_wdata[9]} {m01_axi_wdata[10]} {m01_axi_wdata[11]} {m01_axi_wdata[12]} {m01_axi_wdata[13]} {m01_axi_wdata[14]} {m01_axi_wdata[15]} {m01_axi_wdata[16]} {m01_axi_wdata[17]} {m01_axi_wdata[18]} {m01_axi_wdata[19]} {m01_axi_wdata[20]} {m01_axi_wdata[21]} {m01_axi_wdata[22]} {m01_axi_wdata[23]} {m01_axi_wdata[24]} {m01_axi_wdata[25]} {m01_axi_wdata[26]} {m01_axi_wdata[27]} {m01_axi_wdata[28]} {m01_axi_wdata[29]} {m01_axi_wdata[30]} {m01_axi_wdata[31]} {m01_axi_wdata[32]} {m01_axi_wdata[33]} {m01_axi_wdata[34]} {m01_axi_wdata[35]} {m01_axi_wdata[36]} {m01_axi_wdata[37]} {m01_axi_wdata[38]} {m01_axi_wdata[39]} {m01_axi_wdata[40]} {m01_axi_wdata[41]} {m01_axi_wdata[42]} {m01_axi_wdata[43]} {m01_axi_wdata[44]} {m01_axi_wdata[45]} {m01_axi_wdata[46]} {m01_axi_wdata[47]} {m01_axi_wdata[48]} {m01_axi_wdata[49]} {m01_axi_wdata[50]} {m01_axi_wdata[51]} {m01_axi_wdata[52]} {m01_axi_wdata[53]} {m01_axi_wdata[54]} {m01_axi_wdata[55]} {m01_axi_wdata[56]} {m01_axi_wdata[57]} {m01_axi_wdata[58]} {m01_axi_wdata[59]} {m01_axi_wdata[60]} {m01_axi_wdata[61]} {m01_axi_wdata[62]} {m01_axi_wdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe200] +set_property port_width 4 [get_debug_ports u_ila_0/probe200] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {SDCin_axi_bready}]] +connect_debug_port u_ila_0/probe200 [get_nets [list {m01_axi_wstrb[0]} {m01_axi_wstrb[1]} {m01_axi_wstrb[2]} {m01_axi_wstrb[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe201] +set_property port_width 1 [get_debug_ports u_ila_0/probe201] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {SDCin_axi_araddr[0]} {SDCin_axi_araddr[1]} {SDCin_axi_araddr[2]} {SDCin_axi_araddr[3]} {SDCin_axi_araddr[4]} {SDCin_axi_araddr[5]} {SDCin_axi_araddr[6]} {SDCin_axi_araddr[7]} {SDCin_axi_araddr[8]} {SDCin_axi_araddr[9]} {SDCin_axi_araddr[10]} {SDCin_axi_araddr[11]} {SDCin_axi_araddr[12]} {SDCin_axi_araddr[13]} {SDCin_axi_araddr[14]} {SDCin_axi_araddr[15]} {SDCin_axi_araddr[16]} {SDCin_axi_araddr[17]} {SDCin_axi_araddr[18]} {SDCin_axi_araddr[19]} {SDCin_axi_araddr[20]} {SDCin_axi_araddr[21]} {SDCin_axi_araddr[22]} {SDCin_axi_araddr[23]} {SDCin_axi_araddr[24]} {SDCin_axi_araddr[25]} {SDCin_axi_araddr[26]} {SDCin_axi_araddr[27]} {SDCin_axi_araddr[28]} {SDCin_axi_araddr[29]} {SDCin_axi_araddr[30]} {SDCin_axi_araddr[31]} ]] +connect_debug_port u_ila_0/probe201 [get_nets [list {m01_axi_wlast}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe202] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {SDCin_axi_arvalid}]] +connect_debug_port u_ila_0/probe202 [get_nets [list {m01_axi_wvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe203] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {SDCin_axi_arready}]] +connect_debug_port u_ila_0/probe203 [get_nets [list {m01_axi_wready}]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe204] +set_property port_width 4 [get_debug_ports u_ila_0/probe204] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {SDCin_axi_rdata[0]} {SDCin_axi_rdata[1]} {SDCin_axi_rdata[2]} {SDCin_axi_rdata[3]} {SDCin_axi_rdata[4]} {SDCin_axi_rdata[5]} {SDCin_axi_rdata[6]} {SDCin_axi_rdata[7]} {SDCin_axi_rdata[8]} {SDCin_axi_rdata[9]} {SDCin_axi_rdata[10]} {SDCin_axi_rdata[11]} {SDCin_axi_rdata[12]} {SDCin_axi_rdata[13]} {SDCin_axi_rdata[14]} {SDCin_axi_rdata[15]} {SDCin_axi_rdata[16]} {SDCin_axi_rdata[17]} {SDCin_axi_rdata[18]} {SDCin_axi_rdata[19]} {SDCin_axi_rdata[20]} {SDCin_axi_rdata[21]} {SDCin_axi_rdata[22]} {SDCin_axi_rdata[23]} {SDCin_axi_rdata[24]} {SDCin_axi_rdata[25]} {SDCin_axi_rdata[26]} {SDCin_axi_rdata[27]} {SDCin_axi_rdata[28]} {SDCin_axi_rdata[29]} {SDCin_axi_rdata[30]} {SDCin_axi_rdata[31]} ]] +connect_debug_port u_ila_0/probe204 [get_nets [list {m01_axi_bid[0]} {m01_axi_bid[1]} {m01_axi_bid[2]} {m01_axi_bid[3]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe205] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {SDCin_axi_rresp[0]} {SDCin_axi_rresp[1]} ]] +connect_debug_port u_ila_0/probe205 [get_nets [list {m01_axi_bresp[0]} {m01_axi_bresp[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe206] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {SDCin_axi_rvalid}]] +connect_debug_port u_ila_0/probe206 [get_nets [list {m01_axi_bvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe207] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {SDCin_axi_rready}]] - +connect_debug_port u_ila_0/probe207 [get_nets [list {m01_axi_bready}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe208] +set_property port_width 4 [get_debug_ports u_ila_0/probe208] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {s01_axi_awvalid}]] +connect_debug_port u_ila_0/probe208 [get_nets [list {m01_axi_arid[0]} {m01_axi_arid[1]} {m01_axi_arid[2]} {m01_axi_arid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe209] +set_property port_width 32 [get_debug_ports u_ila_0/probe209] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] -connect_debug_port u_ila_0/probe209 [get_nets [list {s01_axi_awready}]] +connect_debug_port u_ila_0/probe209 [get_nets [list {m01_axi_araddr[0]} {m01_axi_araddr[1]} {m01_axi_araddr[2]} {m01_axi_araddr[3]} {m01_axi_araddr[4]} {m01_axi_araddr[5]} {m01_axi_araddr[6]} {m01_axi_araddr[7]} {m01_axi_araddr[8]} {m01_axi_araddr[9]} {m01_axi_araddr[10]} {m01_axi_araddr[11]} {m01_axi_araddr[12]} {m01_axi_araddr[13]} {m01_axi_araddr[14]} {m01_axi_araddr[15]} {m01_axi_araddr[16]} {m01_axi_araddr[17]} {m01_axi_araddr[18]} {m01_axi_araddr[19]} {m01_axi_araddr[20]} {m01_axi_araddr[21]} {m01_axi_araddr[22]} {m01_axi_araddr[23]} {m01_axi_araddr[24]} {m01_axi_araddr[25]} {m01_axi_araddr[26]} {m01_axi_araddr[27]} {m01_axi_araddr[28]} {m01_axi_araddr[29]} {m01_axi_araddr[30]} {m01_axi_araddr[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe210] +set_property port_width 8 [get_debug_ports u_ila_0/probe210] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] -connect_debug_port u_ila_0/probe210 [get_nets [list {s00_axi_awvalid}]] +connect_debug_port u_ila_0/probe210 [get_nets [list {m01_axi_arlen[0]} {m01_axi_arlen[1]} {m01_axi_arlen[2]} {m01_axi_arlen[3]} {m01_axi_arlen[4]} {m01_axi_arlen[5]} {m01_axi_arlen[6]} {m01_axi_arlen[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe211] +set_property port_width 3 [get_debug_ports u_ila_0/probe211] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] -connect_debug_port u_ila_0/probe211 [get_nets [list {s00_axi_awready}]] +connect_debug_port u_ila_0/probe211 [get_nets [list {m01_axi_arsize[0]} {m01_axi_arsize[1]} {m01_axi_arsize[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe212] +set_property port_width 2 [get_debug_ports u_ila_0/probe212] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] -connect_debug_port u_ila_0/probe212 [get_nets [list {axi4in_axi_awvalid}]] +connect_debug_port u_ila_0/probe212 [get_nets [list {m01_axi_arburst[0]} {m01_axi_arburst[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe213] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] -connect_debug_port u_ila_0/probe213 [get_nets [list {axi4in_axi_awready}]] +connect_debug_port u_ila_0/probe213 [get_nets [list {m01_axi_arlock}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe214] +set_property port_width 4 [get_debug_ports u_ila_0/probe214] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] -connect_debug_port u_ila_0/probe214 [get_nets [list {SDCout_axi_awvalid}]] +connect_debug_port u_ila_0/probe214 [get_nets [list {m01_axi_arcache[0]} {m01_axi_arcache[1]} {m01_axi_arcache[2]} {m01_axi_arcache[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe215] +set_property port_width 3 [get_debug_ports u_ila_0/probe215] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] -connect_debug_port u_ila_0/probe215 [get_nets [list {SDCout_axi_awready}]] +connect_debug_port u_ila_0/probe215 [get_nets [list {m01_axi_arprot[0]} {m01_axi_arprot[1]} {m01_axi_arprot[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe216] +set_property port_width 4 [get_debug_ports u_ila_0/probe216] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_awvalid}]] +connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_arregion[0]} {m01_axi_arregion[1]} {m01_axi_arregion[2]} {m01_axi_arregion[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe217] +set_property port_width 4 [get_debug_ports u_ila_0/probe217] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] -connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_awready}]] +connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_arqos[0]} {m01_axi_arqos[1]} {m01_axi_arqos[2]} {m01_axi_arqos[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe218] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218] +connect_debug_port u_ila_0/probe218 [get_nets [list {m01_axi_arvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe219] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219] +connect_debug_port u_ila_0/probe219 [get_nets [list {m01_axi_arready}]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe220] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220] +connect_debug_port u_ila_0/probe220 [get_nets [list {m01_axi_rid[0]} {m01_axi_rid[1]} {m01_axi_rid[2]} {m01_axi_rid[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe221] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] +connect_debug_port u_ila_0/probe221 [get_nets [list {m01_axi_rdata[0]} {m01_axi_rdata[1]} {m01_axi_rdata[2]} {m01_axi_rdata[3]} {m01_axi_rdata[4]} {m01_axi_rdata[5]} {m01_axi_rdata[6]} {m01_axi_rdata[7]} {m01_axi_rdata[8]} {m01_axi_rdata[9]} {m01_axi_rdata[10]} {m01_axi_rdata[11]} {m01_axi_rdata[12]} {m01_axi_rdata[13]} {m01_axi_rdata[14]} {m01_axi_rdata[15]} {m01_axi_rdata[16]} {m01_axi_rdata[17]} {m01_axi_rdata[18]} {m01_axi_rdata[19]} {m01_axi_rdata[20]} {m01_axi_rdata[21]} {m01_axi_rdata[22]} {m01_axi_rdata[23]} {m01_axi_rdata[24]} {m01_axi_rdata[25]} {m01_axi_rdata[26]} {m01_axi_rdata[27]} {m01_axi_rdata[28]} {m01_axi_rdata[29]} {m01_axi_rdata[30]} {m01_axi_rdata[31]} {m01_axi_rdata[32]} {m01_axi_rdata[33]} {m01_axi_rdata[34]} {m01_axi_rdata[35]} {m01_axi_rdata[36]} {m01_axi_rdata[37]} {m01_axi_rdata[38]} {m01_axi_rdata[39]} {m01_axi_rdata[40]} {m01_axi_rdata[41]} {m01_axi_rdata[42]} {m01_axi_rdata[43]} {m01_axi_rdata[44]} {m01_axi_rdata[45]} {m01_axi_rdata[46]} {m01_axi_rdata[47]} {m01_axi_rdata[48]} {m01_axi_rdata[49]} {m01_axi_rdata[50]} {m01_axi_rdata[51]} {m01_axi_rdata[52]} {m01_axi_rdata[53]} {m01_axi_rdata[54]} {m01_axi_rdata[55]} {m01_axi_rdata[56]} {m01_axi_rdata[57]} {m01_axi_rdata[58]} {m01_axi_rdata[59]} {m01_axi_rdata[60]} {m01_axi_rdata[61]} {m01_axi_rdata[62]} {m01_axi_rdata[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe222] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] +connect_debug_port u_ila_0/probe222 [get_nets [list {m01_axi_rresp[0]} {m01_axi_rresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe223] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223] +connect_debug_port u_ila_0/probe223 [get_nets [list {m01_axi_rlast}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe224] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe224] +connect_debug_port u_ila_0/probe224 [get_nets [list {m01_axi_rvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe225] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe225] +connect_debug_port u_ila_0/probe225 [get_nets [list {m01_axi_rready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe226] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe226] +connect_debug_port u_ila_0/probe226 [get_nets [list {SDCout_axi_awaddr[0]} {SDCout_axi_awaddr[1]} {SDCout_axi_awaddr[2]} {SDCout_axi_awaddr[3]} {SDCout_axi_awaddr[4]} {SDCout_axi_awaddr[5]} {SDCout_axi_awaddr[6]} {SDCout_axi_awaddr[7]} {SDCout_axi_awaddr[8]} {SDCout_axi_awaddr[9]} {SDCout_axi_awaddr[10]} {SDCout_axi_awaddr[11]} {SDCout_axi_awaddr[12]} {SDCout_axi_awaddr[13]} {SDCout_axi_awaddr[14]} {SDCout_axi_awaddr[15]} {SDCout_axi_awaddr[16]} {SDCout_axi_awaddr[17]} {SDCout_axi_awaddr[18]} {SDCout_axi_awaddr[19]} {SDCout_axi_awaddr[20]} {SDCout_axi_awaddr[21]} {SDCout_axi_awaddr[22]} {SDCout_axi_awaddr[23]} {SDCout_axi_awaddr[24]} {SDCout_axi_awaddr[25]} {SDCout_axi_awaddr[26]} {SDCout_axi_awaddr[27]} {SDCout_axi_awaddr[28]} {SDCout_axi_awaddr[29]} {SDCout_axi_awaddr[30]} {SDCout_axi_awaddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe227] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe227] +connect_debug_port u_ila_0/probe227 [get_nets [list {SDCout_axi_awlen[0]} {SDCout_axi_awlen[1]} {SDCout_axi_awlen[2]} {SDCout_axi_awlen[3]} {SDCout_axi_awlen[4]} {SDCout_axi_awlen[5]} {SDCout_axi_awlen[6]} {SDCout_axi_awlen[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe228] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe228] +connect_debug_port u_ila_0/probe228 [get_nets [list {SDCout_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe229] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe229] +connect_debug_port u_ila_0/probe229 [get_nets [list {SDCout_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe230] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe230] +connect_debug_port u_ila_0/probe230 [get_nets [list {SDCout_axi_wdata[0]} {SDCout_axi_wdata[1]} {SDCout_axi_wdata[2]} {SDCout_axi_wdata[3]} {SDCout_axi_wdata[4]} {SDCout_axi_wdata[5]} {SDCout_axi_wdata[6]} {SDCout_axi_wdata[7]} {SDCout_axi_wdata[8]} {SDCout_axi_wdata[9]} {SDCout_axi_wdata[10]} {SDCout_axi_wdata[11]} {SDCout_axi_wdata[12]} {SDCout_axi_wdata[13]} {SDCout_axi_wdata[14]} {SDCout_axi_wdata[15]} {SDCout_axi_wdata[16]} {SDCout_axi_wdata[17]} {SDCout_axi_wdata[18]} {SDCout_axi_wdata[19]} {SDCout_axi_wdata[20]} {SDCout_axi_wdata[21]} {SDCout_axi_wdata[22]} {SDCout_axi_wdata[23]} {SDCout_axi_wdata[24]} {SDCout_axi_wdata[25]} {SDCout_axi_wdata[26]} {SDCout_axi_wdata[27]} {SDCout_axi_wdata[28]} {SDCout_axi_wdata[29]} {SDCout_axi_wdata[30]} {SDCout_axi_wdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe231] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe231] +connect_debug_port u_ila_0/probe231 [get_nets [list {SDCout_axi_wlast}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe232] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe232] +connect_debug_port u_ila_0/probe232 [get_nets [list {SDCout_axi_wvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe233] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe233] +connect_debug_port u_ila_0/probe233 [get_nets [list {SDCout_axi_wready}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe234] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe234] +connect_debug_port u_ila_0/probe234 [get_nets [list {SDCout_axi_bresp[0]} {SDCout_axi_bresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe235] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe235] +connect_debug_port u_ila_0/probe235 [get_nets [list {SDCout_axi_bvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe236] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe236] +connect_debug_port u_ila_0/probe236 [get_nets [list {SDCout_axi_bready}]] + +create_debug_port u_ila_0 probe +set_property port_width 28 [get_debug_ports u_ila_0/probe237] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe237] +connect_debug_port u_ila_0/probe237 [get_nets [list {axiSDC/sd_data_master0/watchdog[0]} {axiSDC/sd_data_master0/watchdog[1]} {axiSDC/sd_data_master0/watchdog[2]} {axiSDC/sd_data_master0/watchdog[3]} {axiSDC/sd_data_master0/watchdog[4]} {axiSDC/sd_data_master0/watchdog[5]} {axiSDC/sd_data_master0/watchdog[6]} {axiSDC/sd_data_master0/watchdog[7]} {axiSDC/sd_data_master0/watchdog[8]} {axiSDC/sd_data_master0/watchdog[9]} {axiSDC/sd_data_master0/watchdog[10]} {axiSDC/sd_data_master0/watchdog[11]} {axiSDC/sd_data_master0/watchdog[12]} {axiSDC/sd_data_master0/watchdog[13]} {axiSDC/sd_data_master0/watchdog[14]} {axiSDC/sd_data_master0/watchdog[15]} {axiSDC/sd_data_master0/watchdog[16]} {axiSDC/sd_data_master0/watchdog[17]} {axiSDC/sd_data_master0/watchdog[18]} {axiSDC/sd_data_master0/watchdog[19]} {axiSDC/sd_data_master0/watchdog[20]} {axiSDC/sd_data_master0/watchdog[21]} {axiSDC/sd_data_master0/watchdog[22]} {axiSDC/sd_data_master0/watchdog[23]} {axiSDC/sd_data_master0/watchdog[24]} {axiSDC/sd_data_master0/watchdog[25]} {axiSDC/sd_data_master0/watchdog[26]} {axiSDC/sd_data_master0/watchdog[27]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe238] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe238] +connect_debug_port u_ila_0/probe238 [get_nets [list {axiSDC/data_busy}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe239] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe239] +connect_debug_port u_ila_0/probe239 [get_nets [list {axiSDC/sd_data_master0/en_tx_fifo}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe240] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe240] +connect_debug_port u_ila_0/probe240 [get_nets [list {axiSDC/sd_data_master0/fifo_empty}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe241] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe241] +connect_debug_port u_ila_0/probe241 [get_nets [list {axiSDC/sd_data_master0/bus_cycle}]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe242] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe242] +connect_debug_port u_ila_0/probe242 [get_nets [list {axiSDC/sd_data_serial_host0/blkcnt_reg[0]} {axiSDC/sd_data_serial_host0/blkcnt_reg[1]} {axiSDC/sd_data_serial_host0/blkcnt_reg[2]} {axiSDC/sd_data_serial_host0/blkcnt_reg[3]} {axiSDC/sd_data_serial_host0/blkcnt_reg[4]} {axiSDC/sd_data_serial_host0/blkcnt_reg[5]} {axiSDC/sd_data_serial_host0/blkcnt_reg[6]} {axiSDC/sd_data_serial_host0/blkcnt_reg[7]} {axiSDC/sd_data_serial_host0/blkcnt_reg[8]} {axiSDC/sd_data_serial_host0/blkcnt_reg[9]} {axiSDC/sd_data_serial_host0/blkcnt_reg[10]} {axiSDC/sd_data_serial_host0/blkcnt_reg[11]}]] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 9e51d15ad..da96aac42 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -101,6 +101,7 @@ uncore/uartPC16550D.sv: logic RXerr uncore/uartPC16550D.sv: logic THRE uncore/uartPC16550D.sv: logic rxdataavailintr uncore/uartPC16550D.sv: logic intrID +uncore/uncore.sv: logic HSELEXTSDCD uncore/plic_apb.sv: logic MExtInt uncore/plic_apb.sv: logic Din uncore/plic_apb.sv: logic requests diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl index ed44d9997..1d9eb4e78 100644 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -19,8 +19,8 @@ create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module set_property -dict [list CONFIG.NUM_SI {2} \ CONFIG.DATA_WIDTH {64} \ CONFIG.ID_WIDTH {4} \ - # CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - # CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ + CONFIG.M01_S01_READ_CONNECTIVITY {0} \ + CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 42957f63b..649b7cd57 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -74,9 +74,10 @@ module fpgaTop wire HCLKOpen; wire HRESETnOpen; wire [`AHBW-1:0] HRDATAEXT; - wire HREADYEXT; + (* mark_debug = "true" *)wire HREADYEXT; wire HRESPEXT; - wire HSELEXT; + (* mark_debug = "true" *) wire HSELEXT; + (* mark_debug = "true" *) wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB wire [31:0] HADDR; wire [`AHBW-1:0] HWDATA; wire HWRITE; @@ -96,41 +97,41 @@ module fpgaTop // wire SDCCmdOE; // wire SDCCmdOut; - (* mark_debug = "true" *) wire [3:0] m_axi_awid; - (* mark_debug = "true" *) wire [7:0] m_axi_awlen; - (* mark_debug = "true" *) wire [2:0] m_axi_awsize; - (* mark_debug = "true" *) wire [1:0] m_axi_awburst; - (* mark_debug = "true" *) wire [3:0] m_axi_awcache; - (* mark_debug = "true" *) wire [31:0] m_axi_awaddr; - (* mark_debug = "true" *) wire [2:0] m_axi_awprot; - (* mark_debug = "true" *) wire m_axi_awvalid; - (* mark_debug = "true" *) wire m_axi_awready; - (* mark_debug = "true" *) wire m_axi_awlock; - (* mark_debug = "true" *) wire [63:0] m_axi_wdata; - (* mark_debug = "true" *) wire [7:0] m_axi_wstrb; - (* mark_debug = "true" *) wire m_axi_wlast; - (* mark_debug = "true" *) wire m_axi_wvalid; - (* mark_debug = "true" *) wire m_axi_wready; - (* mark_debug = "true" *) wire [3:0] m_axi_bid; - (* mark_debug = "true" *) wire [1:0] m_axi_bresp; - (* mark_debug = "true" *) wire m_axi_bvalid; - (* mark_debug = "true" *) wire m_axi_bready; - (* mark_debug = "true" *) wire [3:0] m_axi_arid; - (* mark_debug = "true" *) wire [7:0] m_axi_arlen; - (* mark_debug = "true" *) wire [2:0] m_axi_arsize; - (* mark_debug = "true" *) wire [1:0] m_axi_arburst; - (* mark_debug = "true" *) wire [2:0] m_axi_arprot; - (* mark_debug = "true" *) wire [3:0] m_axi_arcache; - (* mark_debug = "true" *) wire m_axi_arvalid; - (* mark_debug = "true" *) wire [31:0] m_axi_araddr; - (* mark_debug = "true" *) wire m_axi_arlock; - (* mark_debug = "true" *) wire m_axi_arready; - (* mark_debug = "true" *) wire [3:0] m_axi_rid; - (* mark_debug = "true" *) wire [63:0] m_axi_rdata; - (* mark_debug = "true" *) wire [1:0] m_axi_rresp; - (* mark_debug = "true" *) wire m_axi_rvalid; - (* mark_debug = "true" *) wire m_axi_rlast; - (* mark_debug = "true" *) wire m_axi_rready; + wire [3:0] m_axi_awid; + wire [7:0] m_axi_awlen; + wire [2:0] m_axi_awsize; + wire [1:0] m_axi_awburst; + wire [3:0] m_axi_awcache; + wire [31:0] m_axi_awaddr; + wire [2:0] m_axi_awprot; + wire m_axi_awvalid; + wire m_axi_awready; + wire m_axi_awlock; + wire [63:0] m_axi_wdata; + wire [7:0] m_axi_wstrb; + wire m_axi_wlast; + wire m_axi_wvalid; + wire m_axi_wready; + wire [3:0] m_axi_bid; + wire [1:0] m_axi_bresp; + wire m_axi_bvalid; + wire m_axi_bready; + wire [3:0] m_axi_arid; + wire [7:0] m_axi_arlen; + wire [2:0] m_axi_arsize; + wire [1:0] m_axi_arburst; + wire [2:0] m_axi_arprot; + wire [3:0] m_axi_arcache; + wire m_axi_arvalid; + wire [31:0] m_axi_araddr; + wire m_axi_arlock; + wire m_axi_arready; + wire [3:0] m_axi_rid; + wire [63:0] m_axi_rdata; + wire [1:0] m_axi_rresp; + wire m_axi_rvalid; + wire m_axi_rlast; + wire m_axi_rready; // Extra Bus signals wire [3:0] BUS_axi_arregion; @@ -187,47 +188,47 @@ module fpgaTop // Crossbar to Bus ------------------------------------------------ - wire s00_axi_aclk; - wire s00_axi_aresetn; - wire [3:0] s00_axi_awid; - wire [31:0]s00_axi_awaddr; - wire [7:0]s00_axi_awlen; - wire [2:0]s00_axi_awsize; - wire [1:0]s00_axi_awburst; - wire [0:0]s00_axi_awlock; - wire [3:0]s00_axi_awcache; - wire [2:0]s00_axi_awprot; - wire [3:0]s00_axi_awregion; - wire [3:0]s00_axi_awqos; + (* mark_debug = "true" *)wire s00_axi_aclk; + (* mark_debug = "true" *)wire s00_axi_aresetn; + (* mark_debug = "true" *)wire [3:0] s00_axi_awid; + (* mark_debug = "true" *)wire [31:0]s00_axi_awaddr; + (* mark_debug = "true" *)wire [7:0]s00_axi_awlen; + (* mark_debug = "true" *)wire [2:0]s00_axi_awsize; + (* mark_debug = "true" *)wire [1:0]s00_axi_awburst; + (* mark_debug = "true" *)wire [0:0]s00_axi_awlock; + (* mark_debug = "true" *)wire [3:0]s00_axi_awcache; + (* mark_debug = "true" *)wire [2:0]s00_axi_awprot; + (* mark_debug = "true" *)wire [3:0]s00_axi_awregion; + (* mark_debug = "true" *)wire [3:0]s00_axi_awqos; (* mark_debug = "true" *) wire s00_axi_awvalid; (* mark_debug = "true" *) wire s00_axi_awready; - wire [63:0]s00_axi_wdata; - wire [7:0]s00_axi_wstrb; - wire s00_axi_wlast; - wire s00_axi_wvalid; - wire s00_axi_wready; - wire [1:0]s00_axi_bresp; - wire s00_axi_bvalid; - wire s00_axi_bready; - wire [31:0]s00_axi_araddr; - wire [7:0]s00_axi_arlen; - wire [2:0]s00_axi_arsize; - wire [1:0]s00_axi_arburst; - wire [0:0]s00_axi_arlock; - wire [3:0]s00_axi_arcache; - wire [2:0]s00_axi_arprot; - wire [3:0]s00_axi_arregion; - wire [3:0]s00_axi_arqos; - wire s00_axi_arvalid; - wire s00_axi_arready; - wire [63:0]s00_axi_rdata; - wire [1:0]s00_axi_rresp; - wire s00_axi_rlast; - wire s00_axi_rvalid; - wire s00_axi_rready; + (* mark_debug = "true" *)wire [63:0]s00_axi_wdata; + (* mark_debug = "true" *)wire [7:0]s00_axi_wstrb; + (* mark_debug = "true" *)wire s00_axi_wlast; + (* mark_debug = "true" *)wire s00_axi_wvalid; + (* mark_debug = "true" *)wire s00_axi_wready; + (* mark_debug = "true" *)wire [1:0]s00_axi_bresp; + (* mark_debug = "true" *)wire s00_axi_bvalid; + (* mark_debug = "true" *)wire s00_axi_bready; + (* mark_debug = "true" *)wire [31:0]s00_axi_araddr; + (* mark_debug = "true" *)wire [7:0]s00_axi_arlen; + (* mark_debug = "true" *)wire [2:0]s00_axi_arsize; + (* mark_debug = "true" *)wire [1:0]s00_axi_arburst; + (* mark_debug = "true" *)wire [0:0]s00_axi_arlock; + (* mark_debug = "true" *)wire [3:0]s00_axi_arcache; + (* mark_debug = "true" *)wire [2:0]s00_axi_arprot; + (* mark_debug = "true" *)wire [3:0]s00_axi_arregion; + (* mark_debug = "true" *)wire [3:0]s00_axi_arqos; + (* mark_debug = "true" *)wire s00_axi_arvalid; + (* mark_debug = "true" *)wire s00_axi_arready; + (* mark_debug = "true" *)wire [63:0]s00_axi_rdata; + (* mark_debug = "true" *)wire [1:0]s00_axi_rresp; + (* mark_debug = "true" *)wire s00_axi_rlast; + (* mark_debug = "true" *)wire s00_axi_rvalid; + (* mark_debug = "true" *)wire s00_axi_rready; - wire [3:0] s00_axi_bid; - wire [3:0] s00_axi_rid; + (* mark_debug = "true" *)wire [3:0] s00_axi_bid; + (* mark_debug = "true" *)wire [3:0] s00_axi_rid; // 64to32 dwidth converter input interface------------------------- wire s01_axi_aclk; @@ -329,8 +330,8 @@ module fpgaTop // ---------------------------------------------------------------- // 32to64 dwidth converter input interface ----------------------- - wire [31:0]SDCout_axi_awaddr; - wire [7:0]SDCout_axi_awlen; + (* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr; + (* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen; wire [2:0]SDCout_axi_awsize; wire [1:0]SDCout_axi_awburst; wire [0:0]SDCout_axi_awlock; @@ -340,14 +341,14 @@ module fpgaTop wire [3:0]SDCout_axi_awqos; (* mark_debug = "true" *) wire SDCout_axi_awvalid; (* mark_debug = "true" *) wire SDCout_axi_awready; - wire [31:0]SDCout_axi_wdata; + (* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata; wire [3:0]SDCout_axi_wstrb; - wire SDCout_axi_wlast; - wire SDCout_axi_wvalid; - wire SDCout_axi_wready; - wire [1:0]SDCout_axi_bresp; - wire SDCout_axi_bvalid; - wire SDCout_axi_bready; + (* mark_debug = "true" *) wire SDCout_axi_wlast; + (* mark_debug = "true" *) wire SDCout_axi_wvalid; + (* mark_debug = "true" *)wire SDCout_axi_wready; + (* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp; + (* mark_debug = "true" *) wire SDCout_axi_bvalid; + (* mark_debug = "true" *) wire SDCout_axi_bready; wire [31:0]SDCout_axi_araddr; wire [7:0]SDCout_axi_arlen; wire [2:0]SDCout_axi_arsize; @@ -366,45 +367,45 @@ module fpgaTop wire SDCout_axi_rready; // Output Interface - wire [3:0]m01_axi_awid; - wire [31:0]m01_axi_awaddr; - wire [7:0]m01_axi_awlen; - wire [2:0]m01_axi_awsize; - wire [1:0]m01_axi_awburst; - wire [0:0]m01_axi_awlock; - wire [3:0]m01_axi_awcache; - wire [2:0]m01_axi_awprot; - wire [3:0]m01_axi_awregion; - wire [3:0]m01_axi_awqos; + (* mark_debug = "true" *) wire [3:0]m01_axi_awid; + (* mark_debug = "true" *) wire [31:0]m01_axi_awaddr; + (* mark_debug = "true" *) wire [7:0]m01_axi_awlen; + (* mark_debug = "true" *) wire [2:0]m01_axi_awsize; + (* mark_debug = "true" *) wire [1:0]m01_axi_awburst; + (* mark_debug = "true" *) wire [0:0]m01_axi_awlock; + (* mark_debug = "true" *) wire [3:0]m01_axi_awcache; + (* mark_debug = "true" *) wire [2:0]m01_axi_awprot; + (* mark_debug = "true" *) wire [3:0]m01_axi_awregion; + (* mark_debug = "true" *) wire [3:0]m01_axi_awqos; (* mark_debug = "true" *) wire m01_axi_awvalid; (* mark_debug = "true" *) wire m01_axi_awready; - wire [63:0]m01_axi_wdata; - wire [3:0]m01_axi_wstrb; - wire m01_axi_wlast; - wire m01_axi_wvalid; - wire m01_axi_wready; - wire [3:0] m01_axi_bid; - wire [1:0]m01_axi_bresp; - wire m01_axi_bvalid; - wire m01_axi_bready; - wire [3:0] m01_axi_arid; - wire [31:0]m01_axi_araddr; - wire [7:0]m01_axi_arlen; - wire [2:0]m01_axi_arsize; - wire [1:0]m01_axi_arburst; - wire [0:0]m01_axi_arlock; - wire [3:0]m01_axi_arcache; - wire [2:0]m01_axi_arprot; - wire [3:0]m01_axi_arregion; - wire [3:0]m01_axi_arqos; - wire m01_axi_arvalid; - wire m01_axi_arready; - wire [3:0] m01_axi_rid; - wire [63:0]m01_axi_rdata; - wire [1:0]m01_axi_rresp; - wire m01_axi_rlast; - wire m01_axi_rvalid; - wire m01_axi_rready; + (* mark_debug = "true" *) wire [63:0]m01_axi_wdata; + (* mark_debug = "true" *) wire [7:0]m01_axi_wstrb; + (* mark_debug = "true" *) wire m01_axi_wlast; + (* mark_debug = "true" *) wire m01_axi_wvalid; + (* mark_debug = "true" *) wire m01_axi_wready; + (* mark_debug = "true" *) wire [3:0] m01_axi_bid; + (* mark_debug = "true" *) wire [1:0]m01_axi_bresp; + (* mark_debug = "true" *) wire m01_axi_bvalid; + (* mark_debug = "true" *) wire m01_axi_bready; + (* mark_debug = "true" *) wire [3:0] m01_axi_arid; + (* mark_debug = "true" *) wire [31:0]m01_axi_araddr; + (* mark_debug = "true" *) wire [7:0]m01_axi_arlen; + (* mark_debug = "true" *) wire [2:0]m01_axi_arsize; + (* mark_debug = "true" *) wire [1:0]m01_axi_arburst; + (* mark_debug = "true" *) wire [0:0]m01_axi_arlock; + (* mark_debug = "true" *) wire [3:0]m01_axi_arcache; + (* mark_debug = "true" *) wire [2:0]m01_axi_arprot; + (* mark_debug = "true" *) wire [3:0]m01_axi_arregion; + (* mark_debug = "true" *) wire [3:0]m01_axi_arqos; + (* mark_debug = "true" *) wire m01_axi_arvalid; + (* mark_debug = "true" *) wire m01_axi_arready; + (* mark_debug = "true" *) wire [3:0] m01_axi_rid; + (* mark_debug = "true" *) wire [63:0]m01_axi_rdata; + (* mark_debug = "true" *) wire [1:0]m01_axi_rresp; + (* mark_debug = "true" *) wire m01_axi_rlast; + (* mark_debug = "true" *) wire m01_axi_rvalid; + (* mark_debug = "true" *) wire m01_axi_rready; // Old SDC input // wire [3:0] SDCDatIn; @@ -487,6 +488,7 @@ module fpgaTop .HREADYEXT(HREADYEXT), .HRESPEXT(HRESPEXT), .HSELEXT(HSELEXT), + .HSELEXTSDC(HSELEXTSDC), .HCLK(HCLKOpen), // open .HRESETn(HRESETnOpen), // open .HADDR(HADDR), @@ -517,7 +519,7 @@ module fpgaTop xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), - .s_ahb_hsel(HSELEXT), + .s_ahb_hsel(HSELEXT | HSELEXTSDC), .s_ahb_haddr(HADDR), .s_ahb_hprot(HPROT), .s_ahb_htrans(HTRANS), @@ -809,7 +811,7 @@ module fpgaTop .async_resetn(peripheral_aresetn), // Slave Interface - .s_axi_awaddr(SDCin_axi_awaddr[15:0]), + .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}), .s_axi_awvalid(SDCin_axi_awvalid), .s_axi_awready(SDCin_axi_awready), .s_axi_wdata(SDCin_axi_wdata), @@ -818,7 +820,7 @@ module fpgaTop .s_axi_bresp(SDCin_axi_bresp), .s_axi_bvalid(SDCin_axi_bvalid), .s_axi_bready(SDCin_axi_bready), - .s_axi_araddr(SDCin_axi_araddr[15:0]), + .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}), .s_axi_arvalid(SDCin_axi_arvalid), .s_axi_arready(SDCin_axi_arready), .s_axi_rdata(SDCin_axi_rdata), @@ -872,8 +874,8 @@ module fpgaTop // Slave interface .s_axi_awaddr(SDCout_axi_awaddr), .s_axi_awlen(SDCout_axi_awlen), - .s_axi_awsize(3'b0), - .s_axi_awburst(2'b0), + .s_axi_awsize(3'b010), + .s_axi_awburst(2'b01), .s_axi_awlock(1'b0), .s_axi_awcache(4'b0), .s_axi_awprot(3'b0), @@ -882,7 +884,7 @@ module fpgaTop .s_axi_awvalid(SDCout_axi_awvalid), .s_axi_awready(SDCout_axi_awready), .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(8'b0), + .s_axi_wstrb(8'b11111111), .s_axi_wlast(SDCout_axi_wlast), .s_axi_wvalid(SDCout_axi_wvalid), .s_axi_wready(SDCout_axi_wready), @@ -891,8 +893,8 @@ module fpgaTop .s_axi_bready(SDCout_axi_bready), .s_axi_araddr(SDCout_axi_araddr), .s_axi_arlen(SDCout_axi_arlen), - .s_axi_arsize(3'b0), - .s_axi_arburst(2'b0), + .s_axi_arsize(3'b010), + .s_axi_arburst(2'b01), .s_axi_arlock(1'b0), .s_axi_arcache(4'b0), .s_axi_arprot(3'b0), diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v index 7e206c676..28994182d 100644 --- a/pipelined/src/uncore/newsdc/axi_sdc_controller.v +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -162,7 +162,7 @@ wire [31:0] data_in_rx_fifo; wire en_tx_fifo; wire en_rx_fifo; wire sd_data_busy; -wire data_busy; +(* mark_debug = "true" *) wire data_busy; wire data_crc_ok; wire tx_fifo_re; wire rx_fifo_we; diff --git a/pipelined/src/uncore/newsdc/sd_data_master.v b/pipelined/src/uncore/newsdc/sd_data_master.v index c85d7ea7a..1fecea418 100644 --- a/pipelined/src/uncore/newsdc/sd_data_master.v +++ b/pipelined/src/uncore/newsdc/sd_data_master.v @@ -42,12 +42,12 @@ module sd_data_master ( output reg d_write, output reg d_read, // To fifo filler - output reg en_tx_fifo, + (* mark_debug = "true" *) output reg en_tx_fifo, output reg en_rx_fifo, - input fifo_empty, + (* mark_debug = "true" *) input fifo_empty, input fifo_ready, input fifo_full, - input bus_cycle, + (* mark_debug = "true" *) input bus_cycle, // SD-DATA_Host input xfr_complete, input crc_error, @@ -63,7 +63,7 @@ localparam START_TX_FIFO = 4'b0010; localparam START_RX_FIFO = 4'b0100; localparam DATA_TRANSFER = 4'b1000; -reg [`DATA_TIMEOUT_W-1:0] watchdog; +(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] watchdog; reg watchdog_enable; always @(posedge clock) begin diff --git a/pipelined/src/uncore/newsdc/sd_data_serial_host.v b/pipelined/src/uncore/newsdc/sd_data_serial_host.v index 9a35e5a88..62891d8b8 100644 --- a/pipelined/src/uncore/newsdc/sd_data_serial_host.v +++ b/pipelined/src/uncore/newsdc/sd_data_serial_host.v @@ -66,7 +66,7 @@ reg [`BLKSIZE_W+4-1:0] data_cycles; reg [`BLKSIZE_W+4-1:0] transf_cnt; reg [3:0] drt_bit; reg [3:0] drt_reg; -reg [`BLKCNT_W-1:0] blkcnt_reg; +(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] blkcnt_reg; reg [1:0] byte_alignment_reg; reg [3:0] crc_bit; reg [3:0] last_din; diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index f1e784c13..8bffee0ea 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( +module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256, PRELOAD_ENABLED=0) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, @@ -95,6 +95,12 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( end else begin: ram integer i; + if (PRELOAD_ENABLED) begin + initial begin + RAM[0] = 64'h00600100d2e3ca40; + end + end + // Read always_ff @(posedge clk) if(ce) dout <= #1 RAM[addr]; diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 927462c78..d50b6c5bb 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -96,7 +96,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[41] = 64'h40a7853b4015551b; ROM[42] = 64'h808210a7a02367c9;*/ - ROM[0] = 64'hc001819300002197; + ROM[0] = 64'h8001819300002197; ROM[1] = 64'h4281420141014081; ROM[2] = 64'h4481440143814301; ROM[3] = 64'h4681460145814501; @@ -107,7 +107,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[8] = 64'h0110011b4f814f01; ROM[9] = 64'h059b45011161016e; ROM[10] = 64'h0004063705fe0010; - ROM[11] = 64'h1ee000ef8006061b; + ROM[11] = 64'h1f6000ef8006061b; ROM[12] = 64'h0ff003930000100f; ROM[13] = 64'h4e952e3110060e37; ROM[14] = 64'hc602829b0053f2b7; @@ -118,627 +118,116 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[19] = 64'h059bf1402573fdd0; ROM[20] = 64'h0000061705e20870; ROM[21] = 64'h0010029b01260613; - ROM[22] = 64'h67110002806702fe; - ROM[23] = 64'h0085179bf0070713; - ROM[24] = 64'h2781038007138ff9; - ROM[25] = 64'h7563470508a76a63; - ROM[26] = 64'h00a71733357902a7; - ROM[27] = 64'h3285350300001517; - ROM[28] = 64'h40301537e9598d79; - ROM[29] = 64'h8d7942250513051a; - ROM[30] = 64'he35d18177713e149; - ROM[31] = 64'he79300367713c295; - ROM[32] = 64'hf330674de3450207; - ROM[33] = 64'h861bc3701ff00613; - ROM[34] = 64'h01000637c730fff6; - ROM[35] = 64'hc35c674dcf10167d; - ROM[36] = 64'hd31c17fd001007b7; - ROM[37] = 64'h0007861b5b5cc30c; - ROM[38] = 64'h674d02072a23dfed; - ROM[39] = 64'h12634785fffd571c; - ROM[40] = 64'h80818793471006f6; - ROM[41] = 64'h4b10474cc3904501; - ROM[42] = 64'hc7d8c790c3cc4b58; - ROM[43] = 64'h086007138082e29d; - ROM[44] = 64'h0a90071300e50c63; - ROM[45] = 64'h0017e793f8e518e3; - ROM[46] = 64'hb74901d7e793b761; - ROM[47] = 64'h674dbfb50197e793; - ROM[48] = 64'h02072e23dffd5f5c; - ROM[49] = 64'h8513ff7d569866cd; - ROM[50] = 64'h053300a03533fff7; - ROM[51] = 64'h00a7e793808240a0; - ROM[52] = 64'h71398082557dbfa1; - ROM[53] = 64'hf8228181ca03e852; - ROM[54] = 64'hf426fc06ec4ef04a; - ROM[55] = 64'h008a7a13e05ae456; - ROM[56] = 64'h1463843289ae892a; - ROM[57] = 64'h4a8500959993000a; - ROM[58] = 64'h4549864ac4296b05; - ROM[59] = 64'h055402630009859b; - ROM[60] = 64'h008b73630004049b; - ROM[61] = 64'hecbff0ef86a66485; - ROM[62] = 64'h45814601468187aa; - ROM[63] = 64'h0207c8639c054531; - ROM[64] = 64'h0094979beb7ff0ef; - ROM[65] = 64'h0205406393811782; - ROM[66] = 64'h99ba020a1863873e; - ROM[67] = 64'ha8014501fc4d993e; - ROM[68] = 64'he93ff0ef45454685; - ROM[69] = 64'h70e24505fe055ae3; - ROM[70] = 64'h69e2790274a27442; - ROM[71] = 64'h61216b026aa26a42; - ROM[72] = 64'h9301020497138082; - ROM[73] = 64'hec26f0227179b7f9; - ROM[74] = 64'he44ef4064705e84a; - ROM[75] = 64'h842e84aad79867cd; - ROM[76] = 64'h8b85571c674d8932; - ROM[77] = 64'hd35c03600793dff5; - ROM[78] = 64'h571c674d02072423; - ROM[79] = 64'ha737b00026f3fffd; - ROM[80] = 64'h27f311f707130007; - ROM[81] = 64'hfef77de38f95b000; - ROM[82] = 64'h80018c235b1c674d; - ROM[83] = 64'he7934f5ccf9d8b89; - ROM[84] = 64'hb00026f3cf5c0027; - ROM[85] = 64'h0ff7071305f5e737; - ROM[86] = 64'h7de38f95b00027f3; - ROM[87] = 64'h9bf54f5c674dfef7; - ROM[88] = 64'h9737b00026f3cf5c; - ROM[89] = 64'h27f367f707130098; - ROM[90] = 64'hfef77de38f95b000; - ROM[91] = 64'h4501458146014681; - ROM[92] = 64'h80818993dd7ff0ef; - ROM[93] = 64'h0593460146814789; - ROM[94] = 64'h00f9882345211aa0; - ROM[95] = 64'ha783e50ddbfff0ef; - ROM[96] = 64'h17d21aa007130009; - ROM[97] = 64'h479102e79e6393d1; - ROM[98] = 64'hf0efa80900f98823; - ROM[99] = 64'ha78302054663da1f; - ROM[100]= 64'h46810207cc630009; - ROM[101]= 64'h0370051345814601; - ROM[102]= 64'h468187aad87ff0ef; - ROM[103]= 64'h0513403005b74601; - ROM[104]= 64'h8522fc07dae30a90; - ROM[105]= 64'h864a69a270a27402; - ROM[106]= 64'h614564e2694285a6; - ROM[107]= 64'hebd18b8583f9b5b9; - ROM[108]= 64'h4509458146014681; - ROM[109]= 64'hfc054de3d4fff0ef; - ROM[110]= 64'h123405b746014681; - ROM[111]= 64'h44e3d3dff0ef450d; - ROM[112]= 64'h77c10009a983fc05; - ROM[113]= 64'h460100f9f9b34681; - ROM[114]= 64'hd23ff0ef451d85ce; - ROM[115]= 64'h470567cdfa0547e3; - ROM[116]= 64'h4737b00026f3d3d8; - ROM[117]= 64'h27f323f70713000f; - ROM[118]= 64'hfef77de38f95b000; - ROM[119]= 64'h46810007ae2367cd; - ROM[120]= 64'h0370051385ce4601; - ROM[121]= 64'hf6054de3cefff0ef; - ROM[122]= 64'h0513458146014681; - ROM[123]= 64'h44e3cddff0ef0860; - ROM[124]= 64'h059346014681f605; - ROM[125]= 64'hccbff0ef45412000; - ROM[126]= 64'he7930109c783bf99; - ROM[127]= 64'hb78d00f988230087; - ROM[128]= 64'h0000000000000000; - ROM[129]= 64'h0000000000000000; - ROM[130]= 64'h0000000000000000; - ROM[131]= 64'h0000000000000000; - ROM[132]= 64'h0000000000000000; - ROM[133]= 64'h0000000000000000; - ROM[134]= 64'h0000000000000000; - ROM[135]= 64'h0000000000000000; - ROM[136]= 64'h0000000000000000; - ROM[137]= 64'h0000000000000000; - ROM[138]= 64'h0000000000000000; - ROM[139]= 64'h0000000000000000; - ROM[140]= 64'h0000000000000000; - ROM[141]= 64'h0000000000000000; - ROM[142]= 64'h0000000000000000; - ROM[143]= 64'h0000000000000000; - ROM[144]= 64'h0000000000000000; - ROM[145]= 64'h0000000000000000; - ROM[146]= 64'h0000000000000000; - ROM[147]= 64'h0000000000000000; - ROM[148]= 64'h0000000000000000; - ROM[149]= 64'h0000000000000000; - ROM[150]= 64'h0000000000000000; - ROM[151]= 64'h0000000000000000; - ROM[152]= 64'h0000000000000000; - ROM[153]= 64'h0000000000000000; - ROM[154]= 64'h0000000000000000; - ROM[155]= 64'h0000000000000000; - ROM[156]= 64'h0000000000000000; - ROM[157]= 64'h0000000000000000; - ROM[158]= 64'h0000000000000000; - ROM[159]= 64'h0000000000000000; - ROM[160]= 64'h0000000000000000; - ROM[161]= 64'h0000000000000000; - ROM[162]= 64'h0000000000000000; - ROM[163]= 64'h0000000000000000; - ROM[164]= 64'h0000000000000000; - ROM[165]= 64'h0000000000000000; - ROM[166]= 64'h0000000000000000; - ROM[167]= 64'h0000000000000000; - ROM[168]= 64'h0000000000000000; - ROM[169]= 64'h0000000000000000; - ROM[170]= 64'h0000000000000000; - ROM[171]= 64'h0000000000000000; - ROM[172]= 64'h0000000000000000; - ROM[173]= 64'h0000000000000000; - ROM[174]= 64'h0000000000000000; - ROM[175]= 64'h0000000000000000; - ROM[176]= 64'h0000000000000000; - ROM[177]= 64'h0000000000000000; - ROM[178]= 64'h0000000000000000; - ROM[179]= 64'h0000000000000000; - ROM[180]= 64'h0000000000000000; - ROM[181]= 64'h0000000000000000; - ROM[182]= 64'h0000000000000000; - ROM[183]= 64'h0000000000000000; - ROM[184]= 64'h0000000000000000; - ROM[185]= 64'h0000000000000000; - ROM[186]= 64'h0000000000000000; - ROM[187]= 64'h0000000000000000; - ROM[188]= 64'h0000000000000000; - ROM[189]= 64'h0000000000000000; - ROM[190]= 64'h0000000000000000; - ROM[191]= 64'h0000000000000000; - ROM[192]= 64'h0000000000000000; - ROM[193]= 64'h0000000000000000; - ROM[194]= 64'h0000000000000000; - ROM[195]= 64'h0000000000000000; - ROM[196]= 64'h0000000000000000; - ROM[197]= 64'h0000000000000000; - ROM[198]= 64'h0000000000000000; - ROM[199]= 64'h0000000000000000; - ROM[200]= 64'h0000000000000000; - ROM[201]= 64'h0000000000000000; - ROM[202]= 64'h0000000000000000; - ROM[203]= 64'h0000000000000000; - ROM[204]= 64'h0000000000000000; - ROM[205]= 64'h0000000000000000; - ROM[206]= 64'h0000000000000000; - ROM[207]= 64'h0000000000000000; - ROM[208]= 64'h0000000000000000; - ROM[209]= 64'h0000000000000000; - ROM[210]= 64'h0000000000000000; - ROM[211]= 64'h0000000000000000; - ROM[212]= 64'h0000000000000000; - ROM[213]= 64'h0000000000000000; - ROM[214]= 64'h0000000000000000; - ROM[215]= 64'h0000000000000000; - ROM[216]= 64'h0000000000000000; - ROM[217]= 64'h0000000000000000; - ROM[218]= 64'h0000000000000000; - ROM[219]= 64'h0000000000000000; - ROM[220]= 64'h0000000000000000; - ROM[221]= 64'h0000000000000000; - ROM[222]= 64'h0000000000000000; - ROM[223]= 64'h0000000000000000; - ROM[224]= 64'h0000000000000000; - ROM[225]= 64'h0000000000000000; - ROM[226]= 64'h0000000000000000; - ROM[227]= 64'h0000000000000000; - ROM[228]= 64'h0000000000000000; - ROM[229]= 64'h0000000000000000; - ROM[230]= 64'h0000000000000000; - ROM[231]= 64'h0000000000000000; - ROM[232]= 64'h0000000000000000; - ROM[233]= 64'h0000000000000000; - ROM[234]= 64'h0000000000000000; - ROM[235]= 64'h0000000000000000; - ROM[236]= 64'h0000000000000000; - ROM[237]= 64'h0000000000000000; - ROM[238]= 64'h0000000000000000; - ROM[239]= 64'h0000000000000000; - ROM[240]= 64'h0000000000000000; - ROM[241]= 64'h0000000000000000; - ROM[242]= 64'h0000000000000000; - ROM[243]= 64'h0000000000000000; - ROM[244]= 64'h0000000000000000; - ROM[245]= 64'h0000000000000000; - ROM[246]= 64'h0000000000000000; - ROM[247]= 64'h0000000000000000; - ROM[248]= 64'h0000000000000000; - ROM[249]= 64'h0000000000000000; - ROM[250]= 64'h0000000000000000; - ROM[251]= 64'h0000000000000000; - ROM[252]= 64'h0000000000000000; - ROM[253]= 64'h0000000000000000; - ROM[254]= 64'h0000000000000000; - ROM[255]= 64'h0000000000000000; - ROM[256]= 64'h0000000000000000; - ROM[257]= 64'h0000000000000000; - ROM[258]= 64'h0000000000000000; - ROM[259]= 64'h0000000000000000; - ROM[260]= 64'h0000000000000000; - ROM[261]= 64'h0000000000000000; - ROM[262]= 64'h0000000000000000; - ROM[263]= 64'h0000000000000000; - ROM[264]= 64'h0000000000000000; - ROM[265]= 64'h0000000000000000; - ROM[266]= 64'h0000000000000000; - ROM[267]= 64'h0000000000000000; - ROM[268]= 64'h0000000000000000; - ROM[269]= 64'h0000000000000000; - ROM[270]= 64'h0000000000000000; - ROM[271]= 64'h0000000000000000; - ROM[272]= 64'h0000000000000000; - ROM[273]= 64'h0000000000000000; - ROM[274]= 64'h0000000000000000; - ROM[275]= 64'h0000000000000000; - ROM[276]= 64'h0000000000000000; - ROM[277]= 64'h0000000000000000; - ROM[278]= 64'h0000000000000000; - ROM[279]= 64'h0000000000000000; - ROM[280]= 64'h0000000000000000; - ROM[281]= 64'h0000000000000000; - ROM[282]= 64'h0000000000000000; - ROM[283]= 64'h0000000000000000; - ROM[284]= 64'h0000000000000000; - ROM[285]= 64'h0000000000000000; - ROM[286]= 64'h0000000000000000; - ROM[287]= 64'h0000000000000000; - ROM[288]= 64'h0000000000000000; - ROM[289]= 64'h0000000000000000; - ROM[290]= 64'h0000000000000000; - ROM[291]= 64'h0000000000000000; - ROM[292]= 64'h0000000000000000; - ROM[293]= 64'h0000000000000000; - ROM[294]= 64'h0000000000000000; - ROM[295]= 64'h0000000000000000; - ROM[296]= 64'h0000000000000000; - ROM[297]= 64'h0000000000000000; - ROM[298]= 64'h0000000000000000; - ROM[299]= 64'h0000000000000000; - ROM[300]= 64'h0000000000000000; - ROM[301]= 64'h0000000000000000; - ROM[302]= 64'h0000000000000000; - ROM[303]= 64'h0000000000000000; - ROM[304]= 64'h0000000000000000; - ROM[305]= 64'h0000000000000000; - ROM[306]= 64'h0000000000000000; - ROM[307]= 64'h0000000000000000; - ROM[308]= 64'h0000000000000000; - ROM[309]= 64'h0000000000000000; - ROM[310]= 64'h0000000000000000; - ROM[311]= 64'h0000000000000000; - ROM[312]= 64'h0000000000000000; - ROM[313]= 64'h0000000000000000; - ROM[314]= 64'h0000000000000000; - ROM[315]= 64'h0000000000000000; - ROM[316]= 64'h0000000000000000; - ROM[317]= 64'h0000000000000000; - ROM[318]= 64'h0000000000000000; - ROM[319]= 64'h0000000000000000; - ROM[320]= 64'h0000000000000000; - ROM[321]= 64'h0000000000000000; - ROM[322]= 64'h0000000000000000; - ROM[323]= 64'h0000000000000000; - ROM[324]= 64'h0000000000000000; - ROM[325]= 64'h0000000000000000; - ROM[326]= 64'h0000000000000000; - ROM[327]= 64'h0000000000000000; - ROM[328]= 64'h0000000000000000; - ROM[329]= 64'h0000000000000000; - ROM[330]= 64'h0000000000000000; - ROM[331]= 64'h0000000000000000; - ROM[332]= 64'h0000000000000000; - ROM[333]= 64'h0000000000000000; - ROM[334]= 64'h0000000000000000; - ROM[335]= 64'h0000000000000000; - ROM[336]= 64'h0000000000000000; - ROM[337]= 64'h0000000000000000; - ROM[338]= 64'h0000000000000000; - ROM[339]= 64'h0000000000000000; - ROM[340]= 64'h0000000000000000; - ROM[341]= 64'h0000000000000000; - ROM[342]= 64'h0000000000000000; - ROM[343]= 64'h0000000000000000; - ROM[344]= 64'h0000000000000000; - ROM[345]= 64'h0000000000000000; - ROM[346]= 64'h0000000000000000; - ROM[347]= 64'h0000000000000000; - ROM[348]= 64'h0000000000000000; - ROM[349]= 64'h0000000000000000; - ROM[350]= 64'h0000000000000000; - ROM[351]= 64'h0000000000000000; - ROM[352]= 64'h0000000000000000; - ROM[353]= 64'h0000000000000000; - ROM[354]= 64'h0000000000000000; - ROM[355]= 64'h0000000000000000; - ROM[356]= 64'h0000000000000000; - ROM[357]= 64'h0000000000000000; - ROM[358]= 64'h0000000000000000; - ROM[359]= 64'h0000000000000000; - ROM[360]= 64'h0000000000000000; - ROM[361]= 64'h0000000000000000; - ROM[362]= 64'h0000000000000000; - ROM[363]= 64'h0000000000000000; - ROM[364]= 64'h0000000000000000; - ROM[365]= 64'h0000000000000000; - ROM[366]= 64'h0000000000000000; - ROM[367]= 64'h0000000000000000; - ROM[368]= 64'h0000000000000000; - ROM[369]= 64'h0000000000000000; - ROM[370]= 64'h0000000000000000; - ROM[371]= 64'h0000000000000000; - ROM[372]= 64'h0000000000000000; - ROM[373]= 64'h0000000000000000; - ROM[374]= 64'h0000000000000000; - ROM[375]= 64'h0000000000000000; - ROM[376]= 64'h0000000000000000; - ROM[377]= 64'h0000000000000000; - ROM[378]= 64'h0000000000000000; - ROM[379]= 64'h0000000000000000; - ROM[380]= 64'h0000000000000000; - ROM[381]= 64'h0000000000000000; - ROM[382]= 64'h0000000000000000; - ROM[383]= 64'h0000000000000000; - ROM[384]= 64'h0000000000000000; - ROM[385]= 64'h0000000000000000; - ROM[386]= 64'h0000000000000000; - ROM[387]= 64'h0000000000000000; - ROM[388]= 64'h0000000000000000; - ROM[389]= 64'h0000000000000000; - ROM[390]= 64'h0000000000000000; - ROM[391]= 64'h0000000000000000; - ROM[392]= 64'h0000000000000000; - ROM[393]= 64'h0000000000000000; - ROM[394]= 64'h0000000000000000; - ROM[395]= 64'h0000000000000000; - ROM[396]= 64'h0000000000000000; - ROM[397]= 64'h0000000000000000; - ROM[398]= 64'h0000000000000000; - ROM[399]= 64'h0000000000000000; - ROM[400]= 64'h0000000000000000; - ROM[401]= 64'h0000000000000000; - ROM[402]= 64'h0000000000000000; - ROM[403]= 64'h0000000000000000; - ROM[404]= 64'h0000000000000000; - ROM[405]= 64'h0000000000000000; - ROM[406]= 64'h0000000000000000; - ROM[407]= 64'h0000000000000000; - ROM[408]= 64'h0000000000000000; - ROM[409]= 64'h0000000000000000; - ROM[410]= 64'h0000000000000000; - ROM[411]= 64'h0000000000000000; - ROM[412]= 64'h0000000000000000; - ROM[413]= 64'h0000000000000000; - ROM[414]= 64'h0000000000000000; - ROM[415]= 64'h0000000000000000; - ROM[416]= 64'h0000000000000000; - ROM[417]= 64'h0000000000000000; - ROM[418]= 64'h0000000000000000; - ROM[419]= 64'h0000000000000000; - ROM[420]= 64'h0000000000000000; - ROM[421]= 64'h0000000000000000; - ROM[422]= 64'h0000000000000000; - ROM[423]= 64'h0000000000000000; - ROM[424]= 64'h0000000000000000; - ROM[425]= 64'h0000000000000000; - ROM[426]= 64'h0000000000000000; - ROM[427]= 64'h0000000000000000; - ROM[428]= 64'h0000000000000000; - ROM[429]= 64'h0000000000000000; - ROM[430]= 64'h0000000000000000; - ROM[431]= 64'h0000000000000000; - ROM[432]= 64'h0000000000000000; - ROM[433]= 64'h0000000000000000; - ROM[434]= 64'h0000000000000000; - ROM[435]= 64'h0000000000000000; - ROM[436]= 64'h0000000000000000; - ROM[437]= 64'h0000000000000000; - ROM[438]= 64'h0000000000000000; - ROM[439]= 64'h0000000000000000; - ROM[440]= 64'h0000000000000000; - ROM[441]= 64'h0000000000000000; - ROM[442]= 64'h0000000000000000; - ROM[443]= 64'h0000000000000000; - ROM[444]= 64'h0000000000000000; - ROM[445]= 64'h0000000000000000; - ROM[446]= 64'h0000000000000000; - ROM[447]= 64'h0000000000000000; - ROM[448]= 64'h0000000000000000; - ROM[449]= 64'h0000000000000000; - ROM[450]= 64'h0000000000000000; - ROM[451]= 64'h0000000000000000; - ROM[452]= 64'h0000000000000000; - ROM[453]= 64'h0000000000000000; - ROM[454]= 64'h0000000000000000; - ROM[455]= 64'h0000000000000000; - ROM[456]= 64'h0000000000000000; - ROM[457]= 64'h0000000000000000; - ROM[458]= 64'h0000000000000000; - ROM[459]= 64'h0000000000000000; - ROM[460]= 64'h0000000000000000; - ROM[461]= 64'h0000000000000000; - ROM[462]= 64'h0000000000000000; - ROM[463]= 64'h0000000000000000; - ROM[464]= 64'h0000000000000000; - ROM[465]= 64'h0000000000000000; - ROM[466]= 64'h0000000000000000; - ROM[467]= 64'h0000000000000000; - ROM[468]= 64'h0000000000000000; - ROM[469]= 64'h0000000000000000; - ROM[470]= 64'h0000000000000000; - ROM[471]= 64'h0000000000000000; - ROM[472]= 64'h0000000000000000; - ROM[473]= 64'h0000000000000000; - ROM[474]= 64'h0000000000000000; - ROM[475]= 64'h0000000000000000; - ROM[476]= 64'h0000000000000000; - ROM[477]= 64'h0000000000000000; - ROM[478]= 64'h0000000000000000; - ROM[479]= 64'h0000000000000000; - ROM[480]= 64'h0000000000000000; - ROM[481]= 64'h0000000000000000; - ROM[482]= 64'h0000000000000000; - ROM[483]= 64'h0000000000000000; - ROM[484]= 64'h0000000000000000; - ROM[485]= 64'h0000000000000000; - ROM[486]= 64'h0000000000000000; - ROM[487]= 64'h0000000000000000; - ROM[488]= 64'h0000000000000000; - ROM[489]= 64'h0000000000000000; - ROM[490]= 64'h0000000000000000; - ROM[491]= 64'h0000000000000000; - ROM[492]= 64'h0000000000000000; - ROM[493]= 64'h0000000000000000; - ROM[494]= 64'h0000000000000000; - ROM[495]= 64'h0000000000000000; - ROM[496]= 64'h0000000000000000; - ROM[497]= 64'h0000000000000000; - ROM[498]= 64'h0000000000000000; - ROM[499]= 64'h0000000000000000; - ROM[500]= 64'h0000000000000000; - ROM[501]= 64'h0000000000000000; - ROM[502]= 64'h0000000000000000; - ROM[503]= 64'h0000000000000000; - ROM[504]= 64'h0000000000000000; - ROM[505]= 64'h0000000000000000; - ROM[506]= 64'h0000000000000000; - ROM[507]= 64'h0000000000000000; - ROM[508]= 64'h0000000000000000; - ROM[509]= 64'h0000000000000000; - ROM[510]= 64'h0000000000000000; - ROM[511]= 64'h0000000000000000; - ROM[512]= 64'h0000000000000000; - ROM[513]= 64'h0000000000000000; - ROM[514]= 64'h0000000000000000; - ROM[515]= 64'h0000000000000000; - ROM[516]= 64'h0000000000000000; - ROM[517]= 64'h0000000000000000; - ROM[518]= 64'h0000000000000000; - ROM[519]= 64'h0000000000000000; - ROM[520]= 64'h0000000000000000; - ROM[521]= 64'h0000000000000000; - ROM[522]= 64'h0000000000000000; - ROM[523]= 64'h0000000000000000; - ROM[524]= 64'h0000000000000000; - ROM[525]= 64'h0000000000000000; - ROM[526]= 64'h0000000000000000; - ROM[527]= 64'h0000000000000000; - ROM[528]= 64'h0000000000000000; - ROM[529]= 64'h0000000000000000; - ROM[530]= 64'h0000000000000000; - ROM[531]= 64'h0000000000000000; - ROM[532]= 64'h0000000000000000; - ROM[533]= 64'h0000000000000000; - ROM[534]= 64'h0000000000000000; - ROM[535]= 64'h0000000000000000; - ROM[536]= 64'h0000000000000000; - ROM[537]= 64'h0000000000000000; - ROM[538]= 64'h0000000000000000; - ROM[539]= 64'h0000000000000000; - ROM[540]= 64'h0000000000000000; - ROM[541]= 64'h0000000000000000; - ROM[542]= 64'h0000000000000000; - ROM[543]= 64'h0000000000000000; - ROM[544]= 64'h0000000000000000; - ROM[545]= 64'h0000000000000000; - ROM[546]= 64'h0000000000000000; - ROM[547]= 64'h0000000000000000; - ROM[548]= 64'h0000000000000000; - ROM[549]= 64'h0000000000000000; - ROM[550]= 64'h0000000000000000; - ROM[551]= 64'h0000000000000000; - ROM[552]= 64'h0000000000000000; - ROM[553]= 64'h0000000000000000; - ROM[554]= 64'h0000000000000000; - ROM[555]= 64'h0000000000000000; - ROM[556]= 64'h0000000000000000; - ROM[557]= 64'h0000000000000000; - ROM[558]= 64'h0000000000000000; - ROM[559]= 64'h0000000000000000; - ROM[560]= 64'h0000000000000000; - ROM[561]= 64'h0000000000000000; - ROM[562]= 64'h0000000000000000; - ROM[563]= 64'h0000000000000000; - ROM[564]= 64'h0000000000000000; - ROM[565]= 64'h0000000000000000; - ROM[566]= 64'h0000000000000000; - ROM[567]= 64'h0000000000000000; - ROM[568]= 64'h0000000000000000; - ROM[569]= 64'h0000000000000000; - ROM[570]= 64'h0000000000000000; - ROM[571]= 64'h0000000000000000; - ROM[572]= 64'h0000000000000000; - ROM[573]= 64'h0000000000000000; - ROM[574]= 64'h0000000000000000; - ROM[575]= 64'h0000000000000000; - ROM[576]= 64'h0000000000000000; - ROM[577]= 64'h0000000000000000; - ROM[578]= 64'h0000000000000000; - ROM[579]= 64'h0000000000000000; - ROM[580]= 64'h0000000000000000; - ROM[581]= 64'h0000000000000000; - ROM[582]= 64'h0000000000000000; - ROM[583]= 64'h0000000000000000; - ROM[584]= 64'h0000000000000000; - ROM[585]= 64'h0000000000000000; - ROM[586]= 64'h0000000000000000; - ROM[587]= 64'h0000000000000000; - ROM[588]= 64'h0000000000000000; - ROM[589]= 64'h0000000000000000; - ROM[590]= 64'h0000000000000000; - ROM[591]= 64'h0000000000000000; - ROM[592]= 64'h0000000000000000; - ROM[593]= 64'h0000000000000000; - ROM[594]= 64'h0000000000000000; - ROM[595]= 64'h0000000000000000; - ROM[596]= 64'h0000000000000000; - ROM[597]= 64'h0000000000000000; - ROM[598]= 64'h0000000000000000; - ROM[599]= 64'h0000000000000000; - ROM[600]= 64'h0000000000000000; - ROM[601]= 64'h0000000000000000; - ROM[602]= 64'h0000000000000000; - ROM[603]= 64'h0000000000000000; - ROM[604]= 64'h0000000000000000; - ROM[605]= 64'h0000000000000000; - ROM[606]= 64'h0000000000000000; - ROM[607]= 64'h0000000000000000; - ROM[608]= 64'h0000000000000000; - ROM[609]= 64'h0000000000000000; - ROM[610]= 64'h0000000000000000; - ROM[611]= 64'h0000000000000000; - ROM[612]= 64'h0000000000000000; - ROM[613]= 64'h0000000000000000; - ROM[614]= 64'h0000000000000000; - ROM[615]= 64'h0000000000000000; - ROM[616]= 64'h0000000000000000; - ROM[617]= 64'h0000000000000000; - ROM[618]= 64'h0000000000000000; - ROM[619]= 64'h0000000000000000; - ROM[620]= 64'h0000000000000000; - ROM[621]= 64'h0000000000000000; - ROM[622]= 64'h0000000000000000; - ROM[623]= 64'h0000000000000000; - ROM[624]= 64'h0000000000000000; - ROM[625]= 64'h0000000000000000; - ROM[626]= 64'h0000000000000000; - ROM[627]= 64'h0000000000000000; - ROM[628]= 64'h0000000000000000; - ROM[629]= 64'h0000000000000000; - ROM[630]= 64'h0000000000000000; - ROM[631]= 64'h0000000000000000; - ROM[632]= 64'h0000000000000000; - ROM[633]= 64'h0000000000000000; - ROM[634]= 64'h0000000000000000; - ROM[635]= 64'h0000000000000000; - ROM[636]= 64'h0000000000000000; - ROM[637]= 64'h0000000000000000; - ROM[638]= 64'h0000000000000000; - ROM[639]= 64'h0000000000000000; - ROM[640]= 64'h00600100d2e3ca40; - end - end + ROM[22] = 64'h68110002806702fe; + ROM[23] = 64'h0085179bf0080813; + ROM[24] = 64'h038008130107f7b3; + ROM[25] = 64'h480508a86c632781; + ROM[26] = 64'h1533357902a87963; + ROM[27] = 64'h38030000181700a8; + ROM[28] = 64'h1c6301057833f268; + ROM[29] = 64'h081a403018370808; + ROM[30] = 64'h0105783342280813; + ROM[31] = 64'h1815751308081063; + ROM[32] = 64'h00367513c295e14d; + ROM[33] = 64'h654ded510207e793; + ROM[34] = 64'hc1701ff00613f130; + ROM[35] = 64'h0637c530fff6861b; + ROM[36] = 64'h664dcd10167d0200; + ROM[37] = 64'h17fd001007b7c25c; + ROM[38] = 64'h859b5a5cc20cd21c; + ROM[39] = 64'h02062a23dfed0007; + ROM[40] = 64'h4785fffd561c664d; + ROM[41] = 64'h4501461c06f59063; + ROM[42] = 64'h4a1cc35c465cc31c; + ROM[43] = 64'he29dc75c4a5cc71c; + ROM[44] = 64'h0c63086008138082; + ROM[45] = 64'h1ae30a9008130105; + ROM[46] = 64'hb7710017e793f905; + ROM[47] = 64'he793b75901d7e793; + ROM[48] = 64'h5f5c674db7410197; + ROM[49] = 64'h66cd02072e23dffd; + ROM[50] = 64'hfff78513ff7d5698; + ROM[51] = 64'h40a0053300a03533; + ROM[52] = 64'hbfb100a7e7938082; + ROM[53] = 64'he0a2715d8082557d; + ROM[54] = 64'he486f052f44ef84a; + ROM[55] = 64'hfa13e85aec56fc26; + ROM[56] = 64'h843289ae892a0086; + ROM[57] = 64'h00959993000a1463; + ROM[58] = 64'h864ac4396b054a85; + ROM[59] = 64'h0009859b4549870a; + ROM[60] = 64'h0004049b05540363; + ROM[61] = 64'h86a66485008b7363; + ROM[62] = 64'h870a87aaec7ff0ef; + ROM[63] = 64'h4531458146014681; + ROM[64] = 64'hf0ef0207c9639c05; + ROM[65] = 64'h17820094979beb1f; + ROM[66] = 64'h873e020541639381; + ROM[67] = 64'h993e99ba020a1963; + ROM[68] = 64'h870aa8094501f85d; + ROM[69] = 64'he8bff0ef45454685; + ROM[70] = 64'h60a64505fe0559e3; + ROM[71] = 64'h79a2794274e26406; + ROM[72] = 64'h61616b426ae27a02; + ROM[73] = 64'h9301020497138082; + ROM[74] = 64'hf426f8227139b7f1; + ROM[75] = 64'hec4efc064705f04a; + ROM[76] = 64'h84aad79867cde852; + ROM[77] = 64'h571c674d8932842e; + ROM[78] = 64'h03600793dff58b85; + ROM[79] = 64'h674d02072423d35c; + ROM[80] = 64'hb00026f3fffd571c; + ROM[81] = 64'h11f707130007a737; + ROM[82] = 64'h7de38f95b00027f3; + ROM[83] = 64'h8b895b1c674dfef7; + ROM[84] = 64'h0027e7934f5ccf9d; + ROM[85] = 64'he737b00026f3cf5c; + ROM[86] = 64'h27f30ff7071305f5; + ROM[87] = 64'hfef77de38f95b000; + ROM[88] = 64'hcf5c9bf54f5c674d; + ROM[89] = 64'h00989737b00026f3; + ROM[90] = 64'hb00027f367f70713; + ROM[91] = 64'h4681fef77de38f95; + ROM[92] = 64'h4501870a45814601; + ROM[93] = 64'h4681870adcfff0ef; + ROM[94] = 64'h45211aa005934601; + ROM[95] = 64'h4782e12ddbfff0ef; + ROM[96] = 64'h17d249911aa00713; + ROM[97] = 64'h099302e7876393d1; + ROM[98] = 64'h70e2744285220ff0; + ROM[99] = 64'h69e2864a86ce6a42; + ROM[100]= 64'h612174a285a67902; + ROM[101]= 64'h40e3d8dff0efb551; + ROM[102]= 64'h0207c7634782fe05; + ROM[103]= 64'h458146014681870a; + ROM[104]= 64'hd73ff0ef03700513; + ROM[105]= 64'h46014681870a87aa; + ROM[106]= 64'h0a900513403005b7; + ROM[107]= 64'h4989bf4dfc07d9e3; + ROM[108]= 64'hc3998b8583f9bfe1; + ROM[109]= 64'h4681870a0089e993; + ROM[110]= 64'hf0ef450945814601; + ROM[111]= 64'h870af8054ae3d41f; + ROM[112]= 64'h123405b746014681; + ROM[113]= 64'h40e3d2dff0ef450d; + ROM[114]= 64'h870a77c14a02f805; + ROM[115]= 64'h4601468100fa7a33; + ROM[116]= 64'hd13ff0ef451d85d2; + ROM[117]= 64'h470567cdf60543e3; + ROM[118]= 64'h4737b00026f3d3d8; + ROM[119]= 64'h27f323f70713000f; + ROM[120]= 64'hfef77de38f95b000; + ROM[121]= 64'h870a0007ae2367cd; + ROM[122]= 64'h051385d246014681; + ROM[123]= 64'h48e3cddff0ef0370; + ROM[124]= 64'h46014681870af205; + ROM[125]= 64'hf0ef086005134581; + ROM[126]= 64'h870af0054ee3cc9f; + ROM[127]= 64'h2000059346014681; + ROM[128]= 64'h56e3cb5ff0ef4541; + ROM[129]= 64'h00000000b711f005; + end // initial begin + end // if (PRELOAD_ENABLED) end endmodule diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index d5cab6f7b..364d9d200 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -51,7 +51,6 @@ module adrdecs ( adrdec newsdc(PhysicalAddress, `SDC2_BASE, `SDC2_RANGE, `SDC2_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]); assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected - endmodule // verilator lint_on UNOPTFLAT diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 09d1d6a1e..efd961e6f 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -71,7 +71,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) ( mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); // single-ported RAM - ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), + ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN), .PRELOAD_ENABLED(`FPGA)) memory(.clk(HCLK), .ce(1'b1), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index c58babb6f..5b1546c3b 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -33,30 +33,31 @@ // *** and use memread signal to reduce power when reads aren't needed module uncore ( // AHB Bus Interface - input logic HCLK, HRESETn, - input logic TIMECLK, - input logic [`PA_BITS-1:0] HADDR, - input logic [`AHBW-1:0] HWDATA, - input logic [`XLEN/8-1:0] HWSTRB, - input logic HWRITE, - input logic [2:0] HSIZE, - input logic [2:0] HBURST, - input logic [3:0] HPROT, - input logic [1:0] HTRANS, - input logic HMASTLOCK, - input logic [`AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic [`AHBW-1:0] HRDATA, - output logic HREADY, HRESP, - output logic HSELEXT, + input logic HCLK, HRESETn, + input logic TIMECLK, + input logic [`PA_BITS-1:0] HADDR, + input logic [`AHBW-1:0] HWDATA, + input logic [`XLEN/8-1:0] HWSTRB, + input logic HWRITE, + input logic [2:0] HSIZE, + input logic [2:0] HBURST, + input logic [3:0] HPROT, + input logic [1:0] HTRANS, + input logic HMASTLOCK, + input logic [`AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + output logic [`AHBW-1:0] HRDATA, + output logic HREADY, HRESP, + output logic HSELEXT, + output logic HSELEXTSDC, // peripheral pins - output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT - output logic MExtInt, SExtInt, // External interrupts from PLIC - output logic [63:0] MTIME_CLINT, // MTIME, from CLINT - input logic [31:0] GPIOPinsIn, // GPIO pin input value - output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable - input logic UARTSin, // UART serial input - output logic UARTSout // UART serial output + output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT + output logic MExtInt, SExtInt, // External interrupts from PLIC + output logic [63:0] MTIME_CLINT, // MTIME, from CLINT + input logic [31:0] GPIOPinsIn, // GPIO pin input value + output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable + input logic UARTSin, // UART serial input + output logic UARTSout // UART serial output /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input @@ -87,13 +88,16 @@ module uncore ( logic [`XLEN-1:0] HREADBRIDGE; logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; + (* mark_debug = "true" *) logic HSELEXTSDCD; + + // Determine which region of physical memory (if any) is being accessed // Use a trimmed down portion of the PMA checker - only the address decoders // Set access types to all 1 as don't cares because the MMU has already done access checking adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions); // unswizzle HSEL signals - assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[10:1]; + assign {HSELEXTSDC, HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[11:1]; // AHB -> APB bridge ahbapbbridge #(4) ahbapbbridge ( @@ -168,19 +172,19 @@ module uncore ( // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | - ({`XLEN{HSELEXTD}} & HRDATAEXT) | + ({`XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) | ({`XLEN{HSELBRIDGED}} & HREADBRIDGE) | ({`XLEN{HSELBootRomD}} & HREADBootRom) | ({`XLEN{HSELSDCD}} & HREADSDC); assign HRESP = HSELRamD & HRESPRam | - HSELEXTD & HRESPEXT | + (HSELEXTD | HSELEXTSDCD) & HRESPEXT | HSELBRIDGE & HRESPBRIDGE | HSELBootRomD & HRESPBootRom | HSELSDC & HRESPSDC; assign HREADY = HSELRamD & HREADYRam | - HSELEXTD & HREADYEXT | + (HSELEXTD | HSELEXTSDCD) & HREADYEXT | HSELBRIDGED & HREADYBRIDGE | HSELBootRomD & HREADYBootRom | HSELSDCD & HREADYSDC | @@ -191,7 +195,7 @@ module uncore ( // takes more than 1 cycle to repsond it needs to hold on to the old select until the // device is ready. Hense this register must be selectively enabled by HREADY. // However on reset None must be seleted. - flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:0], 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); + flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[11:0], 11'b1, {HSELEXTSDCD, HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 4fd50a2fe..50946ada1 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -30,32 +30,33 @@ `include "wally-config.vh" module wallypipelinedsoc ( - input logic clk, - input logic reset_ext, // external asynchronous reset pin - output logic reset, // reset synchronized to clk to prevent races on release + input logic clk, + input logic reset_ext, // external asynchronous reset pin + output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [`AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic HSELEXT, + input logic [`AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + output logic HSELEXT, + output logic HSELEXTSDC, // outputs to external memory, shared with uncore memory - output logic HCLK, HRESETn, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, - output logic HREADY, + output logic HCLK, HRESETn, + output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, + output logic HREADY, // I/O Interface - input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO - input logic UARTSin, // UART serial data input - output logic UARTSout // UART serial data output + input logic TIMECLK, // optional for CLINT MTIME counter + input logic [31:0] GPIOPinsIn, // inputs from GPIO + output logic [31:0] GPIOPinsOut, // output values for GPIO + output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic UARTSin, // UART serial data input + output logic UARTSout // UART serial data output /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable @@ -84,7 +85,7 @@ module wallypipelinedsoc ( if (`BUS_SUPPORTED) begin : uncore uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, - .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index c9b2c6451..3f0a22c49 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -116,15 +116,17 @@ struct sdc_regs { #define MAX_BLOCK_CNT 0x1000 -static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; +#define SDC 0x00013000; -static int errno __attribute__((section(".bss"))); +// static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; + +// static int errno __attribute__((section(".bss"))); // static DSTATUS drv_status __attribute__((section(".bss"))); -static BYTE card_type __attribute__((section(".bss"))); -static uint32_t response[4] __attribute__((section(".bss"))); -static int alt_mem __attribute__((section(".bss"))); +// static BYTE card_type __attribute__((section(".bss"))); +// static uint32_t response[4] __attribute__((section(".bss"))); +// static int alt_mem __attribute__((section(".bss"))); -static const char * errno_to_str(void) { +/*static const char * errno_to_str(void) { switch (errno) { case ERR_EOF: return "Unexpected EOF"; case ERR_NOT_ELF: return "Not an ELF file"; @@ -139,7 +141,7 @@ static const char * errno_to_str(void) { case FR_TIMEOUT: return "Timeout"; } return "Unknown error code"; -} + }*/ static void usleep(unsigned us) { uintptr_t cycles0; @@ -151,7 +153,9 @@ static void usleep(unsigned us) { } } -static int sdc_cmd_finish(unsigned cmd) { +static int sdc_cmd_finish(unsigned cmd, uint32_t * response) { + struct sdc_regs * regs = (struct sdc_regs *)SDC; + while (1) { unsigned status = regs->cmd_int_status; if (status) { @@ -166,10 +170,10 @@ static int sdc_cmd_finish(unsigned cmd) { response[3] = regs->response4; return 0; } - errno = FR_DISK_ERR; + /* errno = FR_DISK_ERR; if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT; if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC; - if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK; + if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;*/ break; } } @@ -178,21 +182,24 @@ static int sdc_cmd_finish(unsigned cmd) { static int sdc_data_finish(void) { int status; - + struct sdc_regs * regs = (struct sdc_regs *)SDC; + while ((status = regs->dat_int_status) == 0) {} regs->dat_int_status = 0; while (regs->software_reset != 0) {} if (status == SDC_DAT_INT_STATUS_TRS) return 0; - errno = FR_DISK_ERR; + /* errno = FR_DISK_ERR; if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT; if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC; - if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO; + if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;*/ return -1; } -static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks) { - unsigned command = (cmd & 0x3f) << 8; +static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks, uint32_t * response) { + struct sdc_regs * regs = (struct sdc_regs *)SDC; + + unsigned command = (cmd & 0x3f) << 8; switch (cmd) { case CMD0: case CMD4: @@ -262,29 +269,32 @@ static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks if (blocks) { command |= 1 << 5; if ((intptr_t)buf & 3) { - errno = ERR_BUF_ALIGNMENT; + // errno = ERR_BUF_ALIGNMENT; return -1; } regs->dma_addres = (uint64_t)(intptr_t)buf; regs->block_size = 511; regs->block_count = blocks - 1; - regs->data_timeout = 0xFFFFFF; + regs->data_timeout = 0x1FFFFFF; } regs->command = command; regs->cmd_timeout = 0xFFFFF; regs->argument = arg; - if (sdc_cmd_finish(cmd) < 0) return -1; + if (sdc_cmd_finish(cmd, response) < 0) return -1; if (blocks) return sdc_data_finish(); return 0; } -#define send_cmd(cmd, arg) send_data_cmd(cmd, arg, NULL, 0) +#define send_cmd(cmd, arg, response) send_data_cmd(cmd, arg, NULL, 0, response) -static int ini_sd(void) { +static BYTE ini_sd(void) { + struct sdc_regs * regs = (struct sdc_regs *)SDC; unsigned rca; + BYTE card_type; + uint32_t response[4]; /* Reset controller */ regs->software_reset = 1; @@ -311,12 +321,12 @@ static int ini_sd(void) { } /* Enter Idle state */ - send_cmd(CMD0, 0); + send_cmd(CMD0, 0, response); card_type = CT_SD1; - if (send_cmd(CMD8, 0x1AA) == 0) { + if (send_cmd(CMD8, 0x1AA, response) == 0) { if ((response[0] & 0xfff) != 0x1AA) { - errno = ERR_CMD_CHECK; + // errno = ERR_CMD_CHECK; return -1; } card_type = CT_SD2; @@ -325,7 +335,7 @@ static int ini_sd(void) { /* Wait for leaving idle state (ACMD41 with HCS bit) */ while (1) { /* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */ - if (send_cmd(CMD55, 0) < 0 || send_cmd(ACMD41, 0x40300000) < 0) return -1; + if (send_cmd(CMD55, 0, response) < 0 || send_cmd(ACMD41, 0x40300000, response) < 0) return -1; if (response[0] & (1 << 31)) { if (response[0] & (1 << 30)) card_type |= CT_BLOCK; break; @@ -333,15 +343,15 @@ static int ini_sd(void) { } /* Enter Identification state */ - if (send_cmd(CMD2, 0) < 0) return -1; + if (send_cmd(CMD2, 0, response) < 0) return -1; /* Get RCA (Relative Card Address) */ rca = 0x1234; - if (send_cmd(CMD3, rca << 16) < 0) return -1; + if (send_cmd(CMD3, rca << 16, response) < 0) return -1; rca = response[0] >> 16; /* Select card */ - if (send_cmd(CMD7, rca << 16) < 0) return -1; + if (send_cmd(CMD7, rca << 16, response) < 0) return -1; /* Clock 25MHz */ // 22Mhz/2 = 11Mhz @@ -350,16 +360,16 @@ static int ini_sd(void) { /* Bus width 1-bit */ regs->control = 0; - if (send_cmd(CMD55, rca << 16) < 0 || send_cmd(ACMD6, 0) < 0) return -1; + if (send_cmd(CMD55, rca << 16, response) < 0 || send_cmd(ACMD6, 0, response) < 0) return -1; /* Set R/W block length to 512 */ - if (send_cmd(CMD16, 512) < 0) return -1; + if (send_cmd(CMD16, 512, response) < 0) return -1; // drv_status &= ~STA_NOINIT; - return 0; + return card_type; } -int disk_read(BYTE * buf, LBA_t sector, UINT count) { +int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { /* This is not needed. This has everything to do with the FAT filesystem stuff that I'm not including. All I need to do is @@ -370,13 +380,16 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { // if (!count) return RES_PARERR; /* if (drv_status & STA_NOINIT) return RES_NOTRDY; */ + uint32_t response[4]; + struct sdc_regs * regs = (struct sdc_regs *)SDC; + /* Convert LBA to byte address if needed */ if (!(card_type & CT_BLOCK)) sector *= 512; while (count > 0) { UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return 1; - if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1; + if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1; sector += (card_type & CT_BLOCK) ? bcnt : bytes; count -= bcnt; buf += bytes; @@ -386,11 +399,13 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { } void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { - ini_sd(); + BYTE card_type; + + card_type = ini_sd(); BYTE * buf = (BYTE *)Dst; - if (disk_read(buf, (LBA_t)address, (UINT)numBlocks) < 0) /* UART Print function?*/; + if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; } /* diff --git a/tests/custom/linker1000.x b/tests/custom/linker1000.x index 4156c6571..6d9e948a6 100644 --- a/tests/custom/linker1000.x +++ b/tests/custom/linker1000.x @@ -72,6 +72,7 @@ SECTIONS PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); + . = 0x0000000000002000; .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } .rodata1 : { *(.rodata1) } .sdata2 : From b3aaa87cba400f41b76d88cb77738cc9fc7c557a Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 14 Jul 2023 13:36:44 -0500 Subject: [PATCH 293/294] Modified bootloader to access GUID partitions. SDC interrupt to PLIC. Since writing an SD card image generation script, the bootloader needed to be altered to access individual binaries from specific partitions. A new file, gpt.c with it's header gpt.h, have been added to the bootloader to facilitate this. The SDC has been added to the device tree for the VCU108 board. Additionally the SDC interrupt signal was added to the PLIC node in the device tree. The PLIC itself was modified to accept the SDC interrupt signal. --- config/fpga/wally-config.vh | 1 + fpga/proberange | 78 +++++++++++++++++++++++++++++++ fpga/probes | 76 ++++++++++++++++++++++++++++++ fpga/src/fpgaTop.v | 12 +++-- linux/buildroot-scripts/Makefile | 1 + linux/devicetree/wally-vcu108.dts | 14 ++++++ src/uncore/plic_apb.sv | 27 ++++++----- src/uncore/uncore.sv | 5 +- src/wally/wallypipelinedsoc.sv | 5 +- tests/custom/boot/Makefile | 6 ++- tests/custom/boot/boot.c | 10 ++-- tests/custom/boot/boot.h | 11 +++++ tests/custom/boot/gpt.c | 46 ++++++++++++++++++ tests/custom/boot/gpt.h | 40 ++++++++++++++++ 14 files changed, 309 insertions(+), 23 deletions(-) create mode 100755 fpga/proberange create mode 100755 fpga/probes create mode 100644 tests/custom/boot/gpt.c create mode 100644 tests/custom/boot/gpt.h diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index c89d3eec8..e3686553f 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -141,6 +141,7 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 10 `define PLIC_GPIO_ID 3 +`define PLIC_SDC_ID 20 `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 diff --git a/fpga/proberange b/fpga/proberange new file mode 100755 index 000000000..a5eccb7f9 --- /dev/null +++ b/fpga/proberange @@ -0,0 +1,78 @@ +#!/usr/bin/python3 + +import sys + +def usage(): + print("Usage: ./probes list_of_probes outfile") + +def header(): + return """create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]""" + +def convertLine(x): + temp = x.split() + temp[1] = int(temp[1]) + temp[2] = int(temp[2]) + return tuple(temp) + +def probeBits( probe ): + str = '' + + if (probe[1] > 1): + for i in range(probe[1]): + if i != (probe[1]-1): + str = str + f"{{{probe[0]}[{i}]}} " + else: + str = str + f"{{{probe[0]}[{i}]}} " + + else: + str = f'{{{probe[0]}}}' + + return str + +def printProbe( probe,): + bits = probeBits(probe) + + return ( + f'create_debug_port u_ila_0 probe\n' + f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{probe[2]}]\n' + f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{probe[2]}]\n' + f'connect_debug_port u_ila_0/probe{probe[2]} [get_nets [list {bits}]]\n\n' + ) + +def main(args): + if (len(args) != 2): + usage() + exit() + + probeList = [] + + with open(args[0]) as probeListFile: + probeList = list(map(convertLine, probeListFile.readlines())) + + with open(args[1], 'w') as outfile: + # outfile.write(header()) + # outfile.write("\n\n") + for i in range(len(probeList)): + outfile.write(printProbe(probeList[i])) + +if __name__ == '__main__': + main(sys.argv[1:]) + + + diff --git a/fpga/probes b/fpga/probes new file mode 100755 index 000000000..5868bc80f --- /dev/null +++ b/fpga/probes @@ -0,0 +1,76 @@ +#!/usr/bin/python3 + +import sys + +def usage(): + print("Usage: ./probes list_of_probes outfile") + +def header(): + return """create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]""" + +def convertLine(x): + temp = x.split() + temp[1] = int(temp[1]) + return tuple(temp) + +def probeBits( probe ): + str = '' + + if (probe[1] > 1): + for i in range(probe[1]): + if i != (probe[1]-1): + str = str + f"{{{probe[0]}[{i}]}} " + else: + str = str + f"{{{probe[0]}[{i}]}} " + + else: + str = f'{{{probe[0]}}}' + + return str + +def printProbe( probe, i ): + bits = probeBits(probe) + + return ( + f'create_debug_port u_ila_0 probe\n' + f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n' + f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n' + f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n' + ) + +def main(args): + if (len(args) != 2): + usage() + exit() + + probeList = [] + + with open(args[0]) as probeListFile: + probeList = list(map(convertLine, probeListFile.readlines())) + + with open(args[1], 'w') as outfile: + outfile.write(header()) + outfile.write("\n\n") + for i in range(len(probeList)): + outfile.write(printProbe(probeList[i], i)) + +if __name__ == '__main__': + main(sys.argv[1:]) + + diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 649b7cd57..3c5b21cb2 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -41,7 +41,7 @@ module fpgaTop inout [3:0] SDCDat, output SDCCLK, inout SDCCmd, - input SDCCD, + input SDCCD, output calib, output cpu_reset, @@ -415,6 +415,9 @@ module fpgaTop wire sd_cmd_reg_o; wire sd_cmd_reg_t; + // SD Card Interrupt signal + wire SDCintr; + // New SDC Data IOBUF connections wire [3:0] sd_dat_i; wire [3:0] sd_dat_reg_o; @@ -506,7 +509,8 @@ module fpgaTop .GPIOPinsEn(GPIOPinsEn), // UART .UARTSin(UARTSin), - .UARTSout(UARTSout) + .UARTSout(UARTSout), + .SDCIntr(SDCIntr) // SD Card /*.SDCDatIn(SDCDatIn), .SDCCmdIn(SDCCmdIn), @@ -864,7 +868,9 @@ module fpgaTop .sd_cmd_i(sd_cmd_i), .sdio_clk(SDCCLK), - .sdio_cd(SDCCD) + .sdio_cd(SDCCD), + + .interrupt(SDCIntr) ); xlnx_axi_dwidth_conv_32to64 axi_conv_up diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile index 41ceacb41..d8da7092f 100644 --- a/linux/buildroot-scripts/Makefile +++ b/linux/buildroot-scripts/Makefile @@ -9,6 +9,7 @@ all: generate: # generating device tree binary dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${IMAGES}/wally-virt.dtb + dtc -I dts -O dtb ../devicetree/wally-vcu108.dts > ${IMAGES}/wally-vcu108.dtb disassemble: mkdir -p ${DIS} diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index a8093042e..6b02a55ba 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -67,6 +67,20 @@ #address-cells = <0x00>; }; + mmc@13000 { + interrupts = <0x14>; + compatible = "riscv,axi-sd-card-1.0"; + reg = <0x00 0x13000 0x00 0x7F>; + fifo-depth = <256>; + bus-width = <4>; + interrupt-parent = <0x03>; + clock = <0x14FB180>; + max-frequency = <0xA7D8C0>; + cap-sd-highspeed; + cap-mmc-highspeed; + no-sdio; + }; + clint@2000000 { interrupts-extended = <0x02 0x03 0x02 0x07>; reg = <0x00 0x2000000 0x00 0x10000>; diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 76b0ebbdc..bd637c358 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -43,17 +43,17 @@ // hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts module plic_apb ( - input logic PCLK, PRESETn, - input logic PSEL, - input logic [27:0] PADDR, - input logic [`XLEN-1:0] PWDATA, - input logic [`XLEN/8-1:0] PSTRB, - input logic PWRITE, - input logic PENABLE, - output logic [`XLEN-1:0] PRDATA, - output logic PREADY, - input logic UARTIntr,GPIOIntr, - output logic MExtInt, SExtInt + input logic PCLK, PRESETn, + input logic PSEL, + input logic [27:0] PADDR, + input logic [`XLEN-1:0] PWDATA, + input logic [`XLEN/8-1:0] PSTRB, + input logic PWRITE, + input logic PENABLE, + output logic [`XLEN-1:0] PRDATA, + output logic PREADY, + input logic UARTIntr,GPIOIntr,SDCIntr, + output logic MExtInt, SExtInt ); logic memwrite, memread; @@ -167,6 +167,11 @@ module plic_apb ( `ifdef PLIC_UART_ID requests[`PLIC_UART_ID] = UARTIntr; `endif + + // Jacob: July 8th 2023 + `ifdef PLIC_SDC_ID + requests[`PLIC_SDC_ID] = SDCIntr; + `endif end // pending interrupt requests diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 5b1546c3b..d66b0e541 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -57,7 +57,8 @@ module uncore ( input logic [31:0] GPIOPinsIn, // GPIO pin input value output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input - output logic UARTSout // UART serial output + output logic UARTSout, // UART serial output + input logic SDCIntr /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input @@ -130,7 +131,7 @@ module uncore ( if (`PLIC_SUPPORTED == 1) begin : plic plic_apb plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, - .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .MExtInt, .SExtInt); + .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .SDCIntr, .MExtInt, .SExtInt); end else begin : plic assign MExtInt = 0; assign SExtInt = 0; diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 50946ada1..0ecccbac0 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -56,7 +56,8 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsOut, // output values for GPIO output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input - output logic UARTSout // UART serial data output + output logic UARTSout, // UART serial data output + input logic SDCIntr /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable @@ -87,7 +88,7 @@ module wallypipelinedsoc ( .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, - .UARTSout, .MTIME_CLINT + .UARTSout, .MTIME_CLINT, .SDCIntr /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile index 8294f2375..1c3b8da6d 100644 --- a/tests/custom/boot/Makefile +++ b/tests/custom/boot/Makefile @@ -28,7 +28,9 @@ LINKER :=$(ROOT)/linker1000.x AFLAGS =$(MARCH) $(MABI) -W -CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2 +# Override directive allows us to prepend other options on the command line +# e.g. $ make CFLAGS=-g +override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 AS=riscv64-unknown-elf-as CC=riscv64-unknown-elf-gcc AR=riscv64-unknown-elf-ar @@ -104,7 +106,7 @@ $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) # convert to hex $(TARGET).memfile: $(TARGET) @echo 'Making object dump file.' - @riscv64-unknown-elf-objdump -D $< > $<.objdump + riscv64-unknown-elf-objdump -DS $< > $<.objdump @echo 'Making memory file' riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@ extractFunctionRadix.sh $<.objdump diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 3f0a22c49..6e4780f55 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -1,5 +1,6 @@ #include #include "boot.h" +#include "gpt.h" /* Card type flags (card_type) */ #define CT_MMC 0x01 /* MMC ver 3 */ @@ -400,12 +401,15 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { BYTE card_type; - + int ret = 0; + card_type = ini_sd(); - BYTE * buf = (BYTE *)Dst; + // BYTE * buf = (BYTE *)Dst; - if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; + // if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; + + ret = gpt_load_partitions(card_type); } /* diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h index 3dd7116a7..0f75fbf9e 100644 --- a/tests/custom/boot/boot.h +++ b/tests/custom/boot/boot.h @@ -11,5 +11,16 @@ typedef WORD WCHAR; typedef QWORD LBA_t; +// Define memory locations of boot images ===================== +// These locations are copied from the generic configuration +// of OpenSBI. These addresses can be found in: +// buildroot/output/build/opensbi-0.9/platform/generic/config.mk +#define FDT_ADDRESS 0x80200000 // FW_JUMP_FDT_ADDR +#define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START +#define KERNEL_ADDRESS 0x82200000 // FW_JUMP_ADDR + +// Export disk_read +int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type); + #endif // WALLYBOOT diff --git a/tests/custom/boot/gpt.c b/tests/custom/boot/gpt.c new file mode 100644 index 000000000..97e3e4e46 --- /dev/null +++ b/tests/custom/boot/gpt.c @@ -0,0 +1,46 @@ +#include "gpt.h" +#include "boot.h" +#include + +/* PSUEDOCODE + + Need to load GPT LBA 1 and read through the partition entries. + I need to find each of the relevant partition entries, possibly + by their partition names. + +*/ + +int gpt_load_partitions(BYTE card_type) { + // In this version of the GPT partition code + // I'm going to assume that the SD card is already initialized. + + // size_t block_size = 512/8; + // long int lba1_buf[block_size]; + + BYTE lba1_buf[512]; + + int ret = 0; + //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */); + ret = disk_read(lba1_buf, 1, 1, card_type); + + /* Possible error handling with UART message + if ( ret != 0 ) { + + }*/ + + gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf; + + BYTE lba2_buf[512]; + ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1, card_type); + + // Load parition entries for the relevant boot partitions. + partition_entries_t *fdt = (partition_entries_t *)(lba2_buf); + partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128); + partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); + + ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1, card_type); + ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1, card_type); + ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1, card_type); + + return 0; +} diff --git a/tests/custom/boot/gpt.h b/tests/custom/boot/gpt.h new file mode 100644 index 000000000..4aefae229 --- /dev/null +++ b/tests/custom/boot/gpt.h @@ -0,0 +1,40 @@ +#pragma once + +#include +#include "boot.h" + +// LBA 0: Protective MBR +// ignored here + +// Partition Table Header (LBA 1) +typedef struct gpt_pth +{ + uint64_t signature; + uint32_t revision; + uint32_t header_size; //! little endian, usually 0x5c = 92 + uint32_t crc_header; + uint32_t reserved; //! must be 0 + uint64_t current_lba; + uint64_t backup_lba; + uint64_t first_usable_lba; + uint64_t last_usable_lba; + uint8_t disk_guid[16]; + uint64_t partition_entries_lba; + uint32_t nr_partition_entries; + uint32_t size_partition_entry; //! usually 0x80 = 128 + uint32_t crc_partition_entry; +} gpt_pth_t; + +// Partition Entries (LBA 2-33) +typedef struct partition_entries +{ + uint8_t partition_type_guid[16]; + uint8_t partition_guid[16]; + uint64_t first_lba; + uint64_t last_lba; //! inclusive + uint64_t attributes; + uint8_t name[72]; //! utf16 encoded +} partition_entries_t; + +// Find boot partition and load it to the destination +int gpt_load_partitions(BYTE card_type); From 380d96b359ff3099ea7c6ee0307994bdaaa563a8 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 20 Jul 2023 14:15:59 -0500 Subject: [PATCH 294/294] Working new boot process. Buildroot package for sdc. --- fpga/constraints/debug2.xdc | 5 + fpga/constraints/vcu-small-debug.xdc | 56 + fpga/generator/wally.tcl | 2 +- fpga/src/fpgaTop.v | 2 +- .../buildroot-packages/fpga-axi-sdc/Config.in | 6 + .../fpga-axi-sdc/fpga-axi-sdc.mk | 10 + .../fpga-axi-sdc/fpga-axi-sdc.mk~ | 7 + linux/buildroot-packages/linux.config | 1423 ++++++ .../package-source/Makefile | 9 + .../package-source/fpga-axi-sdc.c | 498 +++ linux/buildroot-packages/package.patch | 12 + linux/buildroot-packages/wally.config | 3808 +++++++++++++++++ linux/sdcard/Makefile | 9 + linux/sdcard/flash-sd.sh | 120 + linux/sdcard/make-img.sh | 110 + src/generic/mem/rom1p1r.sv | 146 + tests/custom/boot/bios.s | 2 +- tests/custom/boot/boot.h | 4 +- 18 files changed, 6224 insertions(+), 5 deletions(-) create mode 100644 fpga/constraints/vcu-small-debug.xdc create mode 100644 linux/buildroot-packages/fpga-axi-sdc/Config.in create mode 100644 linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk create mode 100644 linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ create mode 100644 linux/buildroot-packages/linux.config create mode 100644 linux/buildroot-packages/package-source/Makefile create mode 100644 linux/buildroot-packages/package-source/fpga-axi-sdc.c create mode 100644 linux/buildroot-packages/package.patch create mode 100644 linux/buildroot-packages/wally.config create mode 100644 linux/sdcard/Makefile create mode 100755 linux/sdcard/flash-sd.sh create mode 100755 linux/sdcard/make-img.sh diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 0db255fa0..0ce60a316 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -1238,3 +1238,8 @@ create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe242] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe242] connect_debug_port u_ila_0/probe242 [get_nets [list {axiSDC/sd_data_serial_host0/blkcnt_reg[0]} {axiSDC/sd_data_serial_host0/blkcnt_reg[1]} {axiSDC/sd_data_serial_host0/blkcnt_reg[2]} {axiSDC/sd_data_serial_host0/blkcnt_reg[3]} {axiSDC/sd_data_serial_host0/blkcnt_reg[4]} {axiSDC/sd_data_serial_host0/blkcnt_reg[5]} {axiSDC/sd_data_serial_host0/blkcnt_reg[6]} {axiSDC/sd_data_serial_host0/blkcnt_reg[7]} {axiSDC/sd_data_serial_host0/blkcnt_reg[8]} {axiSDC/sd_data_serial_host0/blkcnt_reg[9]} {axiSDC/sd_data_serial_host0/blkcnt_reg[10]} {axiSDC/sd_data_serial_host0/blkcnt_reg[11]}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe243] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe243] +connect_debug_port u_ila_0/probe243 [get_nets [list {SDCIntr}]] diff --git a/fpga/constraints/vcu-small-debug.xdc b/fpga/constraints/vcu-small-debug.xdc new file mode 100644 index 000000000..2b3fab112 --- /dev/null +++ b/fpga/constraints/vcu-small-debug.xdc @@ -0,0 +1,56 @@ +create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]] + +set_property port_width 64 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {SDCIntr}]] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index d58199e19..0380dcb12 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -68,7 +68,7 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v -source ../constraints/debug2.xdc +source ../constraints/vcu-small-debug.xdc # set for RuntimeOptimized implementation diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 3c5b21cb2..b939c6121 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -416,7 +416,7 @@ module fpgaTop wire sd_cmd_reg_t; // SD Card Interrupt signal - wire SDCintr; + (* mark_debug = "true" *) wire SDCIntr; // New SDC Data IOBUF connections wire [3:0] sd_dat_i; diff --git a/linux/buildroot-packages/fpga-axi-sdc/Config.in b/linux/buildroot-packages/fpga-axi-sdc/Config.in new file mode 100644 index 000000000..8cd3c0087 --- /dev/null +++ b/linux/buildroot-packages/fpga-axi-sdc/Config.in @@ -0,0 +1,6 @@ +config BR2_PACKAGE_FPGA_AXI_SDC + bool "FPGA AXI SDC" + help + The Vivado-RISC-V SDC Drivers. + + https://www.github.com/eugene-tarassov/vivado-risc-v \ No newline at end of file diff --git a/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk new file mode 100644 index 000000000..3ee762493 --- /dev/null +++ b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk @@ -0,0 +1,10 @@ +FPGA_AXI_SDC_MODULE_VERSION = 1.0 +# TODO This variable needs to change based on where the package +# contents are stored on each individual computer. Might parameterize +# this somehow. +FPGA_AXI_SDC_SITE = /home/jpease/repos/fpga-axi-sdc +FPGA_AXI_SDC_SITE_METHOD = local +FPGA_AXI_SDC_LICENSE = GPLv2 + +$(eval $(kernel-module)) +$(eval $(generic-package)) diff --git a/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ new file mode 100644 index 000000000..92308225d --- /dev/null +++ b/linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~ @@ -0,0 +1,7 @@ +FPGA_AXI_SDC_MODULE_VERSION = 1.0 +FPGA_AXI_SDC_SITE = /home/jpease/repos/fpga-axi-sdc +FPGA_AXI_SDC_SITE_METHOD = local +FPGA_AXI_SDC_LICENSE = GPLv2 + +$(eval $(kernel-module)) +$(eval $(generic-package)) diff --git a/linux/buildroot-packages/linux.config b/linux/buildroot-packages/linux.config new file mode 100644 index 000000000..ad2ba8669 --- /dev/null +++ b/linux/buildroot-packages/linux.config @@ -0,0 +1,1423 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 5.10.7 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2021.05-dirty) 10.3.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100300 +CONFIG_LD_VERSION=235020000 +CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_IRQ_WORK=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="WallyDefaultHostname" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# end of Timers subsystem + +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TINY_SRCU=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +# CONFIG_CGROUPS is not set +# CONFIG_NAMESPACES is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_BOOT_CONFIG is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +# CONFIG_USERFAULTFD is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# end of Kernel Performance Events And Counters + +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +# CONFIG_PROFILING is not set +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_ZONE_DMA32=y +CONFIG_VA_BITS=39 +CONFIG_PA_BITS=56 +CONFIG_PAGE_OFFSET=0xffffffff80000000 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_LOCKDEP_SUPPORT=y + +# +# SoC selection +# +# CONFIG_SOC_SIFIVE is not set +# CONFIG_SOC_VIRT is not set +# end of SoC selection + +# +# Platform type +# +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MAXPHYSMEM_2GB=y +# CONFIG_MAXPHYSMEM_128GB is not set +# CONFIG_SMP is not set +CONFIG_TUNE_GENERIC=y +CONFIG_RISCV_ISA_C=y +CONFIG_FPU=y +# end of Platform type + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_RISCV_SBI_V01 is not set +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +# CONFIG_EFI is not set +# end of Boot options + +# +# Power management options +# +# CONFIG_PM is not set +# end of Power management options + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# +# General architecture-dependent options +# +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# end of Partition Types + +CONFIG_BLK_MQ_VIRTIO=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_HAS_MMIOWB=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +# CONFIG_NET is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_PCI=y +# CONFIG_PCI is not set +# CONFIG_PCCARD is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_MHI_BUS is not set +# end of Bus devices + +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS or INET not selected +# +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_VIRTIO_BLK is not set + +# +# NVME Support +# +# CONFIG_NVME_FC is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_SRAM is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# end of EEPROM support + +# +# Texas Instruments shared transport line discipline +# +# end of Texas Instruments shared transport line discipline + +# +# Altera FPGA firmware download module (requires I2C) +# +# CONFIG_ECHO is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# end of SCSI device support + +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_16550A_VARIANTS=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +CONFIG_HVC_DRIVER=y +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set +CONFIG_HW_RANDOM_VIRTIO=y +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + +# +# I2C support +# +# CONFIG_I2C is not set +# end of I2C support + +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +# CONFIG_PINCTRL is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=32 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set +CONFIG_GPIO_CDEV=y +# CONFIG_GPIO_CDEV_V1 is not set +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_MB86S7X is not set +CONFIG_GPIO_SIFIVE=y +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_W1 is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TQMX86 is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set + +# +# ARM devices +# +# end of ARM devices + +# +# Frame buffer Devices +# +# CONFIG_FB is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# end of Backlight & LCD device support + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# end of Console display driver support +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_HEAPS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VDPA is not set +# CONFIG_VHOST_MENU is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +CONFIG_HAVE_CLK=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_CLK_SIFIVE is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_RISCV_TIMER=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +# CONFIG_AL_FIC is not set +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +# CONFIG_NVMEM is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +# CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_AUTOFS_FS=y +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EXFAT_FS is not set +# CONFIG_NTFS_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set +# CONFIG_HUGETLBFS is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +# CONFIG_CONFIGFS_FS is not set +# end of Pseudo filesystems + +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NLS is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Public-key cryptography +# +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_ECHAINIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set + +# +# Crypto library routines +# +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_HW is not set + +# +# Certificates for signature checking +# +# end of Certificates for signature checking + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +# CONFIG_XZ_DEC is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_BTF is not set +CONFIG_GDB_SCRIPTS=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_READABLE_ASM=y +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +# CONFIG_KGDB is not set +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +CONFIG_DEBUG_PAGEALLOC=y +# CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_VM=y +# CONFIG_DEBUG_VM_VMACACHE is not set +# CONFIG_DEBUG_VM_RB is not set +CONFIG_DEBUG_VM_PGFLAGS=y +CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_WQ_WATCHDOG=y +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# end of Scheduler Debugging + +CONFIG_DEBUG_TIMEKEEPING=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +CONFIG_DEBUG_RWSEMS=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_PLIST=y +CONFIG_DEBUG_SG=y +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_EQS_DEBUG=y +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set + +# +# riscv Debugging +# + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/linux/buildroot-packages/package-source/Makefile b/linux/buildroot-packages/package-source/Makefile new file mode 100644 index 000000000..4981239eb --- /dev/null +++ b/linux/buildroot-packages/package-source/Makefile @@ -0,0 +1,9 @@ +.PHONY: all clean +obj-m += fpga-axi-sdc.o + +all: + $(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' modules + $(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' modules_install + +clean: + $(MAKE) -C '$(LINUX-DIR)' M='$(PWD)' clean diff --git a/linux/buildroot-packages/package-source/fpga-axi-sdc.c b/linux/buildroot-packages/package-source/fpga-axi-sdc.c new file mode 100644 index 000000000..ebe916a4c --- /dev/null +++ b/linux/buildroot-packages/package-source/fpga-axi-sdc.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * AXI SD Card driver. + * + * AXI SD Card is open source Verilog implementation of high speed SD card controller. + * It is mainly used in FPGA designs. + */ + +#ifdef CONFIG_DEBUG_INFO +#pragma GCC optimize("O0") +#endif + +// Capability bits +#define SDC_CAPABILITY_SD_4BIT 0x0001 +#define SDC_CAPABILITY_SD_RESET 0x0002 +#define SDC_CAPABILITY_ADDR 0xff00 + +// Control bits +#define SDC_CONTROL_SD_4BIT 0x0001 +#define SDC_CONTROL_SD_RESET 0x0002 + +// Card detect bits +#define SDC_CARD_INSERT_INT_EN 0x0001 +#define SDC_CARD_INSERT_INT_REQ 0x0002 +#define SDC_CARD_REMOVE_INT_EN 0x0004 +#define SDC_CARD_REMOVE_INT_REQ 0x0008 + +// Command status bits +#define SDC_CMD_INT_STATUS_CC 0x0001 // Command complete +#define SDC_CMD_INT_STATUS_EI 0x0002 // Any error +#define SDC_CMD_INT_STATUS_CTE 0x0004 // Timeout +#define SDC_CMD_INT_STATUS_CCRC 0x0008 // CRC error +#define SDC_CMD_INT_STATUS_CIE 0x0010 // Command code check error + +// Data status bits +#define SDC_DAT_INT_STATUS_TRS 0x0001 // Transfer complete +#define SDC_DAT_INT_STATUS_ERR 0x0002 // Any error +#define SDC_DAT_INT_STATUS_CTE 0x0004 // Timeout +#define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error +#define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun + +#define CMD_TIMEOUT_MS 1000 +#define BUSY_TIMEOUT_MS 500 + +struct sdc_regs { + volatile uint32_t argument; + volatile uint32_t command; + volatile uint32_t response1; + volatile uint32_t response2; + volatile uint32_t response3; + volatile uint32_t response4; + volatile uint32_t data_timeout; + volatile uint32_t control; + volatile uint32_t cmd_timeout; + volatile uint32_t clock_divider; + volatile uint32_t software_reset; + volatile uint32_t power_control; + volatile uint32_t capability; + volatile uint32_t cmd_int_status; + volatile uint32_t cmd_int_enable; + volatile uint32_t dat_int_status; + volatile uint32_t dat_int_enable; + volatile uint32_t block_size; + volatile uint32_t block_count; + volatile uint32_t card_detect; + volatile uint32_t res_50; + volatile uint32_t res_54; + volatile uint32_t res_58; + volatile uint32_t res_5c; + volatile uint64_t dma_addres; +}; + +struct sdc_host { + struct platform_device * pdev; + struct sdc_regs __iomem * regs; + uint32_t clk_freq; + spinlock_t lock; + struct mmc_request * mrq; + struct mmc_data * data; + unsigned dma_addr_bits; + unsigned dma_count; + dma_addr_t dma_addr; + unsigned dma_size; + int irq; +}; + +static const struct of_device_id axi_sdc_of_match_table[] = { + { .compatible = "riscv,axi-sd-card-1.0" }, + {}, +}; +MODULE_DEVICE_TABLE(of, axi_sdc_of_match_table); + +/* Set clock prescalar value based on the required clock in HZ */ +static void sdc_set_clock(struct sdc_host * host, uint clock) { + unsigned clk_div; + + /* Min clock frequency should be 400KHz */ + if (clock < 400000) clock = 400000; + + clk_div = host->clk_freq / (2 * clock); + if (clk_div > 0x100) clk_div = 0x100; + if (clk_div < 1) clk_div = 1; + + if (host->regs->clock_divider != clk_div - 1) { + host->regs->clock_divider = clk_div - 1; + udelay(10000); + } +} + +static void sdc_cmd_finish(struct sdc_host * host, struct mmc_command * cmd) { + while (1) { + unsigned status = host->regs->cmd_int_status; + if (status) { + // clear interrupts + host->regs->cmd_int_status = 0; + while (host->regs->software_reset != 0) {} + if (status == SDC_CMD_INT_STATUS_CC) { + // get response + cmd->resp[0] = host->regs->response1; + if (cmd->flags & MMC_RSP_136) { + cmd->resp[1] = host->regs->response2; + cmd->resp[2] = host->regs->response3; + cmd->resp[3] = host->regs->response4; + } + break; + } + cmd->error = (status & SDC_CMD_INT_STATUS_CTE) ? -ETIME : -EIO; + break; + } + } +} + +static int sdc_setup_data_xfer(struct sdc_host * host, struct mmc_host * mmc, struct mmc_data * data) { + uint64_t timeout = 0; + + data->bytes_xfered = 0; + + if (host->dma_addr & 3) return -EINVAL; + if (data->blksz & 3) return -EINVAL; + if (data->blksz < 4) return -EINVAL; + if (data->blksz > 0x1000) return -EINVAL; + if (data->blocks > 0x10000) return -EINVAL; + if (host->dma_addr + data->blksz * data->blocks > ((uint64_t)1 << host->dma_addr_bits)) return -EINVAL; + if (data->sg->length < data->blksz * data->blocks) return -EINVAL; + + // SD card data transfer time + timeout += data->blocks * data->blksz * 8 / (1 << mmc->ios.bus_width); + // SD card "busy" time + timeout += (uint64_t)mmc->ios.clock * BUSY_TIMEOUT_MS / 1000 * data->blocks; + + host->regs->dma_addres = (uint64_t)host->dma_addr; + host->regs->block_size = data->blksz - 1; + host->regs->block_count = data->blocks - 1; + host->regs->data_timeout = (uint32_t)timeout; + if (host->regs->data_timeout != timeout) host->regs->data_timeout = 0; + + return 0; +} + +static int sdc_send_cmd(struct sdc_host * host, struct mmc_host * mmc, struct mmc_command * cmd, struct mmc_data * data) { + int command = cmd->opcode << 8; + uint64_t timeout = 0; + int xfer = 0; + + if (cmd->flags & MMC_RSP_PRESENT) { + if (cmd->flags & MMC_RSP_136) + command |= 2; + else { + command |= 1; + } + } + if (cmd->flags & MMC_RSP_BUSY) command |= 1 << 2; + if (cmd->flags & MMC_RSP_CRC) command |= 1 << 3; + if (cmd->flags & MMC_RSP_OPCODE) command |= 1 << 4; + + if (data && (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) && data->blocks) { + host->dma_count = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + if (host->dma_count != 1) { + dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + return data->error = -EIO; + } + host->dma_addr = sg_dma_address(data->sg); + host->dma_size = sg_dma_len(data->sg); + if (data->flags & MMC_DATA_READ) command |= 1 << 5; + if (data->flags & MMC_DATA_WRITE) command |= 1 << 6; + data->error = sdc_setup_data_xfer(host, mmc, data); + if (data->error < 0) { + dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + return data->error; + } + xfer = 1; + } + + timeout = (uint64_t)mmc->ios.clock * CMD_TIMEOUT_MS / 1000; + + host->regs->command = command; + host->regs->cmd_timeout = (uint32_t)timeout; + if (host->regs->cmd_timeout != timeout) host->regs->cmd_timeout = 0; + host->regs->argument = cmd->arg; + + sdc_cmd_finish(host, cmd); + if (cmd->error < 0) { + if (xfer) dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + return cmd->error; + } + if (xfer) host->data = data; + + return 0; +} + +static void sdc_request(struct mmc_host * mmc, struct mmc_request * mrq) { + struct sdc_host * host = mmc_priv(mmc); + + /* Clear the error statuses in case this is a retry */ + if (mrq->sbc) mrq->sbc->error = 0; + if (mrq->cmd) mrq->cmd->error = 0; + if (mrq->data) mrq->data->error = 0; + if (mrq->stop) mrq->stop->error = 0; + + spin_lock_irq(&host->lock); + host->data = NULL; + host->mrq = mrq; + + if (!mrq->sbc || sdc_send_cmd(host, mmc, mrq->sbc, NULL) == 0) { + sdc_send_cmd(host, mmc, mrq->cmd, mrq->data); + } + + if (host->data == NULL) { + mmc_request_done(mmc, mrq); + host->mrq = NULL; + } + else { + host->regs->dat_int_enable = SDC_DAT_INT_STATUS_TRS | SDC_DAT_INT_STATUS_ERR; + } + + spin_unlock_irq(&host->lock); +} + +static void sdc_set_ios(struct mmc_host * mmc, struct mmc_ios * ios) { + struct sdc_host * host = mmc_priv(mmc); + + spin_lock_irq(&host->lock); + + sdc_set_clock(host, ios->clock); + host->regs->control = ios->bus_width == MMC_BUS_WIDTH_4 ? SDC_CONTROL_SD_4BIT : 0; + + spin_unlock_irq(&host->lock); +} + +static void sdc_reset(struct mmc_host * mmc) { + struct sdc_host * host = mmc_priv(mmc); + uint32_t card_detect = 0; + + spin_lock_irq(&host->lock); + + sdc_set_clock(host, 400000); + + // software reset + host->regs->software_reset = 1; + while ((host->regs->software_reset & 1) == 0) {} + // clear software reset + host->regs->software_reset = 0; + while (host->regs->software_reset != 0) {} + udelay(10000); + + // set bus width 1 bit + host->regs->control = 0; + + // disable cmd/data interrupts + host->regs->cmd_int_enable = 0; + host->regs->dat_int_enable = 0; + // clear cmd/data interrupts + host->regs->cmd_int_status = 0; + host->regs->dat_int_status = 0; + // enable card detect interrupt + card_detect = host->regs->card_detect; + if (card_detect & SDC_CARD_INSERT_INT_REQ) { + host->regs->card_detect = SDC_CARD_REMOVE_INT_EN; + } + else if (card_detect & SDC_CARD_REMOVE_INT_REQ) { + host->regs->card_detect = SDC_CARD_INSERT_INT_EN; + } + while (host->regs->software_reset != 0) {} + + spin_unlock_irq(&host->lock); +} + +static void sdc_card_reset(struct mmc_host * mmc) { + struct sdc_host * host = mmc_priv(mmc); + uint32_t control = 0; + + spin_lock_irq(&host->lock); + + control = host->regs->control; + host->regs->control = control | SDC_CONTROL_SD_RESET; + udelay(10); + host->regs->control = control & ~(uint32_t)SDC_CONTROL_SD_RESET; + udelay(10); + + spin_unlock_irq(&host->lock); +} + +static int sdc_get_cd(struct mmc_host * mmc) { + struct sdc_host * host = mmc_priv(mmc); + uint32_t card_detect = host->regs->card_detect; + if (card_detect == 0) return 1; /* Card detect not supported */ + return (card_detect & SDC_CARD_INSERT_INT_REQ) != 0; +} + +static irqreturn_t sdc_isr(int irq, void * dev_id) { + struct mmc_host * mmc = (struct mmc_host *)dev_id; + struct sdc_host * host = mmc_priv(mmc); + uint32_t card_detect = 0; + uint32_t data_status = 0; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + + card_detect = host->regs->card_detect; + if (card_detect & SDC_CARD_INSERT_INT_REQ) { + if (card_detect & SDC_CARD_INSERT_INT_EN) { + host->regs->card_detect = SDC_CARD_REMOVE_INT_EN; + mmc_detect_change(mmc, 0); + } + } + else if (card_detect & SDC_CARD_REMOVE_INT_REQ) { + if (card_detect & SDC_CARD_REMOVE_INT_EN) { + host->regs->card_detect = SDC_CARD_INSERT_INT_EN; + mmc_detect_change(mmc, 0); + } + } + + if ((data_status = host->regs->dat_int_status) != 0) { + host->regs->dat_int_enable = 0; + host->regs->dat_int_status = 0; + while (host->regs->software_reset != 0) {} + if (host->data) { + struct mmc_request * mrq = host->mrq; + struct mmc_data * data = host->data; + if (data_status == SDC_DAT_INT_STATUS_TRS) { + data->bytes_xfered = data->blksz * data->blocks; + } + else { + data->error = -EIO; + if (data_status & SDC_DAT_INT_STATUS_CTE) data->error = -ETIME; + } + if (mrq->stop) sdc_send_cmd(host, mmc, mrq->stop, NULL); + mmc_request_done(mmc, mrq); + dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); + host->data = NULL; + host->mrq = NULL; + } + } + + spin_unlock_irqrestore(&host->lock, flags); + return IRQ_HANDLED; +} + +/*---------------------------------------------------------------------*/ + +// JACOB: Had to modify this to resemble the older version of Linux +// Used to be called hw_reset in older versions. Now it's +// called .card_hw_reset to make it unambiguous what it's +// resetting. When I update Linux, this will be changed back. +static const struct mmc_host_ops axi_sdc_ops = { + .request = sdc_request, + .set_ios = sdc_set_ios, + .get_cd = sdc_get_cd, + .hw_reset = sdc_card_reset, +}; + +static int axi_sdc_probe(struct platform_device * pdev) { + struct device * dev = &pdev->dev; + struct resource * iomem; + struct sdc_host * host; + struct mmc_host * mmc; + void __iomem * ioaddr; + uint32_t capability; + int irq; + int ret; + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ioaddr = devm_ioremap_resource(dev, iomem); + if (IS_ERR(ioaddr)) return PTR_ERR(ioaddr); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) return -ENXIO; + + mmc = mmc_alloc_host(sizeof(*host), dev); + if (!mmc) return -ENOMEM; + + mmc->ops = &axi_sdc_ops; + host = mmc_priv(mmc); + host->pdev = pdev; + host->regs = (struct sdc_regs __iomem *)ioaddr; + host->irq = irq; + + ret = of_property_read_u32(dev->of_node, "clock", &host->clk_freq); + if (ret) host->clk_freq = 100000000; + + ret = mmc_of_parse(mmc); + if (ret) { + mmc_free_host(mmc); + return ret; + } + + if (mmc->f_min == 0) mmc->f_min = host->clk_freq / 0x200; /* maximum clock division 256 * 2 */ + if (mmc->f_max == 0) mmc->f_max = host->clk_freq / 2; /* minimum clock division 2 */ + if ((mmc->caps2 & MMC_CAP2_NO_SDIO) == 0) { + /* TODO: deprecated 10/19/2022, set in DTS */ + mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + mmc->caps2 |= MMC_CAP2_NO_SDIO; + } + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->max_segs = 1; + mmc->max_req_size = 0x2000000; + mmc->max_seg_size = 0x2000000; + mmc->max_blk_size = 0x1000; + mmc->max_blk_count = 0x10000; + + ret = request_irq(host->irq, sdc_isr, IRQF_TRIGGER_HIGH, "fpga-axi-sdc", mmc); + if (ret) { + mmc_free_host(mmc); + return ret; + } + + host->dma_addr_bits = 32; + capability = host->regs->capability; + if (capability & SDC_CAPABILITY_ADDR) { + host->dma_addr_bits = (capability & SDC_CAPABILITY_ADDR) >> __builtin_ctz(SDC_CAPABILITY_ADDR); + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(host->dma_addr_bits)); + if (ret) { + printk(KERN_ERR "AXI-SDC: Can't set DMA mask\n"); + mmc_free_host(mmc); + return ret; + } + } + + sdc_reset(mmc); + + ret = mmc_add_host(mmc); + if (ret) { + printk(KERN_ERR "AXI-SDC: Can't register device\n"); + mmc_free_host(mmc); + return ret; + } + + spin_lock_init(&host->lock); + + platform_set_drvdata(pdev, host); + return 0; +} + +static int axi_sdc_remove(struct platform_device * pdev) { + struct sdc_host * host = platform_get_drvdata(pdev); + struct mmc_host * mmc = mmc_from_priv(host); + + free_irq(host->irq, mmc); + mmc_remove_host(mmc); + mmc_free_host(mmc); + return 0; +} + +static struct platform_driver axi_sdc_driver = { + .driver = { + .name = "riscv-axi-sdc", + .of_match_table = axi_sdc_of_match_table, + }, + .probe = axi_sdc_probe, + .remove = axi_sdc_remove, +}; + +module_platform_driver(axi_sdc_driver); + +MODULE_DESCRIPTION("AXI SD Card driver"); +MODULE_AUTHOR("Eugene Tarassov"); +MODULE_LICENSE("GPL v2"); diff --git a/linux/buildroot-packages/package.patch b/linux/buildroot-packages/package.patch new file mode 100644 index 000000000..2069a005c --- /dev/null +++ b/linux/buildroot-packages/package.patch @@ -0,0 +1,12 @@ +diff --git a/package/Config.in b/package/Config.in +index 82b28d2835..29e8bb66ac 100644 +--- a/package/Config.in ++++ b/package/Config.in +@@ -469,6 +469,7 @@ endmenu + source "package/fconfig/Config.in" + source "package/flashrom/Config.in" + source "package/fmtools/Config.in" ++ source "package/fpga-axi-sdc/Config.in" + source "package/freescale-imx/Config.in" + source "package/fxload/Config.in" + source "package/gcnano-binaries/Config.in" diff --git a/linux/buildroot-packages/wally.config b/linux/buildroot-packages/wally.config new file mode 100644 index 000000000..e5fb96464 --- /dev/null +++ b/linux/buildroot-packages/wally.config @@ -0,0 +1,3808 @@ +# +# Automatically generated file; DO NOT EDIT. +# Buildroot 2021.05-dirty Configuration +# +BR2_HAVE_DOT_CONFIG=y +BR2_HOST_GCC_AT_LEAST_4_9=y +BR2_HOST_GCC_AT_LEAST_5=y +BR2_HOST_GCC_AT_LEAST_6=y +BR2_HOST_GCC_AT_LEAST_7=y +BR2_HOST_GCC_AT_LEAST_8=y +BR2_HOST_GCC_AT_LEAST_9=y + +# +# Target options +# +BR2_ARCH_IS_64=y +BR2_ARCH_HAS_MMU_MANDATORY=y +# BR2_arcle is not set +# BR2_arceb is not set +# BR2_arm is not set +# BR2_armeb is not set +# BR2_aarch64 is not set +# BR2_aarch64_be is not set +# BR2_csky is not set +# BR2_i386 is not set +# BR2_m68k is not set +# BR2_microblazeel is not set +# BR2_microblazebe is not set +# BR2_mips is not set +# BR2_mipsel is not set +# BR2_mips64 is not set +# BR2_mips64el is not set +# BR2_nds32 is not set +# BR2_nios2 is not set +# BR2_or1k is not set +# BR2_powerpc is not set +# BR2_powerpc64 is not set +# BR2_powerpc64le is not set +BR2_riscv=y +# BR2_s390x is not set +# BR2_sh is not set +# BR2_sparc is not set +# BR2_sparc64 is not set +# BR2_x86_64 is not set +# BR2_xtensa is not set +BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_5=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_6=y +BR2_ARCH_NEEDS_GCC_AT_LEAST_7=y +BR2_ARCH="riscv64" +BR2_ENDIAN="LITTLE" +BR2_GCC_TARGET_ABI="lp64d" +BR2_BINFMT_SUPPORTS_SHARED=y +BR2_READELF_ARCH_NAME="RISC-V" +BR2_BINFMT_ELF=y +BR2_RISCV_ISA_RVI=y +BR2_RISCV_ISA_RVM=y +BR2_RISCV_ISA_RVA=y +BR2_RISCV_ISA_RVF=y +BR2_RISCV_ISA_RVD=y +BR2_riscv_g=y +# BR2_riscv_custom is not set +# BR2_RISCV_32 is not set +BR2_RISCV_64=y +# BR2_RISCV_ABI_LP64 is not set +# BR2_RISCV_ABI_LP64F is not set +BR2_RISCV_ABI_LP64D=y + +# +# Build options +# + +# +# Commands +# +BR2_WGET="wget --passive-ftp -nd -t 3" +BR2_SVN="svn --non-interactive" +BR2_BZR="bzr" +BR2_GIT="git" +BR2_CVS="cvs" +BR2_LOCALFILES="cp" +BR2_SCP="scp" +BR2_HG="hg" +BR2_ZCAT="gzip -d -c" +BR2_BZCAT="bzcat" +BR2_XZCAT="xzcat" +BR2_LZCAT="lzip -d -c" +BR2_TAR_OPTIONS="" +BR2_DEFCONFIG="./board/wally/main.config" +BR2_DL_DIR="$(TOPDIR)/dl" +BR2_HOST_DIR="$(BASE_DIR)/host" + +# +# Mirrors and Download locations +# +BR2_PRIMARY_SITE="" +BR2_BACKUP_SITE="http://sources.buildroot.net" +BR2_KERNEL_MIRROR="https://cdn.kernel.org/pub" +BR2_GNU_MIRROR="http://ftpmirror.gnu.org" +BR2_LUAROCKS_MIRROR="http://rocks.moonscript.org" +BR2_CPAN_MIRROR="http://cpan.metacpan.org" +BR2_JLEVEL=0 +# BR2_CCACHE is not set +BR2_ENABLE_DEBUG=y +# BR2_DEBUG_1 is not set +# BR2_DEBUG_2 is not set +BR2_DEBUG_3=y +# BR2_STRIP_strip is not set +# BR2_OPTIMIZE_0 is not set +# BR2_OPTIMIZE_1 is not set +# BR2_OPTIMIZE_2 is not set +# BR2_OPTIMIZE_3 is not set +# BR2_OPTIMIZE_G is not set +BR2_OPTIMIZE_S=y +# BR2_OPTIMIZE_FAST is not set +# BR2_STATIC_LIBS is not set +BR2_SHARED_LIBS=y +# BR2_SHARED_STATIC_LIBS is not set +BR2_PACKAGE_OVERRIDE_FILE="$(CONFIG_DIR)/local.mk" +BR2_GLOBAL_PATCH_DIR="" + +# +# Advanced +# +BR2_COMPILER_PARANOID_UNSAFE_PATH=y +# BR2_FORCE_HOST_BUILD is not set +# BR2_REPRODUCIBLE is not set +# BR2_PER_PACKAGE_DIRECTORIES is not set + +# +# Security Hardening Options +# +# BR2_PIC_PIE is not set +BR2_SSP_NONE=y +# BR2_SSP_REGULAR is not set +# BR2_SSP_STRONG is not set +# BR2_SSP_ALL is not set +BR2_RELRO_NONE=y +# BR2_RELRO_PARTIAL is not set +# BR2_RELRO_FULL is not set +BR2_FORTIFY_SOURCE_NONE=y +# BR2_FORTIFY_SOURCE_1 is not set +# BR2_FORTIFY_SOURCE_2 is not set + +# +# Toolchain +# +BR2_TOOLCHAIN=y +BR2_TOOLCHAIN_USES_GLIBC=y +BR2_TOOLCHAIN_BUILDROOT=y +# BR2_TOOLCHAIN_EXTERNAL is not set + +# +# Toolchain Buildroot Options +# +BR2_TOOLCHAIN_BUILDROOT_VENDOR="buildroot" +# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set +BR2_TOOLCHAIN_BUILDROOT_GLIBC=y +# BR2_TOOLCHAIN_BUILDROOT_MUSL is not set +BR2_TOOLCHAIN_BUILDROOT_LIBC="glibc" + +# +# Kernel Header Options +# +BR2_KERNEL_HEADERS_AS_KERNEL=y +# BR2_KERNEL_HEADERS_4_19 is not set +# BR2_KERNEL_HEADERS_5_4 is not set +# BR2_KERNEL_HEADERS_5_10 is not set +# BR2_KERNEL_HEADERS_5_11 is not set +# BR2_KERNEL_HEADERS_5_12 is not set +# BR2_KERNEL_HEADERS_VERSION is not set +# BR2_KERNEL_HEADERS_CUSTOM_TARBALL is not set +# BR2_KERNEL_HEADERS_CUSTOM_GIT is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_12 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_11 is not set +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_10=y +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_9 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_8 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_7 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_6 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_5 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_4 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_3 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_2 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_1 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_20 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_19 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_18 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_17 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_16 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_15 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_14 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_13 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_12 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_11 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_10 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_8 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_7 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_6 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_5 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_4 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_3 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_2 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_1 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_0 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_19 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_18 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_17 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_16 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_15 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_14 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_13 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_12 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_11 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_10 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_9 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_8 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_7 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_6 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_5 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_4 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_3 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_2 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_1 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_0 is not set +# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_REALLY_OLD is not set +BR2_PACKAGE_LINUX_HEADERS=y + +# +# Glibc Options +# +BR2_PACKAGE_GLIBC=y +# BR2_PACKAGE_GLIBC_UTILS is not set + +# +# Binutils Options +# +BR2_PACKAGE_HOST_BINUTILS_SUPPORTS_CFI=y +# BR2_BINUTILS_VERSION_2_32_X is not set +# BR2_BINUTILS_VERSION_2_34_X is not set +BR2_BINUTILS_VERSION_2_35_X=y +# BR2_BINUTILS_VERSION_2_36_X is not set +BR2_BINUTILS_VERSION="2.35.2" +BR2_BINUTILS_EXTRA_CONFIG_OPTIONS="" + +# +# GCC Options +# +# BR2_GCC_VERSION_8_X is not set +# BR2_GCC_VERSION_9_X is not set +BR2_GCC_VERSION_10_X=y +BR2_GCC_VERSION="10.3.0" +BR2_EXTRA_GCC_CONFIG_OPTIONS="" +# BR2_TOOLCHAIN_BUILDROOT_CXX is not set +# BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set +# BR2_GCC_ENABLE_LTO is not set +# BR2_GCC_ENABLE_OPENMP is not set +# BR2_GCC_ENABLE_GRAPHITE is not set + +# +# Toolchain Generic Options +# +BR2_TOOLCHAIN_SUPPORTS_ALWAYS_LOCKFREE_ATOMIC_INTS=y +BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y +BR2_USE_WCHAR=y +BR2_ENABLE_LOCALE=y +BR2_TOOLCHAIN_HAS_THREADS=y +BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y +BR2_TOOLCHAIN_HAS_THREADS_NPTL=y +BR2_TOOLCHAIN_HAS_SSP=y +BR2_TOOLCHAIN_HAS_SSP_STRONG=y +BR2_TOOLCHAIN_HAS_UCONTEXT=y +BR2_TOOLCHAIN_SUPPORTS_PIE=y +# BR2_TOOLCHAIN_GLIBC_GCONV_LIBS_COPY is not set +BR2_TOOLCHAIN_EXTRA_LIBS="" +BR2_TOOLCHAIN_HAS_FULL_GETTEXT=y +BR2_USE_MMU=y +BR2_TARGET_OPTIMIZATION="" +BR2_TARGET_LDFLAGS="" +# BR2_ECLIPSE_REGISTER is not set +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_0=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_1=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_2=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_3=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_4=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_5=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_6=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_7=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_8=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_9=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_10=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_11=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_12=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_13=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_14=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_15=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_16=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_17=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_18=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_19=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_0=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_1=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_2=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_3=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_4=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_5=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_6=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_7=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_8=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_10=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_11=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_12=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_13=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_14=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_15=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_16=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_17=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_18=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_19=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_20=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_0=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_1=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_2=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_3=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_5=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_6=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_7=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_8=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_9=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_10=y +BR2_TOOLCHAIN_HEADERS_AT_LEAST="5.10" +BR2_TOOLCHAIN_GCC_AT_LEAST_4_3=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_4=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_5=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_6=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_7=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_8=y +BR2_TOOLCHAIN_GCC_AT_LEAST_4_9=y +BR2_TOOLCHAIN_GCC_AT_LEAST_5=y +BR2_TOOLCHAIN_GCC_AT_LEAST_6=y +BR2_TOOLCHAIN_GCC_AT_LEAST_7=y +BR2_TOOLCHAIN_GCC_AT_LEAST_8=y +BR2_TOOLCHAIN_GCC_AT_LEAST_9=y +BR2_TOOLCHAIN_GCC_AT_LEAST_10=y +BR2_TOOLCHAIN_GCC_AT_LEAST="10" +BR2_TOOLCHAIN_HAS_MNAN_OPTION=y +BR2_TOOLCHAIN_HAS_SYNC_1=y +BR2_TOOLCHAIN_HAS_SYNC_2=y +BR2_TOOLCHAIN_HAS_SYNC_4=y +BR2_TOOLCHAIN_HAS_SYNC_8=y +BR2_TOOLCHAIN_HAS_LIBATOMIC=y +BR2_TOOLCHAIN_HAS_ATOMIC=y + +# +# System configuration +# +BR2_ROOTFS_SKELETON_DEFAULT=y +# BR2_ROOTFS_SKELETON_CUSTOM is not set +BR2_TARGET_GENERIC_HOSTNAME="WallyHostname" +BR2_TARGET_GENERIC_ISSUE="Greetings! This RISC-V Linux image was built for Wally on Buildroot!" +BR2_TARGET_GENERIC_PASSWD_SHA256=y +# BR2_TARGET_GENERIC_PASSWD_SHA512 is not set +BR2_TARGET_GENERIC_PASSWD_METHOD="sha-256" +BR2_INIT_BUSYBOX=y +# BR2_INIT_SYSV is not set +# BR2_INIT_OPENRC is not set +# BR2_INIT_SYSTEMD is not set +# BR2_INIT_NONE is not set +# BR2_ROOTFS_DEVICE_CREATION_STATIC is not set +BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y +# BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV is not set +# BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV is not set +BR2_ROOTFS_DEVICE_TABLE="system/device_table.txt" +BR2_ROOTFS_DEVICE_TABLE_SUPPORTS_EXTENDED_ATTRIBUTES=y +# BR2_ROOTFS_MERGED_USR is not set +BR2_TARGET_ENABLE_ROOT_LOGIN=y +BR2_TARGET_GENERIC_ROOT_PASSWD="" +BR2_SYSTEM_BIN_SH_BUSYBOX=y + +# +# bash, dash, mksh, zsh need BR2_PACKAGE_BUSYBOX_SHOW_OTHERS +# +# BR2_SYSTEM_BIN_SH_NONE is not set +BR2_TARGET_GENERIC_GETTY=y +BR2_TARGET_GENERIC_GETTY_PORT="console" +BR2_TARGET_GENERIC_GETTY_BAUDRATE_KEEP=y +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_9600 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_19200 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_38400 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_57600 is not set +# BR2_TARGET_GENERIC_GETTY_BAUDRATE_115200 is not set +BR2_TARGET_GENERIC_GETTY_BAUDRATE="0" +BR2_TARGET_GENERIC_GETTY_TERM="vt100" +BR2_TARGET_GENERIC_GETTY_OPTIONS="" +BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y +BR2_SYSTEM_DHCP="eth0" +BR2_SYSTEM_DEFAULT_PATH="/bin:/sbin:/usr/bin:/usr/sbin" +BR2_ENABLE_LOCALE_PURGE=y +BR2_ENABLE_LOCALE_WHITELIST="C en_US" +BR2_GENERATE_LOCALE="" +# BR2_SYSTEM_ENABLE_NLS is not set +# BR2_TARGET_TZ_INFO is not set +BR2_ROOTFS_USERS_TABLES="" +BR2_ROOTFS_OVERLAY="./board/wally/rootfs_overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="" +BR2_ROOTFS_POST_FAKEROOT_SCRIPT="" +BR2_ROOTFS_POST_IMAGE_SCRIPT="" + +# +# Kernel +# +BR2_LINUX_KERNEL=y +# BR2_LINUX_KERNEL_LATEST_VERSION is not set +# BR2_LINUX_KERNEL_LATEST_CIP_VERSION is not set +# BR2_LINUX_KERNEL_LATEST_CIP_RT_VERSION is not set +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +# BR2_LINUX_KERNEL_CUSTOM_TARBALL is not set +# BR2_LINUX_KERNEL_CUSTOM_GIT is not set +# BR2_LINUX_KERNEL_CUSTOM_HG is not set +# BR2_LINUX_KERNEL_CUSTOM_SVN is not set +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.7" +BR2_LINUX_KERNEL_VERSION="5.10.7" +BR2_LINUX_KERNEL_PATCH="" +# BR2_LINUX_KERNEL_USE_DEFCONFIG is not set +# BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="./board/wally/linux.config" +BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="" +BR2_LINUX_KERNEL_CUSTOM_LOGO_PATH="" +BR2_LINUX_KERNEL_IMAGE=y +# BR2_LINUX_KERNEL_IMAGEGZ is not set +# BR2_LINUX_KERNEL_VMLINUX is not set +# BR2_LINUX_KERNEL_IMAGE_TARGET_CUSTOM is not set +BR2_LINUX_KERNEL_GZIP=y +# BR2_LINUX_KERNEL_LZ4 is not set +# BR2_LINUX_KERNEL_LZMA is not set +# BR2_LINUX_KERNEL_LZO is not set +# BR2_LINUX_KERNEL_XZ is not set +# BR2_LINUX_KERNEL_ZSTD is not set +# BR2_LINUX_KERNEL_DTS_SUPPORT is not set +# BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL is not set +# BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF is not set + +# +# Linux Kernel Extensions +# +# BR2_LINUX_KERNEL_EXT_RTAI is not set +# BR2_LINUX_KERNEL_EXT_EV3DEV_LINUX_DRIVERS is not set +# BR2_LINUX_KERNEL_EXT_FBTFT is not set +# BR2_LINUX_KERNEL_EXT_AUFS is not set + +# +# Linux Kernel Tools +# +# BR2_PACKAGE_LINUX_TOOLS_CPUPOWER is not set +# BR2_PACKAGE_LINUX_TOOLS_GPIO is not set +# BR2_PACKAGE_LINUX_TOOLS_IIO is not set +# BR2_PACKAGE_LINUX_TOOLS_PCI is not set +# BR2_PACKAGE_LINUX_TOOLS_PERF is not set + +# +# selftests needs BR2_PACKAGE_BUSYBOX_SHOW_OTHERS and a toolchain w/ dynamic library +# +# BR2_PACKAGE_LINUX_TOOLS_TMON is not set + +# +# Target packages +# +BR2_PACKAGE_BUSYBOX=y +BR2_PACKAGE_BUSYBOX_CONFIG="./board/wally/busybox.config" +BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="" +# BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set +# BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set +# BR2_PACKAGE_BUSYBOX_WATCHDOG is not set +BR2_PACKAGE_SKELETON=y +BR2_PACKAGE_HAS_SKELETON=y +BR2_PACKAGE_PROVIDES_SKELETON="skeleton-init-sysv" +BR2_PACKAGE_SKELETON_INIT_COMMON=y +BR2_PACKAGE_SKELETON_INIT_SYSV=y + +# +# Audio and video applications +# +# BR2_PACKAGE_ALSA_UTILS is not set +# BR2_PACKAGE_ATEST is not set +# BR2_PACKAGE_AUMIX is not set +# BR2_PACKAGE_BLUEZ_ALSA is not set +# BR2_PACKAGE_DVBLAST is not set +# BR2_PACKAGE_DVDAUTHOR is not set + +# +# dvdrw-tools needs a toolchain w/ threads, C++, wchar +# + +# +# espeak needs a toolchain w/ C++, wchar, threads, dynamic library +# +# BR2_PACKAGE_FAAD2 is not set +BR2_PACKAGE_FFMPEG_ARCH_SUPPORTS=y +# BR2_PACKAGE_FFMPEG is not set +# BR2_PACKAGE_FLAC is not set +# BR2_PACKAGE_FLITE is not set +# BR2_PACKAGE_FLUID_SOUNDFONT is not set +# BR2_PACKAGE_FLUIDSYNTH is not set +# BR2_PACKAGE_GMRENDER_RESURRECT is not set +# BR2_PACKAGE_GSTREAMER1 is not set +# BR2_PACKAGE_JACK1 is not set + +# +# jack2 needs a toolchain w/ threads, C++, dynamic library +# +BR2_PACKAGE_KODI_ARCH_SUPPORTS=y + +# +# kodi needs python3 w/ .py modules, a uClibc or glibc toolchain w/ C++, threads, wchar, dynamic library, gcc >= 4.9 +# + +# +# kodi needs an OpenGL EGL backend with OpenGL or GLES support +# +# BR2_PACKAGE_LAME is not set +# BR2_PACKAGE_MADPLAY is not set +# BR2_PACKAGE_MIMIC is not set +# BR2_PACKAGE_MINIMODEM is not set + +# +# miraclecast needs systemd and a glibc toolchain w/ threads and wchar +# + +# +# mjpegtools needs a toolchain w/ C++, threads +# + +# +# modplugtools needs a toolchain w/ C++ +# +# BR2_PACKAGE_MOTION is not set + +# +# mpd needs a toolchain w/ C++, threads, wchar, gcc >= 7, host gcc >= 7 +# +# BR2_PACKAGE_MPD_MPC is not set +# BR2_PACKAGE_MPG123 is not set + +# +# mpv needs a toolchain w/ C++, threads, gcc >= 4.9 +# +# BR2_PACKAGE_MULTICAT is not set +# BR2_PACKAGE_MUSEPACK is not set + +# +# ncmpc needs a toolchain w/ C++, wchar, threads, gcc >= 7 +# +# BR2_PACKAGE_OPUS_TOOLS is not set +BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y +# BR2_PACKAGE_PULSEAUDIO is not set +# BR2_PACKAGE_SOX is not set +# BR2_PACKAGE_SQUEEZELITE is not set + +# +# tovid needs a toolchain w/ threads, C++, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_TSTOOLS is not set +# BR2_PACKAGE_TWOLAME is not set +# BR2_PACKAGE_UDPXY is not set + +# +# upmpdcli needs a toolchain w/ C++, NPTL, gcc >= 4.9 +# + +# +# v4l2grab needs a toolchain w/ threads, dynamic library, C++ and headers >= 3.0 +# +# BR2_PACKAGE_V4L2LOOPBACK is not set + +# +# vlc needs a toolchain w/ C++, dynamic library, wchar, threads, gcc >= 4.9, headers >= 3.7 +# +# BR2_PACKAGE_VORBIS_TOOLS is not set +# BR2_PACKAGE_WAVPACK is not set +# BR2_PACKAGE_YAVTA is not set +# BR2_PACKAGE_YMPD is not set + +# +# Compressors and decompressors +# +# BR2_PACKAGE_BROTLI is not set +# BR2_PACKAGE_BZIP2 is not set + +# +# lrzip needs a toolchain w/ wchar, threads, C++ +# + +# +# lzip needs a toolchain w/ C++ +# +# BR2_PACKAGE_LZOP is not set + +# +# p7zip needs a toolchain w/ threads, wchar, C++ +# +# BR2_PACKAGE_PIGZ is not set +# BR2_PACKAGE_PIXZ is not set + +# +# unrar needs a toolchain w/ C++, wchar, threads +# +# BR2_PACKAGE_XZ is not set +# BR2_PACKAGE_ZIP is not set +# BR2_PACKAGE_ZSTD is not set + +# +# Debugging, profiling and benchmark +# +# BR2_PACKAGE_BABELTRACE2 is not set +# BR2_PACKAGE_BLKTRACE is not set + +# +# bonnie++ needs a toolchain w/ C++ +# +# BR2_PACKAGE_CACHE_CALIBRATOR is not set + +# +# clinfo needs an OpenCL provider +# +# BR2_PACKAGE_COREMARK is not set +# BR2_PACKAGE_COREMARK_PRO is not set + +# +# dacapo needs OpenJDK +# +# BR2_PACKAGE_DHRYSTONE is not set +# BR2_PACKAGE_DIEHARDER is not set +# BR2_PACKAGE_DMALLOC is not set +# BR2_PACKAGE_DROPWATCH is not set +# BR2_PACKAGE_DSTAT is not set +# BR2_PACKAGE_DT is not set + +# +# duma needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_FIO is not set +BR2_PACKAGE_GDB_ARCH_SUPPORTS=y + +# +# gdb/gdbserver >= 8.x needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_IOZONE is not set +# BR2_PACKAGE_KTAP is not set +# BR2_PACKAGE_LATENCYTOP is not set +# BR2_PACKAGE_LMBENCH is not set +BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y +# BR2_PACKAGE_LTP_TESTSUITE is not set +# BR2_PACKAGE_LTTNG_BABELTRACE is not set +# BR2_PACKAGE_LTTNG_MODULES is not set +# BR2_PACKAGE_LTTNG_TOOLS is not set +# BR2_PACKAGE_MEMSTAT is not set +# BR2_PACKAGE_NETPERF is not set +# BR2_PACKAGE_NETSNIFF_NG is not set +# BR2_PACKAGE_NMON is not set +# BR2_PACKAGE_PAX_UTILS is not set +# BR2_PACKAGE_PV is not set +# BR2_PACKAGE_RAMSMP is not set +# BR2_PACKAGE_RAMSPEED is not set +# BR2_PACKAGE_RT_TESTS is not set +# BR2_PACKAGE_SPIDEV_TEST is not set +# BR2_PACKAGE_STRACE is not set +# BR2_PACKAGE_STRESS is not set +# BR2_PACKAGE_STRESS_NG is not set + +# +# sysdig needs a glibc or uclibc toolchain w/ C++, threads, gcc >= 4.8, dynamic library, a Linux kernel, and luajit or lua 5.1 to be built +# +# BR2_PACKAGE_TINYMEMBENCH is not set +# BR2_PACKAGE_TRACE_CMD is not set +# BR2_PACKAGE_UCLIBC_NG_TEST is not set +# BR2_PACKAGE_VMTOUCH is not set +# BR2_PACKAGE_WHETSTONE is not set + +# +# Development tools +# +# BR2_PACKAGE_BINUTILS is not set +# BR2_PACKAGE_BITWISE is not set +# BR2_PACKAGE_BSDIFF is not set +# BR2_PACKAGE_CHECK is not set + +# +# cppunit needs a toolchain w/ C++, dynamic library +# +# BR2_PACKAGE_CUKINIA is not set +# BR2_PACKAGE_CUNIT is not set +# BR2_PACKAGE_CVS is not set + +# +# cxxtest needs a toolchain w/ C++ support +# +# BR2_PACKAGE_FLEX is not set +# BR2_PACKAGE_GETTEXT is not set +BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny" +# BR2_PACKAGE_GIT is not set + +# +# git-crypt needs a toolchain w/ C++, gcc >= 4.9 +# + +# +# gperf needs a toolchain w/ C++ +# +# BR2_PACKAGE_JO is not set +# BR2_PACKAGE_JQ is not set +# BR2_PACKAGE_LIBTOOL is not set +# BR2_PACKAGE_MAKE is not set +# BR2_PACKAGE_MAWK is not set +# BR2_PACKAGE_PKGCONF is not set +# BR2_PACKAGE_SUBVERSION is not set +# BR2_PACKAGE_TREE is not set + +# +# Filesystem and flash utilities +# +# BR2_PACKAGE_ABOOTIMG is not set +# BR2_PACKAGE_AUFS_UTIL is not set +# BR2_PACKAGE_AUTOFS is not set +# BR2_PACKAGE_BTRFS_PROGS is not set +# BR2_PACKAGE_CIFS_UTILS is not set +# BR2_PACKAGE_CPIO is not set +# BR2_PACKAGE_CRAMFS is not set +# BR2_PACKAGE_CURLFTPFS is not set +# BR2_PACKAGE_DAVFS2 is not set +# BR2_PACKAGE_DOSFSTOOLS is not set +# BR2_PACKAGE_E2FSPROGS is not set +# BR2_PACKAGE_E2TOOLS is not set +# BR2_PACKAGE_ECRYPTFS_UTILS is not set +# BR2_PACKAGE_EROFS_UTILS is not set +# BR2_PACKAGE_EXFAT is not set +# BR2_PACKAGE_EXFAT_UTILS is not set +# BR2_PACKAGE_EXFATPROGS is not set +# BR2_PACKAGE_F2FS_TOOLS is not set +# BR2_PACKAGE_FLASHBENCH is not set +# BR2_PACKAGE_FSCRYPTCTL is not set +# BR2_PACKAGE_FUSE_OVERLAYFS is not set +# BR2_PACKAGE_FWUP is not set +# BR2_PACKAGE_GENEXT2FS is not set +# BR2_PACKAGE_GENPART is not set +# BR2_PACKAGE_GENROMFS is not set +# BR2_PACKAGE_IMX_USB_LOADER is not set +# BR2_PACKAGE_MMC_UTILS is not set +# BR2_PACKAGE_MTD is not set +# BR2_PACKAGE_MTOOLS is not set +# BR2_PACKAGE_NFS_UTILS is not set +# BR2_PACKAGE_NILFS_UTILS is not set +# BR2_PACKAGE_NTFS_3G is not set +# BR2_PACKAGE_SP_OOPS_EXTRACT is not set +# BR2_PACKAGE_SQUASHFS is not set +# BR2_PACKAGE_SSHFS is not set +# BR2_PACKAGE_UDFTOOLS is not set +# BR2_PACKAGE_UNIONFS is not set +# BR2_PACKAGE_XFSPROGS is not set + +# +# zfs needs udev /dev management +# + +# +# Fonts, cursors, icons, sounds and themes +# + +# +# Cursors +# +# BR2_PACKAGE_COMIX_CURSORS is not set +# BR2_PACKAGE_OBSIDIAN_CURSORS is not set + +# +# Fonts +# +# BR2_PACKAGE_BITSTREAM_VERA is not set +# BR2_PACKAGE_CANTARELL is not set +# BR2_PACKAGE_DEJAVU is not set +# BR2_PACKAGE_FONT_AWESOME is not set +# BR2_PACKAGE_GHOSTSCRIPT_FONTS is not set +# BR2_PACKAGE_INCONSOLATA is not set +# BR2_PACKAGE_LIBERATION is not set +# BR2_PACKAGE_WQY_ZENHEI is not set + +# +# Icons +# +# BR2_PACKAGE_GOOGLE_MATERIAL_DESIGN_ICONS is not set +# BR2_PACKAGE_HICOLOR_ICON_THEME is not set + +# +# Sounds +# +# BR2_PACKAGE_SOUND_THEME_BOREALIS is not set +# BR2_PACKAGE_SOUND_THEME_FREEDESKTOP is not set + +# +# Themes +# + +# +# Games +# +# BR2_PACKAGE_ASCII_INVADERS is not set +# BR2_PACKAGE_CHOCOLATE_DOOM is not set + +# +# flare-engine needs a toolchain w/ C++, dynamic library +# +# BR2_PACKAGE_FROTZ is not set + +# +# gnuchess needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LBREAKOUT2 is not set +# BR2_PACKAGE_LTRIS is not set +# BR2_PACKAGE_OPENTYRIAN is not set +# BR2_PACKAGE_PRBOOM is not set +# BR2_PACKAGE_SL is not set + +# +# solarus needs OpenGL and a toolchain w/ C++, gcc >= 4.9, NPTL, dynamic library, and luajit or lua 5.1 +# + +# +# stella needs a toolchain w/ dynamic library, C++, threads, gcc >= 6 +# +# BR2_PACKAGE_XORCURSES is not set + +# +# Graphic libraries and applications (graphic/text) +# + +# +# Graphic applications +# + +# +# cage needs udev, EGL w/ Wayland backend and OpenGL ES support +# + +# +# cog needs wpewebkit and a toolchain w/ threads +# +# BR2_PACKAGE_FSWEBCAM is not set +# BR2_PACKAGE_GHOSTSCRIPT is not set + +# +# glmark2 needs a toolchain w/ C++, gcc >= 4.9 +# + +# +# glslsandbox-player needs a toolchain w/ threads and an openGL ES and EGL driver +# +# BR2_PACKAGE_GNUPLOT is not set +# BR2_PACKAGE_JHEAD is not set + +# +# libva-utils needs a toolchain w/ C++, threads, dynamic library +# +BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y +# BR2_PACKAGE_NETSURF is not set +# BR2_PACKAGE_PNGQUANT is not set +# BR2_PACKAGE_RRDTOOL is not set + +# +# stellarium needs Qt5 and an OpenGL provider +# + +# +# tesseract-ocr needs a toolchain w/ threads, C++, gcc >= 4.8, dynamic library, wchar +# + +# +# Graphic libraries +# + +# +# cegui needs a toolchain w/ C++, threads, dynamic library, wchar +# + +# +# directfb needs a glibc or uClibc toolchain w/ C++, NPTL, gcc >= 4.5, dynamic library +# + +# +# efl needs a toolchain w/ C++, dynamic library, gcc >= 4.9, host gcc >= 4.9, threads, wchar +# +# BR2_PACKAGE_FB_TEST_APP is not set +# BR2_PACKAGE_FBDUMP is not set +# BR2_PACKAGE_FBGRAB is not set + +# +# fbterm needs a toolchain w/ C++, wchar, locale +# +# BR2_PACKAGE_FBV is not set + +# +# freerdp needs a toolchain w/ wchar, dynamic library, threads, C++ +# +# BR2_PACKAGE_GRAPHICSMAGICK is not set +# BR2_PACKAGE_IMAGEMAGICK is not set +# BR2_PACKAGE_LINUX_FUSION is not set + +# +# mesa3d needs a toolchain w/ C++, NPTL, dynamic library +# + +# +# ocrad needs a toolchain w/ C++ +# + +# +# ogre needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads, wchar +# +# BR2_PACKAGE_PSPLASH is not set +# BR2_PACKAGE_SDL is not set +# BR2_PACKAGE_SDL2 is not set + +# +# Other GUIs +# + +# +# Qt5 needs host g++ >= 5.0, and a toolchain w/ gcc >= 5.0, wchar, NPTL, C++, dynamic library +# + +# +# tekui needs a Lua interpreter and a toolchain w/ threads, dynamic library +# + +# +# weston needs udev and a toolchain w/ locale, threads, dynamic library, headers >= 3.0 +# +# BR2_PACKAGE_XORG7 is not set + +# +# apitrace needs a toolchain w/ C++, wchar, dynamic library, threads, gcc >= 4.9 +# + +# +# vte needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# + +# +# vte needs an OpenGL or an OpenGL-EGL/wayland backend +# +# BR2_PACKAGE_XKEYBOARD_CONFIG is not set + +# +# Hardware handling +# + +# +# Firmware +# +# BR2_PACKAGE_ARMBIAN_FIRMWARE is not set +# BR2_PACKAGE_B43_FIRMWARE is not set +# BR2_PACKAGE_LINUX_FIRMWARE is not set +# BR2_PACKAGE_MURATA_CYW_FW is not set +# BR2_PACKAGE_ODROIDC2_FIRMWARE is not set +# BR2_PACKAGE_QCOM_DB410C_FIRMWARE is not set +# BR2_PACKAGE_RCW_SMARC_SAL28 is not set +# BR2_PACKAGE_UX500_FIRMWARE is not set +# BR2_PACKAGE_WILC1000_FIRMWARE is not set +# BR2_PACKAGE_WILINK_BT_FIRMWARE is not set +# BR2_PACKAGE_ZD1211_FIRMWARE is not set +# BR2_PACKAGE_18XX_TI_UTILS is not set +# BR2_PACKAGE_ACPICA is not set +# BR2_PACKAGE_ACPID is not set + +# +# acpitool needs a toolchain w/ threads, C++, dynamic library +# +# BR2_PACKAGE_AER_INJECT is not set +# BR2_PACKAGE_ALTERA_STAPL is not set + +# +# apcupsd needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_AVRDUDE is not set + +# +# bcache-tools needs udev /dev management +# + +# +# brickd needs udev /dev management, a toolchain w/ threads, wchar +# +# BR2_PACKAGE_BRLTTY is not set + +# +# cc-tool needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_CDRKIT is not set +# BR2_PACKAGE_CRYPTSETUP is not set +# BR2_PACKAGE_CWIID is not set +# BR2_PACKAGE_DAHDI_LINUX is not set +# BR2_PACKAGE_DAHDI_TOOLS is not set +# BR2_PACKAGE_DBUS is not set +# BR2_PACKAGE_DFU_UTIL is not set +# BR2_PACKAGE_DMRAID is not set + +# +# dt-utils needs udev /dev management +# +# BR2_PACKAGE_DTV_SCAN_TABLES is not set +# BR2_PACKAGE_DUMP1090 is not set +# BR2_PACKAGE_DVB_APPS is not set +# BR2_PACKAGE_DVBSNOOP is not set + +# +# eudev needs eudev /dev management +# +# BR2_PACKAGE_EVEMU is not set +# BR2_PACKAGE_EVTEST is not set +# BR2_PACKAGE_FAN_CTRL is not set +# BR2_PACKAGE_FCONFIG is not set +BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y +# BR2_PACKAGE_FLASHROM is not set +# BR2_PACKAGE_FMTOOLS is not set +BR2_PACKAGE_FPGA_AXI_SDC=y +# BR2_PACKAGE_FXLOAD is not set +# BR2_PACKAGE_GPM is not set +# BR2_PACKAGE_GPSD is not set + +# +# gptfdisk needs a toolchain w/ C++ +# +# BR2_PACKAGE_GVFS is not set +# BR2_PACKAGE_HWDATA is not set +# BR2_PACKAGE_HWLOC is not set +# BR2_PACKAGE_INPUT_EVENT_DAEMON is not set +# BR2_PACKAGE_IPMITOOL is not set +# BR2_PACKAGE_IRDA_UTILS is not set +# BR2_PACKAGE_KBD is not set +# BR2_PACKAGE_LCDPROC is not set + +# +# libiec61850 needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_LIBUBOOTENV is not set +# BR2_PACKAGE_LIBUIO is not set +# BR2_PACKAGE_LINUX_BACKPORTS is not set +# BR2_PACKAGE_LINUX_SERIAL_TEST is not set +# BR2_PACKAGE_LINUXCONSOLETOOLS is not set + +# +# lirc-tools needs a toolchain w/ threads, dynamic library, C++ +# +# BR2_PACKAGE_LM_SENSORS is not set + +# +# lshw needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LSSCSI is not set +# BR2_PACKAGE_LSUIO is not set +# BR2_PACKAGE_LUKSMETA is not set +# BR2_PACKAGE_LVM2 is not set +# BR2_PACKAGE_MBPFAN is not set +# BR2_PACKAGE_MDADM is not set +# BR2_PACKAGE_MDEVD is not set +# BR2_PACKAGE_MEMTESTER is not set +# BR2_PACKAGE_MEMTOOL is not set +# BR2_PACKAGE_MINICOM is not set +# BR2_PACKAGE_NANOCOM is not set +# BR2_PACKAGE_NEARD is not set +# BR2_PACKAGE_NVIDIA_MODPROBE is not set +# BR2_PACKAGE_NVME is not set +# BR2_PACKAGE_OFONO is not set +# BR2_PACKAGE_OPEN2300 is not set + +# +# openfpgaloader needs a toolchain w/ threads, C++, gcc >= 4.9 +# +# BR2_PACKAGE_OPENIPMI is not set +# BR2_PACKAGE_OPENOCD is not set +# BR2_PACKAGE_PARTED is not set +# BR2_PACKAGE_PCIUTILS is not set +# BR2_PACKAGE_PDBG is not set +# BR2_PACKAGE_PICOCOM is not set + +# +# powertop needs a toolchain w/ C++, threads, wchar +# +# BR2_PACKAGE_PPS_TOOLS is not set +# BR2_PACKAGE_RASPI_GPIO is not set +# BR2_PACKAGE_READ_EDID is not set +# BR2_PACKAGE_RNG_TOOLS is not set +# BR2_PACKAGE_RS485CONF is not set +# BR2_PACKAGE_RTC_TOOLS is not set +# BR2_PACKAGE_RTL8188EU is not set +# BR2_PACKAGE_RTL8189FS is not set +# BR2_PACKAGE_RTL8723BS is not set +# BR2_PACKAGE_RTL8723BU is not set +# BR2_PACKAGE_RTL8821AU is not set +# BR2_PACKAGE_SANE_BACKENDS is not set +# BR2_PACKAGE_SDPARM is not set +# BR2_PACKAGE_SETSERIAL is not set +# BR2_PACKAGE_SG3_UTILS is not set +# BR2_PACKAGE_SIGROK_CLI is not set +# BR2_PACKAGE_SISPMCTL is not set + +# +# smartmontools needs a toolchain w/ C++ +# +# BR2_PACKAGE_SMSTOOLS3 is not set +# BR2_PACKAGE_SPI_TOOLS is not set +# BR2_PACKAGE_SREDIRD is not set +# BR2_PACKAGE_STATSERIAL is not set +# BR2_PACKAGE_STM32FLASH is not set +# BR2_PACKAGE_SYSSTAT is not set + +# +# targetcli-fb depends on Python +# + +# +# ti-sgx-um needs the ti-sgx-km driver +# + +# +# ti-sgx-um needs udev and a glibc toolchain w/ threads +# +# BR2_PACKAGE_TI_UIM is not set +# BR2_PACKAGE_TI_UTILS is not set +# BR2_PACKAGE_TIO is not set +# BR2_PACKAGE_TRIGGERHAPPY is not set +# BR2_PACKAGE_UBOOT_TOOLS is not set +# BR2_PACKAGE_UBUS is not set +# BR2_PACKAGE_UCCP420WLAN is not set + +# +# udisks needs udev /dev management +# + +# +# udisks needs a glibc or musl toolchain with locale, C++, wchar, dynamic library, NPTL, gcc >= 4.9 +# +# BR2_PACKAGE_UHUBCTL is not set +# BR2_PACKAGE_UMTPRD is not set + +# +# upower needs udev /dev management +# +# BR2_PACKAGE_USB_MODESWITCH is not set +# BR2_PACKAGE_USB_MODESWITCH_DATA is not set + +# +# usbmount requires udev to be enabled +# + +# +# usbutils needs udev /dev management and toolchain w/ threads, gcc >= 4.9 +# +# BR2_PACKAGE_W_SCAN is not set +# BR2_PACKAGE_WIPE is not set +# BR2_PACKAGE_XORRISO is not set +# BR2_PACKAGE_XR819_XRADIO is not set + +# +# Interpreter languages and scripting +# +# BR2_PACKAGE_4TH is not set +# BR2_PACKAGE_ENSCRIPT is not set +BR2_PACKAGE_HOST_ERLANG_ARCH_SUPPORTS=y +# BR2_PACKAGE_EXECLINE is not set +# BR2_PACKAGE_FICL is not set +# BR2_PACKAGE_HASERL is not set +# BR2_PACKAGE_JANET is not set +# BR2_PACKAGE_JIMTCL is not set +# BR2_PACKAGE_LUA is not set +BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua" +# BR2_PACKAGE_MICROPYTHON is not set +BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y +# BR2_PACKAGE_PERL is not set +# BR2_PACKAGE_PHP is not set +# BR2_PACKAGE_PYTHON is not set +# BR2_PACKAGE_PYTHON3 is not set +# BR2_PACKAGE_QUICKJS is not set +# BR2_PACKAGE_RUBY is not set +# BR2_PACKAGE_TCL is not set + +# +# Libraries +# + +# +# Audio/Sound +# +# BR2_PACKAGE_ALSA_LIB is not set + +# +# alure needs a toolchain w/ C++, gcc >= 4.9, NPTL, wchar +# +# BR2_PACKAGE_AUBIO is not set +# BR2_PACKAGE_BCG729 is not set + +# +# caps needs a toolchain w/ C++, dynamic library +# +# BR2_PACKAGE_LIBAO is not set + +# +# asplib needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBBROADVOICE is not set +# BR2_PACKAGE_LIBCDAUDIO is not set +# BR2_PACKAGE_LIBCDDB is not set +# BR2_PACKAGE_LIBCDIO is not set +# BR2_PACKAGE_LIBCDIO_PARANOIA is not set +# BR2_PACKAGE_LIBCODEC2 is not set +# BR2_PACKAGE_LIBCUE is not set +# BR2_PACKAGE_LIBCUEFILE is not set +# BR2_PACKAGE_LIBEBUR128 is not set +# BR2_PACKAGE_LIBG7221 is not set +# BR2_PACKAGE_LIBGSM is not set +# BR2_PACKAGE_LIBID3TAG is not set +# BR2_PACKAGE_LIBILBC is not set +# BR2_PACKAGE_LIBLO is not set +# BR2_PACKAGE_LIBMAD is not set + +# +# libmodplug needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBMPD is not set +# BR2_PACKAGE_LIBMPDCLIENT is not set +# BR2_PACKAGE_LIBREPLAYGAIN is not set +# BR2_PACKAGE_LIBSAMPLERATE is not set + +# +# libsidplay2 needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBSILK is not set +# BR2_PACKAGE_LIBSNDFILE is not set + +# +# libsoundtouch needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBSOXR is not set +# BR2_PACKAGE_LIBVORBIS is not set + +# +# mp4v2 needs a toolchain w/ C++ +# +BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y + +# +# openal needs a toolchain w/ NPTL, C++, gcc >= 4.9 +# + +# +# opencore-amr needs a toolchain w/ C++ +# +# BR2_PACKAGE_OPUS is not set +# BR2_PACKAGE_OPUSFILE is not set +# BR2_PACKAGE_PORTAUDIO is not set +# BR2_PACKAGE_SBC is not set +# BR2_PACKAGE_SPANDSP is not set +# BR2_PACKAGE_SPEEX is not set +# BR2_PACKAGE_SPEEXDSP is not set + +# +# taglib needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_TINYALSA is not set +# BR2_PACKAGE_TREMOR is not set +# BR2_PACKAGE_VO_AACENC is not set + +# +# Compression and decompression +# +# BR2_PACKAGE_LIBARCHIVE is not set +# BR2_PACKAGE_LIBMSPACK is not set + +# +# libsquish needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBZIP is not set +# BR2_PACKAGE_LZ4 is not set +# BR2_PACKAGE_LZO is not set +# BR2_PACKAGE_MINIZIP is not set + +# +# snappy needs a toolchain w/ C++ +# +# BR2_PACKAGE_SZIP is not set +# BR2_PACKAGE_ZLIB is not set +BR2_PACKAGE_PROVIDES_HOST_ZLIB="host-libzlib" +# BR2_PACKAGE_ZZIPLIB is not set + +# +# Crypto +# +# BR2_PACKAGE_BEARSSL is not set +# BR2_PACKAGE_BEECRYPT is not set +BR2_PACKAGE_BOTAN_ARCH_SUPPORTS=y + +# +# botan needs a toolchain w/ C++, threads, gcc >= 4.8 +# +# BR2_PACKAGE_CA_CERTIFICATES is not set +# BR2_PACKAGE_CRYPTODEV is not set +# BR2_PACKAGE_GCR is not set +# BR2_PACKAGE_GNUTLS is not set +# BR2_PACKAGE_LIBARGON2 is not set +# BR2_PACKAGE_LIBASSUAN is not set +# BR2_PACKAGE_LIBGCRYPT is not set +BR2_PACKAGE_LIBGPG_ERROR_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBGPG_ERROR is not set +BR2_PACKAGE_LIBGPG_ERROR_SYSCFG="riscv64-unknown-linux-gnu" +# BR2_PACKAGE_LIBGPGME is not set +# BR2_PACKAGE_LIBKCAPI is not set +# BR2_PACKAGE_LIBKSBA is not set +# BR2_PACKAGE_LIBMCRYPT is not set +# BR2_PACKAGE_LIBMHASH is not set +# BR2_PACKAGE_LIBNSS is not set + +# +# libolm needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_LIBP11 is not set +# BR2_PACKAGE_LIBSCRYPT is not set +# BR2_PACKAGE_LIBSECRET is not set +# BR2_PACKAGE_LIBSHA1 is not set +# BR2_PACKAGE_LIBSODIUM is not set +# BR2_PACKAGE_LIBSSH is not set +# BR2_PACKAGE_LIBSSH2 is not set +# BR2_PACKAGE_LIBTOMCRYPT is not set +# BR2_PACKAGE_LIBUECC is not set +# BR2_PACKAGE_LIBXCRYPT is not set +# BR2_PACKAGE_MBEDTLS is not set +# BR2_PACKAGE_NETTLE is not set +# BR2_PACKAGE_OPENSSL is not set +BR2_PACKAGE_PROVIDES_HOST_OPENSSL="host-libopenssl" +# BR2_PACKAGE_PKCS11_HELPER is not set +# BR2_PACKAGE_RHASH is not set +# BR2_PACKAGE_TINYDTLS is not set +# BR2_PACKAGE_TPM2_PKCS11 is not set +# BR2_PACKAGE_TPM2_TSS is not set +# BR2_PACKAGE_TROUSERS is not set +# BR2_PACKAGE_USTREAM_SSL is not set +# BR2_PACKAGE_WOLFSSL is not set + +# +# Database +# +# BR2_PACKAGE_BERKELEYDB is not set +# BR2_PACKAGE_GDBM is not set +# BR2_PACKAGE_HIREDIS is not set + +# +# kompexsqlite needs a toolchain w/ C++, wchar, threads, dynamic library +# + +# +# leveldb needs a toolchain w/ C++, threads, gcc >= 4.8 +# +# BR2_PACKAGE_LIBGIT2 is not set +# BR2_PACKAGE_LIBMDBX is not set + +# +# libodb needs a toolchain w/ C++, threads +# + +# +# mysql needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_POSTGRESQL is not set +# BR2_PACKAGE_REDIS is not set +# BR2_PACKAGE_SQLCIPHER is not set +# BR2_PACKAGE_SQLITE is not set +# BR2_PACKAGE_UNIXODBC is not set + +# +# Filesystem +# +# BR2_PACKAGE_GAMIN is not set +# BR2_PACKAGE_LIBCONFIG is not set +# BR2_PACKAGE_LIBCONFUSE is not set +# BR2_PACKAGE_LIBFUSE is not set +# BR2_PACKAGE_LIBFUSE3 is not set +# BR2_PACKAGE_LIBLOCKFILE is not set +# BR2_PACKAGE_LIBNFS is not set +# BR2_PACKAGE_LIBSYSFS is not set +# BR2_PACKAGE_LOCKDEV is not set + +# +# physfs needs a toolchain w/ C++, threads +# + +# +# Graphics +# + +# +# assimp needs libzlib +# + +# +# at-spi2-atk depends on X.org +# + +# +# at-spi2-core depends on X.org +# +# BR2_PACKAGE_ATK is not set + +# +# atkmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# + +# +# bullet needs a toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_CAIRO is not set + +# +# cairomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.8 +# + +# +# chipmunk needs an OpenGL backend +# + +# +# exempi needs a toolchain w/ C++, dynamic library, threads, wchar +# + +# +# exiv2 needs a uClibc or glibc toolchain w/ C++, wchar, dynamic library, threads +# +# BR2_PACKAGE_FONTCONFIG is not set +# BR2_PACKAGE_FREETYPE is not set +# BR2_PACKAGE_GD is not set +# BR2_PACKAGE_GDK_PIXBUF is not set +# BR2_PACKAGE_GIFLIB is not set + +# +# granite needs libgtk3 and a toolchain w/ wchar, threads +# + +# +# graphite2 needs a toolchain w/ C++ +# + +# +# gtkmm3 needs libgtk3 and a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# + +# +# harfbuzz needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_IJS is not set +# BR2_PACKAGE_IMLIB2 is not set + +# +# irrlicht needs a toolchain w/ C++ +# +# BR2_PACKAGE_JASPER is not set +# BR2_PACKAGE_JBIG2DEC is not set +# BR2_PACKAGE_JPEG is not set + +# +# kms++ needs a toolchain w/ threads, C++, gcc >= 4.8, headers >= 4.11, wchar +# +# BR2_PACKAGE_LCMS2 is not set + +# +# lensfun needs a toolchain w/ C++, threads, wchar +# +# BR2_PACKAGE_LEPTONICA is not set +# BR2_PACKAGE_LIBART is not set +# BR2_PACKAGE_LIBDMTX is not set +# BR2_PACKAGE_LIBDRM is not set + +# +# libepoxy needs an OpenGL and/or OpenGL EGL backend +# +# BR2_PACKAGE_LIBEXIF is not set + +# +# libfm needs X.org and a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# +# BR2_PACKAGE_LIBFM_EXTRA is not set + +# +# libfreeglut depends on X.org and needs an OpenGL backend +# + +# +# libfreeimage needs a toolchain w/ C++, dynamic library, wchar +# + +# +# libgeotiff needs a toolchain w/ C++, gcc >= 4.7, threads, wchar +# + +# +# libglew depends on X.org and needs an OpenGL backend +# + +# +# libglfw depends on X.org and needs an OpenGL backend +# + +# +# libglu needs an OpenGL backend +# +# BR2_PACKAGE_LIBGTA is not set + +# +# libgtk3 needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# + +# +# libgtk3 needs an OpenGL or an OpenGL-EGL/wayland backend +# +# BR2_PACKAGE_LIBMEDIAART is not set +# BR2_PACKAGE_LIBMNG is not set +# BR2_PACKAGE_LIBPNG is not set +# BR2_PACKAGE_LIBQRENCODE is not set + +# +# libraw needs a toolchain w/ C++ +# + +# +# libsoil needs an OpenGL backend and a toolchain w/ dynamic library +# +# BR2_PACKAGE_LIBSVG is not set +# BR2_PACKAGE_LIBSVG_CAIRO is not set +# BR2_PACKAGE_LIBSVGTINY is not set +# BR2_PACKAGE_LIBVA is not set + +# +# libvips needs a toolchain w/ wchar, threads, C++ +# + +# +# libwpe needs a toolchain w/ C++, dynamic library and an OpenEGL-capable backend +# +# BR2_PACKAGE_MENU_CACHE is not set + +# +# opencv3 needs a toolchain w/ C++, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_OPENJPEG is not set + +# +# pango needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 +# + +# +# pangomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# +# BR2_PACKAGE_PIPEWIRE is not set +# BR2_PACKAGE_PIXMAN is not set + +# +# poppler needs a toolchain w/ wchar, C++, threads, dynamic library, gcc >= 5 +# +# BR2_PACKAGE_TIFF is not set +# BR2_PACKAGE_WAYLAND is not set +# BR2_PACKAGE_WEBP is not set + +# +# wlroots needs udev, EGL w/ Wayland backend and OpenGL ES support +# + +# +# woff2 needs a toolchain w/ C++ +# + +# +# wpebackend-fdo needs a toolchain w/ C++, wchar, threads, dynamic library and an OpenEGL-capable Wayland backend +# + +# +# zbar needs a toolchain w/ threads, C++ and headers >= 3.0 +# + +# +# zxing-cpp needs a toolchain w/ C++, dynamic library +# + +# +# Hardware handling +# +# BR2_PACKAGE_ACSCCID is not set +# BR2_PACKAGE_C_PERIPHERY is not set +# BR2_PACKAGE_CCID is not set +# BR2_PACKAGE_DTC is not set +# BR2_PACKAGE_HACKRF is not set + +# +# hidapi needs udev /dev management and a toolchain w/ NPTL, threads, gcc >= 4.9 +# +# BR2_PACKAGE_JITTERENTROPY_LIBRARY is not set + +# +# lcdapi needs a toolchain w/ C++, threads +# + +# +# let-me-create needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_LIBAIO is not set + +# +# libatasmart requires udev to be enabled +# + +# +# libblockdev needs udev /dev management and a toolchain w/ wchar, threads, dynamic library +# + +# +# libcec needs a toolchain w/ C++, wchar, threads, dynamic library, gcc >= 4.7 +# +# BR2_PACKAGE_LIBFREEFARE is not set +# BR2_PACKAGE_LIBFTDI is not set +# BR2_PACKAGE_LIBFTDI1 is not set +# BR2_PACKAGE_LIBGPHOTO2 is not set +# BR2_PACKAGE_LIBGPIOD is not set + +# +# libgudev needs udev /dev handling and a toolchain w/ wchar, threads +# +# BR2_PACKAGE_LIBHID is not set +# BR2_PACKAGE_LIBIIO is not set + +# +# libinput needs udev /dev management +# +# BR2_PACKAGE_LIBIQRF is not set +# BR2_PACKAGE_LIBLLCP is not set +# BR2_PACKAGE_LIBMBIM is not set +# BR2_PACKAGE_LIBNFC is not set +# BR2_PACKAGE_LIBPCIACCESS is not set +# BR2_PACKAGE_LIBPHIDGET is not set +# BR2_PACKAGE_LIBPRI is not set +# BR2_PACKAGE_LIBQMI is not set +# BR2_PACKAGE_LIBQRTR_GLIB is not set +# BR2_PACKAGE_LIBRAW1394 is not set +# BR2_PACKAGE_LIBRTLSDR is not set + +# +# libserial needs a toolchain w/ C++, gcc >= 5, threads, wchar +# +# BR2_PACKAGE_LIBSERIALPORT is not set +# BR2_PACKAGE_LIBSIGROK is not set +# BR2_PACKAGE_LIBSIGROKDECODE is not set +# BR2_PACKAGE_LIBSOC is not set +# BR2_PACKAGE_LIBSS7 is not set +# BR2_PACKAGE_LIBUSB is not set +# BR2_PACKAGE_LIBUSBGX is not set + +# +# libv4l needs a toolchain w/ threads, C++ and headers >= 3.0 +# +# BR2_PACKAGE_LIBXKBCOMMON is not set +# BR2_PACKAGE_MTDEV is not set +# BR2_PACKAGE_NEARDAL is not set +# BR2_PACKAGE_OWFS is not set +# BR2_PACKAGE_PCSC_LITE is not set +# BR2_PACKAGE_TSLIB is not set + +# +# uhd needs a toolchain w/ C++, NPTL, wchar, dynamic library +# + +# +# urg needs a toolchain w/ C++ +# + +# +# Javascript +# +# BR2_PACKAGE_ANGULARJS is not set +# BR2_PACKAGE_BOOTSTRAP is not set +# BR2_PACKAGE_CHARTJS is not set +# BR2_PACKAGE_DATATABLES is not set +# BR2_PACKAGE_DUKTAPE is not set +# BR2_PACKAGE_EXPLORERCANVAS is not set +# BR2_PACKAGE_FLOT is not set +# BR2_PACKAGE_JQUERY is not set +# BR2_PACKAGE_JSMIN is not set +# BR2_PACKAGE_JSON_JAVASCRIPT is not set +# BR2_PACKAGE_JSZIP is not set +# BR2_PACKAGE_OPENLAYERS is not set +# BR2_PACKAGE_POPPERJS is not set +BR2_PACKAGE_SPIDERMONKEY_ARCH_SUPPORTS=y + +# +# spidermonkey needs a glibc or musl toolchain with C++, wchar, dynamic library, NPTL, gcc >= 4.9 +# +# BR2_PACKAGE_VUEJS is not set + +# +# JSON/XML +# + +# +# benejson needs a toolchain w/ C++ +# +# BR2_PACKAGE_CJSON is not set +# BR2_PACKAGE_EXPAT is not set +# BR2_PACKAGE_JANSSON is not set +# BR2_PACKAGE_JOSE is not set +# BR2_PACKAGE_JSMN is not set +# BR2_PACKAGE_JSON_C is not set + +# +# json-for-modern-cpp needs a toolchain w/ C++, gcc >= 4.9 +# +# BR2_PACKAGE_JSON_GLIB is not set + +# +# jsoncpp needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_LIBBSON is not set +# BR2_PACKAGE_LIBFASTJSON is not set + +# +# libjson needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBROXML is not set +# BR2_PACKAGE_LIBUCL is not set +# BR2_PACKAGE_LIBXML2 is not set + +# +# libxml++ needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# +# BR2_PACKAGE_LIBXMLRPC is not set +# BR2_PACKAGE_LIBXSLT is not set +# BR2_PACKAGE_LIBYAML is not set +# BR2_PACKAGE_MXML is not set + +# +# pugixml needs a toolchain w/ C++ +# + +# +# rapidjson needs a toolchain w/ C++ +# +# BR2_PACKAGE_RAPIDXML is not set +# BR2_PACKAGE_RAPTOR is not set + +# +# tinyxml needs a toolchain w/ C++ +# + +# +# tinyxml2 needs a toolchain w/ C++ +# + +# +# valijson needs a toolchain w/ C++, threads, wchar support +# + +# +# xerces-c++ needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_YAJL is not set + +# +# yaml-cpp needs a toolchain w/ C++, gcc >= 4.7 +# + +# +# Logging +# + +# +# glog needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBLOG4C_LOCALTIME is not set +# BR2_PACKAGE_LIBLOGGING is not set + +# +# log4cplus needs a toolchain w/ C++, wchar, threads, gcc >= 4.8 +# + +# +# log4cpp needs a toolchain w/ C++, threads +# + +# +# log4cxx needs a toolchain w/ C++, threads, dynamic library +# + +# +# log4qt needs qt5 +# + +# +# opentracing-cpp needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 +# + +# +# spdlog needs a toolchain w/ C++, threads, wchar +# +# BR2_PACKAGE_ZLOG is not set + +# +# Multimedia +# +# BR2_PACKAGE_BITSTREAM is not set +# BR2_PACKAGE_DAV1D is not set + +# +# kvazaar needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBAACS is not set + +# +# libass needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_LIBBDPLUS is not set +# BR2_PACKAGE_LIBBLURAY is not set +BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y + +# +# libcamera needs a toolchain w/ C++, threads, wchar, dynamic library, gcc >= 7 +# +# BR2_PACKAGE_LIBDCADEC is not set +# BR2_PACKAGE_LIBDVBCSA is not set +# BR2_PACKAGE_LIBDVBPSI is not set + +# +# libdvbsi++ needs a toolchain w/ C++, wchar, threads +# +# BR2_PACKAGE_LIBDVDCSS is not set +# BR2_PACKAGE_LIBDVDNAV is not set +# BR2_PACKAGE_LIBDVDREAD is not set + +# +# libebml needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LIBHDHOMERUN is not set + +# +# libmatroska needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LIBMMS is not set +# BR2_PACKAGE_LIBMPEG2 is not set +# BR2_PACKAGE_LIBOGG is not set +# BR2_PACKAGE_LIBOPUSENC is not set +# BR2_PACKAGE_LIBTHEORA is not set +# BR2_PACKAGE_LIBUDFREAD is not set +# BR2_PACKAGE_LIBVPX is not set + +# +# libyuv needs a toolchain w/ C++, dynamic library +# + +# +# live555 needs a toolchain w/ C++ +# + +# +# mediastreamer needs a toolchain w/ threads, C++, dynamic library, gcc >= 5 +# +# BR2_PACKAGE_X264 is not set + +# +# x265 needs a toolchain w/ C++, threads, dynamic library +# + +# +# Networking +# + +# +# agent++ needs a toolchain w/ threads, C++, dynamic library +# + +# +# azmq needs a toolchain w/ C++11, wchar and NPTL +# + +# +# azure-iot-sdk-c needs a toolchain w/ C++, NPTL and wchar +# +# BR2_PACKAGE_BATMAN_ADV is not set + +# +# belle-sip needs a toolchain w/ threads, C++, dynamic library, wchar +# +# BR2_PACKAGE_C_ARES is not set +# BR2_PACKAGE_CGIC is not set + +# +# cppzmq needs a toolchain w/ C++, threads +# + +# +# curlpp needs a toolchain w/ C++, dynamic library +# + +# +# czmq needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_DAQ is not set +# BR2_PACKAGE_DAVICI is not set +# BR2_PACKAGE_ENET is not set + +# +# filemq needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_FLICKCURL is not set +# BR2_PACKAGE_FREERADIUS_CLIENT is not set +# BR2_PACKAGE_GENSIO is not set +# BR2_PACKAGE_GEOIP is not set +# BR2_PACKAGE_GLIB_NETWORKING is not set + +# +# grpc needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.9, host gcc >= 4.9 +# +# BR2_PACKAGE_GSSDP is not set +# BR2_PACKAGE_GUPNP is not set +# BR2_PACKAGE_GUPNP_AV is not set +# BR2_PACKAGE_GUPNP_DLNA is not set + +# +# ibrcommon needs a toolchain w/ C++, threads +# + +# +# ibrdtn needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBCGI is not set + +# +# libcgicc needs a toolchain w/ C++ +# +# BR2_PACKAGE_LIBCOAP is not set + +# +# libcpprestsdk needs a toolchain w/ NPTL, C++, wchar, locale +# +# BR2_PACKAGE_LIBCURL is not set +# BR2_PACKAGE_LIBDNET is not set +# BR2_PACKAGE_LIBEXOSIP2 is not set +# BR2_PACKAGE_LIBFCGI is not set +# BR2_PACKAGE_LIBGSASL is not set +# BR2_PACKAGE_LIBHTP is not set +# BR2_PACKAGE_LIBHTTPPARSER is not set + +# +# libhttpserver needs a toolchain w/ C++, threads, gcc >= 5 +# +# BR2_PACKAGE_LIBIDN is not set +# BR2_PACKAGE_LIBIDN2 is not set +# BR2_PACKAGE_LIBISCSI is not set +# BR2_PACKAGE_LIBKRB5 is not set +# BR2_PACKAGE_LIBLDNS is not set +# BR2_PACKAGE_LIBMAXMINDDB is not set +# BR2_PACKAGE_LIBMBUS is not set + +# +# libmemcached needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBMICROHTTPD is not set +# BR2_PACKAGE_LIBMINIUPNPC is not set +# BR2_PACKAGE_LIBMNL is not set +# BR2_PACKAGE_LIBMODBUS is not set + +# +# libmodsecurity needs a toolchain w/ C++, dynamic library, threads +# +# BR2_PACKAGE_LIBNATPMP is not set +# BR2_PACKAGE_LIBNDP is not set +# BR2_PACKAGE_LIBNET is not set +# BR2_PACKAGE_LIBNETCONF2 is not set +# BR2_PACKAGE_LIBNETFILTER_ACCT is not set +# BR2_PACKAGE_LIBNETFILTER_CONNTRACK is not set +# BR2_PACKAGE_LIBNETFILTER_CTHELPER is not set +# BR2_PACKAGE_LIBNETFILTER_CTTIMEOUT is not set +# BR2_PACKAGE_LIBNETFILTER_LOG is not set +# BR2_PACKAGE_LIBNETFILTER_QUEUE is not set +# BR2_PACKAGE_LIBNFNETLINK is not set +# BR2_PACKAGE_LIBNFTNL is not set +# BR2_PACKAGE_LIBNICE is not set +# BR2_PACKAGE_LIBNIDS is not set +# BR2_PACKAGE_LIBNL is not set + +# +# libnpupnp needs a toolchain w/ C++, threads, gcc >= 4.9 +# +# BR2_PACKAGE_LIBOAUTH is not set +# BR2_PACKAGE_LIBOPING is not set +# BR2_PACKAGE_LIBOSIP2 is not set +# BR2_PACKAGE_LIBPAGEKITE is not set +# BR2_PACKAGE_LIBPCAP is not set + +# +# libpjsip needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBRELP is not set +# BR2_PACKAGE_LIBRSYNC is not set +# BR2_PACKAGE_LIBSHAIRPLAY is not set +# BR2_PACKAGE_LIBSHOUT is not set +# BR2_PACKAGE_LIBSOCKETCAN is not set +# BR2_PACKAGE_LIBSOUP is not set +# BR2_PACKAGE_LIBSRTP is not set +# BR2_PACKAGE_LIBSTROPHE is not set +# BR2_PACKAGE_LIBTELNET is not set +# BR2_PACKAGE_LIBTIRPC is not set + +# +# libtorrent needs a toolchain w/ C++, threads +# + +# +# libtorrent-rasterbar needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_LIBUEV is not set +# BR2_PACKAGE_LIBUHTTPD is not set +# BR2_PACKAGE_LIBUPNP is not set + +# +# libupnpp needs a toolchain w/ C++, threads, gcc >= 4.9 +# +# BR2_PACKAGE_LIBURIPARSER is not set +# BR2_PACKAGE_LIBUWSC is not set +# BR2_PACKAGE_LIBVNCSERVER is not set +# BR2_PACKAGE_LIBWEBSOCK is not set +# BR2_PACKAGE_LIBWEBSOCKETS is not set +# BR2_PACKAGE_LIBYANG is not set +# BR2_PACKAGE_LKSCTP_TOOLS is not set +# BR2_PACKAGE_MBUFFER is not set +# BR2_PACKAGE_MONGOOSE is not set +# BR2_PACKAGE_NANOMSG is not set +# BR2_PACKAGE_NEON is not set + +# +# netopeer2 needs a toolchain w/ gcc >= 4.8, C++, threads, dynamic library +# +# BR2_PACKAGE_NGHTTP2 is not set + +# +# norm needs a toolchain w/ C++, threads, dynamic library +# +# BR2_PACKAGE_NSS_MYHOSTNAME is not set +# BR2_PACKAGE_NSS_PAM_LDAPD is not set + +# +# omniORB needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_OPEN62541 is not set +# BR2_PACKAGE_OPENLDAP is not set + +# +# openmpi needs a toolchain w/ dynamic library, NPTL, wchar, C++ +# +# BR2_PACKAGE_OPENPGM is not set + +# +# openzwave needs a toolchain w/ C++, dynamic library, NPTL, wchar +# + +# +# ortp needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_PAHO_MQTT_C is not set + +# +# paho-mqtt-cpp needs a toolchain w/ threads, C++ +# + +# +# pistache needs a glibc toolchain w/ C++, gcc >= 4.9, threads, wchar +# +# BR2_PACKAGE_QDECODER is not set +# BR2_PACKAGE_QPID_PROTON is not set +# BR2_PACKAGE_RABBITMQ_C is not set + +# +# resiprocate needs a toolchain w/ C++, threads, wchar +# + +# +# restclient-cpp needs a toolchain w/ C++, gcc >= 4.8 +# +# BR2_PACKAGE_RTMPDUMP is not set +# BR2_PACKAGE_SIPROXD is not set +# BR2_PACKAGE_SLIRP is not set + +# +# snmp++ needs a toolchain w/ threads, C++, dynamic library +# +# BR2_PACKAGE_SOFIA_SIP is not set + +# +# sysrepo needs a toolchain w/ C++, NPTL, dynamic library, gcc >= 4.8 +# + +# +# thrift needs a toolchain w/ C++, wchar, threads +# +# BR2_PACKAGE_USBREDIR is not set + +# +# wampcc needs a toolchain w/ C++, NPTL, dynamic library +# + +# +# websocketpp needs a toolchain w/ C++ and gcc >= 4.8 +# + +# +# zeromq needs a toolchain w/ C++, threads +# + +# +# zmqpp needs a toolchain w/ C++, threads, gcc >= 4.7 +# + +# +# zyre needs a toolchain w/ C++, threads +# + +# +# Other +# +# BR2_PACKAGE_APR is not set +# BR2_PACKAGE_APR_UTIL is not set + +# +# armadillo needs a toolchain w/ C++ +# + +# +# atf needs a toolchain w/ C++ +# +# BR2_PACKAGE_AVRO_C is not set + +# +# bctoolbox needs a toolchain w/ C++, threads +# + +# +# belr needs a toolchain w/ threads, C++ +# + +# +# boost needs a toolchain w/ C++, threads, wchar +# + +# +# c-capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735 +# + +# +# capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735 +# + +# +# cctz needs a toolchain w/ C++, threads, gcc >= 4.8 +# + +# +# cereal needs a toolchain w/ C++, gcc >= 4.7, threads, wchar +# +# BR2_PACKAGE_CLAPACK is not set +# BR2_PACKAGE_CMOCKA is not set + +# +# cppcms needs a toolchain w/ C++, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_CRACKLIB is not set + +# +# dawgdic needs a toolchain w/ C++, gcc >= 4.6 +# +# BR2_PACKAGE_DING_LIBS is not set + +# +# eigen needs a toolchain w/ C++ +# +# BR2_PACKAGE_ELFUTILS is not set +# BR2_PACKAGE_ELL is not set +# BR2_PACKAGE_FFTW is not set + +# +# flann needs a toolchain w/ C++, dynamic library +# + +# +# flatbuffers needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_FLATCC is not set +# BR2_PACKAGE_GCONF is not set + +# +# gflags needs a toolchain w/ C++ +# + +# +# gli needs a toolchain w/ C++ +# + +# +# glibmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 +# + +# +# glm needs a toolchain w/ C++ +# +# BR2_PACKAGE_GMP is not set +BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y + +# +# gobject-introspection needs python3 +# +# BR2_PACKAGE_GSL is not set + +# +# gtest needs a toolchain w/ C++, wchar, threads +# +BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y +# BR2_PACKAGE_JEMALLOC is not set + +# +# lapack/blas needs a toolchain w/ fortran +# +BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y + +# +# libabseil-cpp needs a toolchain w/ gcc >= 4.9, C++, threads, dynamic library +# +# BR2_PACKAGE_LIBARGTABLE2 is not set +# BR2_PACKAGE_LIBAVL is not set +# BR2_PACKAGE_LIBB64 is not set +# BR2_PACKAGE_LIBBACKTRACE is not set +BR2_PACKAGE_LIBBSD_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBBSD is not set +# BR2_PACKAGE_LIBBYTESIZE is not set +# BR2_PACKAGE_LIBCAP is not set +# BR2_PACKAGE_LIBCAP_NG is not set + +# +# libcgroup needs a glibc toolchain w/ C++ +# +# BR2_PACKAGE_LIBCORRECT is not set + +# +# libcrossguid needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_LIBCSV is not set +# BR2_PACKAGE_LIBDAEMON is not set +# BR2_PACKAGE_LIBEE is not set +# BR2_PACKAGE_LIBEV is not set +# BR2_PACKAGE_LIBEVDEV is not set +# BR2_PACKAGE_LIBEVENT is not set +# BR2_PACKAGE_LIBFFI is not set +# BR2_PACKAGE_LIBGEE is not set + +# +# libgeos needs a toolchain w/ C++, wchar, not binutils bug 21464, 27597 +# +# BR2_PACKAGE_LIBGLIB2 is not set +# BR2_PACKAGE_LIBGLOB is not set + +# +# libical needs a toolchain w/ C++, dynamic library, wchar +# +# BR2_PACKAGE_LIBITE is not set + +# +# liblinear needs a toolchain w/ C++ +# + +# +# libloki needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBNPTH is not set +BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y +# BR2_PACKAGE_LIBNSPR is not set +# BR2_PACKAGE_LIBPFM4 is not set + +# +# libplist needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_LIBPTHREAD_STUBS is not set +# BR2_PACKAGE_LIBPTHSEM is not set +# BR2_PACKAGE_LIBPWQUALITY is not set + +# +# libsigc++ needs a toolchain w/ C++, gcc >= 4.8 +# +BR2_PACKAGE_LIBSIGSEGV_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBSIGSEGV is not set + +# +# libspatialindex needs a toolchain w/ C++, gcc >= 4.7 +# +# BR2_PACKAGE_LIBTASN1 is not set +# BR2_PACKAGE_LIBTOMMATH is not set +# BR2_PACKAGE_LIBTPL is not set +# BR2_PACKAGE_LIBUBOX is not set +# BR2_PACKAGE_LIBUCI is not set +BR2_PACKAGE_LIBURCU_ARCH_SUPPORTS=y +# BR2_PACKAGE_LIBURCU is not set +# BR2_PACKAGE_LIBUV is not set +# BR2_PACKAGE_LIGHTNING is not set +# BR2_PACKAGE_LINUX_PAM is not set +# BR2_PACKAGE_LIQUID_DSP is not set +# BR2_PACKAGE_LTTNG_LIBUST is not set +# BR2_PACKAGE_MATIO is not set +# BR2_PACKAGE_MPC is not set +# BR2_PACKAGE_MPDECIMAL is not set +# BR2_PACKAGE_MPFR is not set +# BR2_PACKAGE_MPIR is not set + +# +# msgpack needs a toolchain w/ C++ +# +# BR2_PACKAGE_ORC is not set +# BR2_PACKAGE_P11_KIT is not set +BR2_PACKAGE_POCO_ARCH_SUPPORTS=y + +# +# poco needs a toolchain w/ wchar, NPTL, C++, dynamic library, gcc >= 5 w/ C++14 +# +BR2_PACKAGE_PROTOBUF_ARCH_SUPPORTS=y + +# +# protobuf needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 +# + +# +# protobuf-c needs a toolchain w/ C++, threads +# + +# +# protozero needs a toolchain w/ C++, gcc >= 4.7 +# + +# +# qhull needs a toolchain w/ C++, gcc >= 4.4 +# +# BR2_PACKAGE_QLIBC is not set + +# +# riemann-c-client needs a toolchain w/ C++, threads +# + +# +# shapelib needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_SKALIBS is not set +# BR2_PACKAGE_SPHINXBASE is not set +# BR2_PACKAGE_TINYCBOR is not set + +# +# uvw needs a toolchain w/ NPTL, dynamic library, C++, gcc >= 7 +# + +# +# xapian needs a toolchain w/ C++ +# + +# +# Security +# +# BR2_PACKAGE_LIBAPPARMOR is not set +# BR2_PACKAGE_LIBSELINUX is not set +# BR2_PACKAGE_LIBSEPOL is not set +# BR2_PACKAGE_SAFECLIB is not set + +# +# Text and terminal handling +# +# BR2_PACKAGE_AUGEAS is not set + +# +# enchant needs a toolchain w/ C++, threads, wchar +# + +# +# fmt needs a toolchain w/ C++, wchar +# +# BR2_PACKAGE_FSTRCMP is not set + +# +# icu needs a toolchain w/ C++, wchar, threads, gcc >= 4.9, host gcc >= 4.9 +# +# BR2_PACKAGE_INIH is not set +# BR2_PACKAGE_LIBCLI is not set +# BR2_PACKAGE_LIBEDIT is not set +# BR2_PACKAGE_LIBENCA is not set +# BR2_PACKAGE_LIBESTR is not set +# BR2_PACKAGE_LIBFRIBIDI is not set +# BR2_PACKAGE_LIBUNISTRING is not set +# BR2_PACKAGE_LINENOISE is not set +# BR2_PACKAGE_NCURSES is not set +# BR2_PACKAGE_NEWT is not set +# BR2_PACKAGE_ONIGURUMA is not set +# BR2_PACKAGE_PCRE is not set +# BR2_PACKAGE_PCRE2 is not set +# BR2_PACKAGE_POPT is not set + +# +# re2 needs a toolchain w/ C++, threads, gcc >= 4.8 +# +# BR2_PACKAGE_READLINE is not set +# BR2_PACKAGE_SLANG is not set + +# +# tclap needs a toolchain w/ C++ +# +# BR2_PACKAGE_UTF8PROC is not set + +# +# Mail +# +# BR2_PACKAGE_DOVECOT is not set +# BR2_PACKAGE_EXIM is not set +# BR2_PACKAGE_FETCHMAIL is not set +# BR2_PACKAGE_HEIRLOOM_MAILX is not set +# BR2_PACKAGE_LIBESMTP is not set +# BR2_PACKAGE_MSMTP is not set +# BR2_PACKAGE_MUTT is not set + +# +# Miscellaneous +# +# BR2_PACKAGE_AESPIPE is not set +# BR2_PACKAGE_BC is not set +BR2_PACKAGE_BITCOIN_ARCH_SUPPORTS=y + +# +# bitcoin needs a toolchain w/ C++, threads, wchar +# + +# +# clamav needs a toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_COLLECTD is not set +# BR2_PACKAGE_COLLECTL is not set + +# +# domoticz needs lua 5.3 and a toolchain w/ C++, gcc >= 6, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_EMPTY is not set + +# +# gnuradio needs a toolchain w/ C++, NPTL, wchar, dynamic library +# +# BR2_PACKAGE_GOOGLEFONTDIRECTORY is not set + +# +# gqrx needs a toolchain w/ C++, threads, wchar, dynamic library +# + +# +# gqrx needs qt5 +# +# BR2_PACKAGE_GSETTINGS_DESKTOP_SCHEMAS is not set +# BR2_PACKAGE_HAVEGED is not set +# BR2_PACKAGE_LINUX_SYSCALL_SUPPORT is not set +# BR2_PACKAGE_MCRYPT is not set +# BR2_PACKAGE_MOBILE_BROADBAND_PROVIDER_INFO is not set +# BR2_PACKAGE_NETDATA is not set + +# +# proj needs a toolchain w/ C++, gcc >= 4.7, threads, wchar +# + +# +# qpdf needs a toolchain w/ C++, wchar, gcc >= 4.7 +# +# BR2_PACKAGE_SHARED_MIME_INFO is not set + +# +# sunwait needs a toolchain w/ C++ +# + +# +# taskd needs a toolchain w/ C++, wchar, dynamic library +# +# BR2_PACKAGE_XUTIL_UTIL_MACROS is not set + +# +# Networking applications +# + +# +# aircrack-ng needs a toolchain w/ dynamic library, threads, C++ +# +# BR2_PACKAGE_AOETOOLS is not set +# BR2_PACKAGE_APACHE is not set +# BR2_PACKAGE_ARGUS is not set +# BR2_PACKAGE_ARP_SCAN is not set +# BR2_PACKAGE_ARPTABLES is not set + +# +# asterisk needs a glibc or uClibc toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_ATFTP is not set +# BR2_PACKAGE_AVAHI is not set +# BR2_PACKAGE_AXEL is not set +# BR2_PACKAGE_BABELD is not set +# BR2_PACKAGE_BANDWIDTHD is not set +# BR2_PACKAGE_BATCTL is not set + +# +# bcusdk needs a toolchain w/ C++ +# +# BR2_PACKAGE_BIND is not set +# BR2_PACKAGE_BIRD is not set +# BR2_PACKAGE_BLUEZ5_UTILS is not set +# BR2_PACKAGE_BMON is not set + +# +# boinc needs a toolchain w/ dynamic library, C++, threads +# +# BR2_PACKAGE_BRCM_PATCHRAM_PLUS is not set +# BR2_PACKAGE_BRIDGE_UTILS is not set +# BR2_PACKAGE_BWM_NG is not set +# BR2_PACKAGE_C_ICAP is not set +# BR2_PACKAGE_CAN_UTILS is not set + +# +# cannelloni needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 +# +# BR2_PACKAGE_CASYNC is not set +# BR2_PACKAGE_CHRONY is not set +# BR2_PACKAGE_CIVETWEB is not set +# BR2_PACKAGE_CONNMAN is not set + +# +# connman-gtk needs libgtk3 and a glibc or uClibc toolchain w/ wchar, threads, resolver, dynamic library +# +# BR2_PACKAGE_CONNTRACK_TOOLS is not set +# BR2_PACKAGE_CORKSCREW is not set +# BR2_PACKAGE_CRDA is not set + +# +# ctorrent needs a toolchain w/ C++ +# + +# +# cups needs a toolchain w/ C++, threads +# + +# +# cups-filters needs a toolchain w/ wchar, C++, threads and dynamic library, gcc >= 4.8 +# +# BR2_PACKAGE_DANTE is not set +# BR2_PACKAGE_DARKHTTPD is not set +# BR2_PACKAGE_DEHYDRATED is not set +# BR2_PACKAGE_DHCPCD is not set +# BR2_PACKAGE_DHCPDUMP is not set +# BR2_PACKAGE_DNSMASQ is not set +# BR2_PACKAGE_DRBD_UTILS is not set +# BR2_PACKAGE_DROPBEAR is not set +# BR2_PACKAGE_EASYFRAMES is not set +# BR2_PACKAGE_EBTABLES is not set + +# +# ejabberd needs erlang, toolchain w/ C++ +# +# BR2_PACKAGE_ETHTOOL is not set +# BR2_PACKAGE_FAIFA is not set +# BR2_PACKAGE_FASTD is not set +# BR2_PACKAGE_FCGIWRAP is not set +# BR2_PACKAGE_FPING is not set + +# +# freeswitch needs a toolchain w/ C++, dynamic library, threads, wchar +# +# BR2_PACKAGE_FRR is not set + +# +# gerbera needs a toolchain w/ C++, dynamic library, threads, wchar, gcc >= 8 +# +# BR2_PACKAGE_GESFTPSERVER is not set + +# +# gloox needs a toolchain w/ C++ +# +# BR2_PACKAGE_GLORYTUN is not set + +# +# gupnp-tools needs libgtk3 +# + +# +# hans needs a toolchain w/ C++ +# +BR2_PACKAGE_HAPROXY_ARCH_SUPPORTS=y +# BR2_PACKAGE_HAPROXY is not set +# BR2_PACKAGE_HIAWATHA is not set +# BR2_PACKAGE_HOSTAPD is not set +# BR2_PACKAGE_HTPDATE is not set +# BR2_PACKAGE_HTTPING is not set + +# +# i2pd needs a toolchain w/ C++, NPTL, wchar +# + +# +# ibrdtn-tools needs a toolchain w/ C++, threads +# + +# +# ibrdtnd needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_IFMETRIC is not set +# BR2_PACKAGE_IFTOP is not set +# BR2_PACKAGE_IFUPDOWN_SCRIPTS is not set +# BR2_PACKAGE_IGD2_FOR_LINUX is not set +# BR2_PACKAGE_IGH_ETHERCAT is not set +# BR2_PACKAGE_IGMPPROXY is not set +# BR2_PACKAGE_INADYN is not set +# BR2_PACKAGE_IODINE is not set + +# +# iperf needs a toolchain w/ C++ +# +# BR2_PACKAGE_IPERF3 is not set +# BR2_PACKAGE_IPROUTE2 is not set +# BR2_PACKAGE_IPSET is not set +# BR2_PACKAGE_IPTABLES is not set +# BR2_PACKAGE_IPTRAF_NG is not set +# BR2_PACKAGE_IPUTILS is not set +# BR2_PACKAGE_IRSSI is not set +# BR2_PACKAGE_IW is not set +# BR2_PACKAGE_IWD is not set +# BR2_PACKAGE_JANUS_GATEWAY is not set +# BR2_PACKAGE_KEEPALIVED is not set + +# +# kismet needs a toolchain w/ threads, C++ +# +# BR2_PACKAGE_KNOCK is not set +# BR2_PACKAGE_LEAFNODE2 is not set +# BR2_PACKAGE_LFT is not set + +# +# lftp requires a toolchain w/ C++, wchar +# +# BR2_PACKAGE_LIGHTTPD is not set + +# +# linknx needs a toolchain w/ C++ +# +# BR2_PACKAGE_LINKS is not set + +# +# linphone needs a toolchain w/ threads, C++, dynamic library, wchar, gcc >= 5 +# +# BR2_PACKAGE_LINUX_ZIGBEE is not set +# BR2_PACKAGE_LINUXPTP is not set +# BR2_PACKAGE_LLDPD is not set +# BR2_PACKAGE_LRZSZ is not set +# BR2_PACKAGE_LYNX is not set +# BR2_PACKAGE_MACCHANGER is not set +# BR2_PACKAGE_MEMCACHED is not set +# BR2_PACKAGE_MII_DIAG is not set +# BR2_PACKAGE_MINI_SNMPD is not set +# BR2_PACKAGE_MINIDLNA is not set +# BR2_PACKAGE_MINISSDPD is not set +# BR2_PACKAGE_MJPG_STREAMER is not set +# BR2_PACKAGE_MODEM_MANAGER is not set +BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y + +# +# mongrel2 needs a uClibc or glibc toolchain w/ C++, threads, dynamic library +# + +# +# mosh needs a toolchain w/ C++, threads, dynamic library, wchar, gcc >= 4.8 +# +# BR2_PACKAGE_MOSQUITTO is not set +# BR2_PACKAGE_MROUTED is not set +# BR2_PACKAGE_MRP is not set +# BR2_PACKAGE_MTR is not set +# BR2_PACKAGE_NBD is not set +# BR2_PACKAGE_NCFTP is not set +# BR2_PACKAGE_NDISC6 is not set +# BR2_PACKAGE_NETATALK is not set +# BR2_PACKAGE_NETCALC is not set +# BR2_PACKAGE_NETPLUG is not set +# BR2_PACKAGE_NETSNMP is not set +# BR2_PACKAGE_NETSTAT_NAT is not set + +# +# NetworkManager needs udev /dev management and a glibc toolchain w/ headers >= 3.2, dynamic library, wchar, threads +# +# BR2_PACKAGE_NFACCT is not set +# BR2_PACKAGE_NFTABLES is not set +# BR2_PACKAGE_NGINX is not set +# BR2_PACKAGE_NGIRCD is not set +# BR2_PACKAGE_NGREP is not set + +# +# nload needs a toolchain w/ C++ +# + +# +# nmap-nmap needs a toolchain w/ C++, threads +# +# BR2_PACKAGE_NOIP is not set +# BR2_PACKAGE_NTP is not set +# BR2_PACKAGE_NUTTCP is not set +# BR2_PACKAGE_ODHCP6C is not set +# BR2_PACKAGE_ODHCPLOC is not set +# BR2_PACKAGE_OLSR is not set +# BR2_PACKAGE_OPEN_LLDP is not set +# BR2_PACKAGE_OPEN_PLC_UTILS is not set +# BR2_PACKAGE_OPENNTPD is not set +# BR2_PACKAGE_OPENOBEX is not set +# BR2_PACKAGE_OPENRESOLV is not set +# BR2_PACKAGE_OPENSSH is not set +# BR2_PACKAGE_OPENSWAN is not set +# BR2_PACKAGE_OPENVPN is not set +# BR2_PACKAGE_P910ND is not set +# BR2_PACKAGE_PARPROUTED is not set +# BR2_PACKAGE_PHIDGETWEBSERVICE is not set +# BR2_PACKAGE_PHYTOOL is not set +# BR2_PACKAGE_PIMD is not set +# BR2_PACKAGE_PIXIEWPS is not set +# BR2_PACKAGE_POUND is not set +# BR2_PACKAGE_PPPD is not set +# BR2_PACKAGE_PPTP_LINUX is not set +# BR2_PACKAGE_PRIVOXY is not set +# BR2_PACKAGE_PROFTPD is not set + +# +# prosody needs the lua interpreter, dynamic library +# +# BR2_PACKAGE_PROXYCHAINS_NG is not set +# BR2_PACKAGE_PTPD is not set +# BR2_PACKAGE_PTPD2 is not set +# BR2_PACKAGE_PURE_FTPD is not set +# BR2_PACKAGE_PUTTY is not set +# BR2_PACKAGE_QUAGGA is not set + +# +# rabbitmq-server needs erlang +# +# BR2_PACKAGE_RADVD is not set +# BR2_PACKAGE_REAVER is not set +# BR2_PACKAGE_REDIR is not set +# BR2_PACKAGE_RP_PPPOE is not set +# BR2_PACKAGE_RPCBIND is not set +# BR2_PACKAGE_RSH_REDONE is not set +# BR2_PACKAGE_RSYNC is not set + +# +# rtorrent needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 +# +# BR2_PACKAGE_RTPTOOLS is not set +# BR2_PACKAGE_RYGEL is not set +# BR2_PACKAGE_S6_DNS is not set +# BR2_PACKAGE_S6_NETWORKING is not set +# BR2_PACKAGE_SAMBA4 is not set + +# +# sconeserver needs a toolchain with dynamic library, C++, NPTL +# +# BR2_PACKAGE_SER2NET is not set +# BR2_PACKAGE_SHADOWSOCKS_LIBEV is not set + +# +# shairport-sync needs a toolchain w/ C++, NPTL +# +# BR2_PACKAGE_SHELLINABOX is not set +# BR2_PACKAGE_SMCROUTE is not set +# BR2_PACKAGE_SNGREP is not set +# BR2_PACKAGE_SNORT is not set +# BR2_PACKAGE_SOCAT is not set +# BR2_PACKAGE_SOCKETCAND is not set +# BR2_PACKAGE_SOFTETHER is not set +# BR2_PACKAGE_SPAWN_FCGI is not set +# BR2_PACKAGE_SPICE_PROTOCOL is not set + +# +# squid needs a toolchain w/ C++, gcc >= 4.8 not affected by bug 64735 +# +# BR2_PACKAGE_SSDP_RESPONDER is not set +# BR2_PACKAGE_SSHGUARD is not set +# BR2_PACKAGE_SSHPASS is not set +# BR2_PACKAGE_SSLH is not set +# BR2_PACKAGE_STRONGSWAN is not set +# BR2_PACKAGE_STUNNEL is not set +# BR2_PACKAGE_TCPDUMP is not set +# BR2_PACKAGE_TCPING is not set +# BR2_PACKAGE_TCPREPLAY is not set +# BR2_PACKAGE_THTTPD is not set +# BR2_PACKAGE_TINC is not set +# BR2_PACKAGE_TINYPROXY is not set +# BR2_PACKAGE_TINYSSH is not set +# BR2_PACKAGE_TOR is not set +# BR2_PACKAGE_TRACEROUTE is not set +# BR2_PACKAGE_TRANSMISSION is not set +# BR2_PACKAGE_TUNCTL is not set +# BR2_PACKAGE_TVHEADEND is not set +# BR2_PACKAGE_UACME is not set +# BR2_PACKAGE_UDPCAST is not set +# BR2_PACKAGE_UFTP is not set +# BR2_PACKAGE_UHTTPD is not set +# BR2_PACKAGE_ULOGD is not set +# BR2_PACKAGE_UNBOUND is not set +# BR2_PACKAGE_UREDIR is not set +# BR2_PACKAGE_USHARE is not set +# BR2_PACKAGE_USSP_PUSH is not set +# BR2_PACKAGE_VDE2 is not set + +# +# vdr needs a glibc toolchain w/ C++, dynamic library, NPTL, wchar, headers >= 3.9 +# +# BR2_PACKAGE_VNSTAT is not set +# BR2_PACKAGE_VPNC is not set +# BR2_PACKAGE_VSFTPD is not set +# BR2_PACKAGE_VTUN is not set +# BR2_PACKAGE_WAVEMON is not set +# BR2_PACKAGE_WIREGUARD_TOOLS is not set +# BR2_PACKAGE_WIRELESS_REGDB is not set +# BR2_PACKAGE_WIRELESS_TOOLS is not set +# BR2_PACKAGE_WIRESHARK is not set +# BR2_PACKAGE_WPA_SUPPLICANT is not set +# BR2_PACKAGE_WPAN_TOOLS is not set +# BR2_PACKAGE_XINETD is not set +# BR2_PACKAGE_XL2TP is not set +# BR2_PACKAGE_XTABLES_ADDONS is not set + +# +# znc needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads +# + +# +# Package managers +# + +# +# ------------------------------------------------------- +# + +# +# Please note: +# + +# +# - Buildroot does *not* generate binary packages, +# + +# +# - Buildroot does *not* install any package database. +# + +# +# * +# + +# +# It is up to you to provide those by yourself if you +# + +# +# want to use any of those package managers. +# + +# +# * +# + +# +# See the manual: +# + +# +# http://buildroot.org/manual.html#faq-no-binary-packages +# + +# +# ------------------------------------------------------- +# +# BR2_PACKAGE_OPKG is not set +# BR2_PACKAGE_OPKG_UTILS is not set + +# +# Real-Time +# +# BR2_PACKAGE_XENOMAI is not set + +# +# Security +# + +# +# apparmor needs a toolchain w/ headers >= 3.16, threads, C++ +# +# BR2_PACKAGE_CHECKPOLICY is not set +# BR2_PACKAGE_IMA_EVM_UTILS is not set +# BR2_PACKAGE_OPTEE_BENCHMARK is not set +# BR2_PACKAGE_OPTEE_CLIENT is not set +# BR2_PACKAGE_PAXTEST is not set +# BR2_PACKAGE_REFPOLICY is not set +# BR2_PACKAGE_RESTORECOND is not set +# BR2_PACKAGE_SELINUX_PYTHON is not set +# BR2_PACKAGE_SEMODULE_UTILS is not set + +# +# setools needs python3 +# +# BR2_PACKAGE_URANDOM_SCRIPTS is not set + +# +# Shell and utilities +# + +# +# Shells +# +# BR2_PACKAGE_MKSH is not set +# BR2_PACKAGE_ZSH is not set + +# +# Utilities +# +# BR2_PACKAGE_AT is not set +# BR2_PACKAGE_CCRYPT is not set +# BR2_PACKAGE_DIALOG is not set +# BR2_PACKAGE_DTACH is not set +# BR2_PACKAGE_EASY_RSA is not set +# BR2_PACKAGE_FILE is not set +# BR2_PACKAGE_GNUPG is not set +# BR2_PACKAGE_GNUPG2 is not set +# BR2_PACKAGE_INOTIFY_TOOLS is not set +# BR2_PACKAGE_LOCKFILE_PROGS is not set +# BR2_PACKAGE_LOGROTATE is not set +# BR2_PACKAGE_LOGSURFER is not set +# BR2_PACKAGE_PDMENU is not set +# BR2_PACKAGE_PINENTRY is not set +# BR2_PACKAGE_QPRINT is not set +# BR2_PACKAGE_RANGER is not set +# BR2_PACKAGE_RTTY is not set +# BR2_PACKAGE_SCREEN is not set +# BR2_PACKAGE_SUDO is not set +# BR2_PACKAGE_TINI is not set +# BR2_PACKAGE_TMUX is not set +# BR2_PACKAGE_TTYD is not set +# BR2_PACKAGE_XMLSTARLET is not set +# BR2_PACKAGE_XXHASH is not set +# BR2_PACKAGE_YTREE is not set + +# +# System tools +# +# BR2_PACKAGE_ACL is not set +# BR2_PACKAGE_ANDROID_TOOLS is not set +# BR2_PACKAGE_ATOP is not set +# BR2_PACKAGE_ATTR is not set +# BR2_PACKAGE_BUBBLEWRAP is not set +# BR2_PACKAGE_CGROUPFS_MOUNT is not set + +# +# circus needs Python 3 and a toolchain w/ C++, threads +# +# BR2_PACKAGE_CPULOAD is not set +# BR2_PACKAGE_DAEMON is not set +# BR2_PACKAGE_DC3DD is not set + +# +# ddrescue needs a toolchain w/ C++ +# + +# +# docker-compose needs a toolchain w/ C++, wchar, threads, dynamic library +# +# BR2_PACKAGE_EARLYOOM is not set +# BR2_PACKAGE_EMLOG is not set +# BR2_PACKAGE_FTOP is not set +# BR2_PACKAGE_GETENT is not set +# BR2_PACKAGE_GKRELLM is not set +# BR2_PACKAGE_HTOP is not set +# BR2_PACKAGE_IBM_SW_TPM2 is not set +BR2_PACKAGE_INITSCRIPTS=y + +# +# iotop depends on python or python3 +# +# BR2_PACKAGE_IPRUTILS is not set +# BR2_PACKAGE_IRQBALANCE is not set +# BR2_PACKAGE_KEYUTILS is not set +# BR2_PACKAGE_KMOD is not set +# BR2_PACKAGE_LIBOSTREE is not set +# BR2_PACKAGE_LXC is not set +# BR2_PACKAGE_MFOC is not set +# BR2_PACKAGE_MONIT is not set + +# +# multipath-tools needs udev and a uClibc or glibc toolchain w/ threads, dynamic library +# +# BR2_PACKAGE_NCDU is not set + +# +# netifrc needs openrc as init system +# +# BR2_PACKAGE_NUMACTL is not set + +# +# nut needs a toolchain w/ C++ +# + +# +# pamtester depends on linux-pam +# + +# +# polkit needs a glibc or musl toolchain with C++, wchar, dynamic library, NPTL, gcc >= 4.9 +# +# BR2_PACKAGE_PROCRANK_LINUX is not set +# BR2_PACKAGE_PWGEN is not set +# BR2_PACKAGE_QUOTA is not set +# BR2_PACKAGE_QUOTATOOL is not set +# BR2_PACKAGE_RAUC is not set +# BR2_PACKAGE_S6 is not set +# BR2_PACKAGE_S6_LINUX_INIT is not set +# BR2_PACKAGE_S6_LINUX_UTILS is not set +# BR2_PACKAGE_S6_PORTABLE_UTILS is not set +# BR2_PACKAGE_S6_RC is not set +# BR2_PACKAGE_SCRUB is not set +# BR2_PACKAGE_SCRYPT is not set + +# +# sdbusplus needs systemd and a toolchain w/ C++, gcc >= 7 +# +# BR2_PACKAGE_SMACK is not set + +# +# supervisor needs a python interpreter +# +# BR2_PACKAGE_SWUPDATE is not set +BR2_PACKAGE_SYSTEMD_ARCH_SUPPORTS=y +# BR2_PACKAGE_TPM_TOOLS is not set +# BR2_PACKAGE_TPM2_ABRMD is not set +# BR2_PACKAGE_TPM2_TOOLS is not set +# BR2_PACKAGE_TPM2_TOTP is not set +# BR2_PACKAGE_UNSCD is not set +# BR2_PACKAGE_UTIL_LINUX is not set +# BR2_PACKAGE_WATCHDOG is not set +# BR2_PACKAGE_XDG_DBUS_PROXY is not set + +# +# Text editors and viewers +# +# BR2_PACKAGE_ED is not set +# BR2_PACKAGE_JOE is not set +# BR2_PACKAGE_MC is not set +# BR2_PACKAGE_MG is not set +# BR2_PACKAGE_MOST is not set +# BR2_PACKAGE_NANO is not set +# BR2_PACKAGE_UEMACS is not set + +# +# Filesystem images +# +# BR2_TARGET_ROOTFS_AXFS is not set +# BR2_TARGET_ROOTFS_BTRFS is not set +# BR2_TARGET_ROOTFS_CLOOP is not set +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_CPIO_NONE=y +# BR2_TARGET_ROOTFS_CPIO_GZIP is not set +# BR2_TARGET_ROOTFS_CPIO_BZIP2 is not set +# BR2_TARGET_ROOTFS_CPIO_LZ4 is not set +# BR2_TARGET_ROOTFS_CPIO_LZMA is not set +# BR2_TARGET_ROOTFS_CPIO_LZO is not set +# BR2_TARGET_ROOTFS_CPIO_XZ is not set +# BR2_TARGET_ROOTFS_CPIO_ZSTD is not set +# BR2_TARGET_ROOTFS_CPIO_UIMAGE is not set +# BR2_TARGET_ROOTFS_CRAMFS is not set +# BR2_TARGET_ROOTFS_EROFS is not set +# BR2_TARGET_ROOTFS_EXT2 is not set +# BR2_TARGET_ROOTFS_F2FS is not set +BR2_TARGET_ROOTFS_INITRAMFS=y +# BR2_TARGET_ROOTFS_JFFS2 is not set +# BR2_TARGET_ROOTFS_ROMFS is not set +# BR2_TARGET_ROOTFS_SQUASHFS is not set +# BR2_TARGET_ROOTFS_TAR is not set +# BR2_TARGET_ROOTFS_UBI is not set +# BR2_TARGET_ROOTFS_UBIFS is not set +# BR2_TARGET_ROOTFS_YAFFS2 is not set + +# +# Bootloaders +# +# BR2_TARGET_BAREBOX is not set +# BR2_TARGET_BEAGLEV_DDRINIT is not set +# BR2_TARGET_BEAGLEV_SECONDBOOT is not set +BR2_TARGET_OPENSBI=y +BR2_TARGET_OPENSBI_LATEST_VERSION=y +# BR2_TARGET_OPENSBI_CUSTOM_VERSION is not set +# BR2_TARGET_OPENSBI_CUSTOM_TARBALL is not set +# BR2_TARGET_OPENSBI_CUSTOM_GIT is not set +BR2_TARGET_OPENSBI_VERSION="0.9" +BR2_TARGET_OPENSBI_PLAT="generic" +BR2_TARGET_OPENSBI_INSTALL_DYNAMIC_IMG=y +BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y +# BR2_TARGET_OPENSBI_INSTALL_PAYLOAD_IMG is not set +# BR2_TARGET_OPENSBI_LINUX_PAYLOAD is not set +# BR2_TARGET_UBOOT is not set + +# +# Host utilities +# +# BR2_PACKAGE_HOST_ABOOTIMG is not set +# BR2_PACKAGE_HOST_AESPIPE is not set +# BR2_PACKAGE_HOST_ANDROID_TOOLS is not set +# BR2_PACKAGE_HOST_ASN1C is not set +# BR2_PACKAGE_HOST_BABELTRACE2 is not set +# BR2_PACKAGE_HOST_BTRFS_PROGS is not set +# BR2_PACKAGE_HOST_CHECKPOLICY is not set +# BR2_PACKAGE_HOST_CHECKSEC is not set +# BR2_PACKAGE_HOST_CMAKE is not set +# BR2_PACKAGE_HOST_CRAMFS is not set +# BR2_PACKAGE_HOST_CRYPTSETUP is not set +# BR2_PACKAGE_HOST_DBUS_PYTHON is not set +# BR2_PACKAGE_HOST_DFU_UTIL is not set +# BR2_PACKAGE_HOST_DOS2UNIX is not set +# BR2_PACKAGE_HOST_DOSFSTOOLS is not set +# BR2_PACKAGE_HOST_DOXYGEN is not set +# BR2_PACKAGE_HOST_DTC is not set +BR2_PACKAGE_HOST_E2FSPROGS=y +# BR2_PACKAGE_HOST_E2TOOLS is not set +# BR2_PACKAGE_HOST_ENVIRONMENT_SETUP is not set +# BR2_PACKAGE_HOST_EROFS_UTILS is not set +# BR2_PACKAGE_HOST_EXFATPROGS is not set +# BR2_PACKAGE_HOST_F2FS_TOOLS is not set +# BR2_PACKAGE_HOST_FAKETIME is not set +# BR2_PACKAGE_HOST_FATCAT is not set +# BR2_PACKAGE_HOST_FWUP is not set +# BR2_PACKAGE_HOST_GENEXT2FS is not set +# BR2_PACKAGE_HOST_GENIMAGE is not set +# BR2_PACKAGE_HOST_GENPART is not set +# BR2_PACKAGE_HOST_GNUPG is not set +BR2_PACKAGE_HOST_GO_HOST_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_GO_BOOTSTRAP_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_GOOGLE_BREAKPAD_ARCH_SUPPORTS=y +# BR2_PACKAGE_HOST_GPTFDISK is not set +# BR2_PACKAGE_HOST_IMAGEMAGICK is not set +# BR2_PACKAGE_HOST_IMX_MKIMAGE is not set +# BR2_PACKAGE_HOST_JH71XX_TOOLS is not set +# BR2_PACKAGE_HOST_JQ is not set +# BR2_PACKAGE_HOST_JSMIN is not set +BR2_PACKAGE_HOST_KMOD=y +# BR2_PACKAGE_HOST_KMOD_GZ is not set +# BR2_PACKAGE_HOST_KMOD_ZSTD is not set +# BR2_PACKAGE_HOST_KMOD_XZ is not set +# BR2_PACKAGE_HOST_LIBP11 is not set +# BR2_PACKAGE_HOST_LPC3250LOADER is not set +# BR2_PACKAGE_HOST_LTTNG_BABELTRACE is not set +# BR2_PACKAGE_HOST_MENDER_ARTIFACT is not set +# BR2_PACKAGE_HOST_MESON_TOOLS is not set +# BR2_PACKAGE_HOST_MKPASSWD is not set +# BR2_PACKAGE_HOST_MTD is not set +# BR2_PACKAGE_HOST_MTOOLS is not set +# BR2_PACKAGE_HOST_ODB is not set +# BR2_PACKAGE_HOST_OPENOCD is not set +# BR2_PACKAGE_HOST_OPKG_UTILS is not set +# BR2_PACKAGE_HOST_PARTED is not set +BR2_PACKAGE_HOST_PATCHELF=y +# BR2_PACKAGE_HOST_PIGZ is not set +# BR2_PACKAGE_HOST_PKGCONF is not set +# BR2_PACKAGE_HOST_PWGEN is not set +# BR2_PACKAGE_HOST_PYTHON is not set +# BR2_PACKAGE_HOST_PYTHON_CYTHON is not set +# BR2_PACKAGE_HOST_PYTHON_LXML is not set +# BR2_PACKAGE_HOST_PYTHON_SIX is not set +# BR2_PACKAGE_HOST_PYTHON_XLRD is not set +# BR2_PACKAGE_HOST_PYTHON3 is not set +BR2_PACKAGE_HOST_QEMU_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_QEMU_SYSTEM_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_QEMU_USER_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_QEMU=y + +# +# Emulators selection +# +BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y +# BR2_PACKAGE_HOST_QEMU_LINUX_USER_MODE is not set +# BR2_PACKAGE_HOST_QEMU_VDE2 is not set +# BR2_PACKAGE_HOST_QEMU_VIRTFS is not set +# BR2_PACKAGE_HOST_QEMU_USB is not set +# BR2_PACKAGE_HOST_QORIQ_RCW is not set +# BR2_PACKAGE_HOST_RAUC is not set +BR2_PACKAGE_HOST_RUSTC_ARCH_SUPPORTS=y +BR2_PACKAGE_HOST_RUSTC_ARCH="riscv64" +# BR2_PACKAGE_HOST_RUSTC is not set +BR2_PACKAGE_PROVIDES_HOST_RUSTC="host-rust-bin" +# BR2_PACKAGE_HOST_SAM_BA is not set +# BR2_PACKAGE_HOST_SDBUSPLUS is not set +# BR2_PACKAGE_HOST_SENTRY_CLI is not set +# BR2_PACKAGE_HOST_SQUASHFS is not set +# BR2_PACKAGE_HOST_SWIG is not set +# BR2_PACKAGE_HOST_UBOOT_TOOLS is not set +BR2_PACKAGE_HOST_UTIL_LINUX=y +# BR2_PACKAGE_HOST_UTP_COM is not set +# BR2_PACKAGE_HOST_VBOOT_UTILS is not set +# BR2_PACKAGE_HOST_XORRISO is not set +# BR2_PACKAGE_HOST_ZIP is not set +# BR2_PACKAGE_HOST_ZSTD is not set + +# +# Legacy config options +# + +# +# Legacy options removed in 2021.05 +# +# BR2_PACKAGE_UDISKS_LVM2 is not set +# BR2_PACKAGE_LVM2_APP_LIBRARY is not set +# BR2_PACKAGE_LVM2_LVMETAD is not set +# BR2_PACKAGE_MONKEY is not set +# BR2_PACKAGE_DOCKER_CONTAINERD is not set +# BR2_PACKAGE_IOSTAT is not set +# BR2_PACKAGE_SCONESERVER_HTTP_SCONESITE_IMAGE is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_EVDEV is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_KBD is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_MOUSE is not set +# BR2_PACKAGE_MESA3D_OSMESA_CLASSIC is not set +# BR2_PACKAGE_MESA3D_DRI_DRIVER_SWRAST is not set +# BR2_PACKAGE_KODI_SCREENSAVER_CRYSTALMORPH is not set + +# +# Legacy options removed in 2021.02 +# +# BR2_PACKAGE_MPD_AUDIOFILE is not set +# BR2_PACKAGE_AUDIOFILE is not set +# BR2_BINUTILS_VERSION_2_33_X is not set +# BR2_PACKAGE_LIBUPNP18 is not set +# BR2_PACKAGE_BOA is not set +# BR2_PACKAGE_LINUX_FIRMWARE_IMX_SDMA is not set +# BR2_GDB_VERSION_8_2 is not set +# BR2_PACKAGE_HOST_RCW is not set +# BR2_KERNEL_HEADERS_5_9 is not set +# BR2_KERNEL_HEADERS_5_8 is not set +# BR2_powerpc_601 is not set +# BR2_PACKAGE_TI_SGX_LIBGBM is not set +# BR2_PACKAGE_IPSEC_TOOLS is not set + +# +# Legacy options removed in 2020.11 +# +# BR2_PACKAGE_OPENCV is not set +# BR2_PACKAGE_LIBCROCO is not set +# BR2_PACKAGE_BELLAGIO is not set +# BR2_PACKAGE_SYSTEMD_JOURNAL_GATEWAY is not set +# BR2_TARGET_UBOOT_BOOT_SCRIPT is not set +# BR2_TARGET_UBOOT_ENVIMAGE is not set +# BR2_PACKAGE_KISMET_CLIENT is not set +# BR2_PACKAGE_KISMET_DRONE is not set +# BR2_GCC_VERSION_7_X is not set +# BR2_PACKAGE_GST1_VALIDATE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_YADIF is not set +# BR2_PACKAGE_GQVIEW is not set +# BR2_PACKAGE_WESTON_IMX is not set +# BR2_KERNEL_HEADERS_5_7 is not set +# BR2_PACKAGE_TINYHTTPD is not set +# BR2_PACKAGE_XSERVER_XORG_SERVER_AIGLX is not set +# BR2_PACKAGE_AMD_CATALYST is not set +# BR2_PACKAGE_NVIDIA_TEGRA23 is not set +# BR2_GDB_VERSION_8_1 is not set + +# +# Legacy options removed in 2020.08 +# +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_AMD64 is not set +# BR2_KERNEL_HEADERS_5_6 is not set +# BR2_KERNEL_HEADERS_5_5 is not set +# BR2_BINUTILS_VERSION_2_31_X is not set +# BR2_PACKAGE_KODI_PERIPHERAL_STEAMCONTROLLER is not set + +# +# Legacy options removed in 2020.05 +# +# BR2_PACKAGE_WIRINGPI is not set +# BR2_PACKAGE_PYTHON_PYCRYPTO is not set +# BR2_PACKAGE_MTDEV2TUIO is not set +# BR2_PACKAGE_EZXML is not set +# BR2_PACKAGE_COLLECTD_LVM is not set +# BR2_PACKAGE_PYTHON_PYASN is not set +# BR2_PACKAGE_PYTHON_PYASN_MODULES is not set +# BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_10K_QCA6174 is not set +# BR2_PACKAGE_QT5CANVAS3D is not set +# BR2_PACKAGE_KODI_LIBTHEORA is not set +# BR2_PACKAGE_CEGUI06 is not set +# BR2_GCC_VERSION_5_X is not set + +# +# Legacy options removed in 2020.02 +# +# BR2_PACKAGE_JAMVM is not set +# BR2_PACKAGE_CLASSPATH is not set +# BR2_PACKAGE_QT5_VERSION_5_6 is not set +# BR2_PACKAGE_CURL is not set +# BR2_PACKAGE_GSTREAMER is not set +# BR2_PACKAGE_NVIDIA_TEGRA23_BINARIES_GSTREAMER_PLUGINS is not set +# BR2_PACKAGE_NVIDIA_TEGRA23_BINARIES_NV_SAMPLE_APPS is not set +# BR2_PACKAGE_FREERDP_GSTREAMER is not set +# BR2_PACKAGE_OPENCV3_WITH_GSTREAMER is not set +# BR2_PACKAGE_OPENCV_WITH_GSTREAMER is not set +# BR2_PACKAGE_LIBPLAYER is not set +# BR2_GCC_VERSION_OR1K is not set +# BR2_PACKAGE_BLUEZ_UTILS is not set +# BR2_PACKAGE_GADGETFS_TEST is not set +# BR2_PACKAGE_FIS is not set +BR2_PACKAGE_REFPOLICY_POLICY_VERSION="" +# BR2_PACKAGE_CELT051 is not set +# BR2_PACKAGE_WIREGUARD is not set +# BR2_PACKAGE_PERL_NET_PING is not set +# BR2_PACKAGE_PERL_MIME_BASE64 is not set +# BR2_PACKAGE_PERL_DIGEST_MD5 is not set +# BR2_PACKAGE_ERLANG_P1_ICONV is not set +# BR2_KERNEL_HEADERS_5_3 is not set +# BR2_PACKAGE_PYTHON_SCAPY3K is not set +# BR2_BINUTILS_VERSION_2_30_X is not set +# BR2_PACKAGE_RPI_USERLAND_START_VCFILED is not set + +# +# Legacy options removed in 2019.11 +# +# BR2_PACKAGE_OPENVMTOOLS_PROCPS is not set +# BR2_PACKAGE_ALLJOYN is not set +# BR2_PACKAGE_ALLJOYN_BASE is not set +# BR2_PACKAGE_ALLJOYN_BASE_CONTROLPANEL is not set +# BR2_PACKAGE_ALLJOYN_BASE_NOTIFICATION is not set +# BR2_PACKAGE_ALLJOYN_BASE_ONBOARDING is not set +# BR2_PACKAGE_ALLJOYN_TCL_BASE is not set +# BR2_PACKAGE_ALLJOYN_TCL is not set +BR2_TOOLCHAIN_EXTRA_EXTERNAL_LIBS="" +# BR2_PACKAGE_PYTHON_PYSNMP_APPS is not set +# BR2_KERNEL_HEADERS_5_2 is not set +# BR2_TARGET_RISCV_PK is not set +# BR2_PACKAGE_SQLITE_STAT3 is not set +# BR2_KERNEL_HEADERS_5_1 is not set +# BR2_PACKAGE_DEVMEM2 is not set +# BR2_PACKAGE_USTR is not set +# BR2_PACKAGE_KODI_SCREENSAVER_PLANESTATE is not set +# BR2_PACKAGE_KODI_VISUALISATION_WAVEFORHUE is not set +# BR2_PACKAGE_KODI_AUDIODECODER_OPUS is not set +# BR2_PACKAGE_MESA3D_OSMESA is not set +# BR2_PACKAGE_HOSTAPD_DRIVER_RTW is not set +# BR2_PACKAGE_WPA_SUPPLICANT_DBUS_NEW is not set +# BR2_PACKAGE_WPA_SUPPLICANT_DBUS_OLD is not set + +# +# Legacy options removed in 2019.08 +# +# BR2_TARGET_TS4800_MBRBOOT is not set +# BR2_PACKAGE_LIBAMCODEC is not set +# BR2_PACKAGE_ODROID_SCRIPTS is not set +# BR2_PACKAGE_ODROID_MALI is not set +# BR2_PACKAGE_KODI_PLATFORM_AML is not set +# BR2_GCC_VERSION_6_X is not set +# BR2_GCC_VERSION_4_9_X is not set +# BR2_GDB_VERSION_7_12 is not set +# BR2_PACKAGE_XAPP_MKFONTDIR is not set +# BR2_GDB_VERSION_8_0 is not set +# BR2_KERNEL_HEADERS_4_20 is not set +# BR2_KERNEL_HEADERS_5_0 is not set + +# +# Legacy options removed in 2019.05 +# +# BR2_CSKY_DSP is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_COMPOSITOR is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_IQA is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_OPENCV is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_STEREO is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VCD is not set +# BR2_PACKAGE_LUNIT is not set +# BR2_PACKAGE_FFMPEG_FFSERVER is not set +# BR2_PACKAGE_LIBUMP is not set +# BR2_PACKAGE_SUNXI_MALI is not set +# BR2_BINUTILS_VERSION_2_29_X is not set +# BR2_BINUTILS_VERSION_2_28_X is not set +# BR2_PACKAGE_GST_PLUGINS_BAD_PLUGIN_APEXSINK is not set + +# +# Legacy options removed in 2019.02 +# +# BR2_PACKAGE_QT is not set +# BR2_PACKAGE_QTUIO is not set +# BR2_PACKAGE_PINENTRY_QT4 is not set +# BR2_PACKAGE_POPPLER_QT is not set +# BR2_PACKAGE_OPENCV3_WITH_QT is not set +# BR2_PACKAGE_OPENCV_WITH_QT is not set +# BR2_PACKAGE_AMD_CATALYST_CCCLE is not set +# BR2_PACKAGE_SDL_QTOPIA is not set +# BR2_PACKAGE_PYTHON_PYQT is not set +# BR2_PACKAGE_LUACRYPTO is not set +# BR2_PACKAGE_TN5250 is not set +# BR2_PACKAGE_BOOST_SIGNALS is not set +# BR2_PACKAGE_FFTW_PRECISION_SINGLE is not set +# BR2_PACKAGE_FFTW_PRECISION_DOUBLE is not set +# BR2_PACKAGE_FFTW_PRECISION_LONG_DOUBLE is not set +# BR2_PACKAGE_LUA_5_2 is not set +# BR2_TARGET_GENERIC_PASSWD_MD5 is not set + +# +# Legacy options removed in 2018.11 +# +# BR2_TARGET_XLOADER is not set +# BR2_PACKAGE_TIDSP_BINARIES is not set +# BR2_PACKAGE_DSP_TOOLS is not set +# BR2_PACKAGE_GST_DSP is not set +# BR2_PACKAGE_BOOTUTILS is not set +# BR2_PACKAGE_EXPEDITE is not set +# BR2_PACKAGE_MESA3D_OPENGL_TEXTURE_FLOAT is not set +# BR2_KERNEL_HEADERS_4_10 is not set +# BR2_KERNEL_HEADERS_4_11 is not set +# BR2_KERNEL_HEADERS_4_12 is not set +# BR2_KERNEL_HEADERS_4_13 is not set +# BR2_KERNEL_HEADERS_4_15 is not set +# BR2_KERNEL_HEADERS_4_17 is not set +# BR2_PACKAGE_LIBNFTNL_XML is not set +# BR2_KERNEL_HEADERS_3_2 is not set +# BR2_KERNEL_HEADERS_4_1 is not set +# BR2_KERNEL_HEADERS_4_16 is not set +# BR2_KERNEL_HEADERS_4_18 is not set + +# +# Legacy options removed in 2018.08 +# +# BR2_PACKAGE_DOCKER_ENGINE_STATIC_CLIENT is not set +# BR2_PACKAGE_XPROTO_APPLEWMPROTO is not set +# BR2_PACKAGE_XPROTO_BIGREQSPROTO is not set +# BR2_PACKAGE_XPROTO_COMPOSITEPROTO is not set +# BR2_PACKAGE_XPROTO_DAMAGEPROTO is not set +# BR2_PACKAGE_XPROTO_DMXPROTO is not set +# BR2_PACKAGE_XPROTO_DRI2PROTO is not set +# BR2_PACKAGE_XPROTO_DRI3PROTO is not set +# BR2_PACKAGE_XPROTO_FIXESPROTO is not set +# BR2_PACKAGE_XPROTO_FONTCACHEPROTO is not set +# BR2_PACKAGE_XPROTO_FONTSPROTO is not set +# BR2_PACKAGE_XPROTO_GLPROTO is not set +# BR2_PACKAGE_XPROTO_INPUTPROTO is not set +# BR2_PACKAGE_XPROTO_KBPROTO is not set +# BR2_PACKAGE_XPROTO_PRESENTPROTO is not set +# BR2_PACKAGE_XPROTO_RANDRPROTO is not set +# BR2_PACKAGE_XPROTO_RECORDPROTO is not set +# BR2_PACKAGE_XPROTO_RENDERPROTO is not set +# BR2_PACKAGE_XPROTO_RESOURCEPROTO is not set +# BR2_PACKAGE_XPROTO_SCRNSAVERPROTO is not set +# BR2_PACKAGE_XPROTO_VIDEOPROTO is not set +# BR2_PACKAGE_XPROTO_WINDOWSWMPROTO is not set +# BR2_PACKAGE_XPROTO_XCMISCPROTO is not set +# BR2_PACKAGE_XPROTO_XEXTPROTO is not set +# BR2_PACKAGE_XPROTO_XF86BIGFONTPROTO is not set +# BR2_PACKAGE_XPROTO_XF86DGAPROTO is not set +# BR2_PACKAGE_XPROTO_XF86DRIPROTO is not set +# BR2_PACKAGE_XPROTO_XF86VIDMODEPROTO is not set +# BR2_PACKAGE_XPROTO_XINERAMAPROTO is not set +# BR2_PACKAGE_XPROTO_XPROTO is not set +# BR2_PACKAGE_XPROTO_XPROXYMANAGEMENTPROTOCOL is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_OPENGL is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLES2 is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLX is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_EGL is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_X11 is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_WAYLAND is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_DISPMANX is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_AUDIOMIXER is not set +# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_LAME is not set +# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MPG123 is not set +# BR2_GDB_VERSION_7_11 is not set +# BR2_GDB_VERSION_7_10 is not set + +# +# Legacy options removed in 2018.05 +# +# BR2_PACKAGE_MEDIAART_BACKEND_NONE is not set +# BR2_PACKAGE_MEDIAART_BACKEND_GDK_PIXBUF is not set +# BR2_PACKAGE_TI_SGX_AM335X is not set +# BR2_PACKAGE_TI_SGX_AM437X is not set +# BR2_PACKAGE_TI_SGX_AM4430 is not set +# BR2_PACKAGE_TI_SGX_AM5430 is not set +# BR2_PACKAGE_JANUS_AUDIO_BRIDGE is not set +# BR2_PACKAGE_JANUS_ECHO_TEST is not set +# BR2_PACKAGE_JANUS_RECORDPLAY is not set +# BR2_PACKAGE_JANUS_SIP_GATEWAY is not set +# BR2_PACKAGE_JANUS_STREAMING is not set +# BR2_PACKAGE_JANUS_TEXT_ROOM is not set +# BR2_PACKAGE_JANUS_VIDEO_CALL is not set +# BR2_PACKAGE_JANUS_VIDEO_ROOM is not set +# BR2_PACKAGE_JANUS_MQTT is not set +# BR2_PACKAGE_JANUS_RABBITMQ is not set +# BR2_PACKAGE_JANUS_REST is not set +# BR2_PACKAGE_JANUS_UNIX_SOCKETS is not set +# BR2_PACKAGE_JANUS_WEBSOCKETS is not set +# BR2_PACKAGE_IPSEC_SECCTX_DISABLE is not set +# BR2_PACKAGE_IPSEC_SECCTX_ENABLE is not set +# BR2_PACKAGE_IPSEC_SECCTX_KERNEL is not set +# BR2_PACKAGE_LIBTFDI_CPP is not set +# BR2_PACKAGE_JQUERY_UI_THEME_BLACK_TIE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_BLITZER is not set +# BR2_PACKAGE_JQUERY_UI_THEME_CUPERTINO is not set +# BR2_PACKAGE_JQUERY_UI_THEME_DARK_HIVE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_DOT_LUV is not set +# BR2_PACKAGE_JQUERY_UI_THEME_EGGPLANT is not set +# BR2_PACKAGE_JQUERY_UI_THEME_EXCITE_BIKE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_FLICK is not set +# BR2_PACKAGE_JQUERY_UI_THEME_HOT_SNEAKS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_HUMANITY is not set +# BR2_PACKAGE_JQUERY_UI_THEME_LE_FROG is not set +# BR2_PACKAGE_JQUERY_UI_THEME_MINT_CHOC is not set +# BR2_PACKAGE_JQUERY_UI_THEME_OVERCAST is not set +# BR2_PACKAGE_JQUERY_UI_THEME_PEPPER_GRINDER is not set +# BR2_PACKAGE_JQUERY_UI_THEME_REDMOND is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SMOOTHNESS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SOUTH_STREET is not set +# BR2_PACKAGE_JQUERY_UI_THEME_START is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SUNNY is not set +# BR2_PACKAGE_JQUERY_UI_THEME_SWANKY_PURSE is not set +# BR2_PACKAGE_JQUERY_UI_THEME_TRONTASTIC is not set +# BR2_PACKAGE_JQUERY_UI_THEME_UI_DARKNESS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_UI_LIGHTNESS is not set +# BR2_PACKAGE_JQUERY_UI_THEME_VADER is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_HEALTH is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_MIDI is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_NFC is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_SAP is not set +# BR2_PACKAGE_BLUEZ5_PLUGINS_SIXAXIS is not set +# BR2_PACKAGE_TRANSMISSION_REMOTE is not set +# BR2_PACKAGE_LIBKCAPI_APPS is not set +# BR2_PACKAGE_MPLAYER is not set +# BR2_PACKAGE_MPLAYER_MPLAYER is not set +# BR2_PACKAGE_MPLAYER_MENCODER is not set +# BR2_PACKAGE_LIBPLAYER_MPLAYER is not set +# BR2_PACKAGE_IQVLINUX is not set +# BR2_BINFMT_FLAT_SEP_DATA is not set +# BR2_bfin is not set +# BR2_PACKAGE_KODI_ADSP_BASIC is not set +# BR2_PACKAGE_KODI_ADSP_FREESURROUND is not set + +# +# Legacy options removed in 2018.02 +# +# BR2_KERNEL_HEADERS_3_4 is not set +# BR2_KERNEL_HEADERS_3_10 is not set +# BR2_KERNEL_HEADERS_3_12 is not set +# BR2_BINUTILS_VERSION_2_27_X is not set +# BR2_PACKAGE_EEPROG is not set +# BR2_PACKAGE_GNUPG2_GPGV2 is not set +# BR2_PACKAGE_IMX_GPU_VIV_APITRACE is not set +# BR2_PACKAGE_IMX_GPU_VIV_G2D is not set + +# +# Legacy options removed in 2017.11 +# +# BR2_PACKAGE_RFKILL is not set +# BR2_PACKAGE_UTIL_LINUX_RESET is not set +# BR2_PACKAGE_POLICYCOREUTILS_AUDIT2ALLOW is not set +# BR2_PACKAGE_POLICYCOREUTILS_RESTORECOND is not set +# BR2_PACKAGE_SEPOLGEN is not set +# BR2_PACKAGE_OPENOBEX_BLUEZ is not set +# BR2_PACKAGE_OPENOBEX_LIBUSB is not set +# BR2_PACKAGE_OPENOBEX_APPS is not set +# BR2_PACKAGE_OPENOBEX_SYSLOG is not set +# BR2_PACKAGE_OPENOBEX_DUMP is not set +# BR2_PACKAGE_AICCU is not set +# BR2_PACKAGE_UTIL_LINUX_LOGIN_UTILS is not set + +# +# Legacy options removed in 2017.08 +# +# BR2_TARGET_GRUB is not set +# BR2_PACKAGE_SIMICSFS is not set +# BR2_BINUTILS_VERSION_2_26_X is not set +BR2_XTENSA_OVERLAY_DIR="" +BR2_XTENSA_CUSTOM_NAME="" +# BR2_PACKAGE_HOST_MKE2IMG is not set +BR2_TARGET_ROOTFS_EXT2_BLOCKS=0 +BR2_TARGET_ROOTFS_EXT2_EXTRA_INODES=0 +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_CDXAPARSE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DATAURISRC is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DCCP is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_HDVPARSE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MVE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_NUVDEMUX is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_PATCHDETECT is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDI is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_TTA is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VIDEOMEASURE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_APEXSINK is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDL is not set +# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MAD is not set +# BR2_STRIP_none is not set +# BR2_PACKAGE_BEECRYPT_CPP is not set +# BR2_PACKAGE_SPICE_CLIENT is not set +# BR2_PACKAGE_SPICE_GUI is not set +# BR2_PACKAGE_SPICE_TUNNEL is not set +# BR2_PACKAGE_INPUT_TOOLS is not set +# BR2_PACKAGE_INPUT_TOOLS_INPUTATTACH is not set +# BR2_PACKAGE_INPUT_TOOLS_JSCAL is not set +# BR2_PACKAGE_INPUT_TOOLS_JSTEST is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_SH is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_X86 is not set +# BR2_GCC_VERSION_4_8_X is not set + +# +# Legacy options removed in 2017.05 +# +# BR2_PACKAGE_SUNXI_MALI_R2P4 is not set +# BR2_PACKAGE_NODEJS_MODULES_COFFEESCRIPT is not set +# BR2_PACKAGE_NODEJS_MODULES_EXPRESS is not set +# BR2_PACKAGE_BLUEZ5_UTILS_GATTTOOL is not set +# BR2_PACKAGE_OPENOCD_FT2XXX is not set +# BR2_PACKAGE_KODI_RTMPDUMP is not set +# BR2_PACKAGE_KODI_VISUALISATION_FOUNTAIN is not set +# BR2_PACKAGE_PORTMAP is not set +# BR2_BINUTILS_VERSION_2_25_X is not set +# BR2_TOOLCHAIN_BUILDROOT_INET_RPC is not set +BR2_TARGET_ROOTFS_EXT2_EXTRA_BLOCKS=0 +# BR2_PACKAGE_SYSTEMD_KDBUS is not set +# BR2_PACKAGE_POLARSSL is not set +# BR2_NBD_CLIENT is not set +# BR2_NBD_SERVER is not set +# BR2_PACKAGE_GMOCK is not set +# BR2_KERNEL_HEADERS_4_8 is not set +# BR2_KERNEL_HEADERS_3_18 is not set +# BR2_GLIBC_VERSION_2_22 is not set + +# +# Legacy options removed in 2017.02 +# +# BR2_PACKAGE_PERL_DB_FILE is not set +# BR2_KERNEL_HEADERS_4_7 is not set +# BR2_KERNEL_HEADERS_4_6 is not set +# BR2_KERNEL_HEADERS_4_5 is not set +# BR2_KERNEL_HEADERS_3_14 is not set +# BR2_TOOLCHAIN_EXTERNAL_MUSL_CROSS is not set +# BR2_UCLIBC_INSTALL_TEST_SUITE is not set +# BR2_TOOLCHAIN_EXTERNAL_BLACKFIN_UCLINUX is not set +# BR2_PACKAGE_MAKEDEVS is not set +# BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV7A is not set +# BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV5TE is not set +# BR2_PACKAGE_SNOWBALL_HDMISERVICE is not set +# BR2_PACKAGE_SNOWBALL_INIT is not set +# BR2_GDB_VERSION_7_9 is not set + +# +# Legacy options removed in 2016.11 +# +# BR2_PACKAGE_PHP_SAPI_CLI_CGI is not set +# BR2_PACKAGE_PHP_SAPI_CLI_FPM is not set +# BR2_PACKAGE_WVSTREAMS is not set +# BR2_PACKAGE_WVDIAL is not set +# BR2_PACKAGE_WEBKITGTK24 is not set +# BR2_PACKAGE_TORSMO is not set +# BR2_PACKAGE_SSTRIP is not set +# BR2_KERNEL_HEADERS_4_3 is not set +# BR2_KERNEL_HEADERS_4_2 is not set +# BR2_PACKAGE_KODI_ADDON_XVDR is not set +# BR2_PACKAGE_IPKG is not set +# BR2_GCC_VERSION_4_7_X is not set +# BR2_BINUTILS_VERSION_2_24_X is not set +# BR2_PACKAGE_WESTON_RPI is not set +# BR2_LINUX_KERNEL_TOOL_CPUPOWER is not set +# BR2_LINUX_KERNEL_TOOL_PERF is not set +# BR2_LINUX_KERNEL_TOOL_SELFTESTS is not set +# BR2_GCC_VERSION_4_8_ARC is not set +# BR2_KERNEL_HEADERS_4_0 is not set +# BR2_KERNEL_HEADERS_3_19 is not set +# BR2_PACKAGE_LIBEVAS_GENERIC_LOADERS is not set +# BR2_PACKAGE_ELEMENTARY is not set +# BR2_LINUX_KERNEL_CUSTOM_LOCAL is not set + +# +# Legacy options removed in 2016.08 +# +# BR2_PACKAGE_EFL_JP2K is not set +# BR2_PACKAGE_SYSTEMD_COMPAT is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_LIVEADDER is not set +# BR2_PACKAGE_LIBFSLVPUWRAP is not set +# BR2_PACKAGE_LIBFSLPARSER is not set +# BR2_PACKAGE_LIBFSLCODEC is not set +# BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE_FIT_SIGNATURE_SUPPORT is not set +# BR2_PTHREADS_OLD is not set +# BR2_BINUTILS_VERSION_2_23_X is not set +# BR2_TOOLCHAIN_BUILDROOT_EGLIBC is not set +# BR2_GDB_VERSION_7_8 is not set + +# +# Legacy options removed in 2016.05 +# +# BR2_PACKAGE_OPENVPN_CRYPTO_POLARSSL is not set +# BR2_PACKAGE_NGINX_HTTP_SPDY_MODULE is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_RTP is not set +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MPG123 is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC is not set +# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC_E500V2 is not set +# BR2_x86_i386 is not set +# BR2_PACKAGE_QT5QUICK1 is not set +BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="" +# BR2_PACKAGE_XDRIVER_XF86_INPUT_VOID is not set +# BR2_KERNEL_HEADERS_3_17 is not set +# BR2_GDB_VERSION_7_7 is not set +# BR2_PACKAGE_FOOMATIC_FILTERS is not set +# BR2_PACKAGE_SAMBA is not set +# BR2_PACKAGE_KODI_WAVPACK is not set +# BR2_PACKAGE_KODI_RSXS is not set +# BR2_PACKAGE_KODI_GOOM is not set +# BR2_PACKAGE_SYSTEMD_ALL_EXTRAS is not set +# BR2_GCC_VERSION_4_5_X is not set +# BR2_PACKAGE_SQLITE_READLINE is not set + +# +# Legacy options removed in 2016.02 +# +# BR2_PACKAGE_DOVECOT_BZIP2 is not set +# BR2_PACKAGE_DOVECOT_ZLIB is not set +# BR2_PACKAGE_E2FSPROGS_FINDFS is not set +# BR2_PACKAGE_OPENPOWERLINK_DEBUG_LEVEL is not set +# BR2_PACKAGE_OPENPOWERLINK_KERNEL_MODULE is not set +# BR2_PACKAGE_OPENPOWERLINK_LIBPCAP is not set +# BR2_LINUX_KERNEL_SAME_AS_HEADERS is not set +# BR2_PACKAGE_CUPS_PDFTOPS is not set +# BR2_KERNEL_HEADERS_3_16 is not set +# BR2_PACKAGE_PYTHON_PYXML is not set +# BR2_ENABLE_SSP is not set +# BR2_PACKAGE_DIRECTFB_CLE266 is not set +# BR2_PACKAGE_DIRECTFB_UNICHROME is not set +# BR2_PACKAGE_LIBELEMENTARY is not set +# BR2_PACKAGE_LIBEINA is not set +# BR2_PACKAGE_LIBEET is not set +# BR2_PACKAGE_LIBEVAS is not set +# BR2_PACKAGE_LIBECORE is not set +# BR2_PACKAGE_LIBEDBUS is not set +# BR2_PACKAGE_LIBEFREET is not set +# BR2_PACKAGE_LIBEIO is not set +# BR2_PACKAGE_LIBEMBRYO is not set +# BR2_PACKAGE_LIBEDJE is not set +# BR2_PACKAGE_LIBETHUMB is not set +# BR2_PACKAGE_INFOZIP is not set +# BR2_BR2_PACKAGE_NODEJS_0_10_X is not set +# BR2_BR2_PACKAGE_NODEJS_0_12_X is not set +# BR2_BR2_PACKAGE_NODEJS_4_X is not set + +# +# Legacy options removed in 2015.11 +# +# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_REAL is not set +# BR2_PACKAGE_MEDIA_CTL is not set +# BR2_PACKAGE_SCHIFRA is not set +# BR2_PACKAGE_ZXING is not set +# BR2_PACKAGE_BLACKBOX is not set +# BR2_KERNEL_HEADERS_3_0 is not set +# BR2_KERNEL_HEADERS_3_11 is not set +# BR2_KERNEL_HEADERS_3_13 is not set +# BR2_KERNEL_HEADERS_3_15 is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_ANDI is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_BLTLOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_CPULOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DATABUFFER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DIOLOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DOK is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_DRIVERTEST is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_FIRE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_FLIP is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_FONTS is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_INPUT is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_JOYSTICK is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_KNUCKLES is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_LAYER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX_WATER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_NEO is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_NETLOAD is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_PALETTE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_PARTICLE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_PORTER is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_STRESS is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_TEXTURE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO_PARTICLE is not set +# BR2_PACKAGE_DIRECTFB_EXAMPLES_WINDOW is not set +# BR2_PACKAGE_KOBS_NG is not set +# BR2_PACKAGE_SAWMAN is not set +# BR2_PACKAGE_DIVINE is not set + +# +# Legacy options removed in 2015.08 +# +# BR2_PACKAGE_KODI_PVR_ADDONS is not set +# BR2_BINUTILS_VERSION_2_23_2 is not set +# BR2_BINUTILS_VERSION_2_24 is not set +# BR2_BINUTILS_VERSION_2_25 is not set +# BR2_PACKAGE_PERF is not set +# BR2_BINUTILS_VERSION_2_22 is not set +# BR2_PACKAGE_GPU_VIV_BIN_MX6Q is not set +# BR2_TARGET_UBOOT_NETWORK is not set diff --git a/linux/sdcard/Makefile b/linux/sdcard/Makefile new file mode 100644 index 000000000..7c6c012f9 --- /dev/null +++ b/linux/sdcard/Makefile @@ -0,0 +1,9 @@ +RISCV := /opt/riscv + +.PHONY: all clean + +all: + ./make-img.sh test.img + +clean: + rm -f test.img diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh new file mode 100755 index 000000000..edc1ca5eb --- /dev/null +++ b/linux/sdcard/flash-sd.sh @@ -0,0 +1,120 @@ +#!/bin/bash + +# Exit on any error (return code != 0) +set -e + +# Output colors +GREEN='\033[1;32m' +RED='\033[1;31m' +NC='\033[0m' +NAME="$GREEN"${0:2}"$NC" + +# File location variables +RISCV=/opt/riscv +IMAGES=$RISCV/buildroot/output/images +FW_JUMP=$IMAGES/fw_jump.bin +LINUX_KERNEL=$IMAGES/Image +DEVICE_TREE=$IMAGES/wally-vcu108.dtb + +# Mount Directory +MNT_DIR=wallyimg + +if [ "$#" -eq "0" ] ; then + echo "$NAME: $RED ERROR $NC: You must supply the SD card device." + echo "usage: ./flash-sd.sh " + exit 1 +fi + +if [ ! -e "$1" ] ; then + echo "$NAME:$RED ERROR $NC: SD card device does not exist." + exit 1 +fi + +if [ ! -z "$2" ] ; then + MNT_DIR=$2 +fi + +# If images are not built, exit +if [ ! -e $FW_JUMP ] || [ ! -e $LINUX_KERNEL ] ; then + echo 'ERROR: Missing images in buildroot output directory.' + echo ' Build images before running this script.' + exit 1 +fi + +if [ ! -e $DEVICE_TREE ] ; then + echo 'ERROR: Missing device tree file' + exit 1 +fi + +# Size of OpenSBI and the Kernel in 512B blocks +DST_SIZE=$(ls -la --block-size=512 $DEVICE_TREE | cut -d' ' -f 5 ) +FW_JUMP_SIZE=$(ls -la --block-size=512 $FW_JUMP | cut -d' ' -f 5 ) +KERNEL_SIZE=$(ls -la --block-size=512 $LINUX_KERNEL | cut -d' ' -f 5 ) + +# Start sectors of OpenSBI and Kernel Partitions +FW_JUMP_START=$(( 34 + $DST_SIZE )) +KERNEL_START=$(( $FW_JUMP_START + $FW_JUMP_SIZE )) +FS_START=$(( $KERNEL_START + $KERNEL_SIZE )) + +# Print out the sizes of the binaries in 512B blocks +echo -e "$NAME: Device tree block size: $DST_SIZE" +echo -e "$NAME: OpenSBI FW_JUMP block size: $FW_JUMP_SIZE" +echo -e "$NAME: Kernel block size: $KERNEL_SIZE" + +read -p "Warning: " -n 1 -r +echo +if [[ $REPLY =~ ^[Yy]$ ]] ; then + # Make empty image + #echo -e "$NAME: Creating blank image" + #sudo dd if=/dev/zero of=$1 bs=4k conv=noerror status=progress && sync + + # GUID Partition Tables (GPT) + # =============================================== + # -g Converts any existing mbr record to a gpt record + # --clear clears any GPT partition table that already exists. + # --set-alignment=1 that we want to align partition starting sectors + # to 1 sector boundaries I think? This would normally be set to 2048 + # apparently. + + # sudo sgdisk -g --clear --set-alignment=1 \ + # --new=1:34:+$FW_JUMP_SIZE: --change-name=1:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + # --new=2:$KERNEL_START:+$KERNEL_SIZE --change-name=2:'kernel' --typecode=2:3000 \ + # --new=3:$FS_START:-0 --change-name=3:'filesystem' \ + # $1 + + echo -e "$NAME: Creating GUID Partition Table" + sudo sgdisk -g --clear --set-alignment=1 \ + --new=1:34:+$DST_SIZE: --change-name=1:'fdt' \ + --new=2:$FW_JUMP_START:+$FW_JUMP_SIZE --change-name=2:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + --new=3:$KERNEL_START:+$KERNEL_SIZE --change-name=3:'kernel' \ + --new=4:$FS_START:-0 --change-name=4:'filesystem' \ + $1 + + sudo partprobe $1 + + echo -e "$NAME: Copying binaries into their partitions." + DD_FLAGS="bs=4k iflag=fullblock oflag=direct conv=fsync status=progress" + + echo -e "$NAME: Copying device tree" + sudo dd if=$DEVICE_TREE of="$1"1 $DD_FLAGS + + echo -e "$NAME: Copying OpenSBI" + sudo dd if=$FW_JUMP of="$1"2 $DD_FLAGS + + echo -e "$NAME: Copying Kernel" + sudo dd if=$LINUX_KERNEL of="$1"3 $DD_FLAGS + + sudo mkfs.ext4 "$1"4 + sudo mkdir /mnt/$MNT_DIR + + sudo mount -v "$1"4 /mnt/$MNT_DIR + + sudo umount -v /mnt/$MNT_DIR + + sudo rmdir /mnt/$MNT_DIR + #sudo losetup -d $LOOPDEVICE +fi + +echo +echo "GPT Information for $1 ===================================" +sgdisk -p $1 diff --git a/linux/sdcard/make-img.sh b/linux/sdcard/make-img.sh new file mode 100755 index 000000000..a635d04db --- /dev/null +++ b/linux/sdcard/make-img.sh @@ -0,0 +1,110 @@ +#!/bin/bash + +# Exit on any error (return code != 0) +set -e + +# Output colors +GREEN='\033[1;32m' +NC='\033[0m' +NAME="$GREEN"${0:2}"$NC" + +# File location variables +RISCV=/opt/riscv +IMAGES=$RISCV/buildroot/output/images +FW_JUMP=$IMAGES/fw_jump.bin +LINUX_KERNEL=$IMAGES/Image +DEVICE_TREE=$IMAGES/wally-vcu108.dtb + +# Mount Directory +MNT_DIR=wallyimg + +if [ ! -z "$2" ] ; then + MNT_DIR=$2 +fi + +# If images are not built, exit +if [ ! -e $FW_JUMP ] || [ ! -e $LINUX_KERNEL ] ; then + echo 'ERROR: Missing images in buildroot output directory.' + echo ' Build images before running this script.' + exit 1 +fi + +if [ ! -e $DEVICE_TREE ] ; then + echo 'ERROR: Missing device tree file' + exit 1 +fi + +# Size of OpenSBI and the Kernel in 512B blocks +DST_SIZE=$(ls -la --block-size=512 $DEVICE_TREE | cut -d' ' -f 5 ) +FW_JUMP_SIZE=$(ls -la --block-size=512 $FW_JUMP | cut -d' ' -f 5 ) +KERNEL_SIZE=$(ls -la --block-size=512 $LINUX_KERNEL | cut -d' ' -f 5 ) + +# Start sectors of OpenSBI and Kernel Partitions +FW_JUMP_START=$(( 34 + $DST_SIZE )) +KERNEL_START=$(( $FW_JUMP_START + $FW_JUMP_SIZE )) +FS_START=$(( $KERNEL_START + $KERNEL_SIZE )) + +# Print out the sizes of the binaries in 512B blocks +echo -e "$NAME: Device tree block size: $DST_SIZE" +echo -e "$NAME: OpenSBI FW_JUMP block size: $FW_JUMP_SIZE" +echo -e "$NAME: Kernel block size: $KERNEL_SIZE" + +if [ ! -e $1 ] ; then + # Make empty image + echo -e "$NAME: Creating blank image" + sudo dd if=/dev/zero of=$1 bs=1M count=1536 + + # GUID Partition Tables (GPT) + # =============================================== + # -g Converts any existing mbr record to a gpt record + # --clear clears any GPT partition table that already exists. + # --set-alignment=1 that we want to align partition starting sectors + # to 1 sector boundaries I think? This would normally be set to 2048 + # apparently. + + # sudo sgdisk -g --clear --set-alignment=1 \ + # --new=1:34:+$FW_JUMP_SIZE: --change-name=1:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + # --new=2:$KERNEL_START:+$KERNEL_SIZE --change-name=2:'kernel' --typecode=2:3000 \ + # --new=3:$FS_START:-0 --change-name=3:'filesystem' \ + # $1 + + echo -e "$NAME: Creating GUID Partition Table" + sudo sgdisk -g --clear --set-alignment=1 \ + --new=1:34:+$DST_SIZE: --change-name=1:'fdt' \ + --new=2:$FW_JUMP_START:+$FW_JUMP_SIZE --change-name=2:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \ + --new=3:$KERNEL_START:+$KERNEL_SIZE --change-name=3:'kernel' \ + --new=4:$FS_START:-0 --change-name=4:'filesystem' \ + $1 + + LOOPDEVICE=$(sudo losetup -f) + echo -e "$NAME: Loop device: $LOOPDEVICE" + + sudo losetup --partscan $LOOPDEVICE $1 + + echo -e "$NAME: Copying binaries into their partitions." + DD_FLAGS="bs=4k iflag=fullblock oflag=direct conv=fsync status=progress" + # Store device tree in device tree partition + + echo -e "$NAME: Copying device tree" + sudo dd if=$DEVICE_TREE of="$LOOPDEVICE"p1 $DD_FLAGS + + echo -e "$NAME: Copying OpenSBI" + sudo dd if=$FW_JUMP of="$LOOPDEVICE"p2 $DD_FLAGS + + echo -e "$NAME: Copying Kernel" + sudo dd if=$LINUX_KERNEL of="$LOOPDEVICE"p3 $DD_FLAGS + + sudo mkfs.ext4 "$LOOPDEVICE"p4 + sudo mkdir /mnt/$MNT_DIR + + sudo mount -v "$LOOPDEVICE"p4 /mnt/$MNT_DIR + + sudo umount -v /mnt/$MNT_DIR + + sudo rmdir /mnt/$MNT_DIR + sudo losetup -d $LOOPDEVICE +fi + +echo +echo "GPT Information for $1 ===================================" +sgdisk -p $1 diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index d50b6c5bb..f9e9cb39d 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -96,6 +96,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[41] = 64'h40a7853b4015551b; ROM[42] = 64'h808210a7a02367c9;*/ + /* ROM[0] = 64'h8001819300002197; ROM[1] = 64'h4281420141014081; ROM[2] = 64'h4481440143814301; @@ -226,6 +227,151 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[127]= 64'h2000059346014681; ROM[128]= 64'h56e3cb5ff0ef4541; ROM[129]= 64'h00000000b711f005; + */ + + ROM[0]=64'h8001819300002197; + ROM[1]=64'h4281420141014081; + ROM[2]=64'h4481440143814301; + ROM[3]=64'h4681460145814501; + ROM[4]=64'h4881480147814701; + ROM[5]=64'h4a814a0149814901; + ROM[6]=64'h4c814c014b814b01; + ROM[7]=64'h4e814e014d814d01; + ROM[8]=64'h0110011b4f814f01; + ROM[9]=64'h059b45011161016e; + ROM[10]=64'h0004063705fe0010; + ROM[11]=64'h1f6000ef8006061b; + ROM[12]=64'h0ff003930000100f; + ROM[13]=64'h4e952e3110060e37; + ROM[14]=64'hc602829b0053f2b7; + ROM[15]=64'h2023fe02dfe312fd; + ROM[16]=64'h829b0053f2b7007e; + ROM[17]=64'hfe02dfe312fdc602; + ROM[18]=64'h4de31efd000e2023; + ROM[19]=64'h059bf1402573fdd0; + ROM[20]=64'h0000061705e20870; + ROM[21]=64'h0010029b01260613; + ROM[22]=64'h68110002806702fe; + ROM[23]=64'h0085179bf0080813; + ROM[24]=64'h038008130107f7b3; + ROM[25]=64'h480508a86c632781; + ROM[26]=64'h1533357902a87963; + ROM[27]=64'h38030000181700a8; + ROM[28]=64'h1c6301057833f268; + ROM[29]=64'h081a403018370808; + ROM[30]=64'h0105783342280813; + ROM[31]=64'h1815751308081063; + ROM[32]=64'h00367513c295e14d; + ROM[33]=64'h654ded510207e793; + ROM[34]=64'hc1701ff00613f130; + ROM[35]=64'h0637c530fff6861b; + ROM[36]=64'h664dcd10167d0200; + ROM[37]=64'h17fd001007b7c25c; + ROM[38]=64'h859b5a5cc20cd21c; + ROM[39]=64'h02062a23dfed0007; + ROM[40]=64'h4785fffd561c664d; + ROM[41]=64'h4501461c06f59063; + ROM[42]=64'h4a1cc35c465cc31c; + ROM[43]=64'he29dc75c4a5cc71c; + ROM[44]=64'h0c63086008138082; + ROM[45]=64'h1ae30a9008130105; + ROM[46]=64'hb7710017e793f905; + ROM[47]=64'he793b75901d7e793; + ROM[48]=64'h5f5c674db7410197; + ROM[49]=64'h66cd02072e23dffd; + ROM[50]=64'hfff78513ff7d5698; + ROM[51]=64'h40a0053300a03533; + ROM[52]=64'hbfb100a7e7938082; + ROM[53]=64'he0a2715d8082557d; + ROM[54]=64'he486f052f44ef84a; + ROM[55]=64'hfa13e85aec56fc26; + ROM[56]=64'h843289ae892a0086; + ROM[57]=64'h00959993000a1463; + ROM[58]=64'h864ac4396b054a85; + ROM[59]=64'h0009859b4549870a; + ROM[60]=64'h0004049b05540363; + ROM[61]=64'h86a66485008b7363; + ROM[62]=64'h870a87aaec7ff0ef; + ROM[63]=64'h4531458146014681; + ROM[64]=64'hf0ef0207c9639c05; + ROM[65]=64'h17820094979beb1f; + ROM[66]=64'h873e020541639381; + ROM[67]=64'h993e99ba020a1963; + ROM[68]=64'h870aa8094501f85d; + ROM[69]=64'he8bff0ef45454685; + ROM[70]=64'h60a64505fe0559e3; + ROM[71]=64'h79a2794274e26406; + ROM[72]=64'h61616b426ae27a02; + ROM[73]=64'h9301020497138082; + ROM[74]=64'hf40647057179b7f1; + ROM[75]=64'hd79867cdec26f022; + ROM[76]=64'hdff58b85571c674d; + ROM[77]=64'h2423d35c03600793; + ROM[78]=64'hfffd571c674d0207; + ROM[79]=64'h0007a737b00026f3; + ROM[80]=64'hb00027f311f70713; + ROM[81]=64'h674dfef77de38f95; + ROM[82]=64'h4f5ccf9d8b895b1c; + ROM[83]=64'h26f3cf5c0027e793; + ROM[84]=64'h071305f5e737b000; + ROM[85]=64'h8f95b00027f30ff7; + ROM[86]=64'h4f5c674dfef77de3; + ROM[87]=64'hb00026f3cf5c9bf5; + ROM[88]=64'h67f7071300989737; + ROM[89]=64'h7de38f95b00027f3; + ROM[90]=64'h458146014681fef7; + ROM[91]=64'hddbff0ef4501870a; + ROM[92]=64'h059346014681870a; + ROM[93]=64'hdcbff0ef45211aa0; + ROM[94]=64'h1aa007134782e939; + ROM[95]=64'h816393d117d24411; + ROM[96]=64'h85220ff0041302e7; + ROM[97]=64'h614564e270a27402; + ROM[98]=64'h46e3da5ff0efa0cd; + ROM[99]=64'h0207c7634782fe05; + ROM[100]=64'h458146014681870a; + ROM[101]=64'hd8bff0ef03700513; + ROM[102]=64'h46014681870a87aa; + ROM[103]=64'h0a900513403005b7; + ROM[104]=64'h4409bf7dfc07d9e3; + ROM[105]=64'hc3998b8583f9bfe1; + ROM[106]=64'h4681870a00846413; + ROM[107]=64'hf0ef450945814601; + ROM[108]=64'h870afa0540e3d59f; + ROM[109]=64'h123405b746014681; + ROM[110]=64'h46e3d45ff0ef450d; + ROM[111]=64'h870a77c14482f805; + ROM[112]=64'h85a6460146818cfd; + ROM[113]=64'h4ae3d2dff0ef451d; + ROM[114]=64'hd3d8470567cdf605; + ROM[115]=64'h000f4737b00026f3; + ROM[116]=64'hb00027f323f70713; + ROM[117]=64'h67cdfef77de38f95; + ROM[118]=64'h4681870a0007ae23; + ROM[119]=64'h0370051385a64601; + ROM[120]=64'hf2054fe3cf7ff0ef; + ROM[121]=64'h458146014681870a; + ROM[122]=64'hce3ff0ef08600513; + ROM[123]=64'h4681870af20545e3; + ROM[124]=64'h4541200005934601; + ROM[125]=64'hf0055de3ccfff0ef; + ROM[126]=64'h3023bf010113bf09; + ROM[127]=64'h4605842a86aa4081; + ROM[128]=64'h40113423850a4585; + ROM[129]=64'h86a265a6da5ff0ef; + ROM[130]=64'hd99ff0ef04084605; + ROM[131]=64'h2201358322813603; + ROM[132]=64'h86a2260508700513; + ROM[133]=64'hd81ff0ef05629e0d; + ROM[134]=64'h2a0135832a813603; + ROM[135]=64'h9e0d86a226054505; + ROM[136]=64'h3603d6bff0ef057e; + ROM[137]=64'h0513320135833281; + ROM[138]=64'h9e0d86a226054010; + ROM[139]=64'h3083d53ff0ef0556; + ROM[140]=64'h4501400134034081; + ROM[141]=64'h0000808241010113; + end // initial begin end // if (PRELOAD_ENABLED) end diff --git a/tests/custom/boot/bios.s b/tests/custom/boot/bios.s index 8057a277d..9a5d6e21f 100644 --- a/tests/custom/boot/bios.s +++ b/tests/custom/boot/bios.s @@ -87,7 +87,7 @@ delay2: # jump to the copied contents of the sd card. jumpToLinux: - csrrs a0, 0xF14, x0 # copy hard ID to a0 + csrrs a0, 0xF14, x0 # copy hart ID to a0 li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB la a2, end_of_bios li t0, 0x80000000 # start of code diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h index 0f75fbf9e..77d403145 100644 --- a/tests/custom/boot/boot.h +++ b/tests/custom/boot/boot.h @@ -15,9 +15,9 @@ typedef QWORD LBA_t; // These locations are copied from the generic configuration // of OpenSBI. These addresses can be found in: // buildroot/output/build/opensbi-0.9/platform/generic/config.mk -#define FDT_ADDRESS 0x80200000 // FW_JUMP_FDT_ADDR +#define FDT_ADDRESS 0x87000000 // FW_JUMP_FDT_ADDR #define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START -#define KERNEL_ADDRESS 0x82200000 // FW_JUMP_ADDR +#define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR // Export disk_read int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type);