diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv
index 145a016c0..3621ce7c0 100644
--- a/pipelined/src/generic/flop/simpleram.sv
+++ b/pipelined/src/generic/flop/simpleram.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 module simpleram #(parameter BASE=0, RANGE = 65535) (
-  input  logic             HCLK, HRESETn, 
+  input  logic             clk, 
   input  logic             HSELRam,
   input  logic [31:0]      HADDR,
   input  logic             HWRITE,
@@ -56,15 +56,15 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
 
   assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
 
-  flopenr #(32)   haddrreg(HCLK, 1'b0, 1'b1, HADDR, A);
+  flopenr #(32)   haddrreg(clk, 1'b0, 1'b1, HADDR, A);
   
   /* verilator lint_off WIDTH */
   if (`XLEN == 64)  begin:ramrw
-    always_ff @(posedge HCLK) begin
+    always_ff @(posedge clk) begin
       if (HWRITE & |HTRANS) RAM[A[31:3]] <= #1 HWDATA;
     end
   end else begin 
-    always_ff @(posedge HCLK) begin:ramrw
+    always_ff @(posedge clk) begin:ramrw
       if (HWRITE & |HTRANS) RAM[A[31:2]] <= #1 HWDATA;
     end
   end
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index a10cf24c8..4f437e2e0 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -235,21 +235,11 @@ module ifu (
 
     simpleram #(
         .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
-        .HCLK(clk), .HRESETn(~reset), 
+        .clk, 
         .HSELRam(1'b1), .HADDR(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
         .HWRITE(1'b0), .HREADY(1'b1),
         .HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
         .HRESPRam(), .HREADYRam());
-
-/* -----\/----- EXCLUDED -----\/-----
-    ram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
-        .HCLK(clk), .HRESETn(~reset), 
-        .HSELRam(1'b1), .HADDR(PCNextF[31:0]),
-        .HWRITE(1'b0), .HREADY(1'b1),
-        .HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
-        .HRESPRam(), .HREADYRam());
- -----/\----- EXCLUDED -----/\----- */
-
 	  assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
     assign BusStall = 0;
     assign IFUBusRead = 0;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 5a6991fd3..1192d62a3 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -246,7 +246,7 @@ module lsu (
 
   if (`MEM_DTIM) begin : dtim
     simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
-        .HCLK(clk), .HRESETn(~reset), 
+        .clk, 
         .HSELRam(1'b1), .HADDR(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
         .HWRITE(LSURWM[0]), .HREADY(1'b1),
         .HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),