diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0c0b398c3..10e36cbab 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -19,6 +19,7 @@ on: - 'bin/wally-tool-chain-install.sh' - 'bin/wally-distro-check.sh' - 'bin/wally-package-install.sh' + - '.github/workflows/install.yml' schedule: - cron: "0 7 * * 3" # Run at 12:00 AM Pacific Time on Wednesdays @@ -108,12 +109,12 @@ jobs: run: | if [ ${{ matrix.imageFamily }} == "debian" ]; then apt-get update - apt-get install -y sudo git + apt-get install -y git elif [ ${{ matrix.imageFamily }} == "redhat" ]; then - dnf install -y sudo git + dnf install -y git dnf install curl -y --allowerasing || true elif [ ${{ matrix.imageFamily }} == "suse" ]; then - zypper install -y sudo git + zypper install -y git fi # Only clone submodules needed for standard tests/regression to save space - uses: actions/checkout@v4 @@ -134,7 +135,9 @@ jobs: # Run main tool chain installation script, either as a user or system wide - name: Install run: | - if [ -z ${{ matrix.user }} ]; then + if [ ! -z ${{ matrix.image }} ]; then + ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + elif [ -z ${{ matrix.user }} ]; then sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} else sudo ./bin/wally-package-install.sh @@ -164,7 +167,7 @@ jobs: # Only the linux-testvectors are needed, so remove the rest of the buildroot to save space - name: Remove Buildroot to Save Space run: | - sudo rm -rf $RISCV/buildroot/output/build + rm -rf $RISCV/buildroot/output/build || sudo rm -rf $RISCV/buildroot/output/build df -h # Run standard regression, skipping distros that are known to be broken with Verilator - name: Regression diff --git a/.gitignore b/.gitignore index 1a8b66e80..f23aec9b5 100644 --- a/.gitignore +++ b/.gitignore @@ -34,6 +34,7 @@ tests/fp/combined_IF_vectors/IF_vectors/*.tv tests/custom/*/*/ tests/custom/*/*/*.memfile sim/tests/riscvdv +testbench/trek_files/uvm_output # Linux linux/buildroot diff --git a/Makefile b/Makefile index 52513a812..b03edea98 100644 --- a/Makefile +++ b/Makefile @@ -39,6 +39,11 @@ coverage: cvw-arch-verif: $(MAKE) -C ${WALLY}/addins/cvw-arch-verif +# Requires a license for the Breker tool. See tests/breker/README.md for details +breker: + $(MAKE) -C ${WALLY}/testbench/trek_files + $(MAKE) -C ${WALLY}/tests/breker + clean: $(MAKE) clean -C sim $(MAKE) clean -C ${WALLY}/tests/fp diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index efd70ce71..cdc400536 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit efd70ce71a352eb8c4ca3d3b63d06a7b076078cb +Subproject commit cdc4005363f7933971c97ec30ae84fbee59adb9f diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index a079bb263..832ab11c0 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca +Subproject commit 832ab11c093f332ef83ca9c0ef55845071a7cb3d diff --git a/bin/regression-wally b/bin/regression-wally index 09bd1fa9c..148ad777e 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -33,7 +33,7 @@ tests = [ "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb", - "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], + "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh", "arch32vm_sv32", "arch32pmp"]], ["rv64i", ["arch64i"]] ] @@ -60,7 +60,7 @@ tests64gc_nofp = [ ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb", "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz" + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64pmp"]] # add when working: "arch64zicboz" ] tests64gc_fp = [ @@ -291,7 +291,7 @@ def addTests(tests, sim): configs.append(tc) -def addTestsByDir(dir, config, sim, lockstepMode=0): +def addTestsByDir(dir, config, sim, lockstepMode=0, brekerMode=0): if os.path.isdir(dir): sim_logdir = WALLY+ "/sim/" + sim + "/logs/" if coverStr == "--fcov": # use --fcov in place of --lockstep @@ -312,6 +312,10 @@ def addTestsByDir(dir, config, sim, lockstepMode=0): cmdPrefix="wsim --lockstep --sim " + sim + " " + config gs="Mismatches : 0" fileEnd = ".elf" + elif brekerMode: + cmdPrefix="wsim --sim " + sim + " " + config + gs="# trek: info: summary: Test PASSED" + fileEnd = ".elf" else: cmdPrefix="wsim --sim " + sim + " " + config gs="Single Elf file tests are not signatured verified." @@ -397,6 +401,7 @@ parser.add_argument("--nightly", help="Run large nightly regression", action="st parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used +parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") args = parser.parse_args() @@ -441,7 +446,8 @@ elif (args.fcov): # run tests in lockstep in functional coverage mode addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim) - +elif (args.breker): + addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", brekerMode=1) else: for sim in sims: if (not (args.buildroot and sim == lockstepsim)): # skip short buildroot sim if running long one @@ -452,9 +458,9 @@ else: # run derivative configurations and lockstep tests in nightly regression if (args.nightly): - addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 1) - addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 1) - addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 1) + addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, lockstepMode=1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, lockstepMode=1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, lockstepMode=1) addTests(derivconfigtests, defaultsim) # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index de8c0ebc1..d7ca0a718 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -55,7 +55,7 @@ case "$FAMILY" in rhel) PYTHON_VERSION=python3.12 PACKAGE_MANAGER="dnf -y" - UPDATE_COMMAND="sudo $PACKAGE_MANAGER update" + UPDATE_COMMAND="$PACKAGE_MANAGER update" GENERAL_PACKAGES+=(which "$PYTHON_VERSION" "$PYTHON_VERSION"-pip pkgconf-pkg-config gcc-c++ ssmtp) GNU_PACKAGES+=(libmpc-devel mpfr-devel gmp-devel zlib-devel expat-devel libslirp-devel ninja-build) QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel) @@ -87,7 +87,7 @@ case "$FAMILY" in VERILATOR_PACKAGES+=(mold) fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get -y" - UPDATE_COMMAND="sudo $PACKAGE_MANAGER update && sudo $PACKAGE_MANAGER upgrade --with-new-pkgs" + UPDATE_COMMAND="$PACKAGE_MANAGER update && $PACKAGE_MANAGER upgrade --with-new-pkgs" GENERAL_PACKAGES+=("$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv pkg-config g++ ssmtp) GNU_PACKAGES+=(autotools-dev libmpc-dev libmpfr-dev libgmp-dev build-essential ninja-build zlib1g-dev libexpat1-dev libglib2.0-dev libslirp-dev) QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) @@ -100,7 +100,7 @@ case "$FAMILY" in PYTHON_VERSION=python3.12 PYTHON_VERSION_PACKAGE=python312 PACKAGE_MANAGER="zypper -n" - UPDATE_COMMAND="sudo $PACKAGE_MANAGER update" + UPDATE_COMMAND="$PACKAGE_MANAGER update" GENERAL_PACKAGES+=("$PYTHON_VERSION_PACKAGE" "$PYTHON_VERSION_PACKAGE"-pip pkg-config) GNU_PACKAGES+=(mpc-devel mpfr-devel gmp-devel zlib-devel libexpat-devel libslirp-devel ninja) QEMU_PACKAGES+=(glib2-devel libpixman-1-0-devel) # maybe also need qemu itself? @@ -132,32 +132,32 @@ else section_header "Installing/Updating Dependencies from Package Manager" # Enable extra repos necessary for rhel if [ "$FAMILY" == rhel ]; then - sudo dnf install -y dnf-plugins-core - sudo dnf group install -y "Development Tools" + dnf install -y dnf-plugins-core + dnf group install -y "Development Tools" if [ "$ID" == rhel ]; then - sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" - sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" + subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" + dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" else # RHEL clone if (( RHEL_VERSION == 8 )); then - sudo dnf config-manager -y --set-enabled powertools + dnf config-manager -y --set-enabled powertools else # Version 9 - sudo dnf config-manager -y --set-enabled crb + dnf config-manager -y --set-enabled crb fi - sudo dnf install -y epel-release + dnf install -y epel-release fi fi # Update and Upgrade tools eval "$UPDATE_COMMAND" # Install packages listed above using appropriate package manager - sudo $PACKAGE_MANAGER install "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" + eval $PACKAGE_MANAGER install "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" # Post install steps # Vivado looks for ncurses5 libraries, but Ubuntu 24.04 only has ncurses6 # Create symbolic links to the ncurses6 libraries to fool Vivado if (( UBUNTU_VERSION >= 24 )); then - sudo ln -vsf /lib/x86_64-linux-gnu/libncurses.so.6 /lib/x86_64-linux-gnu/libncurses.so.5 - sudo ln -vsf /lib/x86_64-linux-gnu/libtinfo.so.6 /lib/x86_64-linux-gnu/libntinfo.so.5 + ln -vsf /lib/x86_64-linux-gnu/libncurses.so.6 /lib/x86_64-linux-gnu/libncurses.so.5 + ln -vsf /lib/x86_64-linux-gnu/libtinfo.so.6 /lib/x86_64-linux-gnu/libntinfo.so.5 fi echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" diff --git a/bin/wsim b/bin/wsim index a89a546b7..843d4cfe6 100755 --- a/bin/wsim +++ b/bin/wsim @@ -50,21 +50,26 @@ def validateArgs(args): elif (args.tb == "testbench_fp" and args.sim != "questa"): print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") sys.exit(1) + elif (args.config == "breker" and args.sim != "questa"): + print("Error: Breker tests currently only supported by Questa") + sys.exit(1) def elfFileCheck(args): ElfFile = "" if os.path.isfile(args.elf): - ElfFile = f"+ElfFile={os.path.abspath(args.elf)}" + ElfFile = os.path.abspath(args.elf) elif args.elf: print(f"ELF file not found: {args.elf}") sys.exit(1) elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead if os.path.isfile(args.testsuite): - ElfFile = f"+ElfFile={os.path.abspath(args.testsuite)}" + ElfFile = os.path.abspath(args.testsuite) # extract the elf name from the path to be the test suite fields = args.testsuite.rsplit('/', 3) # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates. - if len(fields) > 3: + if "breker" in args.testsuite: + args.testsuite = fields[-1] + elif len(fields) > 3: if fields[2] == "ref": args.testsuite = f"{fields[1]}_{fields[3]}" else: @@ -89,7 +94,7 @@ def prepSim(args, ElfFile): if args.tb == "testbench_fp": paramsList.append(f'TEST="{args.testsuite}"') if ElfFile: - argsList.append(f"{ElfFile}") + argsList.append(f"+ElfFile={ElfFile}") if args.gui and args.tb == "testbench": paramsList.append("DEBUG=1") if args.ccov: @@ -105,6 +110,11 @@ def prepSim(args, ElfFile): if args.lockstep or args.lockstepverbose or args.fcov: prefix = lockstepSetup(args) defineList.append("+define+USE_IMPERAS_DV") + if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details + ElfFileNoExtension = os.path.splitext(ElfFile)[0] + flagsList.append("--breker") + defineList.append("+define+USE_TREK_DV") + argsList.append(f"+TREK_TBX_FILE={ElfFileNoExtension}.tbx") # Combine into a single string args.args += " ".join(argsList) args.params += " ".join(paramsList) diff --git a/config/derivlist.txt b/config/derivlist.txt index a82339cfc..c83fd60ec 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -1432,5 +1432,8 @@ UART_SUPPORTED 0 PLIC_SUPPORTED 0 SPI_SUPPORTED 0 - - +# Breker tests require a different memory configuration +# See tests/breker/README.md for details on the testsuite +derive breker rv64gc +EXT_MEM_SUPPORTED 1 +EXT_MEM_BASE 64'h90000000 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index db0838550..7b0f43913 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 1; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index af2032937..14c100a49 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 1; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index ccc194a27..20bddd5c0 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -26,6 +26,10 @@ `include "ZfaZfh_coverage.svh" `include "Zfh_coverage.svh" `include "ZfhD_coverage.svh" +// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled +`include "Zfhmin_coverage.svh" +// Note: Zmmul is a subset of M, so usually only one or the other would be used. +`include "Zmmul_coverage.svh" `include "Zicond_coverage.svh" `include "Zca_coverage.svh" `include "Zcb_coverage.svh" diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index ede534f0b..2eb40c8d4 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 0; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 0; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index e9f986a07..ec0563316 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd32; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 0; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 0; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 4f833178a..9c0bef1a1 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd64; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 1; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index d0ec96fb8..aa4e071fb 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -26,6 +26,10 @@ `include "ZfaZfh_coverage.svh" `include "ZfhD_coverage.svh" `include "Zfh_coverage.svh" +// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled +`include "Zfhmin_coverage.svh" +// Note: Zmmul is a subset of M, so usually only one or the other would be used. +`include "Zmmul_coverage.svh" `include "Zicond_coverage.svh" `include "Zca_coverage.svh" `include "Zcb_coverage.svh" diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 3a8bae1bc..1779d764d 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -31,7 +31,7 @@ localparam XLEN = 32'd64; // IEEE 754 compliance -localparam IEEE754 = 0; +localparam logic IEEE754 = 0; // RISC-V configuration per specification // Base instruction set (defaults to I if E is not supported) @@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; localparam logic BOOTROM_SUPPORTED = 0; localparam logic [63:0] BOOTROM_BASE = 64'h00001000; localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; +localparam logic BOOTROM_PRELOAD = 1'b0; localparam logic UNCORE_RAM_SUPPORTED = 0; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam logic UNCORE_RAM_PRELOAD = 1'b0; localparam logic EXT_MEM_SUPPORTED = 0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; @@ -178,7 +178,7 @@ localparam logic [63:0] PLIC_BASE = 64'h0C000000; localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; localparam logic SDC_SUPPORTED = 0; localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam logic [63:0] SDC_RANGE = 64'h00000FFF; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index a5ffb3c83..9df1e86c3 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -5,39 +5,36 @@ wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic MemRWM mmu/hptw.sv: logic SATP_REGW -uncore/uncore.sv: logic SDCCmd -uncore/uncore.sv: logic SDCCLK -uncore/uncore.sv: logic SDCIn -uncore/uncore.sv: logic SDCCS -uncore/spi_apb.sv: logic InterruptPending -uncore/spi_apb.sv: logic TransmitFIFOWriteInc -uncore/spi_apb.sv: logic TransmitFIFOEmpty -uncore/spi_apb.sv: logic TransmitFIFOReadInc -uncore/spi_apb.sv: logic TransmitLoad -uncore/spi_apb.sv: logic ShiftEdge -uncore/spi_apb.sv: logic SampleEdge -uncore/spi_apb.sv: logic ReceiveShiftReg -uncore/spi_apb.sv: logic TransmitReg -uncore/spi_apb.sv: logic ShiftIn -uncore/spi_apb.sv: logic EndOfFrame -uncore/spi_apb.sv: logic TransmitRegLoaded -uncore/spi_apb.sv: logic TransmitData -uncore/spi_apb.sv: logic ReceiveFIFOWriteInc -uncore/spi_apb.sv: logic ReceiveFIFOReadInc -uncore/spi_apb.sv: logic ReceiveShiftRegEndian -uncore/spi_apb.sv: logic ReceiveWatermark -uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel -uncore/spi_apb.sv: logic ReceiveData -uncore/spi_apb.sv: logic ReceiveFIFOFull -uncore/spi_apb.sv: logic ReceiveFIFOEmpty -uncore/spi_controller.sv: logic SCLKenable -uncore/spi_controller.sv: statetype CurrState -uncore/spi_controller.sv: statetype NextState -uncore/spi_controller.sv: logic BitNum -uncore/spi_controller.sv: logic ContinueTransmit -uncore/spi_controller.sv: logic PhaseOneOffset -uncore/spi_controller.sv: logic SPICLK -uncore/spi_fifo.sv: logic rptr -uncore/spi_fifo.sv: logic rptrnext -uncore/spi_fifo.sv: logic raddr -uncore/spi_fifo.sv: logic waddr +uncore/uartPC16550D.sv : logic MCR +uncore/uartPC16550D.sv : logic FCR +uncore/uartPC16550D.sv : logic MSR +uncore/uartPC16550D.sv : logic DTRb +uncore/uartPC16550D.sv : logic INTR +uncore/uartPC16550D.sv : logic RXRDYb +uncore/uartPC16550D.sv : logic TXRDYb +uncore/uartPC16550D.sv : logic RXerrIP +uncore/uartPC16550D.sv : logic IER +uncore/uartPC16550D.sv : logic LSR +uncore/uartPC16550D.sv : logic SCR +uncore/uartPC16550D.sv : statetype txstate +uncore/uartPC16550D.sv : logic RBR +uncore/uartPC16550D.sv : logic rxparityerr +uncore/uartPC16550D.sv : logic LCR +uncore/uartPC16550D.sv : logic intrID +uncore/uartPC16550D.sv : logic rxdataavailintr +uncore/uartPC16550D.sv : logic fifoenabled +uncore/uartPC16550D.sv : logic rxfifoentries +uncore/uartPC16550D.sv : logic txsrfull +uncore/uartPC16550D.sv : logic txhrfull +uncore/uartPC16550D.sv : logic txfifofull +uncore/uartPC16550D.sv : logic txfifotail +uncore/uartPC16550D.sv : logic txfifohead +uncore/uartPC16550D.sv : logic rxfifotriggered +uncore/uartPC16550D.sv : logic rxdataready +privileged/privdec.sv : logic wfiM +privileged/privdec.sv : logic wfiW +privileged/privdec.sv : logic WFITimeoutM +uncore/plic_apb.sv : logic requests +uncore/plic_apb.sv : logic intInProgress +uncore/plic_apb.sv : logic intPending +uncore/plic_apb.sv : logic intClaim diff --git a/fpga/constraints/marked_debug_spi.txt b/fpga/constraints/marked_debug_spi.txt index c840f6b99..a5ffb3c83 100644 --- a/fpga/constraints/marked_debug_spi.txt +++ b/fpga/constraints/marked_debug_spi.txt @@ -5,32 +5,39 @@ wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic MemRWM mmu/hptw.sv: logic SATP_REGW -uncore/spi_apb.sv: logic ShiftIn -uncore/spi_apb.sv: logic ReceiveShiftReg -uncore/spi_apb.sv: logic SCLKenable -uncore/spi_apb.sv: logic SampleEdge -uncore/spi_apb.sv: logic Active -uncore/spi_apb.sv: statetype state -uncore/spi_apb.sv: typedef rsrstatetype -uncore/spi_apb.sv: logic SPICLK -uncore/spi_apb.sv: logic SPIOut -uncore/spi_apb.sv: logic SPICS -uncore/spi_apb.sv: logic SckMode -uncore/spi_apb.sv: logic SckDiv +uncore/uncore.sv: logic SDCCmd +uncore/uncore.sv: logic SDCCLK +uncore/uncore.sv: logic SDCIn +uncore/uncore.sv: logic SDCCS +uncore/spi_apb.sv: logic InterruptPending +uncore/spi_apb.sv: logic TransmitFIFOWriteInc +uncore/spi_apb.sv: logic TransmitFIFOEmpty +uncore/spi_apb.sv: logic TransmitFIFOReadInc +uncore/spi_apb.sv: logic TransmitLoad uncore/spi_apb.sv: logic ShiftEdge -uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle -uncore/spi_apb.sv: logic TransmitShiftReg +uncore/spi_apb.sv: logic SampleEdge +uncore/spi_apb.sv: logic ReceiveShiftReg +uncore/spi_apb.sv: logic TransmitReg +uncore/spi_apb.sv: logic ShiftIn +uncore/spi_apb.sv: logic EndOfFrame +uncore/spi_apb.sv: logic TransmitRegLoaded uncore/spi_apb.sv: logic TransmitData -uncore/spi_apb.sv: logic ReceiveData +uncore/spi_apb.sv: logic ReceiveFIFOWriteInc +uncore/spi_apb.sv: logic ReceiveFIFOReadInc uncore/spi_apb.sv: logic ReceiveShiftRegEndian -uncore/spi_apb.sv: logic TransmitShiftReg -uncore/spi_apb.sv: logic TransmitShift -uncore/spi_apb.sv: logic ReceiveShiftFullDelay -uncore/spi_apb.sv: logic TransmitShiftEmpty -uncore/spi_apb.sv: logic ReceiveFIFOWriteFull -uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement -uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty -uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement -uncore/spi_apb.sv: logic TransmitFIFOReadIncrement -uncore/spi_apb.sv: logic TransmitFIFOWriteFull -uncore/spi_apb.sv: logic TransmitFIFOReadEmpty +uncore/spi_apb.sv: logic ReceiveWatermark +uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel +uncore/spi_apb.sv: logic ReceiveData +uncore/spi_apb.sv: logic ReceiveFIFOFull +uncore/spi_apb.sv: logic ReceiveFIFOEmpty +uncore/spi_controller.sv: logic SCLKenable +uncore/spi_controller.sv: statetype CurrState +uncore/spi_controller.sv: statetype NextState +uncore/spi_controller.sv: logic BitNum +uncore/spi_controller.sv: logic ContinueTransmit +uncore/spi_controller.sv: logic PhaseOneOffset +uncore/spi_controller.sv: logic SPICLK +uncore/spi_fifo.sv: logic rptr +uncore/spi_fifo.sv: logic rptrnext +uncore/spi_fifo.sv: logic raddr +uncore/spi_fifo.sv: logic waddr diff --git a/fpga/constraints/marked_debug_uart.txt b/fpga/constraints/marked_debug_uart.txt new file mode 100644 index 000000000..4ac6b1bc6 --- /dev/null +++ b/fpga/constraints/marked_debug_uart.txt @@ -0,0 +1,33 @@ +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic MemRWM +mmu/hptw.sv: logic SATP_REGW +uncore/uartPC16550D.sv : logic MCR +uncore/uartPC16550D.sv : logic FCR +uncore/uartPC16550D.sv : logic MSR +uncore/uartPC16550D.sv : logic DTRb +uncore/uartPC16550D.sv : logic INTR +uncore/uartPC16550D.sv : logic RXRDYb +uncore/uartPC16550D.sv : logic TXRDYb +uncore/uartPC16550D.sv : logic RXerrIP +uncore/uartPC16550D.sv : logic IER +uncore/uartPC16550D.sv : logic LSR +uncore/uartPC16550D.sv : logic SCR +uncore/uartPC16550D.sv : statetype txstate +uncore/uartPC16550D.sv : logic RBR +uncore/uartPC16550D.sv : logic rxparityerr +uncore/uartPC16550D.sv : logic LCR +uncore/uartPC16550D.sv : logic intrID +uncore/uartPC16550D.sv : logic rxdataavailintr +uncore/uartPC16550D.sv : logic fifoenabled +uncore/uartPC16550D.sv : logic rxfifoentries +uncore/uartPC16550D.sv : logic txsrfull +uncore/uartPC16550D.sv : logic txhrfull +uncore/uartPC16550D.sv : logic txfifofull +uncore/uartPC16550D.sv : logic txfifotail +uncore/uartPC16550D.sv : logic txfifohead +uncore/uartPC16550D.sv : logic rxfifotriggered +uncore/uartPC16550D.sv : logic rxdataready diff --git a/fpga/constraints/small-debug-uart.xdc b/fpga/constraints/small-debug-uart.xdc new file mode 100644 index 000000000..01e8f9199 --- /dev/null +++ b/fpga/constraints/small-debug-uart.xdc @@ -0,0 +1,208 @@ +create_debug_core u_ila_0 ila + + + + +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets CPUCLK] + +set_property port_width 33 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 5 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[4]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[3]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/DTRb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]] + + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe13] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/TXRDYb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXerrIP} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 11 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[7]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[8]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[9]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[10]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe26] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxparityerr} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe27] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe28] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe29] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataavailintr} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe32] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] +connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe33] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] +connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe34] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] +connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe35] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] +connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]] + + +# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. +#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] +connect_debug_port dbg_hub/clk [get_nets CPUCLK] diff --git a/fpga/constraints/small-debug-wfi.xdc b/fpga/constraints/small-debug-wfi.xdc new file mode 100644 index 000000000..e87f3bce9 --- /dev/null +++ b/fpga/constraints/small-debug-wfi.xdc @@ -0,0 +1,191 @@ +create_debug_core u_ila_0 ila + + + + +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets CPUCLK] + +set_property port_width 33 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiM} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiW} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]] + + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe13] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/WFITimeoutM} ]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[12]}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe26] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe27] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe28] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe29] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]] + + + + +# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. +#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] +connect_debug_port dbg_hub/clk [get_nets CPUCLK] diff --git a/fpga/generator/debug/plic.tsm b/fpga/generator/debug/plic.tsm new file mode 100644 index 000000000..13edad457 --- /dev/null +++ b/fpga/generator/debug/plic.tsm @@ -0,0 +1,32 @@ +################################################## +# +# For info on creating trigger state machines: +# 1) In the main Vivado menu bar, select +# Window > Language Templates +# 2) In the Templates window, select +# Debug > Trigger State Machine +# 3) Refer to the entry 'Info' for an overview +# of the trigger state machine language. +# +# More information can be found in this document: +# +# Vivado Design Suite User Guide: Programming +# and Debugging (UG908) +# +################################################## +state state_reset: + if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h200) then + goto state_1; + else + goto state_reset; + endif + +state state_1: + if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h000) then + goto state_trigger; + else + goto state_1; + endif + +state state_trigger: + trigger; diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 7935b5913..29e3a5a92 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -98,7 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { #source ../constraints/small-debug.xdc #source ../constraints/small-debug-rvvi.xdc - #source ../constraints/small-debug-spi.xdc + source ../constraints/small-debug-wfi.xdc } else { #source ../constraints/vcu-small-debug.xdc #source ../constraints/small-debug.xdc diff --git a/fpga/zsbl/Makefile b/fpga/zsbl/Makefile index 8ba2b84d2..581a9496b 100644 --- a/fpga/zsbl/Makefile +++ b/fpga/zsbl/Makefile @@ -117,8 +117,6 @@ $(TARGET).memfile: $(TARGET) @echo 'Making memory file' riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@ extractFunctionRadix.sh $<.objdump - mkdir -p ../../imperas-riscv-tests/work/rv64BP/ - cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ @echo 'Splitting memfile.' ./splitfile.sh $@ mv boot.mem ../src/boot.mem diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 626d02837..945cb6ef4 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -63,8 +63,13 @@ set CoverageVsimArg "" set FunctCoverage 0 set FCvlog "" +set breker 0 +set brekervlog "" +set brekervopt "" + set lockstep 0 set lockstepvlog "" + set SVLib "" set GUI 0 @@ -121,7 +126,18 @@ if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" - set SVLib "-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model" + set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " +} + +# if --breker found set flag and remove from list +# Requires a license for the breker tool. See tests/breker/README.md for details +if {[lcheck lst "--breker"]} { + set breker 1 + set BREKER_HOME $::env(BREKER_HOME) + set brekervlog "+incdir+${WALLY}/testbench/trek_files \ + ${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv" + set brekervopt "${WKDIR}.trek_uvm" + append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek " } # Set PlusArgs passed using the --args flag @@ -155,6 +171,7 @@ if {$DEBUG > 0} { echo "ccov = $ccov" echo "lockstep = $lockstep" echo "FunctCoverage = $FunctCoverage" + echo "Breker = $breker" echo "remaining list = $lst" echo "Extra +args = $PlusArgs" echo "Extra params = $ExpandedParamArgs" @@ -167,11 +184,11 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286,2605,2250 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} +vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg} diff --git a/site-setup.sh b/site-setup.sh index 4699ff348..81f17fff2 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -15,6 +15,7 @@ export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change thi export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys DC, excluding bin export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin +export BREKER_HOME=/cad/breker/trek5-2.1.10b-GCC6_el7 # Change this for your path to Breker Trek # Tools # Questa and Synopsys diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 85796f060..a53392fc9 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -118,7 +118,7 @@ module mmu import cvw::*; #(parameter cvw_t P, if (P.PMP_ENTRIES > 0) begin : pmp pmpchecker #(P) pmpchecker(.PhysicalAddress, .PrivilegeModeW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .CMOpM, + .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .Size, .CMOpM, .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); end else begin assign PMPInstrAccessFaultF = 1'b0; @@ -131,7 +131,7 @@ module mmu import cvw::*; #(parameter cvw_t P, // Misaligned faults always_comb // exclusion-tag: immu-wordaccess - case(Size[1:0]) + case(Size) 2'b00: DataMisalignedM = 1'b0; // lb, sb, lbu 2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu 2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 71a6b890a..fab15b24d 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -35,9 +35,11 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) ( input logic [P.PA_BITS-1:0] PhysicalAddress, input logic [7:0] PMPCfg, input logic [P.PA_BITS-3:0] PMPAdr, + input logic FirstMatch, input logic PAgePMPAdrIn, output logic PAgePMPAdrOut, output logic Match, + output logic [P.PA_BITS-1:0] PMPTop, output logic L, X, W, R ); @@ -50,7 +52,8 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) ( logic PAltPMPAdr; logic [P.PA_BITS-1:0] CurrentAdrFull; logic [1:0] AdrMode; - + logic [P.PA_BITS-1:0] PMPTop1; + assign AdrMode = PMPCfg[4:3]; // The two lsb of the physical address don't matter for this checking. @@ -71,20 +74,22 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) ( assign NAMask[P.PA_BITS-1:2] = (PMPAdr + {{(P.PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr; // form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region. // This assumes we're using at least an NA4 region, but works for any size NAPOT region. - assign NABase = {(PMPAdr & ~NAMask[P.PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. - + assign NABase = {(PMPAdr & ~NAMask[P.PA_BITS-1:2]), 2'b00}; // base physical address of the pmp region assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range + // finally pick the appropriate match for the access type assign Match = (AdrMode == TOR) ? TORMatch : (AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch : 1'b0; + // Report top of region for first matching region + assign PMPTop1 = {PMPAdr,2'b00} | NAMask; // top of the pmp region. All 1s in the lower bits. Used to check the address doesn't pass the top + assign PMPTop = FirstMatch ? PMPTop1 : '0; // AND portion of distributed AND-OR mux (OR portion in pmpchhecker) + + // PMP should match but fail if the size is too big (8-byte accesses spanning to TOR or NA4 region) assign L = PMPCfg[7]; assign X = PMPCfg[2]; assign W = PMPCfg[1]; assign R = PMPCfg[0]; - // known bug: The size of the access is not yet checked. For example, if an NA4 entry matches 0xC-0xF and the system - // attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This - // implementation will not detect the failure. - endmodule +endmodule diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index a55e137ef..27f8745fe 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -43,6 +43,7 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], input logic ExecuteAccessF, WriteAccessM, ReadAccessM, + input logic [1:0] Size, input logic [3:0] CMOpM, output logic PMPInstrAccessFaultF, output logic PMPLoadAccessFaultM, @@ -55,29 +56,55 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( logic [P.PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address. logic [P.PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set logic [P.PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] + logic [P.PA_BITS-1:0] PMPTop[P.PMP_ENTRIES-1:0]; // Upper end of each region, for checking that the access is fully within the region logic PMPCMOAccessFault, PMPCBOMAccessFault, PMPCBOZAccessFault; - + logic [2:0] SizeBytesMinus1; + logic MatchingR, MatchingW, MatchingX, MatchingL; + logic [P.PA_BITS-1:0] MatchingPMPTop, PhysicalAddressTop; + logic TooBig; if (P.PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0 pmpadrdec #(P) pmpadrdecs[P.PMP_ENTRIES-1:0]( .PhysicalAddress, .PMPCfg(PMPCFG_ARRAY_REGW), .PMPAdr(PMPADDR_ARRAY_REGW), + .FirstMatch, .PAgePMPAdrIn({PAgePMPAdr[P.PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), - .Match, .L, .X, .W, .R); + .Match, .PMPTop, .L, .X, .W, .R); end priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. - // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); + // Distributed AND-OR mux to select the first matching results + // If the access does not match all bytes of the PMP region, it is too big and the matches are disabled + assign MatchingR = |(R & FirstMatch) & ~TooBig; + assign MatchingW = |(W & FirstMatch) & ~TooBig; + assign MatchingX = |(X & FirstMatch) & ~TooBig; + assign MatchingL = |(L & FirstMatch); + or_rows #(P.PMP_ENTRIES, P.PA_BITS) PTEOr(PMPTop, MatchingPMPTop); - assign PMPCBOMAccessFault = EnforcePMP & (|CMOpM[2:0]) & ~|((R|W) & FirstMatch) ; // exclusion-tag: immu-pmpcbom - assign PMPCBOZAccessFault = EnforcePMP & CMOpM[3] & ~|(W & FirstMatch) ; // exclusion-tag: immu-pmpcboz + // Matching PMP entry must match all bytes of an access, or the access fails (Priv Spec 3.7.1.3) + // First find the size of the access in terms of the offset to the most significant byte + always_comb + case (Size) + 2'b00: SizeBytesMinus1 = 3'd0; + 2'b01: SizeBytesMinus1 = 3'd1; + 2'b10: SizeBytesMinus1 = 3'd3; + 2'b11: SizeBytesMinus1 = 3'd7; + endcase + // Then find the top of the access and see if it is beyond the top of the region + assign PhysicalAddressTop = PhysicalAddress + {{P.PA_BITS-3{1'b0}}, SizeBytesMinus1}; // top of the access range + assign TooBig = PhysicalAddressTop > MatchingPMPTop; // check if the access goes beyond the top of the PMP region + + // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region + assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | MatchingL; + + assign PMPCBOMAccessFault = EnforcePMP & (|CMOpM[2:0]) & ~MatchingR ; // checking R is sufficient because W implies R in PMP // exclusion-tag: immu-pmpcbom + assign PMPCBOZAccessFault = EnforcePMP & CMOpM[3] & ~MatchingW ; // exclusion-tag: immu-pmpcboz assign PMPCMOAccessFault = PMPCBOZAccessFault | PMPCBOMAccessFault; // exclusion-tag: immu-pmpcboaccess - - assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; - assign PMPStoreAmoAccessFaultM = (EnforcePMP & WriteAccessM & ~|(W & FirstMatch)) | PMPCMOAccessFault; // exclusion-tag: immu-pmpstoreamoaccessfault - assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~WriteAccessM & ~|(R & FirstMatch) ; + + assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~MatchingX ; + assign PMPStoreAmoAccessFaultM = (EnforcePMP & WriteAccessM & ~MatchingW) | PMPCMOAccessFault; // exclusion-tag: immu-pmpstoreamoaccessfault + assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~WriteAccessM & ~MatchingR; endmodule diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index 9bd3b8148..4bc7501f9 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -61,6 +61,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( logic TLBAccess; logic ImproperPrivilege; logic BadPBMT, BadNAPOT, BadReserved; + logic ReservedRW; logic InvalidAccess; logic PreUpdateDA, PrePageFault; @@ -88,6 +89,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( assign BadPBMT = ((PTE_PBMT != 0) & ~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE)) | PTE_PBMT == 3; // PBMT must be zero if not supported; value of 3 is reserved assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region assign BadReserved = PTE_RESERVED; // Reserved bits must be zero + assign ReservedRW = PTE_W & ~PTE_R; // page fault on reserved encoding with R=0, W=1 per Privileged Spec 10.3.1 // Check whether the access is allowed, page faulting if not. if (ITLB == 1) begin:itlb // Instruction TLB fault checking @@ -95,9 +97,9 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( // only execute non-user mode pages. assign ImproperPrivilege = ((PrivilegeModeW == P.U_MODE) & ~PTE_U) | ((PrivilegeModeW == P.S_MODE) & PTE_U); assign PreUpdateDA = ~PTE_A; - assign InvalidAccess = ~PTE_X; + assign InvalidAccess = ~PTE_X | ReservedRW; end else begin:dtlb // Data TLB fault checking - logic InvalidRead, InvalidWrite, ReservedEncoding; + logic InvalidRead, InvalidWrite; logic InvalidCBOM, InvalidCBOZ; // User mode may only load/store from user mode pages, and supervisor mode @@ -112,8 +114,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( assign InvalidWrite = WriteAccess & ~PTE_W; assign InvalidCBOM = (|CMOpM[2:0]) & (~PTE_R & (~STATUS_MXR | ~PTE_X)); assign InvalidCBOZ = CMOpM[3] & ~PTE_W; - assign ReservedEncoding = PTE_W & ~PTE_R; // fault on reserved encoding with R=0, W=1 to match ImperasDV behavior - assign InvalidAccess = InvalidRead | InvalidWrite | InvalidCBOM | InvalidCBOZ | ReservedEncoding; + assign InvalidAccess = InvalidRead | InvalidWrite | InvalidCBOM | InvalidCBOZ | ReservedRW; assign PreUpdateDA = ~PTE_A | WriteAccess & ~PTE_D; end diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 3b329705d..a252bbd23 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -51,6 +51,6 @@ module tlbram import cvw::*; #(parameter cvw_t P, or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry); // Rename the bits read from the TLB RAM - assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bitss + assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits assign PPN = PageTableEntry[P.PPN_BITS+9:10]; endmodule diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 1cdfd7d85..8716ce63c 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -121,7 +121,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7]; else assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01); - + assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~ADDRLocked[i]; flopenr #(P.PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[P.PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]); if (P.XLEN==64) begin @@ -134,7 +134,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign CSRPMPWRLegalizedWriteValM[i] = {(CSRPMPWriteValM[i][1] & CSRPMPWriteValM[i][0]), CSRPMPWriteValM[i][0]}; // legalize WR fields (reserved 10 written as 00) assign CSRPMPLegalizedWriteValM[i] = {CSRPMPWriteValM[i][7], 2'b00, CSRPMPWriteValM[i][4:2], CSRPMPWRLegalizedWriteValM[i]}; - flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRPMPWriteValM[i], PMPCFG_ARRAY_REGW[i]); + flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRPMPLegalizedWriteValM[i], PMPCFG_ARRAY_REGW[i]); end end diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index f74fb3d06..0261fa137 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -23,7 +23,7 @@ `define NUM_REGS 32 `define NUM_CSRS 4096 -`define STD_LOG 1 +`define STD_LOG 0 `define PRINT_PC_INSTR 0 `define PRINT_MOST 0 `define PRINT_ALL 0 @@ -45,6 +45,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic InstrValidM, InstrValidW; logic StallE, StallM, StallW; logic GatedStallW; + logic SelHPTW; logic FlushD, FlushE, FlushM, FlushW; logic TrapM, TrapW; logic HaltM, HaltW; @@ -66,11 +67,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic InterruptM, InterruptW; //For VM Verification - logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW; - logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; - logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; - logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW; - logic [1:0] PageType_iM, PageType_iW, PageType_dM, PageType_dW; + logic [(P.XLEN-1):0] IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW; + logic [(P.XLEN-1):0] IPTEF,IPTED,IPTEE,IPTEM,IPTEW,DPTEM,DPTEW; + logic [(P.PA_BITS-1):0] IPAF,IPAD,IPAE,IPAM,IPAW,DPAM,DPAW; + logic [(P.PPN_BITS-1):0] IPPNF,IPPND,IPPNE,IPPNM,IPPNW,DPPNM,DPPNW; + logic [1:0] IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; @@ -91,7 +92,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign StallE = testbench.dut.core.StallE; assign StallM = testbench.dut.core.StallM; assign StallW = testbench.dut.core.StallW; - assign GatedStallW = testbench.dut.core.lsu.GatedStallW; + assign GatedStallW = testbench.dut.core.lsu.GatedStallW; + assign SelHPTW = testbench.dut.core.lsu.hptw.hptw.SelHPTW; assign FlushD = testbench.dut.core.FlushD; assign FlushE = testbench.dut.core.FlushE; assign FlushM = testbench.dut.core.FlushM; @@ -113,19 +115,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end //For VM Verification - assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; - assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; - assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; - assign PADM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; + assign IVAdrF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; + assign DVAdrM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; + assign IPAF = testbench.dut.core.ifu.immu.immu.PhysicalAddress; + assign DPAM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM; assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM; assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF; - assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE; - assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; - assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; - assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - assign PageType_iM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; - assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; + assign IPTEF = testbench.dut.core.ifu.immu.immu.PTE; + assign DPTEM = testbench.dut.core.lsu.dmmu.dmmu.PTE; + assign IPPNF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; + assign DPPNM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; + assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; + assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; logic valid; @@ -360,28 +362,43 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); //for VM Verification - flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); //Virtual Address for IMMU - flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); //Virtual Address for DMMU + flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD + flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU + flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU + flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW - flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); //Physical Address for IMMU - flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); //Physical Address for DMMU + flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD + flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU + flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU + flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); //PTE for IMMU - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); //PTE for DMMU + flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD + flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU + flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU + flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW - flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); //Page Type (kilo, mega, giga, tera) from IMMU - flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); //Page Type (kilo, mega, giga, tera) from DMMU + flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~StallD + flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU + flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW + flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW - flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU - flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU + flopenrc #(P.PPN_BITS) IPPNDReg (clk, reset, 1'b0, ~StallD, IPPNF, IPPND); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) IPPNEReg (clk, reset, 1'b0, ~StallE, IPPND, IPPNE); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) IPPNMReg (clk, reset, 1'b0, ~StallM, IPPNE, IPPNM); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) IPPNWReg (clk, reset, 1'b0, ~StallW, IPPNM, IPPNW); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) DPPNWReg (clk, reset, 1'b0, ~StallW, DPPNM, DPPNW); //Physical Page Number for DMMU - flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess - flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess + flopenrc #(1) ReadAccessWReg (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess + flopenrc #(1) WriteAccessWReg (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess - flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access - flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access - flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access - flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessDReg (clk, reset, 1'b0, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessEReg (clk, reset, 1'b0, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessMReg (clk, reset, 1'b0, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessWReg (clk, reset, 1'b0, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 40f5410ef..8ba10b292 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -46,6 +46,14 @@ module testbench; parameter RVVI_SYNTH_SUPPORTED=0; parameter MAKE_VCD=0; + // TREK Requires a license for the Breker tool. See tests/breker/README.md for details + `ifdef USE_TREK_DV + event trek_start; + always @(testbench.trek_start) begin + trek_uvm_pkg::trek_uvm_events::do_backdoor_init(); + end + `endif + `ifdef USE_IMPERAS_DV import idvPkg::*; import rvviApiPkg::*; @@ -137,7 +145,9 @@ module testbench; "arch64i": tests = arch64i; "arch64priv": tests = arch64priv; "arch64c": if (P.ZCA_SUPPORTED) - if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; + if (P.ZICSR_SUPPORTED) + if (P.ZCD_SUPPORTED) tests = {arch64c, arch64cpriv, arch64zcd}; + else tests = {arch64c, arch64cpriv}; else tests = {arch64c}; "arch64m": if (P.M_SUPPORTED) tests = arch64m; "arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo; @@ -164,7 +174,9 @@ module testbench; "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; - "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; + "arch64zfh": if (P.ZFH_SUPPORTED) + if (P.D_SUPPORTED) tests = {arch64zfh, arch64zfh_d}; + else tests = arch64zfh; "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; "arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; @@ -184,7 +196,11 @@ module testbench; "arch32i": tests = arch32i; "arch32priv": tests = arch32priv; "arch32c": if (P.C_SUPPORTED) - if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; + if (P.ZICSR_SUPPORTED) + if (P.ZCF_SUPPORTED) + if (P.ZCD_SUPPORTED) tests = {arch32c, arch32cpriv, arch32zcf, arch32zcd}; + else tests = {arch32c, arch32cpriv, arch32zcf}; + else tests = {arch32c, arch32cpriv}; else tests = {arch32c}; "arch32m": if (P.M_SUPPORTED) tests = arch32m; "arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo; @@ -208,7 +224,9 @@ module testbench; "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; - "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; + "arch32zfh": if (P.ZFH_SUPPORTED) + if (P.D_SUPPORTED) tests = {arch32zfh, arch32zfh_d}; + else tests = arch32zfh; "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; @@ -412,7 +430,11 @@ module testbench; end else if (TEST == "coverage64gc") begin $display("%s ran. Coverage tests don't get checked", tests[test]); end else if (ElfFile != "none") begin - $display("Single Elf file tests are not signatured verified."); + `ifdef USE_TREK_DV + $display("Breker test is done."); + `else + $display("Single Elf file tests are not signatured verified."); + `endif `ifdef QUESTA $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug `else @@ -519,6 +541,10 @@ module testbench; end else begin $fclose(uncoreMemFile); $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM); + `ifdef USE_TREK_DV + -> trek_start; + $display("starting Trek...."); + `endif end end if (TEST == "embench") $display("Read memfile %s", memfilename); diff --git a/testbench/tests.vh b/testbench/tests.vh index 59cd84437..923327986 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -194,69 +194,78 @@ string arch32pmp[] = '{ "rv32i_m/pmp32/src/pmp-TOR-X.S" }; +// Tests commented out pending riscv-arch-test issue #588 string arch64pmp[] = '{ `RISCVARCHTEST, - "rv64i_m/pmp64/pmp64-CFG-reg.S", - "rv64i_m/pmp64/pmp64-CSR-access.S", - "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-R-priority.S", - "rv64i_m/pmp64/pmp64-NA4-R.S", - "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-RW-priority.S", - "rv64i_m/pmp64/pmp64-NA4-RW.S", - "rv64i_m/pmp64/pmp64-NA4-RWX.S", - "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-RX-priority.S", - "rv64i_m/pmp64/pmp64-NA4-RX.S", - "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NA4-X-priority.S", - "rv64i_m/pmp64/pmp64-NA4-X.S", - "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-R.S", - "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-RW.S", - "rv64i_m/pmp64/pmp64-NAPOT-RWX.S", - "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-RX.S", - "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S", - "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S", - "rv64i_m/pmp64/pmp64-NAPOT-X.S", - "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S", - "rv64i_m/pmp64/pmp64-TOR-R-priority.S", - "rv64i_m/pmp64/pmp64-TOR-R.S", - "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S", - "rv64i_m/pmp64/pmp64-TOR-RW-priority.S", - "rv64i_m/pmp64/pmp64-TOR-RW.S", - "rv64i_m/pmp64/pmp64-TOR-RWX.S", - "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S", - "rv64i_m/pmp64/pmp64-TOR-RX-priority.S", - "rv64i_m/pmp64/pmp64-TOR-RX.S", - "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S", - "rv64i_m/pmp64/pmp64-TOR-X-priority.S", - "rv64i_m/pmp64/pmp64-TOR-X.S" + "rv64i_m/pmp64/src/pmp64-CFG-reg.S", + "rv64i_m/pmp64/src/pmp64-CSR-access.S", + "rv64i_m/pmp64/src/pmp64-NA4-R-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-R-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-R.S", + "rv64i_m/pmp64/src/pmp64-NA4-RW-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-RW-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-RW.S", + "rv64i_m/pmp64/src/pmp64-NA4-RWX.S", + "rv64i_m/pmp64/src/pmp64-NA4-RX-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-RX-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-RX.S", + "rv64i_m/pmp64/src/pmp64-NA4-X-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NA4-X-priority.S", + "rv64i_m/pmp64/src/pmp64-NA4-X.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-R-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-R-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-R.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RW-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RW-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RW.S", + // "rv64i_m/pmp64/src/pmp64-NAPOT-RWX.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RX-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RX-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-RX.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-X-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-X-priority.S", + "rv64i_m/pmp64/src/pmp64-NAPOT-X.S", + "rv64i_m/pmp64/src/pmp64-TOR-R-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-TOR-R-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-R.S", + "rv64i_m/pmp64/src/pmp64-TOR-RW-priority-level-2..S", + "rv64i_m/pmp64/src/pmp64-TOR-RW-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-RW.S", + // "rv64i_m/pmp64/src/pmp64-TOR-RWX.S", + "rv64i_m/pmp64/src/pmp64-TOR-RX-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-TOR-RX-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-RX.S", + "rv64i_m/pmp64/src/pmp64-TOR-X-priority-level-2.S", + "rv64i_m/pmp64/src/pmp64-TOR-X-priority.S", + "rv64i_m/pmp64/src/pmp64-TOR-X.S" }; string arch32vm_sv32[] = '{ `RISCVARCHTEST, + "rv32i_m/vm_sv32/src/mstatus_tvm_test.S", "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S", "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S", "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S", "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S", + "rv32i_m/vm_sv32/src/satp_access_tests.S", "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S", "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S", "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S", "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S", "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S", "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_S_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_U_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S", "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S", "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S", "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S", "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S", - "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S", - "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S", "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S", "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S", "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S", @@ -528,6 +537,15 @@ string arch64cpriv[] = '{ "rv64i_m/C/src/cebreak-01.S" }; +// Tests commented out pending riscv-arch-test issue #590 +string arch64zcd[] = '{ + // `RISCVARCHTEST, + "rv64i_m/D_Zcd/src/c.fld-01.S", + "rv64i_m/D_Zcd/src/c.fldsp-01.S", + "rv64i_m/D_Zcd/src/c.fsd-01.S", + "rv64i_m/D_Zcd/src/c.fsdsp-01.S" +}; + string arch64i[] = '{ `RISCVARCHTEST, "rv64i_m/I/src/add-01.S", @@ -1000,10 +1018,23 @@ string arch64zfh[] = '{ "rv64i_m/Zfh/src/fadd_b7-01.S", "rv64i_m/Zfh/src/fadd_b8-01.S", "rv64i_m/Zfh/src/fclass_b1-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b1-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b22-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b23-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b24-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b27-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b28-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b29-01.S", "rv64i_m/Zfh/src/fcvt.h.w_b25-01.S", "rv64i_m/Zfh/src/fcvt.h.w_b26-01.S", "rv64i_m/Zfh/src/fcvt.h.wu_b25-01.S", "rv64i_m/Zfh/src/fcvt.h.wu_b26-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b29-01.S", "rv64i_m/Zfh/src/fcvt.w.h_b1-01.S", "rv64i_m/Zfh/src/fcvt.w.h_b22-01.S", "rv64i_m/Zfh/src/fcvt.w.h_b23-01.S", @@ -1130,7 +1161,23 @@ string arch64zfh[] = '{ "rv64i_m/Zfh/src/fnmsub_b8-01.S" }; - +string arch64zfh_d[] = '{ + // `RISCVARCHTEST, + "rv64i_m/Zfh/src/fcvt.d.h_b1-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b29-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b1-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b22-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b23-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b24-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b27-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b28-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b29-01.S" +}; string arch64d_fma[] = '{ `RISCVARCHTEST, @@ -2413,10 +2460,23 @@ string arch32zfh[] = '{ "rv32i_m/Zfh/src/fadd_b7-01.S", "rv32i_m/Zfh/src/fadd_b8-01.S", "rv32i_m/Zfh/src/fclass_b1-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b1-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b22-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b23-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b24-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b27-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b28-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b29-01.S", "rv32i_m/Zfh/src/fcvt.h.w_b25-01.S", "rv32i_m/Zfh/src/fcvt.h.w_b26-01.S", "rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S", "rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b22-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b23-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b24-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b27-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b28-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b29-01.S", "rv32i_m/Zfh/src/fcvt.w.h_b1-01.S", "rv32i_m/Zfh/src/fcvt.w.h_b22-01.S", "rv32i_m/Zfh/src/fcvt.w.h_b23-01.S", @@ -2525,6 +2585,24 @@ string arch32zfh[] = '{ "rv32i_m/Zfh/src/fnmsub_b8-01.S" }; +string arch32zfh_d[] = '{ + // `RISCVARCHTEST, + "rv32i_m/Zfh/src/fcvt.d.h_b1-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b22-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b23-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b24-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b27-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b28-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b29-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b1-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b22-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b23-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b24-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b27-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b28-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b29-01.S" +}; + string arch32zfaf[] = '{ `RISCVARCHTEST, "rv32i_m/F_Zfa/src/fround_b1-01.S", @@ -3353,6 +3431,23 @@ string arch32cpriv[] = '{ "rv32i_m/C/src/cebreak-01.S" }; +// Tests commented out pending riscv-arch-test issue #590 +string arch32zcf[] = '{ + // `RISCVARCHTEST, + // "rv32i_m/F_Zcf/src/c.flw-01.S", + // "rv32i_m/F_Zcf/src/c.flwsp-01.S", + // "rv32i_m/F_Zcf/src/c.fsw-01.S", + "rv32i_m/F_Zcf/src/c.fswsp-01.S" +}; + +// Tests commented out pending riscv-arch-test issue #590 +string arch32zcd[] = '{ + // `RISCVARCHTEST, + "rv32i_m/D_Zcd/src/c.fld-01.S", + // "rv32i_m/D_Zcd/src/c.fldsp-01.S", + "rv32i_m/D_Zcd/src/c.fsd-01.S", + "rv32i_m/D_Zcd/src/c.fsdsp-01.S" +}; string arch32i[] = '{ `RISCVARCHTEST, diff --git a/testbench/trek_files/Makefile b/testbench/trek_files/Makefile new file mode 100644 index 000000000..62a045af2 --- /dev/null +++ b/testbench/trek_files/Makefile @@ -0,0 +1,14 @@ +SHELL := /bin/bash +TREKFILES := $(WALLY)/testbench/trek_files +PLATFORM_YAML := $(TREKFILES)/platform.yaml +TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml +TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation +TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) + +uvm_output: uvm_output/trek_uvm.sv + +uvm_output/trek_uvm.sv: $(PLATFORM_YAML) $(TREKSVIP_YAML) + $(TREKSVIP) -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) --uvm_output=uvm_output + +clean: + rm -rf uvm_output diff --git a/testbench/trek_files/README.md b/testbench/trek_files/README.md new file mode 100644 index 000000000..1c7c14b38 --- /dev/null +++ b/testbench/trek_files/README.md @@ -0,0 +1,9 @@ +Jordan Carlin, jcarlin@hmc.edu, December 2024 + +# Breker Trek Tests Support Files for CVW + +[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users). + +This directory contains the support files necessary to run Breker's Trek Tests on CVW. For additional details on the tests see [`$WALLY/tests/breker/README.md`](../../tests/breker/README.md) + +To generate the Breker support files (with a license), run `make` in the `testbench/trek_files` directory (this one). Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. This Makefile only needs to be run once. diff --git a/testbench/trek_files/breker-setup.sh b/testbench/trek_files/breker-setup.sh new file mode 100644 index 000000000..9b651eeef --- /dev/null +++ b/testbench/trek_files/breker-setup.sh @@ -0,0 +1,5 @@ +#!/bin/bash +export BREKER_ARCH=${BREKER_HOME}/linux64 +export PATH=${BREKER_HOME}/bin:${BREKER_HOME}/examples/tutorials/apps/coherency/bin:${PATH} +export LD_LIBRARY_PATH=".:${BREKER_ARCH}/lib:${BREKER_HOME}/opensrc/gcc/lib:${BREKER_HOME}/opensrc/gcc/lib64":${LD_LIBRARY_PATH} +export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu/:$LIBRARY_PATH diff --git a/testbench/trek_files/customer.yaml b/testbench/trek_files/customer.yaml new file mode 100644 index 000000000..e06733797 --- /dev/null +++ b/testbench/trek_files/customer.yaml @@ -0,0 +1,27 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 5 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + # uncomment the `weights:` line below if any entries under `weights:` need to be enabled + # weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + + diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml new file mode 100644 index 000000000..d7f7b8dad --- /dev/null +++ b/testbench/trek_files/platform.yaml @@ -0,0 +1,263 @@ +trek: + platform_config: + doc: >- + Testbench platform specific configuration. + processors: + doc: >- + Information about available processors. + processor_count: + value: 1 + doc: >- + How many processors can be used by the generated test case + sw_threads_per_processor: + value: 2 + doc: >- + How many software threads to put on each processor + tlm_generic_ports: + doc: >- + Information about available tlm_generic_payload ports + port_count: + value: 0 + doc: >- + How many tlm ports to use for memory operations + threads_per_port: + value: 4 + doc: >- + How many threads to put on each tlm port + debug: + value: 1 + doc: >- + Turn on for verbose tlm port messages + memories: + doc: >- + Information about memory regions that can be used by the generated test case. + defaults: + doc: >- + Default values for all memories + natural_alignment: + value: 1 + doc: >- + Should all memory addresses be naturally aligned (up to 8 byte alignment) + init_type: + value: frontdoor + doc: >- + Strategy to use for memory initialization. + Options are: + - static + - backdoor + - frontdoor + memory: + doc: >- + Define a memory region. + Multiple memory regions may be defined in this section. + name: + value: ddr0 + doc: >- + Name of the memory region + base: + value: 0x83000000 + doc: >- + Base address of memory region. + Ignored for `static` initialized memory + size: + value: 0x100000 + doc: >- + Size of memory region in bytes. + init_type: + value: backdoor #frontdoor + doc: >- + Strategy to use for memory initialization. + Options are: + - static + - backdoor + - frontdoor + caches: + doc: >- + parameters related to cache architecture + cache_line_size: + value: 64 + doc: >- + Size of a cache line in bytes + llc_cache_size: + value: 0x200000 + doc: >- + size of last level cache in bytes + llc_cache_ways: + value: 8 + doc: >- + number of ways in the last level cache + mailbox: + doc: >- + Configure memory mailbox usage + type: + value: single + doc: >- + Configure mailbox type. + Options are: + - single: for use by TrekBox with backdoor access + - queue: for use in post-silicon post-process flow + single: + doc: >- + Detail settings when mailbox type is `single` + init_type: + value: backdoor #static + doc: >- + Strategy to use for mailbox memory initialization. + Options are: + - static + - backdoor + - frontdoor + c2t_base: + value: 0x82000000 + doc: >- + Fixed base address of C to trekbox mailbox region. + Allow 64 bytes per processor. + Used for init_type of `backdoor` and `frontdoor` only. + t2c_base: + value: 0x82001000 + doc: >- + Fixed base address of trekbox to C mailbox region. + Allow 64 bytes per processor. + Used for init_type of `backdoor` and `frontdoor` only. + cacheable: + value: 1 + doc: >- + Set this parameter to 1 to do a cache flush after every mailbox + write. + queue: + doc: >- + Detail settings when mailbox type is `queue` + length: + value: 1000 + doc: >- + Max number of messages that can be stored in the queue mailbox. + Longer tests may need a larger queue. + debug: + value: 0 + doc: >- + If this flag is set to 1, messages will be printed directly to the + console instead of being queued in memory. + stdio: + doc: >- + Is the standard library available for use by the generated test. + available: + value: 0 + doc: >- + Set this value to 0 of the library is not available in + your system. + use_lock: + value: 1 + doc: >- + Calls to console print messages will be mutex locked unless + this flag is set to 0. + header: + doc: >- + Verbatim code that will be put into the header section of the test. + value: |- + + declaration: + doc: >- + Verbatim code that will be put into the declaration section of the test. + value: |- + extern void tohost_exit(int status); + + #undef trek_exit + #define trek_exit(status) tohost_exit(status); + + int main(void) + { + return trek_main(); + } + + mmu: # Trek can generate code to program page/translation tables + # that you MAY want to use with your SDV generated C files. + # Here, you have some control over that process. + + va_bits: 39 # How many bits are used for virtual addresses + # + # For aarch64, the value here is used to determine the + # "initial lookup level" (as detailed in Table D5-13). + # This must correlate to TCR_EL3.T0SZ! + # + # For riscv64, only 39, 48, and 57 are supported + # corresponding to "Sv39", "Sv48", and "Sv57". + # + # default: 39 [from T0SZ=64-39=25(0x19)] + + memory_map: # A *MAP* of all memory regions, excluding the + # memory_resources in your platformConfig.h file. + # + # Each map entry should be a unique name. + # + # Mandatory submap pairs: + # normal: *true*/false (false = "device"/"io" memory) + # begin: starting address + # end: ending address + # + # Optional submap pairs: + # readable: *true*/false + # writeable: *true*/false + # executable: true/*false* + # cacheable: *true*/false (*false* for device) + # share_type (aarch64 only): *inner-shareable*, + # outer-shareable, non-shareable + # + # Note that memory_resources will use all defaults. + # + # Note that "normal: false" (device-memory) change defaults + # to "cacheable = false", and on arch64 it implies + # share_type = non-shareable, and alloc_type = no-allocate + + UART0: + type: device + begin: 0x10000000 + end: 0x10000fff + + code: + type: normal + begin: 0x80000000 + end: 0x807fffff + executable: true + + stack: + type: normal + begin: 0x87000000 + end: 0x87ffffff + + + aarch64: # Customizations that are only valid for aarch64. + + TCR_EL3: 0x80923519 # Should Trek to program the TCR_TL3 register? If + # so, put the value here. If not, comment out + # this option. + # NOTE: T0SZ should correlate to va_bits above! + # default: -no default- + + allocate_type: read-write-allocate # Default allocate_type. + # read-allocate, write-allocate, + # *read-write-allocate*, no-allocate + + cache_type: write-back-nontransient # non-cacheable, + # write-through-transient, + # write-back-transient, + # write-through-non-transient, + # *write-back-non-transient* + + device_type: nGnRnE # *nGnRnE*, nGnRE, nGRE, GRE + + share_type: inner-shareable # non-shareable + # inner-shareable + # outer-shareable + + riscv64: # Customizations that are only valid for riscv64. + + Svnapot: false # If standard extension "Svnapot" is implemented, and + # when you are using Sv39, you might set this to "true" + # to allow PTE bit[63] "N" to be set when appropriate. + # default: false + + Svpbmt: true # If standard extension "Svpbmt" is implemented, and + # when you are using Sv39, you might set this to "true" + # to allow cacheable/device information to flow into + # bits[62:61] "PBMT" as appropriate. + # default: false diff --git a/testbench/trek_files/trek_user_backdoor.sv b/testbench/trek_files/trek_user_backdoor.sv new file mode 100644 index 000000000..342ade7b9 --- /dev/null +++ b/testbench/trek_files/trek_user_backdoor.sv @@ -0,0 +1,91 @@ +/// custom routines defined for the platform + +// Design parameters, used in the code below and custom to this design! +//`define RAM_PATH soc_top.soc_instance.i_sram_subsystem.i_shared_ram +//sim:/testbench/dut/uncore/uncore/ram/ram/memory/RAM +//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory.RAM +//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory +`define RAM_PATH testbench.dut.uncoregen.uncore.ram.ram.memory.ram +//`define RAM_BASE_ADDR 32'h80000000 +`define RAM_BASE_ADDR testbench.P.UNCORE_RAM_BASE + +// These two routines are specific to a particular design. They are used +// to read and write to the "mailbox" locations, to synchronize behaviors +// between C code on the processors with activity performed in UVM (and +// among activities in UVM). +// +// Every design will be different. Here we just have a simple Verilog +// array that we can read and write. +// +function automatic void trek_backdoor_read64( + input longint unsigned address, + output longint unsigned data, + input int unsigned debug = 1); + + //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2; + bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8)); + if (address[1:0] != 2'b00) begin: misaligned + $display("%t trek_backdoor_read64: Misaligned address", $time); + $finish(); + end + + //data[63:32] = `RAM_PATH[offset + 0]; + //data[31: 0] = `RAM_PATH[offset + 1]; + data[63:0] = `RAM_PATH.RAM[offset + 0]; +if (data != 0) + $display("%t trek_backdoor_read64: Read 64'h%016h from address 64'h%016h", + $time, data, address); +endfunction: trek_backdoor_read64 + + +function automatic void trek_backdoor_write64( + input longint unsigned address, + input longint unsigned data, + input int unsigned debug = 1); + + //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2; + bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8)); + + if (address[1:0] != 2'b00) begin: misaligned + $display("%t trek_backdoor_write64: Misaligned address", $time); + $finish(); + end + //`RAM_PATH[offset + 0] = data[63:32]; + //`RAM_PATH[offset + 1] = data[31: 0]; + `RAM_PATH.RAM[offset + 0] = data[63:0]; + //$display("%t trek_backdoor_write64: Wrote 64'h%016h to address 64'h%016h", + //$time, data, address); +endfunction: trek_backdoor_write64 + + +// For performance, we want to read mailboxes ONLY when they're written to! +// (This is very important on emulators!) +// +// Here we trigger a signal when a memory write happens to the range of +// addresses where the mailboxes are. +// +// A clock later, we go poll all the mailboxes (using the "backdoor_read" +// method above. +// +// Each design will be different, depending on where you are able to snoop +// for writes and how long it takes a write to propagate from that point +// to the place where the backdoor read will find it. + +bit trek_c2t_mbox_event; +bit trek_is_event_addr; + +//assign trek_is_event_addr = +// ((((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) >= `TREK_C2T_MBOX_BASE) && +// (((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) < `TREK_C2T_MBOX_LIMIT)); +// +//always_ff @(posedge `RAM_PATH.clk) begin: trigger_reading_of_mailboxes +// trek_c2t_mbox_event <= (trek_is_event_addr && +// (`RAM_PATH.n_cs == 1'b0) && +// (`RAM_PATH.n_we == 1'b0)); +//end + +// Design specifc: one stage delayed so write has a time to settle +//always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes +always @(posedge testbench.clk) begin: read_all_mailboxes + trek_poll_mbox(); +end diff --git a/tests/breker/Makefile b/tests/breker/Makefile new file mode 100644 index 000000000..fc56d8805 --- /dev/null +++ b/tests/breker/Makefile @@ -0,0 +1,53 @@ +SHELL := /bin/bash + +# Breker/Trek paths and variables +TESTDIR := $(WALLY)/tests/breker/work +TREKFILES := $(WALLY)/testbench/trek_files +CONSTRAINTS_DIR := $(WALLY)/tests/breker/constraints +PLATFORM_YAML := $(TREKFILES)/platform.yaml +CUSTOMER_YAML := $(TREKFILES)/customer.yaml +TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml +CONSTRAINT_FILES := $(shell find $(CONSTRAINTS_DIR) -type f) +TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation +TREKSVIP := source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) + +# Compilation paths and variables +START_LIB_DIR := $(WALLY)/examples/C/common +START_LIB := $(START_LIB_DIR)/crt.S $(START_LIB_DIR)/syscalls.c +MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval +MABI :=-mabi=lp64d +LINKER := $(START_LIB_DIR)/test.ld +LINK_FLAGS := -nostartfiles +CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU +WIDTH := 64 + +# Find all constraint files and generate tests for each one +TESTS = $(patsubst $(CONSTRAINTS_DIR)/%.yaml,$(TESTDIR)/%,$(CONSTRAINT_FILES)) +.PHONY: all clean +all: $(TESTS) + +# Generate c tests +$(TESTDIR)/%: $(CONSTRAINTS_DIR)/%.yaml | $(TESTDIR) + $(TREKSVIP) -p $< -p $(CUSTOMER_YAML) -o $@/$* -e pss_top.entry + $(MAKE) $@/$*.elf.memfile + +# Compile c code +.PRECIOUS: %.elf +%.elf: %.c + riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -T$(LINKER) -I$(START_LIB_DIR) $(START_LIB) -g -o $@ $< > /dev/null + +# Convert elf to hex +%.elf.memfile: %.elf + riscv64-unknown-elf-objdump -D $< > $<.objdump + riscv64-unknown-elf-elf2hex --bit-width $(WIDTH) --input $< --output $@ + extractFunctionRadix.sh $<.objdump + +# View the model graph TODO: What does this do? Move to another makefile? +%.view_graph: $(CONSTRAINTS_DIR)/%.yaml + $(TREKSVIP) -p $(CONSTRAINTS_DIR)/$^.yaml -p $(CUSTOMER_YAML) -t pss_top.entry + +$(TESTDIR): + mkdir -p $(TESTDIR) + +clean: + rm -rf $(TESTS) diff --git a/tests/breker/README.md b/tests/breker/README.md new file mode 100644 index 000000000..300ebc16e --- /dev/null +++ b/tests/breker/README.md @@ -0,0 +1,18 @@ +Jordan Carlin, jcarlin@hmc.edu, December 2024 + +# Breker Tests for CVW + +[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users). + +To generate the Breker tests (with a license), run `make` in both the `tests/breker` and `testbench/trek_files` directories. Alternatively, running `make breker` from the top-level `$WALLY` directory will run both of these. Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. The `testbench/trek_files` Makefile only needs to be run once, but the tests that are generated can be different each time so rerunning the `tests/breker` Makefile is worthwhile. + +This will generate a testsuite for each of the constraint yaml files in the `constraints` directory. These generated tests are produced in the `tests/breker/work` directory. To run a single test use `wsim` to run the elf. The `breker` configuration must be used. For example, + +```bash +$ wsim breker $WALLY/tests/breker/riscv/riscv.elf +``` + +To run all of the generated Breker tests use +```bash +$ regression-wally --breker +``` diff --git a/tests/breker/constraints/atomics.yaml b/tests/breker/constraints/atomics.yaml new file mode 100644 index 000000000..c505b957d --- /dev/null +++ b/tests/breker/constraints/atomics.yaml @@ -0,0 +1,73 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + pss_top.dekker.dekkerTest: 0 + # pss_top.atomics.atomicsTest: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/coherency.yaml b/tests/breker/constraints/coherency.yaml new file mode 100644 index 000000000..62908c90c --- /dev/null +++ b/tests/breker/constraints/coherency.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/dekker.yaml b/tests/breker/constraints/dekker.yaml new file mode 100644 index 000000000..052c7e02d --- /dev/null +++ b/tests/breker/constraints/dekker.yaml @@ -0,0 +1,73 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + # pss_top.dekker.dekkerTest: 0 + pss_top.atomics.atomicsTest: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/hello.yaml b/tests/breker/constraints/hello.yaml new file mode 100644 index 000000000..94b30664d --- /dev/null +++ b/tests/breker/constraints/hello.yaml @@ -0,0 +1,58 @@ +# Constraint file to generate simple hello world test that checks the +# initialized values for a few memory locations. + +# This constraint file disable all features other than the +trek: + svip: + global: + scenarios: + scenario_count: + # reduce number of scenarios + value: 2 + memory_allocation: + memory_sets: + block_size: + # force 4 byte operation + min: 4 + max: 4 + block_count: + # force a single memory block + min: 1 + max: 1 + riscv: + extensions: + # disable hypervisor extension + # if your system does not support this feature + h_hypervisor: + value: 0 + coherency: + cacheline_states: + scenario_length: + # minimize scenario length + min: 1 + max: 1 + weights: + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off memory workload tests + # pss_top.workload.entry: 0 + + # turn of various cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of micro loop feature + pss_top.microLoops.microLoopScn: 0 + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + diff --git a/tests/breker/constraints/microloops.yaml b/tests/breker/constraints/microloops.yaml new file mode 100644 index 000000000..b8502b0f6 --- /dev/null +++ b/tests/breker/constraints/microloops.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/mmu.yaml b/tests/breker/constraints/mmu.yaml new file mode 100644 index 000000000..2b2dbac44 --- /dev/null +++ b/tests/breker/constraints/mmu.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + # pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/riscv.yaml b/tests/breker/constraints/riscv.yaml new file mode 100644 index 000000000..7e8a6c0d1 --- /dev/null +++ b/tests/breker/constraints/riscv.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + # pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + # pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/test.yaml b/tests/breker/constraints/test.yaml new file mode 100644 index 000000000..fdf3e294b --- /dev/null +++ b/tests/breker/constraints/test.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + # weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + # pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + + + # turn off RV64 opcode tests + # pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + # pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/workload.yaml b/tests/breker/constraints/workload.yaml new file mode 100644 index 000000000..61f641ea5 --- /dev/null +++ b/tests/breker/constraints/workload.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + pss_top.microLoops.microLoopScn: 0 diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 0b07212cc..281f58a7b 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: # ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x4000112D + reset-val: 0x4014112D rv32: accessible: true mxl: @@ -24,6 +24,6 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x000112D, 0x0000000] + - extensions[25:0] bitmask [0x014112D, 0x0000000] wr_illegal: - Unchanged \ No newline at end of file