From 90b2a4882f0313ef48c58fc52f89a072535dcdd8 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 29 Apr 2023 05:58:40 -0700
Subject: [PATCH 1/2] Fixed redundant check of SupportedFmt on fmv that caused
 coverage problem on fctrl

---
 src/fpu/fctrl.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index 206cefbb4..3252e0d9f 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -138,9 +138,9 @@ module fctrl (
                                   endcase
                       7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)          
                                                 ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass
-                                  else if (Funct3D == 3'b000 & Rs2D == 5'b00000 & SupportedFmt) 
+                                  else if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
                                                 ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w/d/h/q  fp to int register
-                      7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000 & SupportedFmt) 
+                      7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
                                                 ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w/d/h/q.x  int to fp reg
                       7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
                                                 ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)

From d5b718be384b58c750fd3de8148da54000b80603 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 1 May 2023 08:14:19 -0700
Subject: [PATCH 2/2] IMMU exclude non word-sized accesses

---
 sim/coverage-exclusions-rv64gc.do | 7 +++++++
 src/mmu/mmu.sv                    | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do
index 88116aa3d..ff9faeb59 100644
--- a/sim/coverage-exclusions-rv64gc.do
+++ b/sim/coverage-exclusions-rv64gc.do
@@ -201,6 +201,13 @@ coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $l
 set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"] 
 coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
 
+# IMMU only makes word-sized accesses
+set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"] 
+set line2 [expr $line + 6 ]
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
+
 # Excluding reset and clear for impossible case in the wficountreg in privdec
 set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
 coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index ccbbfaf78..380787e6b 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -128,7 +128,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
   assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss;
 
   // Misaligned faults
-   always_comb
+   always_comb // exclusion-tag: immu-wordaccess
     case(Size[1:0]) 
       2'b00:  DataMisalignedM = 0;                 // lb, sb, lbu
       2'b01:  DataMisalignedM = VAdr[0];           // lh, sh, lhu