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https://github.com/openhwgroup/cvw
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Added tests for full coverage of the FPU result sign module
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@ -32,10 +32,19 @@ main:
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csrs mstatus, t0
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csrs mstatus, t0
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#Pull denormalized FP number from memory and pass it to fclass.S for coverage
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#Pull denormalized FP number from memory and pass it to fclass.S for coverage
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la t0, TestData
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la t0, TestData1
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flw ft0, 0(t0)
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flw ft0, 0(t0)
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fclass.s t1, ft0
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fclass.s t1, ft0
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#Result Sign Test Coverage
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la t0, TestData2
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flw ft0, 0(t0)
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flw ft1, 4(t0)
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fadd.s ft2, ft0, ft1 #Adds coverage for inf as arg for FADD
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flw ft2, 4(t0)
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fmsub.s ft3, ft0, ft1, ft2 #Adds coverage for fmaAs or Z Sign Bit
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# Test legal instructions not covered elsewhere
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# Test legal instructions not covered elsewhere
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flq ft0, 0(a0)
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flq ft0, 0(a0)
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flh ft0, 8(a0)
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flh ft0, 8(a0)
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@ -105,5 +114,8 @@ main:
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.section .data
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.section .data
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.align 3
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.align 3
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TestData:
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TestData1:
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.int 0x00100000 #Denormalized FP number
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.int 0x00100000 #Denormalized FP number
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TestData2:
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.word 0x60000001 #Random FP Number (Pos)
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.word 0x7f800000 #INF
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