From 6988c8c37cffe852a8183e214dd0b1e65447b219 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 10 Oct 2021 10:55:02 -0700
Subject: [PATCH] divider control signal simplificaiton

---
 wally-pipelined/src/muldiv/intdivrestoring.sv | 19 ++++++++++---------
 wally-pipelined/src/muldiv/muldiv.sv          |  6 ++----
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv
index 4ca12f4be..327a37b6b 100644
--- a/wally-pipelined/src/muldiv/intdivrestoring.sv
+++ b/wally-pipelined/src/muldiv/intdivrestoring.sv
@@ -32,9 +32,9 @@ module intdivrestoring (
   input  logic reset,
   input  logic StallM, FlushM,
   input  logic DivSignedE, W64E,
-  input  logic DivStartE,
+  input  logic DivE,
   input  logic [`XLEN-1:0] SrcAE, SrcBE,
-  output logic BusyE, DivDoneM,
+  output logic DivBusyE, 
   output logic [`XLEN-1:0] QuotM, RemM
  );
 
@@ -44,7 +44,8 @@ module intdivrestoring (
   localparam STEPBITS = $clog2(`XLEN/`DIV_BITSPERCYCLE);
   logic [STEPBITS:0] step;
   logic Div0E, Div0M;
-  logic DivInitE, SignXE, SignXM, SignDE, SignDM, NegWM, NegQM;
+  logic DivStartE, SignXE, SignXM, SignDE, SignDM, NegWM, NegQM;
+  logic BusyE, DivDoneM;
 
   logic [`XLEN-1:0] WNextE, XQNextE;
  
@@ -54,6 +55,9 @@ module intdivrestoring (
   //flopen #(`XLEN) xsavereg(~clk, DivStartE, SrcAE, XSavedE);
  // flopen #(`XLEN) dsavereg(~clk, DivStartE, SrcBE, DSavedE); 
 
+  assign DivStartE = DivE & ~BusyE & ~DivDoneM; 
+  assign DivBusyE = BusyE | DivStartE;
+
   // Handle sign extension for W-type instructions
   generate
     if (`XLEN == 64) begin // RV64 has W-type instructions
@@ -112,26 +116,23 @@ module intdivrestoring (
   mux3 #(`XLEN) qmux(XQM, XQnM, {`XLEN{1'b1}}, {Div0M, NegQM}, QuotM); // Q taken from XQ register, negated if necessary, or all 1s when dividing by zero
   mux3 #(`XLEN) remmux(WM, WnM, XSavedM, {Div0M, NegWM}, RemM); // REM taken from W register, negated if necessary, or from X when dividing by zero
 
-  // Divider FSM to sequence Init, Busy, and Done
+  // Divider FSM to sequence Busy, and Done
   always_ff @(posedge clk) 
     if (reset) begin
-        BusyE = 0; DivDoneM = 0; step = 0; DivInitE = 0;
+        BusyE = 0; DivDoneM = 0; step = 0; 
     end else if (DivStartE & ~StallM) begin 
         if (Div0E) DivDoneM = 1;
         else begin
-            BusyE = 1; step = 0; DivInitE = 1; // *** can drop DivInit
+            BusyE = 1; step = 0; 
         end
     end else if (BusyE & ~DivDoneM) begin // pause one cycle at beginning of signed operations for absolute value
-        DivInitE = 0;
         step = step + 1;
         if (step[STEPBITS] | (`XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
-            step = 0;
             BusyE = 0;
             DivDoneM = 1;
         end
     end else if (DivDoneM) begin
         DivDoneM = StallM;
-        BusyE = 0;
     end 
 
 endmodule 
diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv
index 09f1547ff..32dccd009 100644
--- a/wally-pipelined/src/muldiv/muldiv.sv
+++ b/wally-pipelined/src/muldiv/muldiv.sv
@@ -48,7 +48,7 @@ module muldiv (
 	 logic [`XLEN-1:0] QuotM, RemM;
 	 logic [`XLEN*2-1:0] ProdE, ProdM; 
 
-	 logic 		     DivStartE, BusyE, DivDoneM;
+	 logic 		     DivE;
 	 logic 		     DivSignedE;	
 	 logic           W64M; 
 	 
@@ -59,11 +59,9 @@ module muldiv (
 	 // Divide
 	 // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
 	 assign DivE = MulDivE & Funct3E[2];
-	 assign DivStartE = MulDivE & Funct3E[2] & ~BusyE & ~DivDoneM; 
 	 assign DivSignedE = ~Funct3E[0];
-	 assign DivBusyE = BusyE | DivStartE;
 	 intdivrestoring div(.clk, .reset, .StallM, .FlushM, 
-	   .DivSignedE, .W64E, .DivStartE, .SrcAE, .SrcBE, .BusyE, .DivDoneM, .QuotM, .RemM);
+	   .DivSignedE, .W64E, .DivE, .SrcAE, .SrcBE, .DivBusyE, .QuotM, .RemM);
 	 	 
 	 // Result multiplexer
 	 always_comb