From 69449963290bdc07ec0dd9b7192684413062a42f Mon Sep 17 00:00:00 2001 From: DTowersM Date: Wed, 8 Jun 2022 16:28:09 +0000 Subject: [PATCH] added #1 delays to Stalls and Flushes in hazard unit --- pipelined/src/hazard/hazard.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index b9163d6b4..3c641180d 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -69,11 +69,11 @@ module hazard( assign StallMCause = wfiM & (~TrapM & ~IntPendingM); assign StallWCause = LSUStallM | IFUStallF; - assign StallF = StallFCause | StallD; - assign StallD = StallDCause | StallE; - assign StallE = StallECause | StallM; - assign StallM = StallMCause | StallW; - assign StallW = StallWCause; + assign #1 StallF = StallFCause | StallD; + assign #1 StallD = StallDCause | StallE; + assign #1 StallE = StallECause | StallM; + assign #1 StallM = StallMCause | StallW; + assign #1 StallW = StallWCause; assign FirstUnstalledD = ~StallD & StallF; assign FirstUnstalledE = ~StallE & StallD; @@ -81,11 +81,11 @@ module hazard( assign FirstUnstalledW = ~StallW & StallM; // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush - assign FlushF = BPPredWrongE; - assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; - assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor - assign FlushM = FirstUnstalledM | TrapM | RetM; + assign #1 FlushF = BPPredWrongE; + assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; + assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor + assign #1 FlushM = FirstUnstalledM | TrapM | RetM; // on Trap the memory stage should be flushed going into the W stage, // except if the instruction causing the Trap is an ecall or ebreak. - assign FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM)); + assign #1 FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM)); endmodule