From 693f32973fd11dcb10fe774222e65781538679ca Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 23 Dec 2022 20:11:36 -0600 Subject: [PATCH] Minor optimizations. --- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/hazard/hazard.sv | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index a8ba78564..51ed22ad6 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -185,6 +185,6 @@ module cachefsm resetDelay; assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; - assign CacheEn = (CurrState == STATE_READY & (~Stall | FlushCache | AnyMiss)) | (CurrState != STATE_READY) | reset; + assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset; endmodule // cachefsm diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index a711b9443..d6441e80a 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -67,8 +67,8 @@ module hazard( // Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents // Branch misprediction is found in the Execute stage and must flush the next two instructions. // However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete - assign FlushDCause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM; - assign FlushECause = TrapM | RetM | (BPPredWrongE & ~(DivBusyE | FDivBusyE)) | CSRWriteFenceM; + assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE; + assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE)); assign FlushMCause = TrapM | RetM | CSRWriteFenceM; assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM);