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Fixed imperas C tests

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This commit is contained in:
David Harris 2021-12-26 04:45:06 +00:00
parent a7cfda8e52
commit 69243f41ad
2 changed files with 3 additions and 3 deletions
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3
tests/wally-riscv-arch-test/Makefile.include
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@ -1,6 +1,5 @@
# set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target # set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target
export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target
#export TARGETDIR ?= ~/riscv-wally/addins/riscv-isa-sim/arch_test_target
export RISCV_PREFIX = riscv64-unknown-elf- export RISCV_PREFIX = riscv64-unknown-elf-

3
wally-pipelined/testbench/testbench.sv
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@ -289,13 +289,14 @@ logic [3:0] dummy;
// Termination condition // Termination condition
// terminate on a specific ECALL after li x3,1 for old Imperas tests, // terminate on a specific ECALL after li x3,1 for old Imperas tests,
// or sw gp,-56(t0) for new Imperas tests // or sw gp,-56(t0) for new Imperas tests
// or sw gp, -56(t0)
// or on a jump to self infinite loop (6f) for RISC-V Arch tests // or on a jump to self infinite loop (6f) for RISC-V Arch tests
assign DCacheFlushStart = dut.hart.priv.priv.EcallFaultM && assign DCacheFlushStart = dut.hart.priv.priv.EcallFaultM &&
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.hart.ieu.dp.regf.we3 && (dut.hart.ieu.dp.regf.we3 &&
dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.a3 == 3 &&
dut.hart.ieu.dp.regf.wd3 == 1)) || dut.hart.ieu.dp.regf.wd3 == 1)) ||
(dut.hart.ifu.InstrM == 32'h6f || dut.hart.ifu.InstrM == 32'hfc32a423) && dut.hart.ieu.c.InstrValidM; (dut.hart.ifu.InstrM == 32'h6f || dut.hart.ifu.InstrM == 32'hfc32a423 || dut.hart.ifu.InstrM == 32'hfc32a823) && dut.hart.ieu.c.InstrValidM;
DCacheFlushFSM DCacheFlushFSM(.clk(clk), DCacheFlushFSM DCacheFlushFSM(.clk(clk),
.reset(reset), .reset(reset),