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https://github.com/openhwgroup/cvw
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Merge branch 'multimanager' into main
This commit is contained in:
Ross Thompson
commit
6912656aab
@ -79,11 +79,12 @@ module ahbmultimanager
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logic [1:0] save, restore, dis, sel;
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logic both;
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logic DoArbitration;
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logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDRRestore;
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logic [1:0] IFUHTRANSSave, IFUHTRANSRestore;
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logic [2:0] IFUHBURSTSave, IFUHBURSTRestore;
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logic [2:0] IFUHSIZERestore;
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logic IFUHWRITERestore;
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logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDRRestore;
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logic [1:0] LSUHTRANSSave, LSUHTRANSRestore;
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@ -94,9 +95,9 @@ module ahbmultimanager
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logic IFUReq, LSUReq;
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logic IFUActive, LSUActive;
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logic WordCntEn;
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logic [4-1:0] NextWordCount, WordCount, WordCountDelayed;
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logic WordCountFlag;
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logic BeatCntEn;
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logic [4-1:0] NextBeatCount, BeatCount, BeatCountDelayed;
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logic FinalBeat;
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logic [2:0] LocalBurstType;
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logic CntReset;
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logic [3:0] Threshold;
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@ -109,32 +110,18 @@ module ahbmultimanager
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// inputs. Abritration scheme is LSU always goes first.
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// input stage IFU
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flopenr #(3+2+`PA_BITS) IFUSaveReg(HCLK, ~HRESETn, save[0],
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{IFUHBURST, IFUHTRANS, IFUHADDR},
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{IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave});
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mux2 #(3+2+`PA_BITS) IFURestorMux({IFUHBURST, IFUHTRANS, IFUHADDR},
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{IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave},
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restore[0],
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{IFUHBURSTRestore, IFUHTRANSRestore, IFUHADDRRestore});
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assign IFUReq = IFUHTRANSRestore != 2'b00;
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assign IFUHREADY = HREADY & ~dis[0];
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assign IFUActive = IFUReq & IFUHREADY;
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managerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
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.Request(IFUReq), .Active(IFUActive),
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.HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
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.HWRITERestore(IFUHWRITERestore), .HSIZERestore(IFUHSIZERestore), .HBURSTRestore(IFUHBURSTRestore), .HREADYRestore(IFUHREADY),
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.HTRANSRestore(IFUHTRANSRestore), .HADDRRestore(IFUHADDRRestore), .HREADYin(HREADY));
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// input stage LSU
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flopenr #(1+3+3+2+`PA_BITS) LSUSaveReg(HCLK, ~HRESETn, save[1],
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{LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR},
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{LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave});
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mux2 #(1+3+3+2+`PA_BITS) LSURestorMux({LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR},
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{LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave},
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restore[1],
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{LSUHWRITERestore, LSUHSIZERestore, LSUHBURSTRestore, LSUHTRANSRestore, LSUHADDRRestore});
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assign LSUReq = LSUHTRANSRestore != 2'b00;
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assign LSUHREADY = HREADY & ~dis[1];
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assign LSUActive = LSUReq & LSUHREADY;
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assign both = LSUActive & IFUActive;
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managerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
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.Request(LSUReq), .Active(LSUActive),
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.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYRestore(LSUHREADY),
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.HWRITERestore(LSUHWRITERestore), .HSIZERestore(LSUHSIZERestore), .HBURSTRestore(LSUHBURSTRestore),
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.HTRANSRestore(LSUHTRANSRestore), .HADDRRestore(LSUHADDRRestore), .HREADYin(HREADY));
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// output mux //*** rewrite for general number of managers.
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assign HADDR = sel[1] ? LSUHADDRRestore : sel[0] ? IFUHADDRRestore : '0;
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@ -145,64 +132,50 @@ module ahbmultimanager
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0;
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// basic arb always selects LSU when both
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assign save[0] = CurrState == IDLE & both;
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assign restore[0] = CurrState == ARBITRATE;
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assign dis[0] = CurrState == ARBITRATE;
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assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
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// data phase muxing. This would be a mux if IFU wrote data.
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assign HWDATA = LSUHWDATA;
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assign HWSTRB = LSUHWSTRB;
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// HRDATA is sent to all managers at the core level.
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//
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assign save[1] = 1'b0;
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assign restore[1] = 1'b0;
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assign dis[1] = 1'b0;
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assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
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// Bus State FSM
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// Data accesses have priority over instructions. However, if a data access comes
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// while an cache line read is occuring, the line read finishes before
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// the data access can take place.
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// FSM decides if arbitration needed. Arbitration is held until the last beat of
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// a burst is completed.
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assign both = LSUActive & IFUActive;
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
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always_comb
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case (CurrState)
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IDLE: if (both) NextState = ARBITRATE;
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else NextState = IDLE;
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ARBITRATE: if (HREADY & WordCountFlag) NextState = IDLE;
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else NextState = ARBITRATE;
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default: NextState = IDLE;
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endcase // case (CurrState)
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assign DoArbitration = CurrState == ARBITRATE;
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assign HWDATA = LSUHWDATA;
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assign HWSTRB = LSUHWSTRB;
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IDLE: if (both) NextState = ARBITRATE;
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else NextState = IDLE;
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ARBITRATE: if (HREADY & FinalBeat) NextState = IDLE;
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else NextState = ARBITRATE;
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default: NextState = IDLE;
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endcase
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// Manager needs to count beats.
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flopenr #(4)
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WordCountReg(.clk(HCLK),
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BeatCountReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(WordCntEn),
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.d(NextWordCount),
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.q(WordCount));
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.en(BeatCntEn),
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.d(NextBeatCount),
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.q(BeatCount));
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// Used to store data from data phase of AHB.
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flopenr #(4)
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WordCountDelayedReg(.clk(HCLK),
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BeatCountDelayedReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(WordCntEn),
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.d(WordCount),
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.q(WordCountDelayed));
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assign NextWordCount = WordCount + 1'b1;
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.en(BeatCntEn),
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.d(BeatCount),
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.q(BeatCountDelayed));
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assign NextBeatCount = BeatCount + 1'b1;
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assign CntReset = NextState == IDLE;
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assign WordCountFlag = (WordCountDelayed == Threshold); // Detect when we are waiting on the final access.
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assign WordCntEn = (NextState == ARBITRATE & HREADY);
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assign FinalBeat = (BeatCountDelayed == Threshold); // Detect when we are waiting on the final access.
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assign BeatCntEn = (NextState == ARBITRATE & HREADY);
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logic [2:0] HBURSTD;
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flopenr #(3) HBURSTReg(.clk(HCLK), .reset(~HRESETn), .en(HTRANS == 2'b10), .d(HBURST), .q(HBURSTD));
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// unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
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always_comb begin
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case(HBURSTD)
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0: Threshold = 4'b0000;
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@ -213,5 +186,17 @@ module ahbmultimanager
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endcase
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end
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// basic arb always selects LSU when both
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// replace this block for more sophisticated arbitration.
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// Manager 0 (IFU)
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assign save[0] = CurrState == IDLE & both;
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assign restore[0] = CurrState == ARBITRATE;
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assign dis[0] = CurrState == ARBITRATE;
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assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
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// Manager 1 (LSU)
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assign save[1] = 1'b0;
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assign restore[1] = 1'b0;
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assign dis[1] = 1'b0;
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assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
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endmodule
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81
pipelined/src/ebu/managerinputstage.sv
Normal file
81
pipelined/src/ebu/managerinputstage.sv
Normal file
@ -0,0 +1,81 @@
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///////////////////////////////////////////
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// manager input stage
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//
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// Written: Ross Thompson August 31, 2022
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// ross1728@gmail.com
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// Modified:
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//
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// Purpose: AHB multi manager interface to merge LSU and IFU controls.
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Connects core to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module managerinputstage
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(input logic HCLK,
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input logic HRESETn,
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input logic Save, Restore, Disable,
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output logic Request, Active,
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// manager input
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input logic HWRITEin,
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input logic [2:0] HSIZEin,
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input logic [2:0] HBURSTin,
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input logic [1:0] HTRANSin,
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input logic [`PA_BITS-1:0] HADDRin,
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output logic HREADYRestore,
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// manager output
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output logic HWRITERestore,
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output logic [2:0] HSIZERestore,
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output logic [2:0] HBURSTRestore,
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output logic [1:0] HTRANSRestore,
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output logic [`PA_BITS-1:0] HADDRRestore,
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input logic HREADYin
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);
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logic HWRITESave;
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logic [2:0] HSIZESave;
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logic [2:0] HBURSTSave;
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logic [1:0] HTRANSSave;
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logic [`PA_BITS-1:0] HADDRSave;
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flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
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{HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
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mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin},
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{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
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Restore,
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{HWRITERestore, HSIZERestore, HBURSTRestore, HTRANSRestore, HADDRRestore});
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assign Request = HTRANSRestore != 2'b00;
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assign HREADYRestore = HREADYin & ~Disable;
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assign Active = Request & HREADYRestore;
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endmodule
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