Merge branch 'multimanager' into main

pipelined/src/ebu/ahbmultimanager.sv

@@ -79,11 +79,12 @@ module ahbmultimanager
 
   logic [1:0]                 save, restore, dis, sel;
   logic                       both;
-  logic                       DoArbitration;
 
   logic [`PA_BITS-1:0]        IFUHADDRSave, IFUHADDRRestore;
   logic [1:0]                 IFUHTRANSSave, IFUHTRANSRestore;
   logic [2:0]                 IFUHBURSTSave, IFUHBURSTRestore;
+  logic [2:0]                 IFUHSIZERestore;
+  logic                       IFUHWRITERestore;
   
   logic [`PA_BITS-1:0]        LSUHADDRSave, LSUHADDRRestore;
   logic [1:0]                 LSUHTRANSSave, LSUHTRANSRestore;
@@ -94,9 +95,9 @@ module ahbmultimanager
   logic                       IFUReq, LSUReq;
   logic                       IFUActive, LSUActive;
 
-  logic                       WordCntEn;
+  logic                       BeatCntEn;
-  logic [4-1:0]               NextWordCount, WordCount, WordCountDelayed;
+  logic [4-1:0]               NextBeatCount, BeatCount, BeatCountDelayed;
-  logic                       WordCountFlag;
+  logic                       FinalBeat;
   logic [2:0]                 LocalBurstType;
   logic                       CntReset;
   logic [3:0]                 Threshold;
@@ -109,32 +110,18 @@ module ahbmultimanager
   // inputs.  Abritration scheme is LSU always goes first.
 
   // input stage IFU
-  flopenr #(3+2+`PA_BITS) IFUSaveReg(HCLK, ~HRESETn, save[0],
+  managerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
-                                     {IFUHBURST, IFUHTRANS, IFUHADDR}, 
+    .Request(IFUReq), .Active(IFUActive),
-                                     {IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave});
+    .HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
-  mux2 #(3+2+`PA_BITS) IFURestorMux({IFUHBURST, IFUHTRANS, IFUHADDR}, 
+    .HWRITERestore(IFUHWRITERestore), .HSIZERestore(IFUHSIZERestore), .HBURSTRestore(IFUHBURSTRestore), .HREADYRestore(IFUHREADY),
-                                    {IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave},
+    .HTRANSRestore(IFUHTRANSRestore), .HADDRRestore(IFUHADDRRestore), .HREADYin(HREADY));
-                                    restore[0],
-                                    {IFUHBURSTRestore, IFUHTRANSRestore, IFUHADDRRestore});
-  assign IFUReq = IFUHTRANSRestore != 2'b00;
-  
-  assign IFUHREADY = HREADY & ~dis[0];
-  assign IFUActive = IFUReq & IFUHREADY;
 
   // input stage LSU
-  flopenr #(1+3+3+2+`PA_BITS) LSUSaveReg(HCLK, ~HRESETn, save[1],
+  managerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
-                                         {LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR}, 
+    .Request(LSUReq), .Active(LSUActive),
-                                         {LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave});
+    .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYRestore(LSUHREADY),
-  mux2 #(1+3+3+2+`PA_BITS) LSURestorMux({LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR}, 
+    .HWRITERestore(LSUHWRITERestore), .HSIZERestore(LSUHSIZERestore), .HBURSTRestore(LSUHBURSTRestore),
-                                        {LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave},
+    .HTRANSRestore(LSUHTRANSRestore), .HADDRRestore(LSUHADDRRestore), .HREADYin(HREADY));
-                                        restore[1],
-                                        {LSUHWRITERestore, LSUHSIZERestore, LSUHBURSTRestore, LSUHTRANSRestore, LSUHADDRRestore});
-
-  assign LSUReq = LSUHTRANSRestore != 2'b00;
-  assign LSUHREADY = HREADY & ~dis[1];
-  assign LSUActive = LSUReq & LSUHREADY;
-
-  assign both = LSUActive & IFUActive;
 
   // output mux //*** rewrite for general number of managers.
   assign HADDR = sel[1] ? LSUHADDRRestore : sel[0] ? IFUHADDRRestore : '0;
@@ -145,64 +132,50 @@ module ahbmultimanager
   assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0;
 
-  // basic arb always selects LSU when both
+  // data phase muxing.  This would be a mux if IFU wrote data.
-  assign save[0] = CurrState == IDLE & both;
+  assign HWDATA = LSUHWDATA;
-  assign restore[0] = CurrState == ARBITRATE;
+  assign HWSTRB = LSUHWSTRB;
-  assign dis[0] = CurrState == ARBITRATE;
+  // HRDATA is sent to all managers at the core level.
-  assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
-
-  //
-  assign save[1] = 1'b0;
-  assign restore[1] = 1'b0;
-  assign dis[1] = 1'b0;
-  assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
-  
-  
-
-  // Bus State FSM
-  // Data accesses have priority over instructions.  However, if a data access comes
-  // while an cache line read is occuring, the line read finishes before
-  // the data access can take place.
 
+  // FSM decides if arbitration needed.  Arbitration is held until the last beat of
+  // a burst is completed.
+  assign both = LSUActive & IFUActive;
   flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
   always_comb 
     case (CurrState) 
-      IDLE: if (both)       NextState = ARBITRATE; 
+      IDLE: if (both)                    NextState = ARBITRATE; 
-      else            NextState = IDLE;
+      else                               NextState = IDLE;
-      ARBITRATE: if (HREADY & WordCountFlag) NextState = IDLE;
+      ARBITRATE: if (HREADY & FinalBeat) NextState = IDLE;
-      else       NextState = ARBITRATE;
+      else                               NextState = ARBITRATE;
-      default:              NextState = IDLE;
+      default:                           NextState = IDLE;
-    endcase // case (CurrState)
+    endcase
-
-  assign DoArbitration = CurrState == ARBITRATE;
-
-  assign HWDATA = LSUHWDATA;
-  assign HWSTRB = LSUHWSTRB;
 
+  // Manager needs to count beats.
   flopenr #(4) 
-  WordCountReg(.clk(HCLK),
+  BeatCountReg(.clk(HCLK),
 		.reset(~HRESETn | CntReset),
-		.en(WordCntEn),
+		.en(BeatCntEn),
-		.d(NextWordCount),
+		.d(NextBeatCount),
-		.q(WordCount));  
+		.q(BeatCount));  
   
   // Used to store data from data phase of AHB.
   flopenr #(4) 
-  WordCountDelayedReg(.clk(HCLK),
+  BeatCountDelayedReg(.clk(HCLK),
 		.reset(~HRESETn | CntReset),
-		.en(WordCntEn),
+		.en(BeatCntEn),
-		.d(WordCount),
+		.d(BeatCount),
-		.q(WordCountDelayed));
+		.q(BeatCountDelayed));
-  assign NextWordCount = WordCount + 1'b1;
+  assign NextBeatCount = BeatCount + 1'b1;
 
   assign CntReset = NextState == IDLE;
-  assign WordCountFlag = (WordCountDelayed == Threshold); // Detect when we are waiting on the final access.
+  assign FinalBeat = (BeatCountDelayed == Threshold); // Detect when we are waiting on the final access.
-  assign WordCntEn = (NextState == ARBITRATE & HREADY);
+  assign BeatCntEn = (NextState == ARBITRATE & HREADY);
 
   logic [2:0]                 HBURSTD;
   
   flopenr #(3) HBURSTReg(.clk(HCLK), .reset(~HRESETn), .en(HTRANS == 2'b10), .d(HBURST), .q(HBURSTD));
 
+  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
   always_comb begin
     case(HBURSTD)
       0:        Threshold = 4'b0000;
@@ -213,5 +186,17 @@ module ahbmultimanager
     endcase
   end
   
+  // basic arb always selects LSU when both
+  // replace this block for more sophisticated arbitration.
+  // Manager 0 (IFU)
+  assign save[0] = CurrState == IDLE & both;
+  assign restore[0] = CurrState == ARBITRATE;
+  assign dis[0] = CurrState == ARBITRATE;
+  assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
+  // Manager 1 (LSU)
+  assign save[1] = 1'b0;
+  assign restore[1] = 1'b0;
+  assign dis[1] = 1'b0;
+  assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
 
 endmodule

pipelined/src/ebu/managerinputstage.sv

@@ -0,0 +1,81 @@
+///////////////////////////////////////////
+// manager input stage
+//
+// Written: Ross Thompson August 31, 2022
+// ross1728@gmail.com
+// Modified: 
+//
+// Purpose: AHB multi manager interface to merge LSU and IFU controls.
+//          See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
+//          Arbitrates requests from instruction and data streams
+//          Connects core to peripherals and I/O pins on SOC
+//          Bus width presently matches XLEN
+//          Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module managerinputstage
+  (input logic HCLK,
+   input logic                 HRESETn,
+   input logic                 Save, Restore, Disable,
+   output logic                Request, Active,
+   // manager input
+   input logic                 HWRITEin,
+   input logic [2:0]           HSIZEin,
+   input logic [2:0]           HBURSTin,
+   input logic [1:0]           HTRANSin,
+   input logic [`PA_BITS-1:0]  HADDRin,
+   output logic                HREADYRestore,
+   // manager output
+   output logic                HWRITERestore,
+   output logic [2:0]          HSIZERestore,
+   output logic [2:0]          HBURSTRestore,
+   output logic [1:0]          HTRANSRestore,
+   output logic [`PA_BITS-1:0] HADDRRestore,
+   input logic                 HREADYin
+   );
+
+  logic                        HWRITESave;
+  logic [2:0]                  HSIZESave;
+  logic [2:0]                  HBURSTSave;
+  logic [1:0]                  HTRANSSave;
+  logic [`PA_BITS-1:0]         HADDRSave;
+
+  flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
+                                      {HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin}, 
+                                      {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
+  mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin}, 
+                                     {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
+                                     Restore,
+                                     {HWRITERestore, HSIZERestore, HBURSTRestore, HTRANSRestore, HADDRRestore});
+
+  assign Request = HTRANSRestore != 2'b00;
+  assign HREADYRestore = HREADYin & ~Disable;
+  assign Active = Request & HREADYRestore;
+
+endmodule
+  
+  
+