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https://github.com/openhwgroup/cvw
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Incorporated fixed fcvt.h.l* instructions; they now run in the testbench
This commit is contained in:
David Harris
parent
fc158689ad
commit
690338b758
@ -1425,10 +1425,10 @@ string imperas32f[] = '{
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"rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
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"rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
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"rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
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// "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S", // tests commented out because they involve a fsd that hangs on vsim -c -do "do wally-batch.do fh_rv64gc arch64zfh" which lacks fsd support
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// "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
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// "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
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// "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
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"rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
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"rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
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"rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
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"rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
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"rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
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"rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
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"rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",
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@ -2,7 +2,7 @@
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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.11.0
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// timestamp : Mon May 8 05:09:38 2023 GMT
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// timestamp : Mon Mar 25 04:42:12 2024 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \
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@ -15,11 +15,11 @@
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.l_b25 covergroup.
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.l_b25 covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64IFD_Zicsr_Zfh")
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RVTEST_ISA("RV64IF_Zicsr_Zfh")
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.section .text.init
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.globl rvtest_entry_point
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@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
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RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
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RVTEST_FP_ENABLE()
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RVTEST_VALBASEUPD(x3,test_dataset_0)
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@ -2,7 +2,7 @@
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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.11.0
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// timestamp : Mon May 8 05:09:38 2023 GMT
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// timestamp : Mon Mar 25 04:42:12 2024 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \
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@ -15,11 +15,11 @@
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.l_b26 covergroup.
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// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.l_b26 covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64IFD_Zicsr_Zfh")
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RVTEST_ISA("RV64IF_Zicsr_Zfh")
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.section .text.init
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.globl rvtest_entry_point
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@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b26)
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RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b26)
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RVTEST_FP_ENABLE()
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RVTEST_VALBASEUPD(x3,test_dataset_0)
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@ -2,7 +2,7 @@
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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.11.0
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// timestamp : Mon May 8 05:17:20 2023 GMT
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// timestamp : Mon Mar 25 04:46:01 2024 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \
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@ -15,11 +15,11 @@
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.lu_b25 covergroup.
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// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.lu_b25 covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64IFD_Zicsr_Zfh")
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RVTEST_ISA("RV64IF_Zicsr_Zfh")
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.section .text.init
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.globl rvtest_entry_point
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@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
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RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
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RVTEST_FP_ENABLE()
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RVTEST_VALBASEUPD(x3,test_dataset_0)
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@ -2,7 +2,7 @@
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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.11.0
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// timestamp : Mon May 8 05:17:20 2023 GMT
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// timestamp : Mon Mar 25 04:46:01 2024 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \
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@ -15,11 +15,11 @@
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.lu_b26 covergroup.
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// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.lu_b26 covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64IFD_Zicsr_Zfh")
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RVTEST_ISA("RV64IF_Zicsr_Zfh")
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.section .text.init
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.globl rvtest_entry_point
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@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b26)
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RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b26)
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RVTEST_FP_ENABLE()
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RVTEST_VALBASEUPD(x3,test_dataset_0)
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