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Incorporated fixed fcvt.h.l* instructions; they now run in the testbench

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This commit is contained in:
David Harris 2024-03-25 06:08:27 -07:00
parent fc158689ad
commit 690338b758
5 changed files with 161 additions and 161 deletions
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8
testbench/tests.vh
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@ -1425,10 +1425,10 @@ string imperas32f[] = '{
"rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S", "rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
"rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S", "rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
"rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S", "rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
// "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S", // tests commented out because they involve a fsd that hangs on vsim -c -do "do wally-batch.do fh_rv64gc arch64zfh" which lacks fsd support "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
// "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S", "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
// "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S", "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
// "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S", "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
"rv64i_m/Zfh/src/fcvt.l.h_b1-01.S", "rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
"rv64i_m/Zfh/src/fcvt.l.h_b22-01.S", "rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
"rv64i_m/Zfh/src/fcvt.l.h_b23-01.S", "rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b25-01.S
View File

@ -2,7 +2,7 @@
// ----------- // -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) // This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0 // version : 0.11.0
// timestamp : Mon May 8 05:09:38 2023 GMT // timestamp : Mon Mar 25 04:42:12 2024 GMT
// usage : riscv_ctg \ // usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ // -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \ // --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \
@ -15,11 +15,11 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
// ----------- // -----------
// //
// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.l_b25 covergroup. // This assembly file tests the fcvt.h.l instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.l_b25 covergroup.
// //
#include "model_test.h" #include "model_test.h"
#include "arch_test.h" #include "arch_test.h"
RVTEST_ISA("RV64IFD_Zicsr_Zfh") RVTEST_ISA("RV64IF_Zicsr_Zfh")
.section .text.init .section .text.init
.globl rvtest_entry_point .globl rvtest_entry_point
@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1 #ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25) RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
RVTEST_FP_ENABLE() RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0) RVTEST_VALBASEUPD(x3,test_dataset_0)

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b26-01.S
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@ -2,7 +2,7 @@
// ----------- // -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) // This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0 // version : 0.11.0
// timestamp : Mon May 8 05:09:38 2023 GMT // timestamp : Mon Mar 25 04:42:12 2024 GMT
// usage : riscv_ctg \ // usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ // -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \ // --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf \
@ -15,11 +15,11 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
// ----------- // -----------
// //
// This assembly file tests the fcvt.h.l instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.l_b26 covergroup. // This assembly file tests the fcvt.h.l instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.l_b26 covergroup.
// //
#include "model_test.h" #include "model_test.h"
#include "arch_test.h" #include "arch_test.h"
RVTEST_ISA("RV64IFD_Zicsr_Zfh") RVTEST_ISA("RV64IF_Zicsr_Zfh")
.section .text.init .section .text.init
.globl rvtest_entry_point .globl rvtest_entry_point
@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1 #ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b26) RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b26)
RVTEST_FP_ENABLE() RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0) RVTEST_VALBASEUPD(x3,test_dataset_0)

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S
View File

@ -2,7 +2,7 @@
// ----------- // -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) // This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0 // version : 0.11.0
// timestamp : Mon May 8 05:17:20 2023 GMT // timestamp : Mon Mar 25 04:46:01 2024 GMT
// usage : riscv_ctg \ // usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ // -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \ // --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \
@ -15,11 +15,11 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
// ----------- // -----------
// //
// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.lu_b25 covergroup. // This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.lu_b25 covergroup.
// //
#include "model_test.h" #include "model_test.h"
#include "arch_test.h" #include "arch_test.h"
RVTEST_ISA("RV64IFD_Zicsr_Zfh") RVTEST_ISA("RV64IF_Zicsr_Zfh")
.section .text.init .section .text.init
.globl rvtest_entry_point .globl rvtest_entry_point
@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1 #ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25) RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
RVTEST_FP_ENABLE() RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0) RVTEST_VALBASEUPD(x3,test_dataset_0)

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S
View File

@ -2,7 +2,7 @@
// ----------- // -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) // This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0 // version : 0.11.0
// timestamp : Mon May 8 05:17:20 2023 GMT // timestamp : Mon Mar 25 04:46:01 2024 GMT
// usage : riscv_ctg \ // usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ // -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \ // --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf \
@ -15,11 +15,11 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
// ----------- // -----------
// //
// This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64FD_Zicsr_Zfh extension for the fcvt.h.lu_b26 covergroup. // This assembly file tests the fcvt.h.lu instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.h.lu_b26 covergroup.
// //
#include "model_test.h" #include "model_test.h"
#include "arch_test.h" #include "arch_test.h"
RVTEST_ISA("RV64IFD_Zicsr_Zfh") RVTEST_ISA("RV64IF_Zicsr_Zfh")
.section .text.init .section .text.init
.globl rvtest_entry_point .globl rvtest_entry_point
@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1 #ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b26) RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b26)
RVTEST_FP_ENABLE() RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0) RVTEST_VALBASEUPD(x3,test_dataset_0)