From 27251a9935d56f5d18e987795a29e7c33253f64b Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Wed, 27 Oct 2021 13:45:37 -0700 Subject: [PATCH 01/19] Have replaced .* with signal names in ifu --- .../src/wally/wallypipelinedhart.sv | 27 ++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 980166d95..ede4460e0 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -154,9 +154,30 @@ module wallypipelinedhart ( logic BreakpointFaultM, EcallFaultM; - ifu ifu(.InstrInF(InstrRData), - .WalkerInstrPageFaultF(WalkerInstrPageFaultF), - .*); // instruction fetch unit: PC, branch prediction, instruction cache + ifu ifu( + .clk, .reset, + .StallF, .StallD, .StallE, .StallM, .StallW, + .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, + .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF, + .PCLinkE, .PCSrcE, .PCTargetE, .PCE, + .BPPredWrongE, + .RetM, .TrapM, + .PrivilegedNextPCM, .InvalidateICacheM, + .InstrD, .InstrM, + .PCM, .InstrClassM, + .BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM, + .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD, + .InstrMisalignedFaultM, .InstrMisalignedAdrM, + .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, + .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, + .ITLBWriteF, .ITLBFlushF, + .WalkerInstrPageFaultF, + .ITLBMissF, + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, + .InstrAccessFaultF + + ); // instruction fetch unit: PC, branch prediction, instruction cache + ieu ieu(.*); // integer execution unit: integer register file, datapath and controller From ab711c498d0bf768e8ddc0d9acaf6d6c6f6c5f27 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 27 Oct 2021 14:10:29 -0700 Subject: [PATCH 02/19] checkpoint generator off-by-one error fix --- .../linux-testgen/testvector-generation/genCheckpoint.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh b/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh index f35420341..fc22dd282 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh @@ -3,7 +3,7 @@ source genSettings.sh tcpPort=1236 -instrs=10000000 +instrs=480000000 checkOutDir="$outDir/checkpoint$instrs" checkIntermedDir="$checkOutDir/intermediate-outputs" @@ -32,7 +32,7 @@ then # Post-Process GDB outputs ./parseState.py "$checkOutDir" ./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt" - tail -n+$instrs "$outDir/$traceFile" > "$checkOutDir/$traceFile" + tail -n+$($instrs+1) "$outDir/$traceFile" > "$checkOutDir/$traceFile" else echo "You can change the number of instructions by editing the \"instrs\" variable in this script." echo "Have a nice day!" From 35fcadbe7fd487e4bdf83d4fea34d6ad2985f0ed Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 28 Oct 2021 11:07:18 -0500 Subject: [PATCH 03/19] Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. --- wally-pipelined/src/cache/dcache.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index bf943169c..b51e77e73 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -142,6 +142,8 @@ module dcache logic LRUWriteEn; + logic [NUMWAYS-1:0] VDWriteEnableWay; + // Read Path CPU (IEU) side mux4 #(INDEXLEN) @@ -167,7 +169,7 @@ module dcache .WAdr, .PAdr(MemPAdrM), .WriteEnable(SRAMWayWriteEnable), - .VDWriteEnable, + .VDWriteEnable(VDWriteEnableWay), .WriteWordEnable(SRAMWordEnable), .TagWriteEnable(SRAMBlockWayWriteEnableM), .WriteData(SRAMWriteData), @@ -329,6 +331,8 @@ module dcache .d(NextFlushWay), .q(FlushWay)); + assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}}; + assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; From 41dbb59e24285b0dbbdcea21a0ea9c9dd73a86cf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 29 Oct 2021 11:03:37 -0500 Subject: [PATCH 06/19] Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. --- .../src/cache/cachereplacementpolicy.sv | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv index e02c36753..47e521a87 100644 --- a/wally-pipelined/src/cache/cachereplacementpolicy.sv +++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv @@ -82,7 +82,31 @@ module cachereplacementpolicy assign VictimWay[1] = ~BlockReplacementBits[0]; assign VictimWay[0] = BlockReplacementBits[0]; - end else if (NUMWAYS == 4) begin : FourWay + end else if (NUMWAYS == 4) begin : FourWay + + + // VictimWay is a function only of the current value of the LRU. + // binary encoding + //assign VictimWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0]; + //assign VictimWay[1] = BlockReplacementBits[2]; + + // 1 hot encoding + assign VictimWay[0] = ~BlockReplacementBits[2] & ~BlockReplacementBits[0]; + assign VictimWay[1] = ~BlockReplacementBits[2] & BlockReplacementBits[0]; + assign VictimWay[2] = BlockReplacementBits[2] & ~BlockReplacementBits[1]; + assign VictimWay[3] = BlockReplacementBits[2] & BlockReplacementBits[1]; + + // New LRU bits which are updated is function only of the WayHit. + // However the not updated bits come from the old LRU. + assign LRUEn[2] = |WayHit; + assign LRUEn[1] = WayHit[3] | WayHit[2]; + assign LRUEn[0] = WayHit[1] | WayHit[0]; + + assign LRUMask[2] = WayHit[1] | WayHit[0]; + assign LRUMask[1] = WayHit[2]; + assign LRUMask[0] = WayHit[0]; + +/* -----\/----- EXCLUDED -----\/----- // selects assign LRUEn[2] = 1'b1; @@ -93,16 +117,19 @@ module cachereplacementpolicy assign LRUMask[0] = WayHit[1]; assign LRUMask[1] = WayHit[3]; assign LRUMask[2] = WayHit[3] | WayHit[2]; + -----/\----- EXCLUDED -----/\----- */ for(index = 0; index < NUMWAYS-1; index++) assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index]; +/* -----\/----- EXCLUDED -----\/----- assign EncVicWay[1] = BlockReplacementBits[2]; assign EncVicWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[0] : BlockReplacementBits[1]; onehotdecoder #(2) waydec(.bin(EncVicWay), .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]})); + -----/\----- EXCLUDED -----/\----- */ end else if (NUMWAYS == 8) begin : EightWay From 9c875d38a99aa4f22da1cb3dfa3e993e44b73401 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 29 Oct 2021 12:46:02 -0500 Subject: [PATCH 08/19] Fixed the 4 way set associative pseudo LRU replacement policy. --- wally-pipelined/src/cache/cachereplacementpolicy.sv | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv index 47e521a87..a0b774745 100644 --- a/wally-pipelined/src/cache/cachereplacementpolicy.sv +++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv @@ -59,7 +59,7 @@ module cachereplacementpolicy ReplacementBits[index] <= '0; end else begin RAdrD <= RAdr; - MemPAdrMD <= MemPAdrMD; + MemPAdrMD <= MemPAdrM; LRUWriteEnD <= LRUWriteEn; NewReplacementD <= NewReplacement; if (LRUWriteEnD) begin @@ -91,6 +91,14 @@ module cachereplacementpolicy //assign VictimWay[1] = BlockReplacementBits[2]; // 1 hot encoding + //| WayHit | LRU 2 | LRU 1 | LRU 0 | + //|--------+-------+-------+-------| + //| 0000 | - | - | - | + //| 0001 | 1 | - | 1 | + //| 0010 | 1 | - | 0 | + //| 0100 | 0 | 1 | - | + //| 1000 | 0 | 0 | - | + assign VictimWay[0] = ~BlockReplacementBits[2] & ~BlockReplacementBits[0]; assign VictimWay[1] = ~BlockReplacementBits[2] & BlockReplacementBits[0]; assign VictimWay[2] = BlockReplacementBits[2] & ~BlockReplacementBits[1]; From 14b9b8126e9d6d97442a913379999e4641360097 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Oct 2021 22:28:37 -0700 Subject: [PATCH 09/19] rearranging testgen --- {wally-pipelined => tests}/testgen/privileged/README.md | 0 {wally-pipelined => tests}/testgen/privileged/run.sh | 0 {wally-pipelined => tests}/testgen/privileged/testgen-CAUSE.py | 0 .../testgen/privileged/testgen-CSR-PERMISSIONS.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-DELEG.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-EPC.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-IE.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-IP.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-READONLY.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-RET.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-TVAL.py | 0 {wally-pipelined => tests}/testgen/privileged/testgen-TVEC.py | 0 .../testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py | 0 .../testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py | 0 .../testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py | 0 .../testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py | 0 {wally-pipelined => tests}/testgen/testgen-BRANCH.py | 0 {wally-pipelined => tests}/testgen/testgen-CSR.py | 0 {wally-pipelined => tests}/testgen/testgen-JAL-JALR.py | 0 {wally-pipelined => tests}/testgen/testgen-LOAD.py | 0 {wally-pipelined => tests}/testgen/testgen-PIPELINE.py | 0 {wally-pipelined => tests}/testgen/testgen-SLL-SRL-SRA.py | 0 {wally-pipelined => tests}/testgen/testgen-SLLI-SRLI-SRAI.py | 0 {wally-pipelined => tests}/testgen/testgen-SLTIU.py | 0 {wally-pipelined => tests}/testgen/testgen-STORE.py | 0 {wally-pipelined => tests}/testgen/testgen-VIRTUALMEMORY.py | 0 {wally-pipelined => tests}/testgen/testgen_footer.S | 0 {wally-pipelined => tests}/testgen/testgen_header.S | 0 {wally-pipelined => tests}/testgen/virtual_memory_util.py | 0 29 files changed, 0 insertions(+), 0 deletions(-) rename {wally-pipelined => tests}/testgen/privileged/README.md (100%) rename {wally-pipelined => tests}/testgen/privileged/run.sh (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-CAUSE.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-CSR-PERMISSIONS.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-DELEG.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-EPC.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-IE.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-IP.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-READONLY.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-RET.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-TVAL.py (100%) rename {wally-pipelined => tests}/testgen/privileged/testgen-TVEC.py (100%) rename {wally-pipelined => tests}/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py (100%) rename {wally-pipelined => tests}/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py (100%) rename {wally-pipelined => tests}/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py (100%) rename {wally-pipelined => tests}/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py (100%) rename {wally-pipelined => tests}/testgen/testgen-BRANCH.py (100%) rename {wally-pipelined => tests}/testgen/testgen-CSR.py (100%) rename {wally-pipelined => tests}/testgen/testgen-JAL-JALR.py (100%) rename {wally-pipelined => tests}/testgen/testgen-LOAD.py (100%) rename {wally-pipelined => tests}/testgen/testgen-PIPELINE.py (100%) rename {wally-pipelined => tests}/testgen/testgen-SLL-SRL-SRA.py (100%) rename {wally-pipelined => tests}/testgen/testgen-SLLI-SRLI-SRAI.py (100%) rename {wally-pipelined => tests}/testgen/testgen-SLTIU.py (100%) rename {wally-pipelined => tests}/testgen/testgen-STORE.py (100%) rename {wally-pipelined => tests}/testgen/testgen-VIRTUALMEMORY.py (100%) rename {wally-pipelined => tests}/testgen/testgen_footer.S (100%) rename {wally-pipelined => tests}/testgen/testgen_header.S (100%) rename {wally-pipelined => tests}/testgen/virtual_memory_util.py (100%) diff --git a/wally-pipelined/testgen/privileged/README.md b/tests/testgen/privileged/README.md similarity index 100% rename from wally-pipelined/testgen/privileged/README.md rename to tests/testgen/privileged/README.md diff --git a/wally-pipelined/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh similarity index 100% rename from wally-pipelined/testgen/privileged/run.sh rename to tests/testgen/privileged/run.sh diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/tests/testgen/privileged/testgen-CAUSE.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-CAUSE.py rename to tests/testgen/privileged/testgen-CAUSE.py diff --git a/wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py b/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py rename to tests/testgen/privileged/testgen-CSR-PERMISSIONS.py diff --git a/wally-pipelined/testgen/privileged/testgen-DELEG.py b/tests/testgen/privileged/testgen-DELEG.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-DELEG.py rename to tests/testgen/privileged/testgen-DELEG.py diff --git a/wally-pipelined/testgen/privileged/testgen-EPC.py b/tests/testgen/privileged/testgen-EPC.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-EPC.py rename to tests/testgen/privileged/testgen-EPC.py diff --git a/wally-pipelined/testgen/privileged/testgen-IE.py b/tests/testgen/privileged/testgen-IE.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-IE.py rename to tests/testgen/privileged/testgen-IE.py diff --git a/wally-pipelined/testgen/privileged/testgen-IP.py b/tests/testgen/privileged/testgen-IP.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-IP.py rename to tests/testgen/privileged/testgen-IP.py diff --git a/wally-pipelined/testgen/privileged/testgen-READONLY.py b/tests/testgen/privileged/testgen-READONLY.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-READONLY.py rename to tests/testgen/privileged/testgen-READONLY.py diff --git a/wally-pipelined/testgen/privileged/testgen-RET.py b/tests/testgen/privileged/testgen-RET.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-RET.py rename to tests/testgen/privileged/testgen-RET.py diff --git a/wally-pipelined/testgen/privileged/testgen-TVAL.py b/tests/testgen/privileged/testgen-TVAL.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-TVAL.py rename to tests/testgen/privileged/testgen-TVAL.py diff --git a/wally-pipelined/testgen/privileged/testgen-TVEC.py b/tests/testgen/privileged/testgen-TVEC.py similarity index 100% rename from wally-pipelined/testgen/privileged/testgen-TVEC.py rename to tests/testgen/privileged/testgen-TVEC.py diff --git a/wally-pipelined/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/tests/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py similarity index 100% rename from wally-pipelined/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py rename to tests/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py diff --git a/wally-pipelined/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/tests/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py similarity index 100% rename from wally-pipelined/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py rename to tests/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py diff --git a/wally-pipelined/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/tests/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py similarity index 100% rename from wally-pipelined/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py rename to tests/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py diff --git a/wally-pipelined/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/tests/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py similarity index 100% rename from wally-pipelined/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py rename to tests/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py diff --git a/wally-pipelined/testgen/testgen-BRANCH.py b/tests/testgen/testgen-BRANCH.py similarity index 100% rename from wally-pipelined/testgen/testgen-BRANCH.py rename to tests/testgen/testgen-BRANCH.py diff --git a/wally-pipelined/testgen/testgen-CSR.py b/tests/testgen/testgen-CSR.py similarity index 100% rename from wally-pipelined/testgen/testgen-CSR.py rename to tests/testgen/testgen-CSR.py diff --git a/wally-pipelined/testgen/testgen-JAL-JALR.py b/tests/testgen/testgen-JAL-JALR.py similarity index 100% rename from wally-pipelined/testgen/testgen-JAL-JALR.py rename to tests/testgen/testgen-JAL-JALR.py diff --git a/wally-pipelined/testgen/testgen-LOAD.py b/tests/testgen/testgen-LOAD.py similarity index 100% rename from wally-pipelined/testgen/testgen-LOAD.py rename to tests/testgen/testgen-LOAD.py diff --git a/wally-pipelined/testgen/testgen-PIPELINE.py b/tests/testgen/testgen-PIPELINE.py similarity index 100% rename from wally-pipelined/testgen/testgen-PIPELINE.py rename to tests/testgen/testgen-PIPELINE.py diff --git a/wally-pipelined/testgen/testgen-SLL-SRL-SRA.py b/tests/testgen/testgen-SLL-SRL-SRA.py similarity index 100% rename from wally-pipelined/testgen/testgen-SLL-SRL-SRA.py rename to tests/testgen/testgen-SLL-SRL-SRA.py diff --git a/wally-pipelined/testgen/testgen-SLLI-SRLI-SRAI.py b/tests/testgen/testgen-SLLI-SRLI-SRAI.py similarity index 100% rename from wally-pipelined/testgen/testgen-SLLI-SRLI-SRAI.py rename to tests/testgen/testgen-SLLI-SRLI-SRAI.py diff --git a/wally-pipelined/testgen/testgen-SLTIU.py b/tests/testgen/testgen-SLTIU.py similarity index 100% rename from wally-pipelined/testgen/testgen-SLTIU.py rename to tests/testgen/testgen-SLTIU.py diff --git a/wally-pipelined/testgen/testgen-STORE.py b/tests/testgen/testgen-STORE.py similarity index 100% rename from wally-pipelined/testgen/testgen-STORE.py rename to tests/testgen/testgen-STORE.py diff --git a/wally-pipelined/testgen/testgen-VIRTUALMEMORY.py b/tests/testgen/testgen-VIRTUALMEMORY.py similarity index 100% rename from wally-pipelined/testgen/testgen-VIRTUALMEMORY.py rename to tests/testgen/testgen-VIRTUALMEMORY.py diff --git a/wally-pipelined/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S similarity index 100% rename from wally-pipelined/testgen/testgen_footer.S rename to tests/testgen/testgen_footer.S diff --git a/wally-pipelined/testgen/testgen_header.S b/tests/testgen/testgen_header.S similarity index 100% rename from wally-pipelined/testgen/testgen_header.S rename to tests/testgen/testgen_header.S diff --git a/wally-pipelined/testgen/virtual_memory_util.py b/tests/testgen/virtual_memory_util.py similarity index 100% rename from wally-pipelined/testgen/virtual_memory_util.py rename to tests/testgen/virtual_memory_util.py From 247f247ad348ffb8ae85bea998620b404f3c5297 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 29 Oct 2021 22:31:48 -0700 Subject: [PATCH 10/19] tesgen cleanup, added riscv-arch-test D tests --- .../testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py | 0 .../testgen-ADDI-XORI-ORI-ANDI-SLTI.py | 0 .../testgen-ADDIW-SLLIW-SRLIW-SRAIW.py | 0 .../testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py | 0 tests/testgen/{ => imperas}/testgen-BRANCH.py | 0 tests/testgen/{ => imperas}/testgen-CSR.py | 0 .../testgen/{ => imperas}/testgen-JAL-JALR.py | 0 tests/testgen/{ => imperas}/testgen-LOAD.py | 0 .../testgen/{ => imperas}/testgen-PIPELINE.py | 0 .../{ => imperas}/testgen-SLL-SRL-SRA.py | 0 .../{ => imperas}/testgen-SLLI-SRLI-SRAI.py | 0 tests/testgen/{ => imperas}/testgen-SLTIU.py | 0 tests/testgen/{ => imperas}/testgen-STORE.py | 0 .../{ => imperas}/testgen-VIRTUALMEMORY.py | 0 tests/testgen/imperas/testgen_footer.S | 18 ++ tests/testgen/imperas/testgen_header.S | 38 ++++ tests/testgen/testgen_footer.S | 54 ++++-- tests/testgen/testgen_header.S | 29 ++- tests/testgen/wally-I.py | 153 +++++++++++++++ .../riscv-test-suite/rv32i_m/I/Makefrag | 2 +- wally-pipelined/regression/sim-wally-batch | 2 +- wally-pipelined/testbench/testbench.sv | 1 + wally-pipelined/testbench/tests.vh | 176 +++++++++++++++++- 23 files changed, 439 insertions(+), 34 deletions(-) rename tests/testgen/{ => imperas}/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py (100%) rename tests/testgen/{ => imperas}/testgen-ADDI-XORI-ORI-ANDI-SLTI.py (100%) rename tests/testgen/{ => imperas}/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py (100%) rename tests/testgen/{ => imperas}/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py (100%) rename tests/testgen/{ => imperas}/testgen-BRANCH.py (100%) rename tests/testgen/{ => imperas}/testgen-CSR.py (100%) rename tests/testgen/{ => imperas}/testgen-JAL-JALR.py (100%) rename tests/testgen/{ => imperas}/testgen-LOAD.py (100%) rename tests/testgen/{ => imperas}/testgen-PIPELINE.py (100%) rename tests/testgen/{ => imperas}/testgen-SLL-SRL-SRA.py (100%) rename tests/testgen/{ => imperas}/testgen-SLLI-SRLI-SRAI.py (100%) rename tests/testgen/{ => imperas}/testgen-SLTIU.py (100%) rename tests/testgen/{ => imperas}/testgen-STORE.py (100%) rename tests/testgen/{ => imperas}/testgen-VIRTUALMEMORY.py (100%) create mode 100644 tests/testgen/imperas/testgen_footer.S create mode 100644 tests/testgen/imperas/testgen_header.S create mode 100755 tests/testgen/wally-I.py diff --git a/tests/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py similarity index 100% rename from tests/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py rename to tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py diff --git a/tests/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py similarity index 100% rename from tests/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py rename to tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py diff --git a/tests/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py similarity index 100% rename from tests/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py rename to tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py diff --git a/tests/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py similarity index 100% rename from tests/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py rename to tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py diff --git a/tests/testgen/testgen-BRANCH.py b/tests/testgen/imperas/testgen-BRANCH.py similarity index 100% rename from tests/testgen/testgen-BRANCH.py rename to tests/testgen/imperas/testgen-BRANCH.py diff --git a/tests/testgen/testgen-CSR.py b/tests/testgen/imperas/testgen-CSR.py similarity index 100% rename from tests/testgen/testgen-CSR.py rename to tests/testgen/imperas/testgen-CSR.py diff --git a/tests/testgen/testgen-JAL-JALR.py b/tests/testgen/imperas/testgen-JAL-JALR.py similarity index 100% rename from tests/testgen/testgen-JAL-JALR.py rename to tests/testgen/imperas/testgen-JAL-JALR.py diff --git a/tests/testgen/testgen-LOAD.py b/tests/testgen/imperas/testgen-LOAD.py similarity index 100% rename from tests/testgen/testgen-LOAD.py rename to tests/testgen/imperas/testgen-LOAD.py diff --git a/tests/testgen/testgen-PIPELINE.py b/tests/testgen/imperas/testgen-PIPELINE.py similarity index 100% rename from tests/testgen/testgen-PIPELINE.py rename to tests/testgen/imperas/testgen-PIPELINE.py diff --git a/tests/testgen/testgen-SLL-SRL-SRA.py b/tests/testgen/imperas/testgen-SLL-SRL-SRA.py similarity index 100% rename from tests/testgen/testgen-SLL-SRL-SRA.py rename to tests/testgen/imperas/testgen-SLL-SRL-SRA.py diff --git a/tests/testgen/testgen-SLLI-SRLI-SRAI.py b/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py similarity index 100% rename from tests/testgen/testgen-SLLI-SRLI-SRAI.py rename to tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py diff --git a/tests/testgen/testgen-SLTIU.py b/tests/testgen/imperas/testgen-SLTIU.py similarity index 100% rename from tests/testgen/testgen-SLTIU.py rename to tests/testgen/imperas/testgen-SLTIU.py diff --git a/tests/testgen/testgen-STORE.py b/tests/testgen/imperas/testgen-STORE.py similarity index 100% rename from tests/testgen/testgen-STORE.py rename to tests/testgen/imperas/testgen-STORE.py diff --git a/tests/testgen/testgen-VIRTUALMEMORY.py b/tests/testgen/imperas/testgen-VIRTUALMEMORY.py similarity index 100% rename from tests/testgen/testgen-VIRTUALMEMORY.py rename to tests/testgen/imperas/testgen-VIRTUALMEMORY.py diff --git a/tests/testgen/imperas/testgen_footer.S b/tests/testgen/imperas/testgen_footer.S new file mode 100644 index 000000000..f7cc0b18b --- /dev/null +++ b/tests/testgen/imperas/testgen_footer.S @@ -0,0 +1,18 @@ + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN + +test_1_res: diff --git a/tests/testgen/imperas/testgen_header.S b/tests/testgen/imperas/testgen_header.S new file mode 100644 index 000000000..118042a5c --- /dev/null +++ b/tests/testgen/imperas/testgen_header.S @@ -0,0 +1,38 @@ +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "riscv_test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV64M + +RV_COMPLIANCE_CODE_BEGIN + + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") + + # --------------------------------------------------------------------------------------------- + + #RVTEST_IO_WRITE_STR(x31, "# Test group 1\n") + + + # address for test results + la x6, test_1_res + \ No newline at end of file diff --git a/tests/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S index f7cc0b18b..b0137b792 100644 --- a/tests/testgen/testgen_footer.S +++ b/tests/testgen/testgen_footer.S @@ -1,18 +1,46 @@ - # --------------------------------------------------------------------------------------------- - - RVTEST_IO_WRITE_STR(x31, "Test End\n") +RVTEST_CODE_END +RVMODEL_HALT - # --------------------------------------------------------------------------------------------- +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END - RV_COMPLIANCE_HALT - -RV_COMPLIANCE_CODE_END - -# Input data section. - .data +RVMODEL_DATA_BEGIN -# Output data section. -RV_COMPLIANCE_DATA_BEGIN +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef -test_1_res: + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S index 118042a5c..3b3bd6876 100644 --- a/tests/testgen/testgen_header.S +++ b/tests/testgen/testgen_header.S @@ -1,6 +1,5 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// Adapted from Imperas RISCV-TEST_SUITE // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, @@ -15,24 +14,18 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "riscv_test_macros.h" -#include "compliance_test.h" -#include "compliance_io.h" +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") -RV_COMPLIANCE_RV64M +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN -RV_COMPLIANCE_CODE_BEGIN +#ifdef TEST_CASE_1 +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - - # --------------------------------------------------------------------------------------------- - - #RVTEST_IO_WRITE_STR(x31, "# Test group 1\n") - - - # address for test results - la x6, test_1_res - \ No newline at end of file +RVTEST_SIGBASE( x8,signature_x8_1) diff --git a/tests/testgen/wally-I.py b/tests/testgen/wally-I.py new file mode 100755 index 000000000..b186e21c5 --- /dev/null +++ b/tests/testgen/wally-I.py @@ -0,0 +1,153 @@ +#!/usr/bin/python3 +################################## +# wally-I.py +# +# David_Harris@hmc.edu 27 October 2021 +# +# Generate directed and random test vectors for RISC-V Design Validation. +################################## + +################################## +# libraries +################################## +from datetime import datetime +from random import randint +from random import seed +from random import getrandbits + +################################## +# functions +################################## + +def twoscomp(a): + amsb = a >> (xlen-1) + alsbs = ((1 << (xlen-1)) - 1) & a + if (amsb): + asigned = a - (1<> 32) + "\n" + r.write(line) + testnum = testnum+1 + +################################## +# main body +################################## + +# change these to suite your tests +instrs = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"] +author = "David_Harris@hmc.edu" +xlens = [32, 64] +numrand = 100 + +# setup +seed(0) # make tests reproducible + +# generate files for each test +for xlen in xlens: + formatstrlen = str(int(xlen/4)) + formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number + formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x + if (xlen == 32): + storecmd = "sw" + wordsize = 4 + else: + storecmd = "sd" + wordsize = 8 + pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/" + fname = pathname + "src/WALLY-PIPELINE.S" + testnum = 0 + + # print custom header part + f = open(fname, "w") +# r = open(refname, "w") + line = "///////////////////////////////////////////\n" + f.write(line) + lines="// "+fname+ "\n// " + author + "\n" + f.write(lines) + line ="// Created " + str(datetime.now()) + f.write(line) + + # insert generic header + h = open("testgen_header.S", "r") + for line in h: + f.write(line) + + # print directed and random test vectors + # for a in corners: + # for b in corners: + # writeVector(a, b, storecmd, xlen) + # for i in range(0,numrand): + # a = getrandbits(xlen) + # b = getrandbits(xlen) + # writeVector(a, b, storecmd, xlen) + + + # print footer + h = open("testgen_footer.S", "r") + for line in h: + f.write(line) + + # Finish +# lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" +# lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + f.write(lines) + f.close() +# r.close() + + + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag index 9331e7e14..e2cdf44da 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag @@ -28,7 +28,7 @@ # Description: Makefrag for RV32I architectural tests rv32i_sc_tests = \ - + WALLY-PIPELINE \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch index 4b627b768..c603b8432 100755 --- a/wally-pipelined/regression/sim-wally-batch +++ b/wally-pipelined/regression/sim-wally-batch @@ -1,3 +1,3 @@ vsim -c < Date: Sat, 30 Oct 2021 07:26:18 -0700 Subject: [PATCH 11/19] Fixed exe2memfile parsing of weird line in arch64d test --- wally-pipelined/bin/exe2memfile.pl | 3 +- wally-pipelined/testbench/tests.vh | 156 ++++++++++++++--------------- 2 files changed, 80 insertions(+), 79 deletions(-) diff --git a/wally-pipelined/bin/exe2memfile.pl b/wally-pipelined/bin/exe2memfile.pl index e681f8419..26d0d2f42 100755 --- a/wally-pipelined/bin/exe2memfile.pl +++ b/wally-pipelined/bin/exe2memfile.pl @@ -62,7 +62,8 @@ for(my $i=0; $i<=$#ARGV; $i++) { } if (/Disassembly of section .data:/) { $mode = 1;} } elsif ($mode == 1) { # Parse data segment - if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { +# if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { # changed to \t 30 Oct 2021 dmh to fix parsing issue in d_fmadd_b17 + if (/^\s*(\S\S\S\S\S\S\S\S):\t+(.*)/) { $address = &fixadr($1); # print "addresss $address maxaddress $maxaddress\n"; if ($address > $maxaddress) { $maxaddress = $address; } diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index c99d64b62..42b1fc0b5 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -640,85 +640,85 @@ string imperas32f[] = '{ string arch64d[] = '{ `RISCVARCHTEST, "rv64i_m/D/d_fadd_b10-01", "8690", - "rv64i_m/D/d_fadd_b1-01", "8430", - "rv64i_m/D/d_fadd_b11-01", "74da0", - "rv64i_m/D/d_fadd_b12-01", "2350", - "rv64i_m/D/d_fadd_b13-01", "3cb0", - "rv64i_m/D/d_fadd_b2-01", "5160", - "rv64i_m/D/d_fadd_b3-01", "d640", - "rv64i_m/D/d_fadd_b4-01", "3900", - "rv64i_m/D/d_fadd_b5-01", "3d50", - "rv64i_m/D/d_fadd_b7-01", "5530", - "rv64i_m/D/d_fadd_b8-01", "11c10", +// "rv64i_m/D/d_fadd_b1-01", "8430", +// "rv64i_m/D/d_fadd_b11-01", "74da0", +// "rv64i_m/D/d_fadd_b12-01", "2350", +// "rv64i_m/D/d_fadd_b13-01", "3cb0", +// "rv64i_m/D/d_fadd_b2-01", "5160", +// "rv64i_m/D/d_fadd_b3-01", "d640", +// "rv64i_m/D/d_fadd_b4-01", "3900", +// "rv64i_m/D/d_fadd_b5-01", "3d50", +// "rv64i_m/D/d_fadd_b7-01", "5530", +// "rv64i_m/D/d_fadd_b8-01", "11c10", "rv64i_m/D/d_fclass_b1-01", "2110", - "rv64i_m/D/d_fcvt.d.l_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.l_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.s_b1-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b22-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b23-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b24-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b27-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b28-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b29-01", "2110", - "rv64i_m/D/d_fcvt.d.w_b25-01", "2120", - "rv64i_m/D/d_fcvt.d.w_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220", - "rv64i_m/D/d_fcvt.l.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.l.d_b22-01", "2260", - "rv64i_m/D/d_fcvt.l.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.l.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.l.d_b27-01", "2110", - "rv64i_m/D/d_fcvt.l.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.l.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.lu.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b22-01", "2260", - "rv64i_m/D/d_fcvt.lu.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.lu.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.lu.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.s.d_b1-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b22-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.s.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.s.d_b27-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b28-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.w.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b22-01", "2160", - "rv64i_m/D/d_fcvt.w.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.w.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.w.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b22-01", "2160", - "rv64i_m/D/d_fcvt.wu.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.wu.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0", - "rv64i_m/D/d_fdiv_b1-01", "8430", - "rv64i_m/D/d_fdiv_b20-01", "3fa0", - "rv64i_m/D/d_fdiv_b2-01", "5170", - "rv64i_m/D/d_fdiv_b21-01", "8a70", - "rv64i_m/D/d_fdiv_b3-01", "d630", - "rv64i_m/D/d_fdiv_b4-01", "38f0", - "rv64i_m/D/d_fdiv_b5-01", "3d50", - "rv64i_m/D/d_fdiv_b6-01", "38f0", - "rv64i_m/D/d_fdiv_b7-01", "5530", - "rv64i_m/D/d_fdiv_b8-01", "11c10", - "rv64i_m/D/d_fdiv_b9-01", "1b0f0", - "rv64i_m/D/d_feq_b1-01", "7430", - "rv64i_m/D/d_feq_b19-01", "c4c0", - "rv64i_m/D/d_fld-align-01", "2010", - "rv64i_m/D/d_fle_b1-01", "7430", - "rv64i_m/D/d_fle_b19-01", "c4c0", - "rv64i_m/D/d_flt_b1-01", "7430", - "rv64i_m/D/d_flt_b19-01", "d800", + // "rv64i_m/D/d_fcvt.d.l_b25-01", "2110", + // "rv64i_m/D/d_fcvt.d.l_b26-01", "2220", + // "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110", + // "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220", + // "rv64i_m/D/d_fcvt.d.s_b1-01", "2110", + // "rv64i_m/D/d_fcvt.d.s_b22-01", "2110", + // "rv64i_m/D/d_fcvt.d.s_b23-01", "2110", + // "rv64i_m/D/d_fcvt.d.s_b24-01", "2110", + // "rv64i_m/D/d_fcvt.d.s_b27-01", "2110", + // "rv64i_m/D/d_fcvt.d.s_b28-01", "2110", + // "rv64i_m/D/d_fcvt.d.s_b29-01", "2110", + // "rv64i_m/D/d_fcvt.d.w_b25-01", "2120", + // "rv64i_m/D/d_fcvt.d.w_b26-01", "2220", + // "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110", + // "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220", + // "rv64i_m/D/d_fcvt.l.d_b1-01", "2120", + // "rv64i_m/D/d_fcvt.l.d_b22-01", "2260", + // "rv64i_m/D/d_fcvt.l.d_b23-01", "2180", + // "rv64i_m/D/d_fcvt.l.d_b24-01", "2360", + // "rv64i_m/D/d_fcvt.l.d_b27-01", "2110", + // "rv64i_m/D/d_fcvt.l.d_b28-01", "2120", + // "rv64i_m/D/d_fcvt.l.d_b29-01", "22a0", + // "rv64i_m/D/d_fcvt.lu.d_b1-01", "2120", + // "rv64i_m/D/d_fcvt.lu.d_b22-01", "2260", + // "rv64i_m/D/d_fcvt.lu.d_b23-01", "2180", + // "rv64i_m/D/d_fcvt.lu.d_b24-01", "2360", + // "rv64i_m/D/d_fcvt.lu.d_b27-01", "2120", + // "rv64i_m/D/d_fcvt.lu.d_b28-01", "2120", + // "rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0", + // "rv64i_m/D/d_fcvt.s.d_b1-01", "2110", + // "rv64i_m/D/d_fcvt.s.d_b22-01", "2110", + // "rv64i_m/D/d_fcvt.s.d_b23-01", "2180", + // "rv64i_m/D/d_fcvt.s.d_b24-01", "2360", + // "rv64i_m/D/d_fcvt.s.d_b27-01", "2110", + // "rv64i_m/D/d_fcvt.s.d_b28-01", "2110", + // "rv64i_m/D/d_fcvt.s.d_b29-01", "22a0", + // "rv64i_m/D/d_fcvt.w.d_b1-01", "2120", + // "rv64i_m/D/d_fcvt.w.d_b22-01", "2160", + // "rv64i_m/D/d_fcvt.w.d_b23-01", "2180", + // "rv64i_m/D/d_fcvt.w.d_b24-01", "2360", + // "rv64i_m/D/d_fcvt.w.d_b27-01", "2120", + // "rv64i_m/D/d_fcvt.w.d_b28-01", "2120", + // "rv64i_m/D/d_fcvt.w.d_b29-01", "22a0", + // "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120", + // "rv64i_m/D/d_fcvt.wu.d_b22-01", "2160", + // "rv64i_m/D/d_fcvt.wu.d_b23-01", "2180", + // "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360", + // "rv64i_m/D/d_fcvt.wu.d_b27-01", "2120", + // "rv64i_m/D/d_fcvt.wu.d_b28-01", "2120", + // "rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0", + // "rv64i_m/D/d_fdiv_b1-01", "8430", + // "rv64i_m/D/d_fdiv_b20-01", "3fa0", + // "rv64i_m/D/d_fdiv_b2-01", "5170", + // "rv64i_m/D/d_fdiv_b21-01", "8a70", + // "rv64i_m/D/d_fdiv_b3-01", "d630", + // "rv64i_m/D/d_fdiv_b4-01", "38f0", + // "rv64i_m/D/d_fdiv_b5-01", "3d50", + // "rv64i_m/D/d_fdiv_b6-01", "38f0", + // "rv64i_m/D/d_fdiv_b7-01", "5530", + // "rv64i_m/D/d_fdiv_b8-01", "11c10", + // "rv64i_m/D/d_fdiv_b9-01", "1b0f0", + // "rv64i_m/D/d_feq_b1-01", "7430", + // "rv64i_m/D/d_feq_b19-01", "c4c0", + // "rv64i_m/D/d_fld-align-01", "2010", + // "rv64i_m/D/d_fle_b1-01", "7430", + // "rv64i_m/D/d_fle_b19-01", "c4c0", + // "rv64i_m/D/d_flt_b1-01", "7430", + // "rv64i_m/D/d_flt_b19-01", "d800", "rv64i_m/D/d_fmadd_b14-01", "3fd0", "rv64i_m/D/d_fmadd_b16-01", "43b0", "rv64i_m/D/d_fmadd_b17-01", "43b0", From db8d5d58e4d26dae97ce6f8d4714951c5ae999f2 Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Sat, 30 Oct 2021 07:34:53 -0700 Subject: [PATCH 12/19] Added instructions for rv64i_m/D --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 420ea87a1..975b8f141 100644 --- a/README.md +++ b/README.md @@ -16,6 +16,8 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F +cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv64i_m/D + mkdir build cd build set RISCV=/cad/riscv/gcc/bin (or whatever your path is) From fe2cda493c77a98d9a4394e571fd20ac805086ca Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 31 Oct 2021 18:33:43 -0700 Subject: [PATCH 13/19] fix buildroot graphical sim --- wally-pipelined/regression/sim-buildroot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/sim-buildroot b/wally-pipelined/regression/sim-buildroot index 04c9919cd..8814ca6f3 100755 --- a/wally-pipelined/regression/sim-buildroot +++ b/wally-pipelined/regression/sim-buildroot @@ -30,4 +30,4 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}" echo "INSTR_WAVEON = ${INSTR_WAVEON}" echo "CHECKPOINT = ${CHECKPOINT}" -vsim -do wally-buildroot.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT +vsim -do "do ./wally-buildroot.do $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT" From 60573b92b257666afb2ae33d2dd6b3c6df112352 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 08:48:46 -0700 Subject: [PATCH 14/19] Adding custom Wally test infrastructure --- .../{wally-I.py => wally-I-PIPELINE.py} | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 82 +++++++++++++++++++ .../riscv-test-suite/rv64i_m/D/Makefile | 3 + .../riscv-test-suite/rv64i_m/D/Makefrag | 35 ++++++++ .../rv64i_m/I/src/WALLY-PIPELINE.S | 82 +++++++++++++++++++ .../regression/regression-wally.py | 2 +- wally-pipelined/testbench/testbench.sv | 51 ++---------- wally-pipelined/testbench/tests.vh | 30 ++++++- 8 files changed, 242 insertions(+), 45 deletions(-) rename tests/testgen/{wally-I.py => wally-I-PIPELINE.py} (99%) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/wally-I.py b/tests/testgen/wally-I-PIPELINE.py similarity index 99% rename from tests/testgen/wally-I.py rename to tests/testgen/wally-I-PIPELINE.py index b186e21c5..80ac853b1 100755 --- a/tests/testgen/wally-I.py +++ b/tests/testgen/wally-I-PIPELINE.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 ################################## -# wally-I.py +# wally-I-PIPELINE.py # # David_Harris@hmc.edu 27 October 2021 # diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S new file mode 100644 index 000000000..28d36e3ed --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S @@ -0,0 +1,82 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 08:46:04.665699// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + +RVTEST_SIGBASE( x8,signature_x8_1) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile new file mode 100644 index 000000000..a474441d6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile @@ -0,0 +1,3 @@ +include ../../Makefile.include + +$(eval $(call compile_template,-march=rv64id -mabi=lp64 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag new file mode 100644 index 000000000..261a9a852 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag @@ -0,0 +1,35 @@ +# RISC-V Architecture Test RV64IM Makefrag +# +# Copyright (c) 2018, Imperas Software Ltd. +# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV64IM architectural tests + +rv64im_sc_tests = \ + +rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests)) + +target_tests += $(rv64im_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S new file mode 100644 index 000000000..e7d29cc8d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S @@ -0,0 +1,82 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 08:46:04.668632// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + +RVTEST_SIGBASE( x8,signature_x8_1) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 79532c5c8..49ca87129 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -41,7 +41,7 @@ def getBuildrootTC(short): BRgrepstr=str(MAX_EXPECTED)+" instructions" return TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr) -tests64 = ["arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"] +tests64 = ["wally64i", "arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"] for test in tests64: tc = TestCase( name=test, diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index 8c25f1549..13ba7e16a 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -94,7 +94,9 @@ logic [3:0] dummy; "imperas64c": if (`C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "testsBP64": tests = testsBP64; - // *** add arch f and d tests, peripheral tests + "wally64i": tests = wally64i; + "wally64priv": tests = wally64priv; + "wally64periph": tests = wally64periph; endcase end else begin // RV32 case (TEST) @@ -111,51 +113,15 @@ logic [3:0] dummy; "imperas32a": if (`A_SUPPORTED) tests = imperas32a; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; - // ***add arch f and d tests + "wally32i": tests = wally32i; + "wally32priv": tests = wally32priv; + "wally32periph": tests = wally32periph; endcase end if (tests.size() == 1) begin $display("TEST %s not supported in this configuration", TEST); $stop; end - //if (TEST == "arch-64m") //tests = {archtests64m}; - /* if (`XLEN == 64) begin // RV64 - if (`TESTSBP) begin - tests = testsBP64; - // testsbp should not run the other tests. It starts at address 0 rather than - // 0x8000_0000, the next if must remain an else if. - end else if (TESTSPERIPH) - tests = imperastests64periph; - else if (TESTSPRIV) - tests = imperastests64p; - else begin - tests = {imperastests64p,imperastests64i, imperastests64periph}; - if (`C_SUPPORTED) tests = {tests, imperastests64ic}; - else tests = {tests, imperastests64iNOc}; - if (`F_SUPPORTED) tests = {imperastests64f, tests}; - if (`D_SUPPORTED) tests = {imperastests64d, tests}; - if (`MEM_VIRTMEM) tests = {imperastests64mmu, tests}; - if (`A_SUPPORTED) tests = {imperastests64a, tests}; - if (`M_SUPPORTED) tests = {imperastests64m, tests}; - end - //tests = {imperastests64a, tests}; - end else begin // RV32 - // *** add the 32 bit bp tests - if (TESTSPERIPH) - tests = imperastests32periph; - else if (TESTSPRIV) - tests = imperastests32p; - else begin - tests = {archtests32i, imperastests32i, imperastests32p};//,imperastests32periph}; *** broken at the moment - if (`C_SUPPORTED) tests = {tests, imperastests32ic}; - else tests = {tests, imperastests32iNOc}; - if (`F_SUPPORTED) tests = {imperastests32f, tests}; - if (`MEM_VIRTMEM) tests = {imperastests32mmu, tests}; - if (`A_SUPPORTED) tests = {imperastests32a, tests}; - if (`M_SUPPORTED) tests = {imperastests32m, tests}; - tests = {archtests32i}; - end - end */ end string signame, memfilename, pathname; @@ -203,9 +169,10 @@ logic [3:0] dummy; end end // read test vectors into memory - if (tests[0] == `IMPERASTEST) + pathname = tvpaths[tests[0].atoi()]; +/* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; - else pathname = tvpaths[1]; + else pathname = tvpaths[1]; */ memfilename = {pathname, tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.uncore.dtim.RAM); ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index 42b1fc0b5..b10be8765 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -25,10 +25,12 @@ `define IMPERASTEST "0" `define RISCVARCHTEST "1" +`define WALLYTEST "2" string tvpaths[] = '{ "../../tests/imperas-riscv-tests/work/", - "../../addins/riscv-arch-test/work/" + "../../addins/riscv-arch-test/work/", + "../../tests/wally-riscv-arch-test/work/" }; string imperas32mmu[] = '{ @@ -1067,4 +1069,30 @@ string imperas32f[] = '{ "rv32i_m/I/xori-01", "4010" }; + string wally64i[] = '{ + `WALLYTEST, + "rv64i_m/I/add-01", "9010" +// "rv64i_m/I/pipeline-01", "9010" + }; + + string wally64priv[] = '{ + `WALLYTEST + }; + + string wally64periph[] = '{ + `WALLYTEST + }; + +string wally32i[] = '{ + `WALLYTEST, + "rv64i_m/I/pipeline-01", "9010" + }; + + string wally32priv[] = '{ + `WALLYTEST + }; + + string wally32periph[] = '{ + `WALLYTEST + }; From dda035891af2bebcb455877026cbb17dc85f9092 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 12:44:35 -0700 Subject: [PATCH 15/19] PIPELINE test running --- .../{wally-I-PIPELINE.py => PIPELINE.py} | 17 +++- tests/testgen/testgen_footer.S | 1 + tests/wally-riscv-arch-test/Makefile | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 9 +- .../riscv-test-suite/rv64i_m/I/Makefrag | 1 + .../rv64i_m/I/src/WALLY-PIPELINE.S | 82 ------------------- wally-pipelined/src/fpu/fpudivsqrtrecur.sv | 2 +- wally-pipelined/src/muldiv/div.sv | 9 +- wally-pipelined/testbench/tests.vh | 4 +- 9 files changed, 36 insertions(+), 91 deletions(-) rename tests/testgen/{wally-I-PIPELINE.py => PIPELINE.py} (90%) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/wally-I-PIPELINE.py b/tests/testgen/PIPELINE.py similarity index 90% rename from tests/testgen/wally-I-PIPELINE.py rename to tests/testgen/PIPELINE.py index 80ac853b1..e6b8bde29 100755 --- a/tests/testgen/wally-I-PIPELINE.py +++ b/tests/testgen/PIPELINE.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 ################################## -# wally-I-PIPELINE.py +# PIPELINE.py # # David_Harris@hmc.edu 27 October 2021 # @@ -108,7 +108,7 @@ for xlen in xlens: storecmd = "sd" wordsize = 8 pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/" - fname = pathname + "src/WALLY-PIPELINE.S" + fname = pathname + "src/PIPELINE.S" testnum = 0 # print custom header part @@ -126,6 +126,19 @@ for xlen in xlens: for line in h: f.write(line) + maxreg = 5 + for i in range(1): + instr = instrs[randint(0,len(instrs)-1)] + reg1 = randint(0,maxreg) + reg2 = randint(0,maxreg) + reg3 = randint(1,maxreg) + line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" + f.write(line) + + for i in range(1,maxreg+1): + line = storecmd + " x" + str(i) + ", " + str(wordsize*(i-1)) + "(x8)\n" + f.write(line) + # print directed and random test vectors # for a in corners: # for b in corners: diff --git a/tests/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S index b0137b792..5f72c5b49 100644 --- a/tests/testgen/testgen_footer.S +++ b/tests/testgen/testgen_footer.S @@ -1,3 +1,4 @@ +#endif RVTEST_CODE_END RVMODEL_HALT diff --git a/tests/wally-riscv-arch-test/Makefile b/tests/wally-riscv-arch-test/Makefile index 8e817231d..0f6f2be08 100644 --- a/tests/wally-riscv-arch-test/Makefile +++ b/tests/wally-riscv-arch-test/Makefile @@ -87,7 +87,7 @@ simulate: run -C $(SUITEDIR) verify: simulate - riscv-test-env/verify.sh +# riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values postverify: ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S index 28d36e3ed..1fd7866e1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S // David_Harris@hmc.edu -// Created 2021-11-01 08:46:04.665699// +// Created 2021-11-01 11:43:39.219968// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -32,6 +32,13 @@ RVTEST_CODE_BEGIN RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) RVTEST_SIGBASE( x8,signature_x8_1) +AND x1, x3, x3 +sw x1, 0(x8) +sw x2, 4(x8) +sw x3, 8(x8) +sw x4, 12(x8) +sw x5, 16(x8) +#endif RVTEST_CODE_END RVMODEL_HALT diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag index f85d344df..d14e2c26b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag @@ -29,6 +29,7 @@ rv64i_sc_tests = \ add-01 \ + PIPELINE \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S deleted file mode 100644 index e7d29cc8d..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +++ /dev/null @@ -1,82 +0,0 @@ -/////////////////////////////////////////// -// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu -// Created 2021-11-01 08:46:04.668632// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - -RVTEST_SIGBASE( x8,signature_x8_1) -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN - - -signature_x8_0: - .fill 0*(XLEN/32),4,0xdeadbeef - - -signature_x8_1: - .fill 19*(XLEN/32),4,0xdeadbeef - - -signature_x1_0: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_1: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_2: - .fill 148*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -RVMODEL_DATA_END -// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu diff --git a/wally-pipelined/src/fpu/fpudivsqrtrecur.sv b/wally-pipelined/src/fpu/fpudivsqrtrecur.sv index 0d1b89ff2..c5a646456 100644 --- a/wally-pipelined/src/fpu/fpudivsqrtrecur.sv +++ b/wally-pipelined/src/fpu/fpudivsqrtrecur.sv @@ -55,7 +55,7 @@ module fpudivsqrtrecur ( // Special Cases // *** shift to handle denorms in hardware - assign FDivSqrtResSign = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs + assign FDivSqrtResSgn = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs always_comb begin if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index b299af032..d7f311a3f 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -64,7 +64,10 @@ module intdiv #(parameter WIDTH=64) logic [WIDTH-1:0] QT, remT; logic D_NegOne; logic Max_N; - + + logic otfzerov; + logic tcQ; + logic tcR; // Check if negative (two's complement) // If so, convert to positive @@ -182,7 +185,9 @@ module divide4 #(parameter WIDTH=64) logic CshiftQ, CshiftQM; logic [WIDTH+3:0] rem1, rem2, rem3; logic [WIDTH+3:0] SumR, CarryR; - logic [WIDTH:0] Qt; + logic [WIDTH:0] Qt; + + logic ulp; // Create one's complement values of Divisor (for q*D) assign divi1 = {3'h0, op2, 1'b0}; diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index b10be8765..e897819f7 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -1071,8 +1071,8 @@ string imperas32f[] = '{ string wally64i[] = '{ `WALLYTEST, - "rv64i_m/I/add-01", "9010" -// "rv64i_m/I/pipeline-01", "9010" + "rv64i_m/I/add-01", "9010", + "rv64i_m/I/PIPELINE", "2010" }; string wally64priv[] = '{ From d7f0abca5a3cfa087ff544e73de621dd5cbffe59 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 13:17:49 -0700 Subject: [PATCH 16/19] Add3d wally32i test --- tests/testgen/PIPELINE.py | 8 +- .../riscv-test-suite/rv32i_m/I/Makefrag | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 89 ------------------- .../regression/regression-wally.py | 2 +- wally-pipelined/testbench/tests.vh | 4 +- 5 files changed, 8 insertions(+), 97 deletions(-) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/PIPELINE.py b/tests/testgen/PIPELINE.py index e6b8bde29..6432bb023 100755 --- a/tests/testgen/PIPELINE.py +++ b/tests/testgen/PIPELINE.py @@ -88,10 +88,10 @@ def writeVector(a, b, storecmd, xlen): ################################## # change these to suite your tests -instrs = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"] +instrs = ["ADD"] # "SUB", "XOR", "OR", "AND", "SLT", "SLTU", ] author = "David_Harris@hmc.edu" xlens = [32, 64] -numrand = 100 +numrand = 1000 # setup seed(0) # make tests reproducible @@ -127,10 +127,10 @@ for xlen in xlens: f.write(line) maxreg = 5 - for i in range(1): + for i in range(numrand): instr = instrs[randint(0,len(instrs)-1)] reg1 = randint(0,maxreg) - reg2 = randint(0,maxreg) + reg2 = randint(1,maxreg) reg3 = randint(1,maxreg) line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" f.write(line) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag index e2cdf44da..49f87b201 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag @@ -28,7 +28,7 @@ # Description: Makefrag for RV32I architectural tests rv32i_sc_tests = \ - WALLY-PIPELINE \ + PIPELINE \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S deleted file mode 100644 index 1fd7866e1..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +++ /dev/null @@ -1,89 +0,0 @@ -/////////////////////////////////////////// -// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu -// Created 2021-11-01 11:43:39.219968// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - -RVTEST_SIGBASE( x8,signature_x8_1) -AND x1, x3, x3 -sw x1, 0(x8) -sw x2, 4(x8) -sw x3, 8(x8) -sw x4, 12(x8) -sw x5, 16(x8) -#endif -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN - - -signature_x8_0: - .fill 0*(XLEN/32),4,0xdeadbeef - - -signature_x8_1: - .fill 19*(XLEN/32),4,0xdeadbeef - - -signature_x1_0: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_1: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_2: - .fill 148*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -RVMODEL_DATA_END -// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 49ca87129..ada9fe383 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -49,7 +49,7 @@ for test in tests64: grepstr="All tests ran without failures") configs.append(tc) #tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] -tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] +tests32 = ["wally32i", "arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] for test in tests32: tc = TestCase( name=test, diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index e897819f7..7e33ef68c 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -1072,7 +1072,7 @@ string imperas32f[] = '{ string wally64i[] = '{ `WALLYTEST, "rv64i_m/I/add-01", "9010", - "rv64i_m/I/PIPELINE", "2010" + "rv64i_m/I/PIPELINE", "3010" }; string wally64priv[] = '{ @@ -1085,7 +1085,7 @@ string imperas32f[] = '{ string wally32i[] = '{ `WALLYTEST, - "rv64i_m/I/pipeline-01", "9010" + "rv32i_m/I/PIPELINE", "3010" }; string wally32priv[] = '{ From d449795b3ea15dc4fe0332011974f4ef2a3c79e4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 13:24:18 -0700 Subject: [PATCH 17/19] simplified header and footer --- tests/testgen/testgen_footer.S | 1 - tests/testgen/testgen_header.S | 5 ----- 2 files changed, 6 deletions(-) diff --git a/tests/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S index 5f72c5b49..b0137b792 100644 --- a/tests/testgen/testgen_footer.S +++ b/tests/testgen/testgen_footer.S @@ -1,4 +1,3 @@ -#endif RVTEST_CODE_END RVMODEL_HALT diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S index 3b3bd6876..df9f0dcfd 100644 --- a/tests/testgen/testgen_header.S +++ b/tests/testgen/testgen_header.S @@ -16,7 +16,6 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -24,8 +23,4 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - RVTEST_SIGBASE( x8,signature_x8_1) From 0cc71f1dec065322dc103b4bd91f1cda7bc91648 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 13:36:07 -0700 Subject: [PATCH 18/19] added some missing files --- .../riscv-test-suite/rv32i_m/I/src/PIPELINE.S | 1082 +++++++++++++++++ .../riscv-test-suite/rv64i_m/I/src/PIPELINE.S | 1082 +++++++++++++++++ 2 files changed, 2164 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S new file mode 100644 index 000000000..370fb8f29 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S @@ -0,0 +1,1082 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 13:22:54.967257// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE( x8,signature_x8_1) +ADD x3, x3, x1 +ADD x4, x3, x3 +ADD x5, x4, x2 +ADD x1, x2, x2 +ADD x2, x4, x5 +ADD x3, x0, x1 +ADD x3, x4, x1 +ADD x2, x2, x5 +ADD x3, x3, x5 +ADD x1, x4, x1 +ADD x5, x5, x1 +ADD x3, x2, x2 +ADD x2, x1, x5 +ADD x4, x1, x5 +ADD x5, x0, x3 +ADD x5, x0, x3 +ADD x5, x5, x1 +ADD x5, x4, x2 +ADD x5, x3, x1 +ADD x2, x2, x5 +ADD x2, x1, x2 +ADD x4, x4, x3 +ADD x2, x0, x2 +ADD x4, x0, x5 +ADD x2, x4, x2 +ADD x4, x4, x3 +ADD x1, x5, x3 +ADD x4, x4, x1 +ADD x1, x1, x2 +ADD x3, x0, x2 +ADD x1, x2, x4 +ADD x1, x1, x2 +ADD x2, x0, x1 +ADD x3, x3, x1 +ADD x1, x0, x5 +ADD x4, x1, x1 +ADD x1, x5, x1 +ADD x3, x4, x1 +ADD x3, x1, x1 +ADD x1, x3, x2 +ADD x1, x0, x5 +ADD x3, x1, x3 +ADD x2, x4, x2 +ADD x2, x5, x2 +ADD x1, x4, x3 +ADD x1, x5, x2 +ADD x5, x5, x4 +ADD x4, x5, x3 +ADD x1, x1, x5 +ADD x3, x5, x1 +ADD x2, x4, x3 +ADD x5, x3, x3 +ADD x5, x5, x3 +ADD x4, x5, x3 +ADD x1, x5, x1 +ADD x2, x5, x3 +ADD x4, x1, x4 +ADD x5, x0, x4 +ADD x2, x5, x1 +ADD x2, x0, x3 +ADD x5, x4, x4 +ADD x3, x0, x4 +ADD x4, x3, x1 +ADD x2, x4, x1 +ADD x3, x3, x4 +ADD x1, x1, x1 +ADD x5, x1, x1 +ADD x2, x2, x3 +ADD x1, x3, x4 +ADD x1, x2, x4 +ADD x3, x1, x5 +ADD x1, x1, x3 +ADD x3, x0, x2 +ADD x1, x2, x5 +ADD x4, x5, x4 +ADD x2, x4, x2 +ADD x1, x4, x3 +ADD x3, x1, x3 +ADD x3, x2, x1 +ADD x2, x0, x3 +ADD x3, x4, x3 +ADD x3, x4, x2 +ADD x1, x3, x2 +ADD x1, x1, x5 +ADD x3, x3, x3 +ADD x5, x0, x1 +ADD x3, x3, x3 +ADD x4, x3, x1 +ADD x3, x0, x3 +ADD x4, x1, x5 +ADD x2, x0, x1 +ADD x1, x0, x4 +ADD x5, x3, x5 +ADD x5, x3, x4 +ADD x3, x3, x1 +ADD x2, x2, x5 +ADD x1, x1, x3 +ADD x5, x5, x1 +ADD x1, x5, x2 +ADD x2, x3, x3 +ADD x2, x1, x5 +ADD x4, x1, x4 +ADD x1, x4, x2 +ADD x4, x1, x5 +ADD x3, x4, x4 +ADD x5, x3, x2 +ADD x3, x0, x3 +ADD x2, x0, x5 +ADD x4, x4, x2 +ADD x1, x5, x4 +ADD x1, x4, x1 +ADD x3, x1, x1 +ADD x2, x3, x3 +ADD x3, x5, x4 +ADD x1, x4, x5 +ADD x5, x5, x5 +ADD x2, x5, x4 +ADD x4, x4, x5 +ADD x5, x3, x5 +ADD x2, x0, x1 +ADD x3, x4, x5 +ADD x3, x0, x4 +ADD x4, x3, x4 +ADD x2, x1, x2 +ADD x1, x5, x3 +ADD x2, x3, x4 +ADD x2, x4, x1 +ADD x5, x3, x1 +ADD x1, x3, x4 +ADD x1, x3, x2 +ADD x2, x4, x5 +ADD x3, x0, x5 +ADD x1, x3, x4 +ADD x5, x4, x4 +ADD x5, x5, x1 +ADD x3, x1, x4 +ADD x1, x4, x2 +ADD x2, x3, x3 +ADD x1, x2, x1 +ADD x1, x3, x3 +ADD x5, x1, x1 +ADD x1, x4, x3 +ADD x4, x3, x5 +ADD x1, x0, x4 +ADD x1, x3, x2 +ADD x1, x3, x4 +ADD x1, x2, x3 +ADD x3, x0, x1 +ADD x2, x2, x3 +ADD x1, x1, x3 +ADD x2, x1, x1 +ADD x3, x5, x1 +ADD x5, x5, x1 +ADD x4, x1, x2 +ADD x3, x3, x3 +ADD x3, x0, x2 +ADD x3, x3, x3 +ADD x1, x1, x5 +ADD x3, x4, x5 +ADD x2, x3, x2 +ADD x2, x2, x5 +ADD x3, x1, x3 +ADD x2, x5, x1 +ADD x1, x3, x1 +ADD x5, x3, x3 +ADD x5, x5, x2 +ADD x1, x2, x3 +ADD x5, x3, x3 +ADD x1, x3, x4 +ADD x4, x5, x3 +ADD x4, x2, x3 +ADD x3, x1, x1 +ADD x2, x4, x5 +ADD x4, x3, x2 +ADD x4, x1, x2 +ADD x3, x4, x2 +ADD x4, x5, x1 +ADD x4, x2, x1 +ADD x3, x0, x2 +ADD x5, x5, x3 +ADD x1, x3, x4 +ADD x4, x1, x5 +ADD x1, x5, x1 +ADD x1, x5, x1 +ADD x5, x3, x5 +ADD x3, x3, x1 +ADD x5, x2, x2 +ADD x3, x0, x1 +ADD x1, x4, x3 +ADD x4, x1, x1 +ADD x2, x2, x5 +ADD x4, x4, x1 +ADD x3, x5, x3 +ADD x2, x2, x5 +ADD x4, x0, x1 +ADD x2, x4, x4 +ADD x4, x2, x4 +ADD x5, x3, x4 +ADD x4, x3, x1 +ADD x1, x1, x4 +ADD x4, x0, x3 +ADD x1, x0, x5 +ADD x1, x5, x4 +ADD x5, x0, x1 +ADD x2, x2, x3 +ADD x2, x4, x3 +ADD x3, x3, x4 +ADD x4, x1, x3 +ADD x2, x1, x4 +ADD x2, x1, x2 +ADD x4, x2, x4 +ADD x2, x3, x2 +ADD x1, x1, x5 +ADD x1, x0, x2 +ADD x2, x2, x1 +ADD x5, x4, x3 +ADD x3, x5, x5 +ADD x1, x3, x4 +ADD x4, x4, x4 +ADD x2, x5, x4 +ADD x1, x2, x1 +ADD x1, x1, x3 +ADD x2, x5, x1 +ADD x5, x3, x2 +ADD x4, x4, x2 +ADD x1, x2, x5 +ADD x5, x2, x3 +ADD x1, x2, x3 +ADD x1, x1, x3 +ADD x2, x4, x3 +ADD x3, x2, x3 +ADD x3, x2, x4 +ADD x5, x0, x3 +ADD x4, x0, x4 +ADD x4, x0, x4 +ADD x1, x3, x1 +ADD x2, x1, x1 +ADD x5, x1, x4 +ADD x4, x3, x5 +ADD x4, x1, x2 +ADD x3, x1, x3 +ADD x5, x3, x1 +ADD x2, x4, x5 +ADD x5, x3, x5 +ADD x3, x4, x3 +ADD x5, x0, x1 +ADD x2, x1, x4 +ADD x5, x2, x1 +ADD x4, x0, x1 +ADD x3, x0, x5 +ADD x3, x5, x5 +ADD x1, x5, x2 +ADD x2, x5, x3 +ADD x3, x5, x4 +ADD x5, x1, x1 +ADD x1, x2, x5 +ADD x2, x3, x2 +ADD x4, x1, x2 +ADD x2, x1, x2 +ADD x5, x2, x5 +ADD x1, x5, x4 +ADD x3, x4, x5 +ADD x1, x3, x3 +ADD x4, x4, x2 +ADD x1, x4, x3 +ADD x4, x1, x5 +ADD x4, x2, x3 +ADD x3, x1, x1 +ADD x2, x2, x4 +ADD x3, x2, x2 +ADD x5, x2, x5 +ADD x3, x5, x2 +ADD x1, x3, x1 +ADD x2, x0, x1 +ADD x3, x0, x1 +ADD x4, x1, x2 +ADD x3, x1, x3 +ADD x4, x5, x3 +ADD x3, x0, x4 +ADD x1, x0, x5 +ADD x1, x3, x2 +ADD x2, x4, x5 +ADD x2, x2, x2 +ADD x5, x0, x2 +ADD x4, x5, x1 +ADD x2, x4, x4 +ADD x4, x2, x3 +ADD x4, x5, x1 +ADD x2, x2, x3 +ADD x3, x1, x5 +ADD x3, x5, x4 +ADD x1, x3, x4 +ADD x5, x4, x3 +ADD x5, x0, x5 +ADD x4, x5, x1 +ADD x4, x5, x1 +ADD x1, x3, x1 +ADD x3, x5, x1 +ADD x5, x5, x2 +ADD x2, x3, x3 +ADD x2, x4, x3 +ADD x3, x1, x2 +ADD x5, x4, x1 +ADD x3, x2, x3 +ADD x4, x2, x4 +ADD x2, x1, x1 +ADD x3, x3, x2 +ADD x3, x5, x4 +ADD x4, x0, x5 +ADD x2, x1, x5 +ADD x5, x5, x2 +ADD x5, x4, x5 +ADD x3, x3, x3 +ADD x3, x0, x4 +ADD x5, x4, x5 +ADD x4, x2, x2 +ADD x2, x0, x5 +ADD x1, x2, x4 +ADD x2, x5, x5 +ADD x2, x2, x5 +ADD x4, x5, x3 +ADD x5, x5, x2 +ADD x4, x2, x2 +ADD x2, x4, x4 +ADD x2, x4, x1 +ADD x4, x3, x1 +ADD x4, x2, x3 +ADD x1, x4, x3 +ADD x1, x0, x4 +ADD x4, x1, x4 +ADD x1, x5, x4 +ADD x2, x2, x5 +ADD x4, x2, x1 +ADD x1, x4, x2 +ADD x3, x4, x3 +ADD x1, x0, x2 +ADD x1, x0, x3 +ADD x3, x3, x2 +ADD x5, x5, x2 +ADD x5, x3, x3 +ADD x2, x1, x2 +ADD x5, x5, x1 +ADD x2, x4, x4 +ADD x1, x4, x1 +ADD x3, x2, x2 +ADD x3, x5, x3 +ADD x5, x1, x4 +ADD x2, x0, x5 +ADD x2, x2, x1 +ADD x4, x4, x2 +ADD x2, x5, x3 +ADD x5, x4, x1 +ADD x1, x4, x3 +ADD x5, x0, x4 +ADD x3, x4, x4 +ADD x1, x4, x3 +ADD x2, x2, x1 +ADD x5, x0, x3 +ADD x1, x0, x4 +ADD x5, x3, x1 +ADD x4, x2, x1 +ADD x5, x3, x3 +ADD x5, x5, x3 +ADD x1, x3, x2 +ADD x4, x2, x2 +ADD x1, x2, x1 +ADD x2, x2, x1 +ADD x3, x4, x1 +ADD x4, x4, x4 +ADD x4, x0, x5 +ADD x1, x0, x5 +ADD x1, x2, x3 +ADD x5, x0, x2 +ADD x4, x0, x1 +ADD x2, x1, x5 +ADD x2, x1, x2 +ADD x4, x0, x4 +ADD x3, x1, x2 +ADD x3, x1, x2 +ADD x4, x1, x4 +ADD x4, x4, x2 +ADD x1, x1, x5 +ADD x2, x5, x2 +ADD x5, x0, x3 +ADD x1, x0, x1 +ADD x1, x1, x4 +ADD x3, x3, x5 +ADD x5, x1, x3 +ADD x1, x4, x4 +ADD x3, x3, x5 +ADD x2, x3, x4 +ADD x4, x3, x2 +ADD x4, x5, x4 +ADD x5, x2, x3 +ADD x5, x4, x1 +ADD x1, x1, x3 +ADD x5, x3, x1 +ADD x1, x1, x4 +ADD x4, x5, x4 +ADD x5, x5, x4 +ADD x3, x1, x2 +ADD x5, x3, x2 +ADD x3, x4, x1 +ADD x4, x1, x3 +ADD x2, x1, x3 +ADD x1, x2, x4 +ADD x1, x4, x4 +ADD x2, x2, x4 +ADD x1, x1, x2 +ADD x4, x1, x1 +ADD x1, x3, x1 +ADD x2, x4, x5 +ADD x2, x1, x2 +ADD x2, x0, x5 +ADD x3, x2, x5 +ADD x4, x5, x1 +ADD x5, x1, x3 +ADD x4, x4, x2 +ADD x3, x1, x4 +ADD x3, x3, x5 +ADD x2, x3, x1 +ADD x5, x0, x5 +ADD x5, x5, x2 +ADD x2, x2, x5 +ADD x1, x0, x1 +ADD x3, x2, x4 +ADD x3, x5, x4 +ADD x2, x5, x4 +ADD x1, x4, x5 +ADD x5, x0, x2 +ADD x4, x4, x2 +ADD x5, x2, x1 +ADD x4, x3, x2 +ADD x5, x3, x1 +ADD x5, x2, x2 +ADD x5, x0, x4 +ADD x4, x2, x5 +ADD x2, x3, x3 +ADD x2, x4, x3 +ADD x4, x4, x2 +ADD x4, x0, x4 +ADD x3, x4, x1 +ADD x3, x1, x1 +ADD x2, x2, x1 +ADD x5, x5, x2 +ADD x4, x0, x1 +ADD x4, x5, x1 +ADD x1, x2, x1 +ADD x3, x1, x4 +ADD x4, x1, x1 +ADD x1, x4, x3 +ADD x4, x2, x5 +ADD x4, x5, x3 +ADD x2, x1, x3 +ADD x3, x5, x3 +ADD x1, x4, x2 +ADD x4, x2, x5 +ADD x3, x5, x3 +ADD x4, x2, x3 +ADD x3, x0, x4 +ADD x3, x3, x2 +ADD x3, x5, x2 +ADD x4, x1, x1 +ADD x4, x3, x5 +ADD x5, x5, x4 +ADD x3, x3, x2 +ADD x3, x0, x4 +ADD x1, x1, x4 +ADD x3, x3, x1 +ADD x2, x5, x3 +ADD x1, x1, x3 +ADD x4, x0, x1 +ADD x5, x1, x1 +ADD x2, x0, x4 +ADD x4, x4, x5 +ADD x2, x4, x2 +ADD x4, x3, x4 +ADD x4, x3, x2 +ADD x1, x4, x3 +ADD x3, x5, x3 +ADD x5, x5, x2 +ADD x1, x2, x1 +ADD x5, x0, x2 +ADD x5, x3, x2 +ADD x5, x1, x4 +ADD x4, x4, x1 +ADD x4, x4, x4 +ADD x3, x3, x5 +ADD x4, x3, x3 +ADD x3, x4, x5 +ADD x3, x3, x2 +ADD x4, x3, x1 +ADD x4, x4, x4 +ADD x3, x3, x2 +ADD x2, x3, x2 +ADD x4, x2, x3 +ADD x2, x4, x1 +ADD x1, x4, x1 +ADD x3, x2, x1 +ADD x2, x3, x4 +ADD x2, x3, x2 +ADD x5, x0, x3 +ADD x2, x5, x3 +ADD x4, x1, x5 +ADD x1, x4, x4 +ADD x3, x3, x5 +ADD x1, x0, x1 +ADD x5, x1, x4 +ADD x5, x5, x1 +ADD x3, x5, x3 +ADD x2, x5, x2 +ADD x4, x4, x3 +ADD x4, x3, x3 +ADD x1, x1, x2 +ADD x5, x3, x4 +ADD x1, x2, x1 +ADD x4, x1, x1 +ADD x1, x4, x2 +ADD x3, x4, x4 +ADD x1, x4, x5 +ADD x1, x4, x4 +ADD x3, x3, x5 +ADD x2, x0, x1 +ADD x3, x4, x5 +ADD x1, x3, x3 +ADD x4, x2, x2 +ADD x3, x5, x5 +ADD x1, x4, x3 +ADD x5, x1, x3 +ADD x4, x0, x5 +ADD x1, x2, x4 +ADD x2, x3, x5 +ADD x4, x0, x1 +ADD x3, x0, x3 +ADD x3, x0, x3 +ADD x5, x4, x2 +ADD x5, x2, x5 +ADD x1, x1, x4 +ADD x3, x2, x2 +ADD x4, x4, x5 +ADD x1, x2, x5 +ADD x4, x4, x2 +ADD x3, x4, x2 +ADD x2, x4, x2 +ADD x5, x3, x2 +ADD x3, x2, x2 +ADD x2, x4, x2 +ADD x3, x2, x2 +ADD x3, x0, x3 +ADD x5, x0, x1 +ADD x2, x2, x1 +ADD x5, x1, x5 +ADD x4, x3, x1 +ADD x5, x0, x1 +ADD x3, x2, x2 +ADD x3, x5, x4 +ADD x3, x0, x1 +ADD x3, x5, x3 +ADD x5, x0, x2 +ADD x1, x2, x5 +ADD x5, x3, x3 +ADD x5, x2, x3 +ADD x4, x3, x1 +ADD x1, x1, x5 +ADD x4, x5, x4 +ADD x3, x1, x1 +ADD x4, x1, x2 +ADD x4, x2, x5 +ADD x4, x4, x2 +ADD x4, x2, x4 +ADD x2, x5, x1 +ADD x2, x1, x2 +ADD x2, x2, x2 +ADD x2, x4, x1 +ADD x2, x5, x4 +ADD x5, x4, x2 +ADD x5, x5, x2 +ADD x4, x5, x1 +ADD x2, x0, x4 +ADD x2, x4, x4 +ADD x4, x4, x5 +ADD x5, x1, x1 +ADD x2, x0, x1 +ADD x4, x3, x3 +ADD x3, x5, x4 +ADD x2, x1, x5 +ADD x5, x0, x1 +ADD x2, x5, x4 +ADD x5, x5, x2 +ADD x2, x0, x5 +ADD x3, x5, x3 +ADD x2, x4, x3 +ADD x5, x3, x2 +ADD x3, x2, x4 +ADD x3, x1, x4 +ADD x4, x2, x5 +ADD x5, x4, x4 +ADD x2, x5, x5 +ADD x3, x3, x2 +ADD x5, x4, x2 +ADD x4, x2, x3 +ADD x1, x3, x5 +ADD x1, x2, x4 +ADD x1, x1, x5 +ADD x2, x0, x2 +ADD x5, x5, x3 +ADD x1, x0, x1 +ADD x4, x2, x2 +ADD x3, x5, x3 +ADD x1, x4, x4 +ADD x5, x1, x1 +ADD x4, x2, x2 +ADD x2, x2, x2 +ADD x5, x5, x2 +ADD x1, x4, x2 +ADD x1, x3, x5 +ADD x4, x4, x1 +ADD x2, x2, x5 +ADD x3, x2, x2 +ADD x5, x3, x4 +ADD x4, x2, x1 +ADD x3, x0, x5 +ADD x4, x4, x4 +ADD x2, x4, x4 +ADD x2, x4, x1 +ADD x4, x2, x1 +ADD x3, x2, x1 +ADD x5, x0, x1 +ADD x4, x1, x1 +ADD x3, x3, x1 +ADD x5, x0, x4 +ADD x4, x0, x2 +ADD x4, x0, x5 +ADD x4, x4, x3 +ADD x4, x4, x1 +ADD x2, x4, x2 +ADD x4, x0, x5 +ADD x2, x2, x3 +ADD x1, x5, x1 +ADD x2, x0, x3 +ADD x1, x4, x2 +ADD x2, x0, x3 +ADD x1, x4, x1 +ADD x4, x1, x3 +ADD x4, x5, x4 +ADD x4, x0, x3 +ADD x4, x3, x5 +ADD x2, x4, x1 +ADD x5, x5, x4 +ADD x2, x1, x1 +ADD x5, x0, x4 +ADD x5, x5, x1 +ADD x3, x4, x3 +ADD x3, x3, x5 +ADD x2, x4, x3 +ADD x3, x5, x4 +ADD x2, x4, x1 +ADD x3, x3, x1 +ADD x5, x4, x2 +ADD x1, x4, x5 +ADD x1, x4, x3 +ADD x3, x1, x3 +ADD x1, x3, x4 +ADD x3, x5, x4 +ADD x5, x0, x4 +ADD x5, x3, x3 +ADD x4, x1, x1 +ADD x3, x4, x4 +ADD x2, x3, x5 +ADD x3, x3, x2 +ADD x2, x2, x2 +ADD x5, x1, x5 +ADD x5, x3, x2 +ADD x3, x4, x2 +ADD x5, x1, x3 +ADD x1, x4, x5 +ADD x2, x3, x2 +ADD x1, x4, x2 +ADD x4, x1, x3 +ADD x3, x4, x2 +ADD x1, x2, x1 +ADD x2, x1, x5 +ADD x5, x0, x3 +ADD x4, x5, x4 +ADD x1, x5, x4 +ADD x2, x0, x3 +ADD x4, x4, x5 +ADD x4, x4, x4 +ADD x1, x1, x1 +ADD x5, x4, x1 +ADD x1, x5, x5 +ADD x1, x0, x1 +ADD x4, x0, x5 +ADD x5, x4, x5 +ADD x2, x2, x3 +ADD x2, x4, x2 +ADD x4, x1, x3 +ADD x3, x1, x5 +ADD x4, x0, x2 +ADD x1, x1, x5 +ADD x2, x4, x4 +ADD x3, x0, x5 +ADD x2, x0, x2 +ADD x2, x3, x2 +ADD x5, x4, x1 +ADD x4, x1, x2 +ADD x2, x5, x4 +ADD x1, x5, x2 +ADD x3, x3, x3 +ADD x5, x1, x3 +ADD x4, x0, x2 +ADD x5, x4, x1 +ADD x2, x5, x4 +ADD x2, x2, x5 +ADD x3, x5, x1 +ADD x5, x2, x4 +ADD x4, x2, x4 +ADD x5, x5, x5 +ADD x3, x5, x1 +ADD x4, x4, x5 +ADD x4, x3, x2 +ADD x4, x0, x5 +ADD x2, x4, x4 +ADD x2, x1, x2 +ADD x4, x4, x4 +ADD x5, x4, x2 +ADD x1, x1, x4 +ADD x2, x0, x5 +ADD x5, x4, x5 +ADD x3, x4, x4 +ADD x1, x5, x5 +ADD x1, x2, x2 +ADD x5, x3, x2 +ADD x2, x0, x2 +ADD x5, x3, x1 +ADD x4, x5, x3 +ADD x1, x5, x3 +ADD x5, x3, x3 +ADD x4, x1, x2 +ADD x3, x0, x4 +ADD x2, x4, x3 +ADD x3, x4, x3 +ADD x2, x2, x2 +ADD x4, x4, x4 +ADD x4, x0, x2 +ADD x5, x2, x2 +ADD x3, x4, x4 +ADD x5, x4, x2 +ADD x1, x2, x2 +ADD x5, x1, x4 +ADD x3, x1, x1 +ADD x3, x4, x1 +ADD x2, x0, x4 +ADD x1, x0, x5 +ADD x3, x2, x5 +ADD x1, x1, x2 +ADD x1, x3, x2 +ADD x2, x1, x5 +ADD x2, x4, x5 +ADD x1, x0, x3 +ADD x5, x4, x4 +ADD x1, x4, x4 +ADD x1, x1, x4 +ADD x4, x2, x3 +ADD x2, x0, x3 +ADD x2, x0, x5 +ADD x4, x4, x2 +ADD x4, x0, x3 +ADD x5, x5, x3 +ADD x1, x1, x3 +ADD x2, x5, x3 +ADD x3, x2, x1 +ADD x4, x3, x1 +ADD x5, x0, x3 +ADD x5, x3, x5 +ADD x3, x1, x1 +ADD x2, x3, x3 +ADD x5, x3, x3 +ADD x4, x1, x5 +ADD x2, x1, x1 +ADD x1, x2, x1 +ADD x5, x2, x3 +ADD x2, x2, x4 +ADD x4, x1, x3 +ADD x4, x1, x3 +ADD x5, x3, x3 +ADD x4, x0, x5 +ADD x5, x0, x1 +ADD x2, x5, x4 +ADD x4, x5, x1 +ADD x5, x5, x3 +ADD x5, x2, x3 +ADD x1, x4, x3 +ADD x3, x0, x1 +ADD x2, x3, x2 +ADD x4, x5, x5 +ADD x4, x4, x2 +ADD x1, x0, x1 +ADD x3, x2, x2 +ADD x1, x4, x3 +ADD x3, x4, x5 +ADD x2, x1, x1 +ADD x4, x1, x2 +ADD x4, x5, x2 +ADD x1, x4, x4 +ADD x1, x0, x3 +ADD x4, x1, x3 +ADD x5, x3, x5 +ADD x1, x1, x4 +ADD x3, x4, x2 +ADD x4, x4, x3 +ADD x3, x5, x3 +ADD x2, x1, x2 +ADD x3, x2, x1 +ADD x2, x4, x3 +ADD x5, x0, x4 +ADD x5, x1, x4 +ADD x1, x4, x2 +ADD x4, x3, x4 +ADD x5, x0, x2 +ADD x2, x0, x4 +ADD x5, x5, x5 +ADD x2, x4, x3 +ADD x5, x3, x1 +ADD x1, x5, x3 +ADD x4, x4, x3 +ADD x3, x5, x5 +ADD x3, x0, x1 +ADD x4, x5, x4 +ADD x4, x2, x4 +ADD x3, x5, x4 +ADD x4, x1, x4 +ADD x5, x5, x5 +ADD x3, x3, x5 +ADD x2, x3, x5 +ADD x4, x0, x4 +ADD x2, x2, x1 +ADD x1, x1, x4 +ADD x4, x1, x2 +ADD x5, x0, x2 +ADD x1, x1, x2 +ADD x2, x5, x4 +ADD x3, x3, x4 +ADD x2, x1, x4 +ADD x4, x5, x1 +ADD x3, x5, x3 +ADD x3, x0, x5 +ADD x1, x3, x1 +ADD x3, x1, x4 +ADD x4, x3, x1 +ADD x3, x0, x1 +ADD x1, x2, x3 +ADD x1, x0, x5 +ADD x4, x4, x2 +ADD x1, x4, x2 +ADD x1, x0, x1 +ADD x4, x1, x1 +ADD x4, x0, x1 +ADD x5, x4, x2 +ADD x4, x1, x3 +ADD x1, x0, x5 +ADD x3, x0, x4 +ADD x5, x4, x5 +ADD x5, x2, x2 +ADD x4, x1, x5 +ADD x3, x5, x3 +ADD x1, x0, x1 +ADD x2, x2, x2 +ADD x4, x0, x4 +ADD x2, x2, x3 +ADD x3, x1, x3 +ADD x5, x5, x1 +ADD x3, x1, x3 +ADD x5, x5, x1 +ADD x1, x2, x4 +ADD x3, x3, x5 +ADD x2, x5, x3 +ADD x5, x0, x4 +ADD x1, x1, x3 +ADD x3, x5, x1 +ADD x2, x0, x3 +ADD x5, x2, x3 +ADD x2, x1, x4 +ADD x1, x3, x3 +ADD x5, x0, x1 +ADD x4, x2, x2 +ADD x2, x4, x5 +ADD x2, x5, x5 +ADD x5, x4, x4 +ADD x1, x2, x3 +ADD x2, x3, x3 +ADD x5, x1, x4 +ADD x5, x5, x2 +ADD x2, x3, x4 +ADD x4, x5, x4 +ADD x3, x5, x2 +ADD x5, x5, x2 +ADD x1, x2, x2 +ADD x4, x2, x2 +ADD x3, x4, x4 +ADD x1, x3, x4 +ADD x3, x4, x3 +ADD x4, x5, x3 +ADD x5, x3, x5 +ADD x4, x3, x3 +ADD x5, x0, x4 +ADD x1, x2, x1 +ADD x5, x5, x4 +ADD x5, x4, x4 +ADD x5, x4, x4 +ADD x5, x4, x1 +ADD x4, x1, x3 +ADD x2, x1, x1 +ADD x4, x5, x2 +ADD x4, x3, x2 +ADD x5, x3, x3 +ADD x5, x0, x3 +ADD x5, x3, x5 +ADD x5, x2, x2 +ADD x3, x1, x1 +ADD x4, x0, x1 +ADD x5, x0, x5 +ADD x5, x1, x4 +ADD x1, x4, x3 +ADD x4, x2, x2 +ADD x1, x0, x3 +ADD x3, x4, x1 +ADD x2, x4, x3 +ADD x4, x5, x4 +ADD x1, x5, x2 +ADD x4, x2, x4 +ADD x4, x3, x2 +ADD x3, x3, x2 +ADD x3, x1, x4 +ADD x3, x2, x4 +ADD x2, x1, x4 +ADD x2, x1, x4 +ADD x5, x4, x5 +ADD x2, x5, x3 +ADD x2, x5, x3 +ADD x1, x2, x1 +ADD x3, x2, x3 +ADD x3, x0, x2 +ADD x2, x1, x5 +ADD x5, x1, x1 +ADD x1, x5, x1 +ADD x4, x5, x1 +ADD x2, x3, x2 +ADD x1, x0, x2 +ADD x3, x4, x1 +ADD x1, x4, x5 +ADD x4, x5, x3 +ADD x3, x4, x4 +ADD x4, x5, x2 +ADD x1, x1, x2 +ADD x3, x5, x5 +ADD x3, x5, x1 +ADD x1, x2, x4 +ADD x4, x2, x2 +ADD x2, x1, x1 +ADD x3, x3, x1 +ADD x2, x0, x3 +ADD x5, x1, x5 +ADD x3, x5, x4 +ADD x3, x4, x3 +ADD x2, x4, x5 +ADD x5, x1, x5 +ADD x2, x2, x4 +ADD x5, x0, x4 +ADD x5, x3, x3 +ADD x4, x1, x3 +ADD x4, x4, x1 +ADD x5, x0, x1 +ADD x1, x1, x1 +ADD x1, x2, x2 +ADD x3, x1, x2 +ADD x5, x5, x5 +ADD x4, x3, x2 +ADD x5, x4, x2 +ADD x4, x3, x1 +ADD x5, x1, x1 +ADD x3, x2, x3 +ADD x4, x2, x5 +ADD x5, x2, x3 +ADD x3, x3, x5 +ADD x4, x5, x3 +ADD x2, x5, x1 +ADD x4, x2, x4 +ADD x2, x1, x4 +ADD x1, x4, x2 +ADD x2, x4, x5 +ADD x1, x5, x4 +ADD x2, x1, x4 +ADD x1, x0, x5 +ADD x5, x5, x1 +ADD x2, x1, x5 +ADD x1, x2, x1 +ADD x3, x3, x2 +ADD x5, x4, x2 +ADD x1, x4, x3 +sw x1, 0(x8) +sw x2, 4(x8) +sw x3, 8(x8) +sw x4, 12(x8) +sw x5, 16(x8) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S new file mode 100644 index 000000000..8ecc6a5a8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S @@ -0,0 +1,1082 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 13:22:54.989066// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE( x8,signature_x8_1) +ADD x2, x3, x1 +ADD x3, x1, x3 +ADD x3, x1, x4 +ADD x1, x0, x4 +ADD x4, x1, x3 +ADD x5, x2, x4 +ADD x4, x2, x1 +ADD x4, x2, x2 +ADD x2, x2, x3 +ADD x4, x4, x3 +ADD x2, x4, x2 +ADD x1, x5, x4 +ADD x3, x2, x4 +ADD x4, x3, x1 +ADD x3, x1, x3 +ADD x4, x4, x2 +ADD x3, x0, x5 +ADD x3, x3, x1 +ADD x1, x4, x2 +ADD x5, x4, x4 +ADD x2, x3, x3 +ADD x1, x4, x2 +ADD x2, x1, x1 +ADD x1, x5, x2 +ADD x3, x2, x3 +ADD x1, x3, x5 +ADD x2, x3, x4 +ADD x5, x0, x5 +ADD x2, x5, x3 +ADD x2, x2, x2 +ADD x3, x1, x1 +ADD x3, x1, x3 +ADD x1, x3, x1 +ADD x1, x3, x4 +ADD x2, x5, x5 +ADD x4, x1, x3 +ADD x5, x1, x2 +ADD x2, x3, x3 +ADD x1, x3, x1 +ADD x2, x4, x2 +ADD x5, x5, x2 +ADD x1, x4, x5 +ADD x1, x2, x5 +ADD x5, x5, x3 +ADD x1, x4, x3 +ADD x3, x2, x1 +ADD x3, x2, x1 +ADD x1, x2, x1 +ADD x2, x0, x4 +ADD x3, x4, x4 +ADD x4, x1, x5 +ADD x1, x5, x1 +ADD x4, x1, x4 +ADD x5, x5, x2 +ADD x4, x0, x1 +ADD x4, x2, x2 +ADD x4, x5, x3 +ADD x5, x4, x3 +ADD x4, x5, x1 +ADD x2, x4, x1 +ADD x5, x3, x2 +ADD x2, x1, x1 +ADD x3, x2, x3 +ADD x5, x1, x2 +ADD x4, x2, x1 +ADD x2, x4, x4 +ADD x4, x1, x4 +ADD x5, x4, x4 +ADD x5, x0, x5 +ADD x4, x1, x5 +ADD x1, x1, x5 +ADD x3, x1, x2 +ADD x2, x2, x1 +ADD x3, x4, x4 +ADD x1, x2, x2 +ADD x5, x5, x4 +ADD x2, x3, x1 +ADD x1, x1, x3 +ADD x3, x3, x3 +ADD x3, x2, x1 +ADD x2, x1, x3 +ADD x4, x1, x2 +ADD x2, x4, x3 +ADD x5, x3, x1 +ADD x1, x4, x4 +ADD x5, x5, x2 +ADD x1, x5, x1 +ADD x3, x5, x5 +ADD x3, x1, x1 +ADD x3, x1, x4 +ADD x2, x4, x5 +ADD x3, x3, x2 +ADD x1, x2, x3 +ADD x5, x3, x3 +ADD x4, x0, x4 +ADD x3, x2, x5 +ADD x1, x1, x3 +ADD x4, x5, x1 +ADD x4, x0, x1 +ADD x4, x2, x1 +ADD x5, x4, x1 +ADD x5, x3, x4 +ADD x2, x1, x2 +ADD x5, x0, x5 +ADD x4, x2, x3 +ADD x5, x3, x2 +ADD x1, x2, x2 +ADD x5, x1, x1 +ADD x1, x4, x2 +ADD x5, x5, x4 +ADD x5, x2, x3 +ADD x4, x1, x1 +ADD x2, x4, x3 +ADD x4, x2, x1 +ADD x4, x0, x1 +ADD x4, x2, x3 +ADD x2, x2, x3 +ADD x3, x5, x3 +ADD x4, x1, x1 +ADD x1, x3, x5 +ADD x4, x2, x1 +ADD x1, x0, x2 +ADD x2, x1, x3 +ADD x3, x1, x4 +ADD x4, x0, x1 +ADD x2, x5, x4 +ADD x1, x5, x4 +ADD x5, x0, x2 +ADD x1, x0, x3 +ADD x3, x1, x4 +ADD x5, x4, x3 +ADD x5, x5, x4 +ADD x2, x1, x2 +ADD x1, x0, x2 +ADD x1, x4, x5 +ADD x4, x3, x4 +ADD x5, x5, x5 +ADD x2, x5, x5 +ADD x5, x4, x3 +ADD x5, x5, x4 +ADD x5, x3, x5 +ADD x5, x3, x3 +ADD x3, x5, x1 +ADD x3, x5, x5 +ADD x5, x3, x1 +ADD x4, x2, x1 +ADD x1, x5, x1 +ADD x5, x4, x1 +ADD x1, x4, x1 +ADD x1, x2, x4 +ADD x3, x3, x2 +ADD x4, x2, x2 +ADD x3, x3, x3 +ADD x5, x4, x5 +ADD x1, x0, x3 +ADD x3, x3, x4 +ADD x2, x2, x5 +ADD x4, x4, x4 +ADD x1, x3, x1 +ADD x3, x4, x1 +ADD x1, x2, x3 +ADD x2, x5, x3 +ADD x5, x3, x1 +ADD x5, x2, x3 +ADD x1, x0, x3 +ADD x3, x4, x2 +ADD x4, x5, x3 +ADD x2, x3, x2 +ADD x1, x1, x1 +ADD x5, x3, x4 +ADD x1, x2, x1 +ADD x2, x2, x2 +ADD x5, x0, x4 +ADD x2, x2, x1 +ADD x4, x0, x3 +ADD x4, x0, x3 +ADD x2, x2, x3 +ADD x2, x5, x5 +ADD x4, x4, x1 +ADD x2, x0, x5 +ADD x1, x4, x2 +ADD x5, x1, x2 +ADD x4, x4, x4 +ADD x2, x3, x3 +ADD x3, x2, x3 +ADD x1, x1, x4 +ADD x2, x5, x1 +ADD x1, x4, x2 +ADD x5, x4, x2 +ADD x2, x0, x2 +ADD x1, x3, x4 +ADD x5, x2, x3 +ADD x1, x1, x5 +ADD x1, x2, x3 +ADD x4, x2, x1 +ADD x3, x2, x5 +ADD x2, x1, x5 +ADD x3, x4, x1 +ADD x3, x4, x2 +ADD x4, x3, x3 +ADD x3, x3, x4 +ADD x3, x2, x2 +ADD x1, x2, x4 +ADD x3, x2, x3 +ADD x2, x3, x2 +ADD x5, x4, x4 +ADD x2, x5, x5 +ADD x1, x2, x2 +ADD x1, x3, x5 +ADD x5, x3, x3 +ADD x5, x3, x1 +ADD x4, x3, x5 +ADD x4, x4, x4 +ADD x2, x0, x3 +ADD x5, x2, x1 +ADD x4, x1, x5 +ADD x3, x5, x2 +ADD x4, x3, x3 +ADD x3, x4, x2 +ADD x3, x3, x2 +ADD x3, x2, x1 +ADD x1, x5, x2 +ADD x2, x4, x4 +ADD x5, x5, x5 +ADD x5, x1, x4 +ADD x5, x2, x4 +ADD x4, x0, x5 +ADD x2, x2, x3 +ADD x4, x3, x3 +ADD x2, x3, x2 +ADD x4, x3, x1 +ADD x4, x4, x3 +ADD x2, x2, x3 +ADD x2, x1, x3 +ADD x5, x2, x2 +ADD x2, x0, x1 +ADD x3, x4, x3 +ADD x5, x0, x3 +ADD x3, x0, x4 +ADD x5, x5, x5 +ADD x5, x0, x5 +ADD x4, x0, x3 +ADD x2, x2, x5 +ADD x1, x3, x4 +ADD x2, x4, x3 +ADD x4, x0, x2 +ADD x3, x0, x3 +ADD x1, x4, x1 +ADD x5, x1, x3 +ADD x1, x1, x1 +ADD x2, x5, x3 +ADD x4, x4, x1 +ADD x1, x2, x1 +ADD x2, x2, x2 +ADD x2, x3, x4 +ADD x3, x0, x5 +ADD x5, x5, x2 +ADD x3, x4, x3 +ADD x4, x4, x2 +ADD x5, x4, x1 +ADD x1, x2, x4 +ADD x3, x0, x3 +ADD x1, x4, x3 +ADD x1, x2, x5 +ADD x2, x3, x4 +ADD x2, x1, x2 +ADD x1, x0, x5 +ADD x5, x3, x5 +ADD x2, x3, x2 +ADD x3, x2, x2 +ADD x2, x3, x4 +ADD x2, x2, x4 +ADD x5, x5, x2 +ADD x3, x4, x4 +ADD x2, x2, x4 +ADD x5, x5, x5 +ADD x5, x0, x2 +ADD x3, x5, x5 +ADD x2, x2, x4 +ADD x5, x1, x3 +ADD x1, x0, x3 +ADD x5, x5, x1 +ADD x1, x5, x1 +ADD x4, x4, x3 +ADD x5, x5, x1 +ADD x3, x0, x4 +ADD x1, x2, x1 +ADD x5, x5, x1 +ADD x1, x5, x5 +ADD x5, x1, x5 +ADD x1, x2, x1 +ADD x5, x0, x2 +ADD x5, x1, x4 +ADD x1, x3, x2 +ADD x2, x0, x2 +ADD x1, x5, x4 +ADD x2, x1, x1 +ADD x4, x5, x4 +ADD x5, x4, x2 +ADD x2, x4, x4 +ADD x2, x5, x5 +ADD x5, x2, x4 +ADD x5, x5, x4 +ADD x2, x2, x5 +ADD x5, x2, x5 +ADD x2, x2, x3 +ADD x4, x2, x3 +ADD x2, x5, x3 +ADD x2, x2, x3 +ADD x5, x1, x4 +ADD x4, x2, x2 +ADD x5, x1, x3 +ADD x5, x3, x1 +ADD x2, x3, x1 +ADD x3, x4, x3 +ADD x2, x3, x4 +ADD x1, x4, x2 +ADD x4, x3, x3 +ADD x4, x0, x3 +ADD x2, x0, x1 +ADD x4, x1, x3 +ADD x4, x4, x3 +ADD x3, x5, x1 +ADD x2, x4, x2 +ADD x4, x0, x1 +ADD x1, x2, x5 +ADD x2, x3, x5 +ADD x5, x1, x1 +ADD x3, x2, x1 +ADD x5, x5, x4 +ADD x1, x2, x4 +ADD x2, x3, x4 +ADD x5, x5, x1 +ADD x5, x4, x2 +ADD x2, x2, x3 +ADD x1, x2, x3 +ADD x1, x0, x4 +ADD x4, x2, x3 +ADD x2, x0, x5 +ADD x3, x3, x2 +ADD x1, x0, x2 +ADD x5, x2, x4 +ADD x3, x2, x5 +ADD x4, x1, x1 +ADD x2, x5, x1 +ADD x2, x2, x4 +ADD x3, x5, x3 +ADD x5, x4, x1 +ADD x1, x5, x4 +ADD x1, x3, x1 +ADD x4, x5, x2 +ADD x1, x3, x5 +ADD x3, x3, x3 +ADD x4, x0, x5 +ADD x5, x4, x2 +ADD x5, x1, x4 +ADD x5, x1, x5 +ADD x3, x5, x2 +ADD x5, x2, x1 +ADD x4, x5, x3 +ADD x5, x0, x2 +ADD x3, x1, x4 +ADD x4, x0, x4 +ADD x1, x5, x2 +ADD x3, x3, x2 +ADD x5, x4, x3 +ADD x3, x5, x1 +ADD x4, x5, x1 +ADD x2, x2, x3 +ADD x5, x4, x5 +ADD x2, x3, x2 +ADD x4, x1, x2 +ADD x2, x0, x1 +ADD x1, x3, x4 +ADD x3, x4, x3 +ADD x3, x4, x2 +ADD x5, x3, x1 +ADD x3, x0, x4 +ADD x1, x4, x5 +ADD x2, x2, x4 +ADD x1, x2, x1 +ADD x4, x5, x5 +ADD x4, x3, x2 +ADD x2, x4, x4 +ADD x4, x0, x5 +ADD x2, x3, x3 +ADD x3, x4, x5 +ADD x4, x4, x2 +ADD x3, x0, x2 +ADD x4, x4, x3 +ADD x1, x5, x4 +ADD x5, x2, x4 +ADD x1, x3, x5 +ADD x4, x1, x4 +ADD x4, x3, x2 +ADD x5, x0, x3 +ADD x5, x4, x2 +ADD x2, x5, x1 +ADD x5, x4, x5 +ADD x3, x4, x4 +ADD x3, x0, x4 +ADD x1, x3, x1 +ADD x1, x1, x4 +ADD x5, x3, x4 +ADD x1, x0, x3 +ADD x1, x3, x5 +ADD x2, x0, x3 +ADD x2, x1, x2 +ADD x1, x4, x1 +ADD x2, x3, x3 +ADD x1, x0, x5 +ADD x4, x5, x2 +ADD x3, x0, x4 +ADD x1, x4, x2 +ADD x5, x5, x3 +ADD x5, x4, x5 +ADD x3, x4, x5 +ADD x3, x1, x2 +ADD x4, x0, x3 +ADD x5, x4, x3 +ADD x4, x0, x3 +ADD x4, x1, x1 +ADD x5, x4, x3 +ADD x1, x1, x1 +ADD x3, x0, x2 +ADD x3, x5, x1 +ADD x1, x3, x1 +ADD x3, x1, x3 +ADD x1, x1, x5 +ADD x3, x2, x3 +ADD x3, x0, x4 +ADD x2, x2, x1 +ADD x2, x2, x2 +ADD x5, x3, x3 +ADD x5, x1, x2 +ADD x3, x4, x1 +ADD x2, x0, x3 +ADD x2, x4, x5 +ADD x4, x4, x1 +ADD x3, x2, x5 +ADD x5, x5, x5 +ADD x3, x3, x1 +ADD x2, x3, x3 +ADD x4, x2, x4 +ADD x2, x5, x2 +ADD x2, x3, x2 +ADD x4, x0, x3 +ADD x5, x0, x5 +ADD x2, x2, x2 +ADD x3, x3, x4 +ADD x4, x2, x3 +ADD x4, x3, x2 +ADD x3, x3, x5 +ADD x2, x0, x1 +ADD x1, x2, x2 +ADD x1, x2, x5 +ADD x5, x5, x4 +ADD x4, x0, x4 +ADD x2, x1, x1 +ADD x2, x5, x5 +ADD x3, x2, x1 +ADD x3, x5, x1 +ADD x4, x2, x2 +ADD x5, x5, x4 +ADD x4, x5, x4 +ADD x1, x0, x3 +ADD x1, x3, x4 +ADD x1, x4, x1 +ADD x2, x0, x4 +ADD x3, x4, x5 +ADD x1, x0, x5 +ADD x2, x1, x5 +ADD x2, x1, x4 +ADD x5, x4, x1 +ADD x3, x3, x4 +ADD x5, x2, x5 +ADD x1, x1, x5 +ADD x3, x3, x4 +ADD x1, x1, x1 +ADD x2, x3, x4 +ADD x5, x4, x2 +ADD x3, x1, x2 +ADD x1, x3, x5 +ADD x1, x3, x2 +ADD x4, x3, x2 +ADD x4, x0, x3 +ADD x3, x2, x4 +ADD x1, x5, x3 +ADD x2, x3, x3 +ADD x4, x2, x1 +ADD x4, x1, x5 +ADD x3, x5, x4 +ADD x3, x0, x2 +ADD x1, x1, x3 +ADD x5, x1, x2 +ADD x3, x5, x3 +ADD x4, x1, x5 +ADD x5, x1, x4 +ADD x4, x0, x3 +ADD x5, x1, x5 +ADD x3, x5, x3 +ADD x4, x1, x3 +ADD x4, x2, x4 +ADD x4, x1, x5 +ADD x4, x2, x4 +ADD x4, x0, x3 +ADD x3, x5, x1 +ADD x1, x2, x4 +ADD x3, x5, x5 +ADD x3, x4, x4 +ADD x4, x0, x3 +ADD x4, x4, x1 +ADD x3, x5, x1 +ADD x5, x4, x4 +ADD x3, x1, x1 +ADD x2, x4, x5 +ADD x1, x4, x4 +ADD x3, x2, x3 +ADD x5, x3, x2 +ADD x5, x4, x5 +ADD x3, x2, x4 +ADD x2, x2, x2 +ADD x2, x3, x2 +ADD x5, x2, x2 +ADD x4, x1, x1 +ADD x5, x1, x5 +ADD x4, x3, x2 +ADD x1, x4, x1 +ADD x1, x1, x1 +ADD x3, x0, x4 +ADD x3, x3, x4 +ADD x3, x5, x5 +ADD x4, x5, x3 +ADD x2, x0, x5 +ADD x4, x4, x5 +ADD x2, x2, x5 +ADD x1, x0, x2 +ADD x5, x0, x2 +ADD x5, x5, x4 +ADD x5, x5, x1 +ADD x5, x0, x2 +ADD x4, x0, x4 +ADD x3, x0, x1 +ADD x2, x4, x3 +ADD x5, x3, x2 +ADD x4, x4, x5 +ADD x3, x0, x1 +ADD x5, x3, x2 +ADD x4, x0, x1 +ADD x5, x3, x3 +ADD x1, x1, x5 +ADD x4, x4, x2 +ADD x3, x0, x5 +ADD x2, x3, x3 +ADD x5, x3, x4 +ADD x5, x4, x5 +ADD x3, x2, x1 +ADD x3, x0, x5 +ADD x1, x4, x3 +ADD x3, x2, x2 +ADD x3, x1, x4 +ADD x5, x2, x3 +ADD x4, x1, x4 +ADD x4, x3, x4 +ADD x1, x1, x4 +ADD x1, x0, x4 +ADD x5, x0, x2 +ADD x1, x5, x1 +ADD x1, x1, x5 +ADD x1, x3, x2 +ADD x2, x2, x5 +ADD x1, x0, x1 +ADD x1, x4, x1 +ADD x1, x4, x1 +ADD x5, x2, x4 +ADD x5, x2, x3 +ADD x2, x2, x3 +ADD x2, x1, x3 +ADD x4, x1, x5 +ADD x5, x3, x1 +ADD x3, x4, x1 +ADD x1, x0, x4 +ADD x1, x1, x3 +ADD x4, x0, x5 +ADD x2, x3, x4 +ADD x3, x5, x1 +ADD x5, x3, x3 +ADD x1, x5, x1 +ADD x4, x3, x2 +ADD x1, x2, x2 +ADD x3, x2, x5 +ADD x2, x3, x3 +ADD x1, x1, x3 +ADD x2, x0, x1 +ADD x5, x4, x1 +ADD x2, x2, x2 +ADD x2, x3, x4 +ADD x2, x4, x5 +ADD x2, x2, x5 +ADD x4, x5, x3 +ADD x1, x1, x2 +ADD x3, x5, x2 +ADD x2, x0, x1 +ADD x1, x2, x2 +ADD x5, x1, x5 +ADD x4, x1, x2 +ADD x4, x3, x5 +ADD x5, x2, x4 +ADD x5, x0, x4 +ADD x4, x4, x2 +ADD x5, x5, x5 +ADD x3, x5, x2 +ADD x1, x4, x4 +ADD x1, x4, x4 +ADD x2, x1, x3 +ADD x1, x2, x4 +ADD x5, x2, x5 +ADD x4, x1, x1 +ADD x4, x5, x2 +ADD x3, x4, x3 +ADD x3, x5, x5 +ADD x1, x5, x1 +ADD x2, x3, x1 +ADD x3, x0, x3 +ADD x2, x0, x1 +ADD x3, x5, x3 +ADD x5, x0, x5 +ADD x3, x5, x4 +ADD x3, x1, x3 +ADD x2, x1, x4 +ADD x3, x0, x1 +ADD x5, x2, x2 +ADD x3, x5, x4 +ADD x5, x0, x1 +ADD x5, x5, x4 +ADD x3, x1, x5 +ADD x5, x5, x4 +ADD x2, x4, x4 +ADD x3, x2, x1 +ADD x2, x4, x3 +ADD x3, x2, x5 +ADD x1, x3, x4 +ADD x2, x3, x2 +ADD x5, x2, x3 +ADD x5, x5, x4 +ADD x4, x1, x5 +ADD x5, x0, x2 +ADD x1, x2, x5 +ADD x2, x0, x1 +ADD x5, x5, x3 +ADD x3, x0, x4 +ADD x3, x3, x1 +ADD x4, x2, x5 +ADD x2, x5, x5 +ADD x2, x3, x5 +ADD x1, x4, x2 +ADD x3, x0, x4 +ADD x5, x2, x2 +ADD x4, x3, x2 +ADD x3, x1, x1 +ADD x1, x5, x4 +ADD x2, x2, x5 +ADD x5, x0, x2 +ADD x1, x2, x2 +ADD x4, x0, x5 +ADD x5, x1, x3 +ADD x2, x0, x2 +ADD x3, x4, x2 +ADD x2, x1, x3 +ADD x3, x5, x4 +ADD x1, x3, x3 +ADD x2, x0, x5 +ADD x5, x4, x1 +ADD x3, x4, x5 +ADD x4, x1, x5 +ADD x5, x5, x4 +ADD x3, x4, x2 +ADD x2, x1, x2 +ADD x4, x2, x5 +ADD x2, x3, x3 +ADD x4, x1, x2 +ADD x2, x1, x5 +ADD x2, x3, x3 +ADD x4, x5, x3 +ADD x4, x5, x4 +ADD x5, x3, x2 +ADD x5, x2, x5 +ADD x5, x5, x4 +ADD x5, x3, x5 +ADD x5, x0, x1 +ADD x1, x1, x1 +ADD x3, x2, x1 +ADD x4, x0, x4 +ADD x2, x1, x2 +ADD x4, x3, x3 +ADD x3, x4, x1 +ADD x2, x4, x1 +ADD x5, x4, x2 +ADD x5, x5, x4 +ADD x4, x0, x3 +ADD x2, x0, x2 +ADD x2, x2, x2 +ADD x5, x2, x3 +ADD x1, x1, x5 +ADD x3, x4, x4 +ADD x4, x3, x4 +ADD x4, x3, x5 +ADD x5, x1, x1 +ADD x3, x3, x5 +ADD x2, x0, x1 +ADD x2, x3, x5 +ADD x5, x3, x2 +ADD x2, x1, x1 +ADD x1, x1, x5 +ADD x3, x2, x4 +ADD x3, x4, x3 +ADD x1, x2, x4 +ADD x5, x4, x3 +ADD x1, x3, x1 +ADD x5, x1, x5 +ADD x1, x1, x1 +ADD x4, x5, x3 +ADD x4, x2, x3 +ADD x3, x1, x3 +ADD x1, x2, x1 +ADD x5, x0, x3 +ADD x3, x5, x1 +ADD x5, x4, x2 +ADD x2, x4, x2 +ADD x4, x4, x4 +ADD x4, x0, x3 +ADD x3, x5, x3 +ADD x1, x2, x2 +ADD x1, x1, x3 +ADD x2, x1, x5 +ADD x1, x2, x5 +ADD x5, x5, x4 +ADD x4, x5, x5 +ADD x2, x4, x5 +ADD x5, x5, x4 +ADD x1, x4, x2 +ADD x4, x2, x5 +ADD x5, x1, x2 +ADD x2, x4, x5 +ADD x2, x5, x1 +ADD x2, x4, x1 +ADD x2, x0, x1 +ADD x3, x1, x2 +ADD x1, x4, x4 +ADD x3, x4, x1 +ADD x3, x0, x5 +ADD x3, x0, x1 +ADD x2, x5, x1 +ADD x3, x2, x3 +ADD x2, x3, x4 +ADD x4, x0, x1 +ADD x5, x3, x5 +ADD x2, x4, x5 +ADD x1, x5, x1 +ADD x3, x1, x2 +ADD x5, x0, x5 +ADD x3, x1, x3 +ADD x1, x0, x4 +ADD x4, x4, x3 +ADD x1, x3, x3 +ADD x1, x3, x2 +ADD x2, x1, x3 +ADD x2, x5, x5 +ADD x4, x4, x3 +ADD x5, x3, x4 +ADD x1, x1, x2 +ADD x3, x2, x2 +ADD x4, x0, x5 +ADD x2, x4, x3 +ADD x2, x2, x1 +ADD x2, x2, x1 +ADD x1, x4, x1 +ADD x4, x0, x2 +ADD x1, x0, x4 +ADD x5, x4, x5 +ADD x1, x1, x2 +ADD x5, x2, x3 +ADD x4, x4, x5 +ADD x1, x0, x2 +ADD x1, x3, x2 +ADD x1, x2, x2 +ADD x4, x2, x4 +ADD x5, x2, x5 +ADD x4, x3, x3 +ADD x4, x4, x5 +ADD x2, x3, x4 +ADD x5, x5, x3 +ADD x5, x5, x1 +ADD x3, x0, x4 +ADD x3, x5, x2 +ADD x4, x0, x1 +ADD x4, x2, x3 +ADD x2, x3, x5 +ADD x2, x0, x1 +ADD x3, x2, x5 +ADD x4, x3, x2 +ADD x4, x2, x5 +ADD x4, x4, x5 +ADD x1, x4, x5 +ADD x5, x2, x2 +ADD x5, x2, x2 +ADD x3, x2, x4 +ADD x4, x4, x1 +ADD x2, x4, x3 +ADD x3, x4, x5 +ADD x4, x3, x3 +ADD x4, x5, x5 +ADD x1, x2, x1 +ADD x4, x4, x5 +ADD x2, x3, x3 +ADD x3, x2, x3 +ADD x1, x2, x3 +ADD x3, x2, x3 +ADD x4, x3, x5 +ADD x2, x4, x1 +ADD x3, x3, x2 +ADD x1, x2, x1 +ADD x1, x2, x3 +ADD x3, x5, x1 +ADD x2, x3, x2 +ADD x3, x0, x1 +ADD x4, x3, x3 +ADD x2, x4, x5 +ADD x4, x0, x2 +ADD x5, x0, x5 +ADD x4, x4, x2 +ADD x3, x1, x3 +ADD x3, x2, x2 +ADD x4, x0, x3 +ADD x1, x2, x4 +ADD x2, x4, x2 +ADD x3, x1, x5 +ADD x1, x0, x2 +ADD x5, x3, x3 +ADD x2, x5, x3 +ADD x2, x4, x3 +ADD x1, x3, x4 +ADD x1, x5, x4 +ADD x2, x3, x4 +ADD x4, x1, x5 +ADD x4, x0, x3 +ADD x4, x3, x4 +ADD x1, x4, x3 +ADD x2, x0, x1 +ADD x5, x3, x1 +ADD x5, x5, x1 +ADD x5, x1, x4 +ADD x2, x1, x3 +ADD x2, x3, x4 +ADD x4, x2, x2 +ADD x3, x5, x2 +ADD x3, x5, x1 +ADD x5, x2, x2 +ADD x5, x3, x4 +ADD x5, x2, x4 +ADD x5, x2, x3 +ADD x1, x2, x3 +ADD x3, x5, x2 +ADD x1, x0, x2 +ADD x4, x0, x3 +ADD x1, x2, x1 +ADD x3, x2, x4 +ADD x3, x3, x3 +ADD x5, x3, x4 +ADD x4, x4, x4 +ADD x4, x5, x2 +ADD x5, x1, x1 +ADD x3, x1, x3 +ADD x1, x0, x3 +ADD x5, x1, x1 +ADD x3, x4, x1 +ADD x2, x3, x1 +ADD x2, x5, x2 +ADD x1, x1, x1 +ADD x1, x1, x1 +ADD x2, x0, x3 +ADD x2, x5, x4 +ADD x5, x5, x5 +ADD x2, x3, x4 +ADD x5, x4, x5 +ADD x2, x4, x4 +ADD x5, x4, x5 +ADD x2, x1, x5 +ADD x5, x4, x2 +ADD x4, x2, x5 +ADD x4, x2, x2 +ADD x5, x4, x4 +ADD x1, x5, x4 +ADD x4, x5, x5 +ADD x3, x2, x3 +ADD x3, x5, x5 +ADD x3, x0, x1 +ADD x1, x2, x2 +ADD x1, x4, x2 +ADD x1, x3, x3 +ADD x2, x0, x2 +ADD x5, x3, x2 +ADD x2, x0, x2 +ADD x5, x4, x1 +ADD x2, x4, x4 +ADD x2, x4, x3 +ADD x4, x0, x3 +ADD x4, x3, x2 +ADD x4, x4, x2 +ADD x5, x4, x1 +ADD x3, x4, x5 +ADD x5, x1, x1 +ADD x4, x1, x2 +ADD x4, x1, x1 +ADD x2, x5, x2 +ADD x3, x4, x4 +ADD x3, x1, x3 +ADD x2, x2, x2 +ADD x4, x3, x2 +ADD x1, x1, x2 +ADD x5, x5, x3 +ADD x4, x2, x2 +ADD x2, x5, x1 +ADD x4, x2, x4 +ADD x2, x4, x2 +ADD x2, x4, x5 +ADD x4, x4, x1 +ADD x5, x0, x2 +ADD x1, x1, x4 +ADD x1, x4, x5 +ADD x3, x3, x1 +ADD x2, x0, x4 +ADD x3, x5, x5 +ADD x1, x2, x1 +ADD x1, x4, x1 +ADD x1, x2, x2 +ADD x4, x1, x3 +ADD x2, x4, x2 +ADD x4, x0, x4 +ADD x1, x3, x2 +ADD x5, x1, x3 +ADD x5, x0, x4 +ADD x1, x3, x2 +ADD x4, x0, x1 +ADD x4, x0, x2 +ADD x5, x2, x1 +ADD x3, x4, x5 +ADD x3, x5, x3 +ADD x1, x2, x1 +ADD x4, x2, x1 +ADD x2, x1, x2 +ADD x4, x2, x4 +ADD x2, x1, x3 +ADD x2, x5, x2 +ADD x4, x2, x4 +ADD x2, x5, x1 +ADD x1, x2, x2 +ADD x5, x2, x2 +ADD x3, x3, x3 +ADD x3, x5, x4 +ADD x4, x3, x3 +ADD x5, x2, x2 +ADD x2, x5, x4 +ADD x3, x0, x3 +ADD x4, x4, x5 +ADD x1, x3, x2 +ADD x2, x4, x3 +ADD x3, x2, x5 +ADD x1, x5, x3 +ADD x5, x5, x3 +ADD x2, x5, x5 +ADD x5, x2, x1 +ADD x2, x2, x5 +ADD x4, x2, x2 +ADD x3, x4, x4 +ADD x4, x5, x4 +ADD x1, x1, x5 +ADD x4, x0, x3 +ADD x5, x4, x4 +ADD x2, x2, x2 +ADD x5, x2, x3 +ADD x1, x2, x5 +ADD x1, x2, x4 +ADD x3, x3, x2 +ADD x3, x0, x5 +ADD x5, x2, x1 +ADD x2, x4, x4 +ADD x3, x5, x4 +ADD x2, x3, x1 +ADD x1, x3, x1 +ADD x2, x0, x3 +ADD x2, x0, x1 +ADD x2, x1, x2 +ADD x2, x0, x5 +ADD x5, x5, x2 +ADD x2, x2, x1 +ADD x5, x1, x1 +ADD x3, x0, x5 +ADD x5, x1, x1 +ADD x5, x5, x5 +sd x1, 0(x8) +sd x2, 8(x8) +sd x3, 16(x8) +sd x4, 24(x8) +sd x5, 32(x8) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu From 0c7681b942b8f5816a4123d2302b3d93ce14cbe3 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 2 Nov 2021 21:19:12 -0700 Subject: [PATCH 19/19] fix testbench interrupt timing --- wally-pipelined/regression/linux-wave.do | 39 +-- wally-pipelined/testbench/testbench-linux.sv | 302 ++++++++++++------- 2 files changed, 210 insertions(+), 131 deletions(-) diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do index 30c2b0365..d2350d0ec 100644 --- a/wally-pipelined/regression/linux-wave.do +++ b/wally-pipelined/regression/linux-wave.do @@ -60,20 +60,26 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -group {WriteBack stage} /testbench/PCW -add wave -noupdate -group {WriteBack stage} /testbench/InstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW -add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -expand -group {Execution Stage} /testbench/textE +add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName +add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/textM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW +add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName +add wave -noupdate -expand -group {WriteBack stage} /testbench/textW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -484,7 +490,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/p add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/line add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW @@ -510,7 +515,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0} +WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {5672440 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -526,4 +531,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {182 ns} {330 ns} +WaveRestoreZoom {5672937 ns} {5673085 ns} diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 72adf589b..72061f9ea 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -103,30 +103,35 @@ module testbench(); string checkpointDir; logic [1:0] initPriv; // Signals used to parse the trace file - integer data_file_all; - string name; - integer matchCount; - string line; - logic [`XLEN-1:0] ExpectedPCM; - logic [31:0] ExpectedInstrM; - string textM; - string token; - string ExpectedTokens [31:0]; - integer index; - integer StartIndex, EndIndex; - integer TokenIndex; - integer MarkerIndex; - integer NumCSRM; + `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ + integer traceFile``STAGE; \ + integer matchCount``STAGE; \ + string line``STAGE; \ + string token``STAGE; \ + string ExpectedTokens``STAGE [31:0]; \ + integer index``STAGE; \ + integer StartIndex``STAGE, EndIndex``STAGE; \ + integer TokenIndex``STAGE; \ + integer MarkerIndex``STAGE; \ + integer NumCSR``STAGE; \ + logic [`XLEN-1:0] ExpectedPC``STAGE; \ + logic [31:0] ExpectedInstr``STAGE; \ + string text``STAGE; \ + string MemOp``STAGE; \ + string RegWrite``STAGE; \ + integer ExpectedRegAdr``STAGE; \ + logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ + logic [`XLEN-1:0] ExpectedMemAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ + string ExpectedCSRArray``STAGE[10:0]; \ + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; + `DECLARE_TRACE_SCANNER_SIGNALS(E) + `DECLARE_TRACE_SCANNER_SIGNALS(M) + integer NextMIPexpected; + integer NextMepcExpected; // Memory stage expected values from trace logic checkInstrM; integer MIPexpected; - string RegWriteM; - integer ExpectedRegAdrM; - logic [`XLEN-1:0] ExpectedRegValueM; - string MemOpM; - logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM; - string ExpectedCSRArrayM[10:0]; - logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0]; + string name; logic [`AHBW-1:0] readDataExpected; // Write back stage expected values from trace logic checkInstrW; @@ -148,6 +153,11 @@ module testbench(); integer NumCSRPostWIndex; logic [`XLEN-1:0] InstrCountW; integer RequestDelayedMIP; + integer ForceMIPFuture; + integer CSRIndex; + longint MepcExpected; + integer CheckMIPFutureE; + integer CheckMIPFutureM; // Useful Aliases `define RF dut.hart.ieu.dp.regf.rf `define PC dut.hart.ifu.pcreg.q @@ -292,13 +302,15 @@ module testbench(); ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"}; if (CHECKPOINT==0) begin // normal $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); - data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); + traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); + traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); InstrCountW = '0; end else begin // checkpoint $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT); checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir}; $readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM); - data_file_all = $fopen({checkpointDir,"all.txt"}, "r"); + traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); + traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); InstrCountW = CHECKPOINT; // manual checkpoint initializations that don't neatly fit into MACRO force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17]; @@ -319,8 +331,12 @@ module testbench(); release `INSTRET; release `CURR_PRIV; end + // Get the E-stage trace reader ahead of the M-stage trace reader + matchCountE = $fgets(lineE,traceFileE); end + + /////////////////////////////////////////////////////////////////////////////// //////////////////////////////////// CORE ///////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// @@ -332,94 +348,158 @@ module testbench(); // on the next falling edge the expected state is compared to the wally state. // step 0: read the expected state - assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM; + assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM; + `define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \ + // always check PC, instruction bits \ + if (checkInstrM) begin \ + // read 1 line of the trace file \ + matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \ + if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ + // extract PC, Instr \ + matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \ + \ + // for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. \ + // strtok was the best idea but it cannot be used correctly as system verilog does not have null \ + // terminated strings. \ + \ + // Just going to do this char by char. \ + StartIndex``STAGE = 0; \ + TokenIndex``STAGE = 0; \ + //$display("len = %d", line``STAGE.len()); \ + for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \ + //$display("char = %s", line``STAGE[index]); \ + if (line``STAGE[index``STAGE] == " " || line``STAGE[index``STAGE] == "\n") begin \ + EndIndex``STAGE = index``STAGE; \ + ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \ + //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \ + StartIndex``STAGE = EndIndex``STAGE + 1; \ + TokenIndex``STAGE++; \ + end \ + end \ + \ + MarkerIndex``STAGE = 3; \ + NumCSR``STAGE = 0; \ + MemOp``STAGE = ""; \ + RegWrite``STAGE = ""; \ + \ + #2; \ + \ + while(TokenIndex``STAGE > MarkerIndex``STAGE) begin \ + // parse the GPR \ + if (ExpectedTokens``STAGE[MarkerIndex``STAGE] == "GPR") begin \ + RegWrite``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%d", ExpectedRegAdr``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedRegValue``STAGE); \ + MarkerIndex``STAGE += 3; \ + // parse memory address, read data, and/or write data \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \ + MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedMemAdr``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \ + MarkerIndex``STAGE += 4; \ + // parse CSRs, because there are 1 or more CSRs after the CSR token \ + // we check if the CSR token or the number of CSRs is greater than 0. \ + // if so then we want to parse for a CSR. \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" || NumCSR``STAGE > 0) begin \ + if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \ + // all additional CSR's won't have this token. \ + MarkerIndex``STAGE++; \ + end \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \ + MarkerIndex``STAGE += 2; \ + if(`"STAGE`"=="E") begin \ + // match MIP to QEMU's because interrupts are imprecise \ + if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "mip") begin \ + CheckMIPFutureE = 1; \ + NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ + end \ + // $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); \ + // $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); \ + // // if PC does not equal MEPC, request delayed MIP is True \ + // if(ExpectedPCM != ExpectedCSRArrayM[7]) begin \ + // RequestDelayedMIP = 1; \ + // end else begin \ + // $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); \ + // MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; \ + // force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; \ + // end \ + // end \ + // $display("%tns: ExpectedCSRArrayM::: %p",$time,ExpectedCSRArrayM); \ + if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \ + $display("hello! we are here."); \ + MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \ + $display("%tns: MepcExpected: %x",$time,MepcExpected); \ + end \ + end \ + \ + NumCSR``STAGE++; \ + end \ + end \ + if(`"STAGE`"=="M") begin \ + // override on special conditions \ + if (ExpectedMemAdrM == 'h10000005) begin \ + //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); \ + force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ + end \ + if(textM.substr(0,5) == "rdtime") begin \ + //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); \ + force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ + end \ + end \ + end \ + always @(negedge clk) begin - // always check PC, instruction bits - if (checkInstrM) begin - // read 1 line of the trace file - matchCount = $fgets(line, data_file_all); - if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line); - // extract PC, Instr - matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM); - //$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM); + `SCAN_NEW_INSTR_FROM_TRACE(E) + end - // for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. - // strtok was the best idea but it cannot be used correctly as system verilog does not have null - // terminated strings. - - // Just going to do this char by char. - StartIndex = 0; - TokenIndex = 0; - //$display("len = %d", line.len()); - for(index = 0; index < line.len(); index++) begin - //$display("char = %s", line[index]); - if (line[index] == " " || line[index] == "\n") begin - EndIndex = index; - ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1); - //$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1)); - StartIndex = EndIndex + 1; - TokenIndex++; - end + always @(negedge clk) begin + `SCAN_NEW_INSTR_FROM_TRACE(M) + end + + // MIP spoofing + always @(posedge clk) begin + #1; + if(CheckMIPFutureE) CheckMIPFutureE <= 0; + CheckMIPFutureM <= CheckMIPFutureE; + if(CheckMIPFutureM) begin + if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + RequestDelayedMIP = 1; + $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); + end else begin // update MIP immediately + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; end - - MarkerIndex = 3; - NumCSRM = 0; - MemOpM = ""; - RegWriteM = ""; - - #2; - - while(TokenIndex > MarkerIndex) begin - // parse the GPR - if (ExpectedTokens[MarkerIndex] == "GPR") begin - RegWriteM = ExpectedTokens[MarkerIndex]; - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM); - MarkerIndex += 3; - // parse memory address, read data, and/or write data - end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin - MemOpM = ExpectedTokens[MarkerIndex]; - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM); - MarkerIndex += 4; - // parse CSRs, because there are 1 or more CSRs after the CSR token - // we check if the CSR token or the number of CSRs is greater than 0. - // if so then we want to parse for a CSR. - end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin - if(ExpectedTokens[MarkerIndex] == "CSR") begin - // all additional CSR's won't have this token. - MarkerIndex++; - end - matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]); - MarkerIndex += 2; - // match MIP to QEMU's because interrupts are imprecise - if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin - $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); - $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); - // if PC does not equal MEPC, request delayed MIP is True - if(ExpectedPCM != ExpectedCSRArrayM[7]) begin - RequestDelayedMIP = 1; - end else begin - $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); - MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; - force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - end - end - NumCSRM++; - end - end - // override on special conditions - if (ExpectedMemAdrM == 'h10000005) begin - //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); - force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; - end - if(textM.substr(0,5) == "rdtime") begin - //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); - force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; + $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); + $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); + $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM); + $display("%tn: MepcExpected = %x",$time,MepcExpected); + $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); + // if PC does not equal MEPC, request delayed MIP is True + $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM)); + $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]); + $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]); + + if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + RequestDelayedMIP = 1; + $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); + end else begin + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; end end + if(RequestDelayedMIP) begin + $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + $display("%tns: MepcExpected %x",$time,MepcExpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; + $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); + RequestDelayedMIP = 0; + end end // step 1: register expected state into the write back stage. @@ -449,7 +529,7 @@ module testbench(); ExpectedMemWriteDataW <= '0; ExpectedMemReadDataW <= '0; NumCSRW <= '0; - end else begin + end else if (dut.hart.ieu.c.InstrValidM) begin ExpectedPCW <= ExpectedPCM; ExpectedInstrW <= ExpectedInstrM; textW <= textM; @@ -484,12 +564,6 @@ module testbench(); // step2: make all checks in the write back stage. assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. always @(negedge clk) begin - if(RequestDelayedMIP) begin - $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]); - MIPexpected = ExpectedCSRArrayValueW[NumCSRM]; - force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - RequestDelayedMIP = 0; - end // always check PC, instruction bits if (checkInstrW) begin InstrCountW += 1; @@ -521,7 +595,7 @@ module testbench(); if(MemOpW == "MemR" || MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin + end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end