From ac5c53a87001fda702fb0a9010413b3effb39188 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 3 Mar 2023 09:46:29 -0800 Subject: [PATCH 1/6] Added correct causing and handling of S time interrupts to test suite. --- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 42 +++++++++++++++---- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 35 ++++++++++++---- 2 files changed, 59 insertions(+), 18 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 1171786f4..7a52b08dd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -125,20 +125,34 @@ cause_m_time_interrupt: lw t2, 0(t5) // low word of MTIME lw t6, 4(t5) // high word of MTIME add t3, t2, t3 // add desired offset to the current time - bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound) + bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word sw t6,4(t4) // store into most significant word of MTIMECMP -nowrap: +nowrap_m: sw t3, 0(t4) // store into least significant word of MTIMECMP -time_loop: +time_loop_m: addi a3, a3, -1 - bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt + bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt ret cause_s_time_interrupt: - li t3, 0x20 - csrs mip, t3 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. - nop // added extra nops in so the csrs can get through the pipeline before returning. + li t3, 0x2 + csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp + li t3, 0x30 // Desired offset from the present time + mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles + // la t4, 0x02004000 // MTIMECMP register in CLINT + la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it + lw t2, 0(t5) // low word of MTIME + lw t6, 4(t5) // high word of MTIME + add t3, t2, t3 // add desired offset to the current time + bgtu t3, t2, nowrap_s // check new time exceeds current time (no wraparound) + addi t6, t6, 1 // if wrap, increment most significant word +nowrap_s: + csrw 0x14D, t3 // store into STIMECMP + csrw 0x15D, t6 // store into STIMECMPH +time_loop_s: + addi a3, a3, -1 + bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt ret cause_m_soft_interrupt: @@ -353,6 +367,9 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w .endif + li t3, 0x2 + csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp + // Respond to trap based on cause // All interrupts should return after being logged csrr ra, \MODE\()cause @@ -423,6 +440,9 @@ trapreturn_specified_\MODE\(): li a2, 0 // reset trapreturn inputs to the trap handler trapreturn_finished_\MODE\(): + li t3, 0x2 + csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp + csrw \MODE\()epc, ra // update the mepc with address of next instruction lw t2, -12(sp) // restore registers from stack before returning lw t0, -8(sp) @@ -545,8 +565,12 @@ soft_interrupt_\MODE\(): time_interrupt_\MODE\(): la t0, 0x02004000 // MTIMECMP register in CLINT li t2, 0xFFFFFFFF - sw t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF - + sw t2, 0(t0) // reset interrupt by setting mtimecmp to max + //sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max + csrw 0x14D, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH. + csrw 0x15D, t2 + + li t0, 0x20 csrc \MODE\()ip, t0 lw ra, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 576636deb..4a6fa94a4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -127,22 +127,32 @@ cause_m_time_interrupt: lw t2, 0(t5) // low word of MTIME lw t6, 4(t5) // high word of MTIME add t3, t2, t3 // add desired offset to the current time - bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound) + bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word sw t6,4(t4) // store into most significant word of MTIMECMP -nowrap: +nowrap_m: sw t3, 0(t4) // store into least significant word of MTIMECMP -time_loop: +time_loop_m: addi a3, a3, -1 - bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt + bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt ret cause_s_time_interrupt: - li t3, 0x20 - csrs mip, t3 // set supervisor time interrupt pending. - nop // added extra nops in so the csrs can get through the pipeline before returning. + li t3, 0x2 + csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp + li t3, 0x30 // Desired offset from the present time + mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles + // la t4, 0x02004000 // MTIMECMP register in CLINT + la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it + lw t2, 0(t5) // low word of MTIME + lw t6, 4(t5) // high word of MTIME + add t3, t2, t3 // add desired offset to the current time + csrw 0x14D, t3 // store into most significant word of STIMECMP +time_loop_s: + addi a3, a3, -1 + bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt ret - + cause_m_soft_interrupt: la t3, 0x02000000 // MSIP register in CLINT li t4, 1 // 1 in the lsb @@ -347,6 +357,9 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w .endif + li t3, 0x2 + csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp + // Respond to trap based on cause // All interrupts should return after being logged csrr ra, \MODE\()cause @@ -417,6 +430,9 @@ trapreturn_specified_\MODE\(): li a2, 0 // reset trapreturn inputs to the trap handler trapreturn_finished_\MODE\(): + li t3, 0x2 + csrc \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp + csrw \MODE\()epc, ra // update the epc with address of next instruction ld t2, -24(sp) // restore registers from stack before returning ld t0, -16(sp) @@ -539,7 +555,8 @@ soft_interrupt_\MODE\(): time_interrupt_\MODE\(): la t0, 0x02004000 // MTIMECMP register in CLINT li t2, 0xFFFFFFFF - sd t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF + sd t2, 0(t0) // reset interrupt by setting mtimecmp to max + csrw 0x14D, t2 // reset stime interrupts by doing the same. li t0, 0x20 csrc \MODE\()ip, t0 From a38f7cc8a10e830ef0c41ad6bede60b9fa0d4f2c Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Thu, 23 Feb 2023 13:45:44 -0800 Subject: [PATCH 2/6] added reset values to stime and stimecmp registers --- src/privileged/csrs.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 253d02457..e47a44426 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -102,10 +102,10 @@ module csrs #(parameter flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); if (`SSTC_SUPPORTED) begin if (`XLEN == 64) - flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW); + flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); else begin - flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]); - flopenr #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]); + flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]); + flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]); end end else assign STIMECMP_REGW = 0; From 75f6e9eb3432f8eb04eb1162274a8e6069a0cd12 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sat, 4 Mar 2023 15:46:26 -0800 Subject: [PATCH 3/6] added S time compare to gc configs --- config/rv32gc/wally-config.vh | 2 +- config/rv64gc/wally-config.vh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index d7475cdbe..359e2d83e 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -43,7 +43,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 +`define SSTC_SUPPORTED 1 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index 4e2ab3dfd..b5038be58 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -44,7 +44,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 +`define SSTC_SUPPORTED 1 // LSU microarchitectural Features `define BUS_SUPPORTED 1 From ab6b953a4b23a962e98e519c32983103ed31cc44 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sat, 4 Mar 2023 15:46:57 -0800 Subject: [PATCH 4/6] removed changes to counteren from stimecmp tests --- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 9 --------- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 8 -------- 2 files changed, 17 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 7a52b08dd..ad892e951 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -136,11 +136,8 @@ time_loop_m: ret cause_s_time_interrupt: - li t3, 0x2 - csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp li t3, 0x30 // Desired offset from the present time mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles - // la t4, 0x02004000 // MTIMECMP register in CLINT la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it lw t2, 0(t5) // low word of MTIME lw t6, 4(t5) // high word of MTIME @@ -367,9 +364,6 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w .endif - li t3, 0x2 - csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp - // Respond to trap based on cause // All interrupts should return after being logged csrr ra, \MODE\()cause @@ -440,9 +434,6 @@ trapreturn_specified_\MODE\(): li a2, 0 // reset trapreturn inputs to the trap handler trapreturn_finished_\MODE\(): - li t3, 0x2 - csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp - csrw \MODE\()epc, ra // update the mepc with address of next instruction lw t2, -12(sp) // restore registers from stack before returning lw t0, -8(sp) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 4a6fa94a4..1e86d963a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -138,8 +138,6 @@ time_loop_m: ret cause_s_time_interrupt: - li t3, 0x2 - csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp li t3, 0x30 // Desired offset from the present time mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles // la t4, 0x02004000 // MTIMECMP register in CLINT @@ -357,9 +355,6 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w .endif - li t3, 0x2 - csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp - // Respond to trap based on cause // All interrupts should return after being logged csrr ra, \MODE\()cause @@ -430,9 +425,6 @@ trapreturn_specified_\MODE\(): li a2, 0 // reset trapreturn inputs to the trap handler trapreturn_finished_\MODE\(): - li t3, 0x2 - csrc \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp - csrw \MODE\()epc, ra // update the epc with address of next instruction ld t2, -24(sp) // restore registers from stack before returning ld t0, -16(sp) From db6caedfec076d73539b4c5e9db844d86db18dc7 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sat, 4 Mar 2023 15:53:03 -0800 Subject: [PATCH 5/6] added in the CSR name for stimecmp(h) --- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 8 ++++---- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index ad892e951..f3f963d8b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -145,8 +145,8 @@ cause_s_time_interrupt: bgtu t3, t2, nowrap_s // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word nowrap_s: - csrw 0x14D, t3 // store into STIMECMP - csrw 0x15D, t6 // store into STIMECMPH + csrw stimecmp, t3 // store into STIMECMP + csrw stimecmph, t6 // store into STIMECMPH time_loop_s: addi a3, a3, -1 bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt @@ -558,8 +558,8 @@ time_interrupt_\MODE\(): li t2, 0xFFFFFFFF sw t2, 0(t0) // reset interrupt by setting mtimecmp to max //sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max - csrw 0x14D, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH. - csrw 0x15D, t2 + csrw stimecmp, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH. + csrw stimecmph, t2 li t0, 0x20 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 1e86d963a..00e235f35 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -145,7 +145,7 @@ cause_s_time_interrupt: lw t2, 0(t5) // low word of MTIME lw t6, 4(t5) // high word of MTIME add t3, t2, t3 // add desired offset to the current time - csrw 0x14D, t3 // store into most significant word of STIMECMP + csrw stimecmp, t3 // store into most significant word of STIMECMP time_loop_s: addi a3, a3, -1 bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt @@ -548,7 +548,7 @@ time_interrupt_\MODE\(): la t0, 0x02004000 // MTIMECMP register in CLINT li t2, 0xFFFFFFFF sd t2, 0(t0) // reset interrupt by setting mtimecmp to max - csrw 0x14D, t2 // reset stime interrupts by doing the same. + csrw stimecmp, t2 // reset stime interrupts by doing the same. li t0, 0x20 csrc \MODE\()ip, t0 From 39ac3cd18f09f9dc5dfbc7a36d68955c356affb5 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Wed, 8 Mar 2023 12:44:53 +0000 Subject: [PATCH 6/6] Add support for setting PMP registers Add support for async DV --- sim/imperas.ic | 7 +++---- testbench/common/wallyTracer.sv | 31 +++++++++++++++++++++++++++++++ testbench/testbench_imperas.sv | 25 ++++++++++--------------- 3 files changed, 44 insertions(+), 19 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index 5e3357eac..8b4ef2d45 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,12 +1,14 @@ #--showoverrides #--help --helpall ---traceregs --override cpu/show_c_prefix=T --override cpu/unaligned=F --override cpu/ignore_non_leaf_DAU=1 --override cpu/wfi_is_nop=T +# this should be 16 not 0 +--override cpu/PMP_registers=0 + # Enable the Imperas instruction coverage #-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 #-override refRoot/cpu/cv/cover=basic @@ -32,9 +34,6 @@ # Store simulator output to logfile --output imperas.log ---override cpu/PMP_registers=0 -#--showoverrides -#--mpdconsole # ignore settings of bits DAU for non leaf page table walks --override cpu/ignore_non_leaf_DAU=1 diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 6daf48e9d..bfe5c4b3f 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -98,6 +98,37 @@ module wallyTracer(rvviTrace rvvi); if(valid) begin // machine CSRs // *** missing PMP and performance counters. + + // PMPCFG space is 0-15 3a0 - 3af + int i, i4, i8, csrid; + logic [`XLEN-1:0] pmp; + for (i=0; i<`PMP_ENTRIES; i+=8) begin + i4 = i / 4; + i8 = (i / 8) * 8; + pmp = 0; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+2] << 16; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+3] << 24; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+4] << 32; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+5] << 40; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48; + pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56; + + csrid = 12'h3A0 + i4; + //if (CSRArray[csrid] != pmp) $display("Info: %m pmpcfg%0d [%03X] %016X -> %016X", i4, csrid, CSRArray[csrid], pmp); + CSRArray[csrid] = pmp; + end + + // PMPADDR space is 0-63 3b0 - 3ef + for (i=0; i<`PMP_ENTRIES; i++) begin + pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i]; + + csrid = 12'h3B0 + i; + //if (CSRArray[csrid] != pmp) $display("Info: %m Change pmpaddr%0d [%03X] %016X -> %016X", i, csrid, CSRArray[csrid], pmp); + CSRArray[csrid] = pmp; + end + CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW; diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 442edec22..f5ad63bcd 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -27,7 +27,7 @@ `include "wally-config.vh" -// This is set from the commsnd line script +// This is set from the command line script // `define USE_IMPERAS_DV `ifdef USE_IMPERAS_DV @@ -121,10 +121,11 @@ module testbench; end - rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); - wallyTracer wallyTracer(rvvi); - `ifdef USE_IMPERAS_DV + + rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); + wallyTracer wallyTracer(rvvi); + trace2log idv_trace2log(rvvi); trace2cov idv_trace2cov(rvvi); @@ -139,6 +140,7 @@ module testbench; int PRIV_RWX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE | RVVI_MEMORY_PRIVILEGE_EXEC; int PRIV_RW = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE; + int PRIV_RX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_EXEC; int PRIV_X = RVVI_MEMORY_PRIVILEGE_EXEC; initial begin @@ -170,11 +172,12 @@ module testbench; // pending and taken void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP - + +/* // Memory lo, hi, priv (RVVI_MEMORY_PRIVILEGE_{READ,WRITE,EXEC}) void'(rvviRefMemorySetPrivilege(56'h0, 56'h7fffffffff, 0)); if (`BOOTROM_SUPPORTED) - void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_X)); + void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_RX)); if (`UNCORE_RAM_SUPPORTED) void'(rvviRefMemorySetPrivilege(`UNCORE_RAM_BASE, (`UNCORE_RAM_BASE + `UNCORE_RAM_RANGE), PRIV_RWX)); if (`EXT_MEM_SUPPORTED) @@ -200,6 +203,7 @@ module testbench; void'(rvviRefMemorySetPrivilege(`SDC_BASE, (`SDC_BASE + `SDC_RANGE), PRIV_RW)); void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE))); end +*/ if(`XLEN==32) begin void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH @@ -210,15 +214,6 @@ module testbench; void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!! - // These should be done in the attached client -// // Enable the trace2log module -// if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin -// msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE)); -// end -// -// if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin -// msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE)); -// end end always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt", dut.core.MTimerInt));