From 78448c70533b27974b55fb96a73915e4afbe45e2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 20:21:33 +0000 Subject: [PATCH 01/18] privileged cleanup --- pipelined/src/privileged/privileged.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 16fb04632..548aa0312 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -159,7 +159,6 @@ module privileged ( flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); - // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021 trap trap(.reset, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, From 14f9f41d2db6f9f2236a6a082ff5646046d4c40d Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 20:45:45 +0000 Subject: [PATCH 02/18] Partitioned privileged pipeline registers into module --- addins/embench-iot | 2 +- addins/riscv-arch-test | 2 +- addins/riscv-dv | 2 +- addins/riscv-tests | 2 +- pipelined/src/ppa/ppa.sv | 6 +-- pipelined/src/privileged/privileged.sv | 25 ++++------ pipelined/src/privileged/privpiperegs.sv | 58 ++++++++++++++++++++++++ pipelined/testbench/testbench.sv | 2 +- 8 files changed, 75 insertions(+), 24 deletions(-) create mode 100644 pipelined/src/privileged/privpiperegs.sv diff --git a/addins/embench-iot b/addins/embench-iot index 261a65e0a..2d2aaa7b8 160000 --- a/addins/embench-iot +++ b/addins/embench-iot @@ -1 +1 @@ -Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9 +Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3 diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..effd553a6 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f diff --git a/addins/riscv-dv b/addins/riscv-dv index a7e27bc04..cb4295f9c 160000 --- a/addins/riscv-dv +++ b/addins/riscv-dv @@ -1 +1 @@ -Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172 +Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071 diff --git a/addins/riscv-tests b/addins/riscv-tests index cf04274f5..3e2bf06b0 160000 --- a/addins/riscv-tests +++ b/addins/riscv-tests @@ -1 +1 @@ -Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7 +Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94 diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 1ce9b4496..083c76bf4 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -264,9 +264,9 @@ module ppa_prioriyencoder #(parameter N = 8) ( end endmodule -module ppa_decoder ( - input logic [$clog2(N)-1:0] a, - output logic [N-1:0] y); +module ppa_decoder #(parameter WIDTH = 8) ( + input logic [$clog2(WIDTH)-1:0] a, + output logic [WIDTH-1:0] y); always_comb begin y = 0; y[a] = 1; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 548aa0312..a0ea3ef65 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -88,10 +88,10 @@ module privileged ( logic sretM, mretM, sfencevmaM; logic IllegalCSRAccessM; - logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; + logic IllegalIEUInstrFaultM; logic IllegalFPUInstrM; - logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM; - logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; + logic InstrPageFaultM; + logic InstrAccessFaultM; logic IllegalInstrFaultM; logic MTrapM, STrapM; @@ -149,16 +149,11 @@ module privileged ( .CSRReadValW, .IllegalCSRAccessM, .BigEndianM); - // pipeline fault signals - flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, - {InstrPageFaultF, InstrAccessFaultF}, - {InstrPageFaultD, InstrAccessFaultD}); - flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE, - {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, // ** vs IllegalInstrFaultInD - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}); - flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, - {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); + privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, + .IllegalFPUInstrE, + .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM, .IllegalFPUInstrM); + trap trap(.reset, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, @@ -169,9 +164,7 @@ module privileged ( .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, - .PCM, - .IEUAdrM, - .InstrM, + .PCM, .IEUAdrM, .InstrM, .InstrValidM, .CommittedM, .TrapM, .MTrapM, .STrapM, .RetM, .InterruptM, .IntPendingM, diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv new file mode 100644 index 000000000..db1a77228 --- /dev/null +++ b/pipelined/src/privileged/privpiperegs.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// privpiperegs.sv +// +// Written: David_Harris@hmc.edu 12 May 2022 +// Modified: +// +// Purpose: Pipeline registers for early exceptions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module privpiperegs ( + input logic clk, reset, + input logic StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + input logic InstrPageFaultF, InstrAccessFaultF, + input logic IllegalIEUInstrFaultD, IllegalFPUInstrD, + output logic IllegalFPUInstrE, + output logic InstrPageFaultM, InstrAccessFaultM, + output logic IllegalIEUInstrFaultM, IllegalFPUInstrM +); + + logic InstrPageFaultD, InstrAccessFaultD; + logic InstrPageFaultE, InstrAccessFaultE; + logic IllegalIEUInstrFaultE; + + // pipeline fault signals + flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, + {InstrPageFaultF, InstrAccessFaultF}, + {InstrPageFaultD, InstrAccessFaultD}); + flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE, + {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}); + flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, + {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); +endmodule \ No newline at end of file diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index bf4903e51..d070aa3f2 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -208,7 +208,7 @@ logic [3:0] dummy; always @(negedge clk) begin if (TEST == "coremark") - if (dut.core.priv.priv.ecallM) begin + if (dut.core.priv.priv.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end From 072c464dc1efb2d0525d0384ca28d9a5060b1bc2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 21:36:13 +0000 Subject: [PATCH 03/18] Simplified MTVAL logic --- pipelined/src/privileged/trap.sv | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 4d3523638..176292f68 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -149,7 +149,14 @@ module trap ( // MTVAL /////////////////////////////////////////// - always_comb + always_comb + case (CauseM) + 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint + 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault + 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults + default: NextFaultMtvalM = 0; // Ecall, interrupts + endcase +/* always_comb if (InstrPageFaultM) NextFaultMtvalM = PCM; else if (InstrAccessFaultM) NextFaultMtvalM = PCM; else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; @@ -162,5 +169,5 @@ module trap ( else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM; else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM; else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM; - else NextFaultMtvalM = 0; + else NextFaultMtvalM = 0; */ endmodule From 21ac969c7dd2b976038374f8d7be35ec7251e658 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 21:50:15 +0000 Subject: [PATCH 04/18] Simplifying trap/csr interface --- pipelined/src/privileged/csr.sv | 53 ++++++++++++++++++++++++-- pipelined/src/privileged/privileged.sv | 12 +++--- pipelined/src/privileged/trap.sv | 23 ++++------- 3 files changed, 63 insertions(+), 25 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 20114b15a..7019675e7 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -40,7 +40,7 @@ module csr #(parameter input logic FlushE, FlushM, FlushW, input logic StallE, StallM, StallW, input logic [31:0] InstrM, - input logic [`XLEN-1:0] PCM, SrcAM, + input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, @@ -55,7 +55,7 @@ module csr #(parameter input logic ICacheMiss, input logic ICacheAccess, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, - input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, + input logic [`XLEN-1:0] CauseM, //NextFaultMtvalM, input logic SelHPTW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, @@ -71,7 +71,7 @@ module csr #(parameter input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, - output logic [`XLEN-1:0] CSRReadValW, + output logic [`XLEN-1:0] CSRReadValW, PrivilegedNextPCM, output logic IllegalCSRAccessM, BigEndianM ); @@ -96,10 +96,57 @@ module csr #(parameter logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; logic [11:0] MIP_REGW_writeable; + logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM; + logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; + /////////////////////////////////////////// + // MTVAL + /////////////////////////////////////////// + + always_comb + case (CauseM) + 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint + 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault + 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults + default: NextFaultMtvalM = 0; // Ecall, interrupts + endcase + + + /////////////////////////////////////////// + // Trap Vectoring + /////////////////////////////////////////// + // + // POSSIBLE OPTIMIZATION: + // From 20190608 privielegd spec page 27 (3.1.7) + // > Allowing coarser alignments in Vectored mode enables vectoring to be + // > implemented without a hardware adder circuit. + // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with + // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} + // However, this is program dependent, so not implemented at this time. + + always_comb + if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; + else PrivilegedTrapVector = MTVEC_REGW; + + if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec + always_comb + if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; + else + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + end + else begin + assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + end + + always_comb + if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; + else if (mretM) PrivilegedNextPCM = MEPC_REGW; + else PrivilegedNextPCM = SEPC_REGW; + // modify CSRs always_comb begin // Choose either rs1 or uimm[4:0] as source diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index a0ea3ef65..62924d899 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -81,7 +81,7 @@ module privileged ( output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM ); - logic [`XLEN-1:0] CauseM, NextFaultMtvalM; + logic [`XLEN-1:0] CauseM; //, NextFaultMtvalM; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEDELEG_REGW; logic [11:0] MIDELEG_REGW; @@ -125,7 +125,7 @@ module privileged ( csr csr(.clk, .reset, .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .PCM, .SrcAM, + .InstrM, .PCM, .SrcAM, .IEUAdrM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, @@ -133,7 +133,7 @@ module privileged ( .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, - .CauseM, .NextFaultMtvalM, .SelHPTW, + .CauseM, /*.NextFaultMtvalM,*/ .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, @@ -146,7 +146,7 @@ module privileged ( .PMPADDR_ARRAY_REGW, .SetFflagsM, .FRM_REGW, - .CSRReadValW, + .CSRReadValW,.PrivilegedNextPCM, .IllegalCSRAccessM, .BigEndianM); privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, @@ -164,11 +164,11 @@ module privileged ( .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, - .PCM, .IEUAdrM, .InstrM, + /* .PCM, .IEUAdrM, .InstrM,*/ .InstrValidM, .CommittedM, .TrapM, .MTrapM, .STrapM, .RetM, .InterruptM, .IntPendingM, - .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); + /* .PrivilegedNextPCM, */.CauseM/*MtvalM*/); endmodule diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 176292f68..cf26a6433 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -42,13 +42,13 @@ module trap ( (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, - input logic [`XLEN-1:0] PCM, - input logic [`XLEN-1:0] IEUAdrM, - input logic [31:0] InstrM, +/* input logic [`XLEN-1:0] PCM, + input logic [`XLEN-1:0] IEUAdrM, + input logic [31:0] InstrM, */ input logic InstrValidM, CommittedM, output logic TrapM, MTrapM, STrapM, RetM, output logic InterruptM, IntPendingM, - output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM + output logic [`XLEN-1:0] /*PrivilegedNextPCM, */CauseM //NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM ); @@ -57,7 +57,7 @@ module trap ( logic ExceptionM; (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; //logic InterruptM; - logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; + //logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; /////////////////////////////////////////// // Determine pending enabled interrupts @@ -87,6 +87,7 @@ module trap ( assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign RetM = mretM | sretM; +/* always_comb if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; else PrivilegedTrapVector = MTVEC_REGW; @@ -118,6 +119,7 @@ module trap ( if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; else if (mretM) PrivilegedNextPCM = MEPC_REGW; else PrivilegedNextPCM = SEPC_REGW; + */ /////////////////////////////////////////// // Cause priority defined in table 3.7 of 20190608 privileged spec @@ -145,17 +147,6 @@ module trap ( else if (StoreAmoAccessFaultM) CauseM = 7; else CauseM = 0; - /////////////////////////////////////////// - // MTVAL - /////////////////////////////////////////// - - always_comb - case (CauseM) - 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint - 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault - 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults - default: NextFaultMtvalM = 0; // Ecall, interrupts - endcase /* always_comb if (InstrPageFaultM) NextFaultMtvalM = PCM; else if (InstrAccessFaultM) NextFaultMtvalM = PCM; From 5f358a37c66c4d002f96f9cb3c2b385e1ffb06eb Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 21:55:50 +0000 Subject: [PATCH 05/18] More trap/csr simplification --- pipelined/src/privileged/csr.sv | 13 ++++-- pipelined/src/privileged/privileged.sv | 7 ++- pipelined/src/privileged/trap.sv | 60 +------------------------- 3 files changed, 15 insertions(+), 65 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 7019675e7..b9ed77e4c 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -114,7 +114,6 @@ module csr #(parameter default: NextFaultMtvalM = 0; // Ecall, interrupts endcase - /////////////////////////////////////////// // Trap Vectoring /////////////////////////////////////////// @@ -147,7 +146,9 @@ module csr #(parameter else if (mretM) PrivilegedNextPCM = MEPC_REGW; else PrivilegedNextPCM = SEPC_REGW; - // modify CSRs + /////////////////////////////////////////// + // CSRWriteValM + /////////////////////////////////////////// always_comb begin // Choose either rs1 or uimm[4:0] as source CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM; @@ -168,7 +169,9 @@ module csr #(parameter endcase end - // write CSRs + /////////////////////////////////////////// + // CSR Write values + /////////////////////////////////////////// assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment @@ -178,6 +181,10 @@ module csr #(parameter assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRUWriteM = CSRWriteM; + /////////////////////////////////////////// + // CSRs + /////////////////////////////////////////// + csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .MExtInt, .SExtInt, .MTimerInt, .MSwInt, diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 62924d899..44c4f4f6f 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -81,7 +81,7 @@ module privileged ( output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM ); - logic [`XLEN-1:0] CauseM; //, NextFaultMtvalM; + logic [`XLEN-1:0] CauseM; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEDELEG_REGW; logic [11:0] MIDELEG_REGW; @@ -133,7 +133,7 @@ module privileged ( .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, - .CauseM, /*.NextFaultMtvalM,*/ .SelHPTW, + .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, @@ -164,11 +164,10 @@ module privileged ( .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, - /* .PCM, .IEUAdrM, .InstrM,*/ .InstrValidM, .CommittedM, .TrapM, .MTrapM, .STrapM, .RetM, .InterruptM, .IntPendingM, - /* .PrivilegedNextPCM, */.CauseM/*MtvalM*/); + .CauseM); endmodule diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index cf26a6433..1566ce411 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -42,22 +42,15 @@ module trap ( (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, -/* input logic [`XLEN-1:0] PCM, - input logic [`XLEN-1:0] IEUAdrM, - input logic [31:0] InstrM, */ input logic InstrValidM, CommittedM, output logic TrapM, MTrapM, STrapM, RetM, output logic InterruptM, IntPendingM, - output logic [`XLEN-1:0] /*PrivilegedNextPCM, */CauseM //NextFaultMtvalM -// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, -// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM + output logic [`XLEN-1:0] CauseM ); logic MIntGlobalEnM, SIntGlobalEnM; logic ExceptionM; (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; - //logic InterruptM; - //logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; /////////////////////////////////////////// // Determine pending enabled interrupts @@ -82,45 +75,11 @@ module trap ( InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM | BreakpointFaultM | EcallFaultM | LoadAccessFaultM | StoreAmoAccessFaultM; - assign TrapM = ExceptionM | InterruptM; // *** clean this up later DH + assign TrapM = ExceptionM | InterruptM; assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign RetM = mretM | sretM; -/* - always_comb - if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; - else PrivilegedTrapVector = MTVEC_REGW; - - /////////////////////////////////////////// - // Handle vectored traps (when mtvec/stvec csr value has bits [1:0] == 01) - // For vectored traps, set program counter to _tvec value + 4 times the cause code - /////////////////////////////////////////// - // - // POSSIBLE OPTIMIZATION: - // From 20190608 privielegd spec page 27 (3.1.7) - // > Allowing coarser alignments in Vectored mode enables vectoring to be - // > implemented without a hardware adder circuit. - // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with - // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} - // However, this is program dependent, so not implemented at this time. - if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec - always_comb - if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; - else - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; - end - else begin - assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; - end - - always_comb - if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; - else if (mretM) PrivilegedNextPCM = MEPC_REGW; - else PrivilegedNextPCM = SEPC_REGW; - */ - /////////////////////////////////////////// // Cause priority defined in table 3.7 of 20190608 privileged spec // Exceptions are of lower priority than all interrupts (3.1.9) @@ -146,19 +105,4 @@ module trap ( else if (LoadAccessFaultM) CauseM = 5; else if (StoreAmoAccessFaultM) CauseM = 7; else CauseM = 0; - -/* always_comb - if (InstrPageFaultM) NextFaultMtvalM = PCM; - else if (InstrAccessFaultM) NextFaultMtvalM = PCM; - else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; - else if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (EcallFaultM) NextFaultMtvalM = 0; - else if (BreakpointFaultM) NextFaultMtvalM = PCM; - else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM; - else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM; - else NextFaultMtvalM = 0; */ endmodule From 16b86c199ca3e9480a7f68fc73e9c05652eba4f7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 22:00:23 +0000 Subject: [PATCH 06/18] More trap/csr simplification --- pipelined/src/privileged/csr.sv | 3 ++- pipelined/src/privileged/privileged.sv | 3 --- pipelined/src/privileged/trap.sv | 1 - 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index b9ed77e4c..c6eec2113 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -59,7 +59,7 @@ module csr #(parameter input logic SelHPTW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, - output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, + output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, @@ -83,6 +83,7 @@ module csr #(parameter (* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM; (* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW; + logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW; logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 44c4f4f6f..61241b178 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -82,7 +82,6 @@ module privileged ( ); logic [`XLEN-1:0] CauseM; - logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEDELEG_REGW; logic [11:0] MIDELEG_REGW; @@ -136,7 +135,6 @@ module privileged ( .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, - .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEDELEG_REGW, .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, @@ -161,7 +159,6 @@ module privileged ( .LoadPageFaultM, .StoreAmoPageFaultM, .mretM, .sretM, .PrivilegeModeW, .NextPrivilegeModeM, - .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .InstrValidM, .CommittedM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 1566ce411..47fdb977f 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -39,7 +39,6 @@ module trap ( (* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, (* mark_debug = "true" *) input logic mretM, sretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, - (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, input logic InstrValidM, CommittedM, From 662fffa830f5de3e3861b4773fc29d1ae93079a3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 22:04:20 +0000 Subject: [PATCH 07/18] More trap/csr simplification --- pipelined/src/privileged/csr.sv | 5 ++++- pipelined/src/privileged/privileged.sv | 5 ++--- pipelined/src/privileged/trap.sv | 2 -- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index c6eec2113..18ecd01df 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -41,7 +41,7 @@ module csr #(parameter input logic StallE, StallM, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, - input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM, + input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, @@ -98,6 +98,7 @@ module csr #(parameter logic [`XLEN-1:0] CSRReadVal2M; logic [11:0] MIP_REGW_writeable; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM; + logic MTrapM, STrapM; logic InstrValidNotFlushedM; @@ -181,6 +182,8 @@ module csr #(parameter assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRUWriteM = CSRWriteM; + assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); + assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; /////////////////////////////////////////// // CSRs diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 61241b178..de2ce351e 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -93,7 +93,6 @@ module privileged ( logic InstrAccessFaultM; logic IllegalInstrFaultM; - logic MTrapM, STrapM; (* mark_debug = "true" *) logic InterruptM; logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; @@ -125,7 +124,7 @@ module privileged ( .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, .IEUAdrM, - .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM, + .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, @@ -162,7 +161,7 @@ module privileged ( .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .InstrValidM, .CommittedM, - .TrapM, .MTrapM, .STrapM, .RetM, + .TrapM, .RetM, .InterruptM, .IntPendingM, .CauseM); endmodule diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 47fdb977f..4467ab6a7 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -75,8 +75,6 @@ module trap ( BreakpointFaultM | EcallFaultM | LoadAccessFaultM | StoreAmoAccessFaultM; assign TrapM = ExceptionM | InterruptM; - assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); - assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign RetM = mretM | sretM; /////////////////////////////////////////// From 292d1f33da290ccc428f1d8c1435e59eb9b16f01 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 22:06:03 +0000 Subject: [PATCH 08/18] More trap/csr simplification --- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/trap.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index de2ce351e..e4d5ded16 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -157,7 +157,7 @@ module privileged ( .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM, .LoadPageFaultM, .StoreAmoPageFaultM, .mretM, .sretM, - .PrivilegeModeW, .NextPrivilegeModeM, + .PrivilegeModeW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .InstrValidM, .CommittedM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 4467ab6a7..f23efeba2 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -38,7 +38,7 @@ module trap ( (* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, (* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, (* mark_debug = "true" *) input logic mretM, sretM, - input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, + input logic [1:0] PrivilegeModeW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, input logic InstrValidM, CommittedM, From c2b9fc0d8e556fb13ff5499c170190ad703e9fc6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 22:26:21 +0000 Subject: [PATCH 09/18] trap/csr cleanup --- pipelined/src/privileged/csr.sv | 3 ++- pipelined/src/privileged/trap.sv | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 18ecd01df..6d71b08df 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -59,7 +59,6 @@ module csr #(parameter input logic SelHPTW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, - output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, @@ -84,6 +83,8 @@ module csr #(parameter (* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW; logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW; + logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW; + logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index f23efeba2..fe2c7cf15 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -42,7 +42,7 @@ module trap ( (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, input logic InstrValidM, CommittedM, - output logic TrapM, MTrapM, STrapM, RetM, + output logic TrapM, RetM, output logic InterruptM, IntPendingM, output logic [`XLEN-1:0] CauseM ); From 94cb6caec6e60a6aaedf58cccaeaab79a33e6b76 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Thu, 12 May 2022 22:29:47 +0000 Subject: [PATCH 10/18] Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024) --- .../privilege/references/WALLY-pma.reference_output | 4 ++++ .../WALLY-status-fp-enabled-01.reference_output | 9 +++++++++ .../references/WALLY-status-sie-01.reference_output | 12 ++++++++++++ .../references/WALLY-status-tw-01.reference_output | 9 +++++++++ .../references/WALLY-trap-01.reference_output | 6 ++++++ .../references/WALLY-trap-s-01.reference_output | 6 ++++++ .../references/WALLY-trap-u-01.reference_output | 6 ++++++ .../references/WALLY-mtvec-01.reference_output | 2 +- .../privilege/references/WALLY-pma.reference_output | 12 ++++++++++++ .../WALLY-status-fp-enabled-01.reference_output | 4 ++++ .../references/WALLY-trap-01.reference_output | 12 ++++++++++++ .../references/WALLY-trap-u-01.reference_output | 12 ++++++++++++ 12 files changed, 93 insertions(+), 1 deletion(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output index a9cdc3633..15626485b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output @@ -1018,3 +1018,7 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output index 18d33c0d3..bb0290716 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output @@ -1013,3 +1013,12 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output index ba197a523..e6297f1e6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output index f37485d3a..f41585309 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output @@ -1013,3 +1013,12 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index 23bdf7233..a9c3da2c0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -1016,3 +1016,9 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 896467ecd..c7a9bac6e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -1016,3 +1016,9 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 85e666b54..5c6d8378d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -1016,3 +1016,9 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output index 5503d02b5..93e18c06d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output @@ -1021,4 +1021,4 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef \ No newline at end of file +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output index 440bee2aa..f6434b676 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output index 936435099..fe33b6398 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output @@ -1018,3 +1018,7 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 7e6231e75..71d93833b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index c42c74f2d..b0fe37c33 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef From 40a401c66c333bada8ba71ce75804724f6adeb6a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Thu, 12 May 2022 22:31:26 +0000 Subject: [PATCH 11/18] Added missing DEADBEEFs to this test as well --- .../WALLY-trap-s-01.reference_output | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index 791ebf777..e837095d4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -1000,3 +1000,25 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef From 2a3f545e0cde8ecf040633f4206592ab5083156e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 23:27:02 +0000 Subject: [PATCH 12/18] Cause simplification --- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/privmode.sv | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index e4d5ded16..8a5068a79 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -104,7 +104,7 @@ module privileged ( // track the current privilege level /////////////////////////////////////////// - privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .CauseM, + privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .InterruptM, .CauseM, .MEDELEG_REGW, .MIDELEG_REGW, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); /////////////////////////////////////////// diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv index d48c57d53..8fcd4905e 100644 --- a/pipelined/src/privileged/privmode.sv +++ b/pipelined/src/privileged/privmode.sv @@ -33,7 +33,7 @@ module privmode ( input logic clk, reset, - input logic StallW, TrapM, mretM, sretM, + input logic StallW, TrapM, mretM, sretM, InterruptM, input logic [`XLEN-1:0] CauseM, MEDELEG_REGW, input logic [11:0] MIDELEG_REGW, input logic [1:0] STATUS_MPP, @@ -45,7 +45,7 @@ module privmode ( logic md; // get bits of DELEG registers based on CAUSE - assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; + assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; // PrivilegeMode FSM always_comb begin From 581d84165322edb4507a948c52b591025a876db3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 23:29:35 +0000 Subject: [PATCH 13/18] Cause simplification --- pipelined/src/privileged/csr.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 6d71b08df..b6b76c93e 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -135,7 +135,7 @@ module csr #(parameter if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec always_comb - if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) + if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM) PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; else PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; @@ -178,7 +178,7 @@ module csr #(parameter assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment - assign NextCauseM = TrapM ? CauseM : CSRWriteValM; + assign NextCauseM = TrapM ? {InterruptM, CauseM[`XLEN-2:0]}: CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); From 5b7cccbc4bd6ec4e912354f6001c5c15ce587b40 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 23:33:22 +0000 Subject: [PATCH 14/18] Cause simplification --- pipelined/src/privileged/trap.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index fe2c7cf15..85f1d53e0 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -94,7 +94,7 @@ module trap ( else if (IllegalInstrFaultM) CauseM = 2; else if (InstrMisalignedFaultM) CauseM = 0; else if (BreakpointFaultM) CauseM = 3; - else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8; + else if (EcallFaultM) CauseM = {{(`XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW}; else if (LoadMisalignedFaultM) CauseM = 4; else if (StoreAmoMisalignedFaultM) CauseM = 6; else if (LoadPageFaultM) CauseM = 13; From f5f187007751fc21999eb3406c004d4c7d877870 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 23:33:35 +0000 Subject: [PATCH 15/18] Cause simplification --- pipelined/src/privileged/csr.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index b6b76c93e..3af62fb8d 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -55,7 +55,7 @@ module csr #(parameter input logic ICacheMiss, input logic ICacheAccess, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, - input logic [`XLEN-1:0] CauseM, //NextFaultMtvalM, + input logic [`XLEN-1:0] CauseM, input logic SelHPTW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, From 2f283d965479aff887eea6ec2890746174819273 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 23:37:40 +0000 Subject: [PATCH 16/18] Cause simplification --- pipelined/src/privileged/csr.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 3af62fb8d..fb78e8a99 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -93,7 +93,6 @@ module csr #(parameter logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; logic [11:0] CSRAdrM; - //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; @@ -110,7 +109,8 @@ module csr #(parameter /////////////////////////////////////////// always_comb - case (CauseM) + if (InterruptM) NextFaultMtvalM = 0; + else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults From 9651ced9bbf9d4ed3f1404068d0a0f8ef8aa84a5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 23:39:10 +0000 Subject: [PATCH 17/18] Cause simplification --- pipelined/src/privileged/trap.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 85f1d53e0..dffa73202 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -83,12 +83,12 @@ module trap ( /////////////////////////////////////////// always_comb if (reset) CauseM = 0; // hard reset 3.3 - else if (ValidIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int - else if (ValidIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int - else if (ValidIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int - else if (ValidIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int - else if (ValidIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int - else if (ValidIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int + else if (ValidIntsM[11]) CauseM = 11; // Machine External Int + else if (ValidIntsM[3]) CauseM = 3; // Machine Sw Int + else if (ValidIntsM[7]) CauseM = 7; // Machine Timer Int + else if (ValidIntsM[9]) CauseM = 9; // Supervisor External Int + else if (ValidIntsM[1]) CauseM = 1; // Supervisor Sw Int + else if (ValidIntsM[5]) CauseM = 5; // Supervisor Timer Int else if (InstrPageFaultM) CauseM = 12; else if (InstrAccessFaultM) CauseM = 1; else if (IllegalInstrFaultM) CauseM = 2; From 48e89485dda2456c6b735b94decf63805f997584 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 23:47:21 +0000 Subject: [PATCH 18/18] Cause simplification --- pipelined/src/privileged/csr.sv | 6 +++--- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/privmode.sv | 5 +++-- pipelined/src/privileged/trap.sv | 4 ++-- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index fb78e8a99..23104f7fd 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -55,7 +55,7 @@ module csr #(parameter input logic ICacheMiss, input logic ICacheAccess, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, - input logic [`XLEN-1:0] CauseM, + input logic [`LOG_XLEN-1:0] CauseM, input logic SelHPTW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, @@ -136,7 +136,7 @@ module csr #(parameter if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec always_comb if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM) - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00}; else PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; end @@ -178,7 +178,7 @@ module csr #(parameter assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment - assign NextCauseM = TrapM ? {InterruptM, CauseM[`XLEN-2:0]}: CSRWriteValM; + assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 8a5068a79..43e2f8f04 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -81,7 +81,7 @@ module privileged ( output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM ); - logic [`XLEN-1:0] CauseM; + logic [`LOG_XLEN-1:0] CauseM; logic [`XLEN-1:0] MEDELEG_REGW; logic [11:0] MIDELEG_REGW; diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv index 8fcd4905e..9446c08ce 100644 --- a/pipelined/src/privileged/privmode.sv +++ b/pipelined/src/privileged/privmode.sv @@ -34,7 +34,8 @@ module privmode ( input logic clk, reset, input logic StallW, TrapM, mretM, sretM, InterruptM, - input logic [`XLEN-1:0] CauseM, MEDELEG_REGW, + input logic [`LOG_XLEN-1:0] CauseM, + input logic [`XLEN-1:0] MEDELEG_REGW, input logic [11:0] MIDELEG_REGW, input logic [1:0] STATUS_MPP, input logic STATUS_SPP, @@ -45,7 +46,7 @@ module privmode ( logic md; // get bits of DELEG registers based on CAUSE - assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; + assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]; // PrivilegeMode FSM always_comb begin diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index dffa73202..6225b9c05 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -44,7 +44,7 @@ module trap ( input logic InstrValidM, CommittedM, output logic TrapM, RetM, output logic InterruptM, IntPendingM, - output logic [`XLEN-1:0] CauseM + output logic [`LOG_XLEN-1:0] CauseM ); logic MIntGlobalEnM, SIntGlobalEnM; @@ -94,7 +94,7 @@ module trap ( else if (IllegalInstrFaultM) CauseM = 2; else if (InstrMisalignedFaultM) CauseM = 0; else if (BreakpointFaultM) CauseM = 3; - else if (EcallFaultM) CauseM = {{(`XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW}; + else if (EcallFaultM) CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW}; else if (LoadMisalignedFaultM) CauseM = 4; else if (StoreAmoMisalignedFaultM) CauseM = 6; else if (LoadPageFaultM) CauseM = 13;