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Fixed bugs in ifu spills and missing reset on bus data register.

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This commit is contained in:
Ross Thompson 2022-02-10 18:11:57 -06:00
parent 39be787821
commit 689c32215f
2 changed files with 2 additions and 2 deletions
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2
pipelined/src/ifu/spillsupport.sv
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@ -39,7 +39,7 @@ module spillsupport (
input logic [`XLEN-1:0] PCF, input logic [`XLEN-1:0] PCF,
input logic [`XLEN-3:0] PCPlusUpperF, input logic [`XLEN-3:0] PCPlusUpperF,
input logic [`XLEN-1:0] PCNextF, input logic [`XLEN-1:0] PCNextF,
logic [31:0] InstrRawF, input logic [31:0] InstrRawF,
input logic IFUCacheBusStallF, input logic IFUCacheBusStallF,
output logic [`XLEN-1:0] PCNextFSpill, output logic [`XLEN-1:0] PCNextFSpill,
output logic [`XLEN-1:0] PCFSpill, output logic [`XLEN-1:0] PCFSpill,

2
pipelined/src/lsu/busdp.sv
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@ -76,7 +76,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)), flopenr #(`XLEN) fb(.clk, .reset, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
.d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); .d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end end