Merge branch 'main' into cache

Conflicts:
	wally-pipelined/src/ifu/ifu.sv

.gitignore

@@ -10,4 +10,5 @@ wally-pipelined/wlft*
 wlft*
 /imperas-riscv-tests/FunctionRadix_32.addr
 /imperas-riscv-tests/FunctionRadix_64.addr
+/imperas-riscv-tests/FunctionRadix.addr
 /imperas-riscv-tests/ProgramMap.txt

wally-pipelined/config/coremark_bare/wally-config.vh

@@ -97,3 +97,4 @@
 
 `define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
 `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt"
+`define BPTYPE "BPGSHARE"

wally-pipelined/src/fpu/FMA/align.sv

@@ -56,7 +56,7 @@ module align(zman, ae, aligncnt, xzero, yzero, zzero, zdenorm, proddenorm, t, bs
 	// addend on right shifts.  Handle special cases of shifting
 	// by too much.
 
-	always @(z2 or aligncnt  or zzero or xzero or yzero or zdenorm or proddenorm)
+	always @(aligncnt or zman or zdenorm)
 		begin
 
 		// Default to clearing sticky bits 
@@ -108,9 +108,9 @@ module align(zman, ae, aligncnt, xzero, yzero, zzero, zdenorm, proddenorm, t, bs
 
 		// use some behavioral code to find sticky bit.  This is really
 		// done by hardware in the shifter.
-		if (aligncnt < 0)
-			for (i=0; i<-aligncnt-52;  i = i+1)
-				bs = bs || z2[i];
+		//if (aligncnt < 0)
+		//	for (i=0; i<-aligncnt-52;  i = i+1)
+		//		bs = bs || z2[i];
 		end 
 	end
 

wally-pipelined/src/fpu/FMA/normalize.sv

@@ -61,7 +61,7 @@ logic tmp,tmp1,tmp2,tmp3;
 	// does not require a true subtraction shown in the model.
  
 	assign tmp = ($signed(ae-normcnt+2) >= $signed(-1022));
-	always @(sum or normcnt or sumshift or ae or aligncnt)
+	always @(sum or sumshift or ae or aligncnt or normcnt or bs or zexp or zdenorm)
 		begin
 		// d = aligncnt
 		// l = normcnt
@@ -106,11 +106,16 @@ logic tmp,tmp1,tmp2,tmp3;
 					v = sumshifted[161:108];
 					sticky = (|sumshifted[107:0]) | bs;
 					de0 = zexp+1;
-				end else begin
+				end else if (sumshifted[161]) begin
 					v = sumshifted[160:107];
 					sticky = (|sumshifted[106:0]) | bs;
 					//de0 = zexp-1;
 					de0 = zexp;
+				end else begin
+					v = sumshifted[159:106];
+					sticky = (|sumshifted[105:0]) | bs;
+					//de0 = zexp-1;
+					de0 = zexp-1;
 				end
 
 				resultdenorm = 0;

wally-pipelined/src/fpu/FMA/tbgen/results.dat

@@ -1,66 +1,11 @@
-3feffff77fffffff bfc0003fffffffbe 40200000fffbffff 402fc00010fc4400 401f800021f88800  Wrong 94657
-0010000000000000 7fe0000000000000 c340000000000000 c34fffffffffffff c33ffffffffffffe  Wrong 308141
 8020007ffdffffff 9beffff7fff7fffe 000ffffffff7fffe 0000000000000000 000ffffffff7fffe  Wrong zdenorm unflw 475303
-3ed03feffffffffe bf1ffbfff7fffffe 3fd000000000037e 3fdfffffff7e143e 3fcffffffefc287c  Wrong 535723
-3fb0ffffffffffff 407000000fffffbf c0f00000000800fe c0fffef00006f0fe c0effde0000de1fc  Wrong 632395
 3cafffffffffffff 3fd0000000000000 3cafffffffffffff 3c8ffffffffffffb 3cb3ffffffffffff  Wrong 706913
-37ffc3cd8026eda0 bfe0000000000000 beab43550afc66d5 bea0000000000000 beab43550afc66d5  Wrong 745179
-bfd000080000000f b7e1fbffffffffff b800200000003ffe b80f003f70203ffd b7fe007ee0407ffa  Wrong 771361
-3fd0000000000000 bfd0000000000001 3ff0000000000001 3fff000000000001 3fee000000000002  Wrong 882131
-3fd0000000000001 c000000000000000 4340000000000000 4350000000000000 433fffffffffffff  Wrong 960677
-3fdffffffffffffe c01ffffffffffffe 4340000000000000 434ffffffffffffe 433ffffffffffffc  Wrong 1105685
-c34ffefe00000000 bc4feffffffffffd c020000000000087 c02fe011017f0087 c01fc02202fe010e  Wrong 1182217
-3fe0000000000001 3fd0000000000001 bff0000000000001 bffe000000000001 bfec000000000001  Wrong 1196315
-3fefffffffffffff 4000000000000000 c340000000000000 c34fffffffffffff c33ffffffffffffe  Wrong 1274861
-3ff0000000000000 401ffffffffffffe c340000000000000 c34ffffffffffffc c33ffffffffffff8  Wrong 1419869
-3ff0000000000000 bfefffffffffffff 4340000000000000 4350000000000000 433fffffffffffff  Wrong 1444037
-3fffffffffffffff c000000000000001 4340000000000000 434ffffffffffffe 433ffffffffffffc  Wrong 1589045
 bfbfffff007fffff 000fffffffffffff 000bffffffc00000 0015000007dc0000 000a00000fb80000  Wrong ydenorm zdenorm 1675647
-4000000000000001 3fefffffffffffff c340000000000000 c34fffffffffffff c33ffffffffffffe  Wrong 1758221
-400ffffffffffffe 4000000000000001 c340000000000000 c34ffffffffffffc c33ffffffffffff8  Wrong 1903229
-400ffffffffffffe bfd0000000000000 4340000000000000 4350000000000000 433fffffffffffff  Wrong 1927397
-4010000000000000 bca0000000000000 3ff0000000000001 3fffffffffffffff 3feffffffffffffe  Wrong 1993859
-4010000000000001 bfeffffffffffffe 4340000000000000 434ffffffffffffe 433ffffffffffffc  Wrong 2072405
-401ffffffffffffe c00fffffffffffff 4340000000000000 434ffffffffffff0 433fffffffffffe0  Wrong 2217413
 00114508bde544e1 3caffffffffffffe 800010000003fffe 801008000001fffe 800010000003fffd  Wrong zdenorm 2310057
-3f8b17d321454789 3fd7ffffffffff7f bfe000080ffffffe bfefd764534e1814 bfdfaec8a69c3027  Wrong 2318113
-ca7fff0000000fff 3ca62fd739ece5a5 48000000003f0000 480fff4e87112667 47fffe9d0e224cce  Wrong 2348323
-c34ffffffffffc00 bbe000000000027f 43dfffffeffffbff 43d487c0c983e604 43dfffffeffffbff  Wrong 2469163
 800ffffffdffffff bfcffe00003ffffe 800ffff01ffffffe 80160018103bfbff 800c00302077f7ff  Wrong xdenorm zdenorm 2475205
-401ffffffbfffbff 3fbfffef80000000 c00000400000007f c0080044210000fb bff00088420001f6  Wrong 2493331
-7feffffffffffffe 001fffffffffffff c340000000000000 c34ffffffffffffc c33ffffffffffff8  Wrong 2724941
-bfdfffe00fffffff 3fccf2165e6eea40 3ff0000023fffffe 3ffe30e08c52e68e 3fec61c118a5cd1c  Wrong 2880019
-c090003ffffffffb 3fefffffffffffff 41d00000003ffe00 41dfffff003bfe00 41cffffe0077fc00  Wrong 3222399
-3fcffffffff7ff7f bff4691aa0d59fcd 40600007ffe00000 406ff5d3728f97bd 405feba6e51f2f7b  Wrong 3260665
-8010000000000000 7fefffffffffffff 4340000000000000 434ffffffffffffe 433ffffffffffffc  Wrong 3377477
-3fbfffffefbfffff 3f600001ff7ffffe bfc000fffffffffe bfcff8ffff044fff bfbff1fffe089ffd  Wrong 3417757
 bcafffffffffffff 3fd0000000000001 bcafffffffffffff bc8ffffffffffffd bcb4000000000000  Wrong 3776249
-bcafffffffffffff 3ff0000000000001 3ff0000000000001 4000000000000000 3ff0000000000000  Wrong 3782291
 bfc0000000800008 43d0001000000002 c3cffffbffff8000 c3a00000007e008a c3d20000000fc011  Wrong 3804445
-bcaffffffffffffe 4340000000000000 4340000000000000 434fffffffffffff 433ffffffffffffe  Wrong 3860837
-bfd0000000000000 bfdfffffffffffff bff0000000000001 bffe000000000001 bfec000000000002  Wrong 3951467
-bfd0000000000001 c000000000000001 c340000000000000 c350000000000000 c33fffffffffffff  Wrong 4030013
-3f3e007ffffffffe bfe0000000000000 3ff0000000001f7f 3fffff0ffc001f7f 3feffe1ff8003efe  Wrong 4092447
-c070000000024000 c01ffffffffffffe c1e0000004003ffe c1efffff04003ffe c1dffffe08007ffc  Wrong 4104531
-4bb000040000003e 318ffffffffff7ff bfe0000000000017 bfeffffffffff817 bfdffffffffff02e  Wrong 4209259
-bfe0000000000001 3fdffffffffffffe 3ff0000000000001 3ffc000000000001 3fe8000000000002  Wrong 4265651
 bfefffffffffffff 3fefffffffffffff bff0000000000001 b950000000000000 c000000000000000  Wrong 4338155
-bfefffffffffffff 400fffffffffffff 4340000000000000 434ffffffffffffe 433ffffffffffffc  Wrong 4344197
-bff0000000000000 bfeffffffffffffe c340000000000000 c350000000000000 c33fffffffffffff  Wrong 4513373
-bfffffffffffffff c00fffffffffffff c340000000000000 c34ffffffffffffc c33ffffffffffff8  Wrong 4658381
-400ffffffffffd7f c000000000000001 c013fffffdffffff c027fffffffffec1 c029fffffefffec0  Wrong 4726857
-c000000000000000 3ca0000000000001 3ff0000000000001 4000000000000000 3ff0000000000000  Wrong 4749011
-3fe0000000000027 bfffffffffffff77 40600001ffffdfff 406fe001ffffdfff 405fc003ffffbffe  Wrong 4777207
-c000000000000001 3ff0000000000000 4340000000000000 434fffffffffffff 433ffffffffffffe  Wrong 4827557
-c00ffffffffffffe 400ffffffffffffe 4340000000000000 434ffffffffffff8 433ffffffffffff0  Wrong 4972565
-c00ffffffffffffe bfd0000000000001 c340000000000000 c350000000000000 c33fffffffffffff  Wrong 4996733
-c010000000000000 bca0000000000001 bff0000000000001 bfffffffffffffff bfeffffffffffffe  Wrong 5063195
-c010000000000001 bff0000000000000 c340000000000000 c34ffffffffffffe c33ffffffffffffc  Wrong 5141741
 37ea3353806450ba bffffffffffffffe b803fffffffff7ff b7c19a9c032205b3 b8108cd4e019102e  Wrong 5143755
-bf1fffffe0ffffff bfcffffffbffff00 bf9000001ffffc00 bf9ff8002008bc00 bf8ff00040117800  Wrong 5236399
 8010000000803fff 3ff0000000000001 000fffe07fffffff fff0000000000000 8000001f80804001  Wrong zdenorm w=-inf 5246469
-41cdffffc0000000 bfbff87ffffffffe 41c000000080ffff 41cc40e1087f1fff 41b881c210fe3ffe  Wrong 5278693
-c01ffffffffffffe c00ffffffffffffe c340000000000000 c34ffffffffffff0 c33fffffffffffe0  Wrong 5286749
-ffe0000000000001 0000000000000001 4340000000000000 4350000000000000 4340000000000000  Wrong ydenorm 5649269
 b7fffff80000001f 001ffffffffffffe 800fffffffff07ff 8000000000000000 800fffffffff07ff  Wrong w=-zero zdenorm unflw 5723787
-bfcc03a8225fe071 ffeffffffffffffe ffe0000420000000 ffe8ff1a176807e4 ffd1fe342ed00fc8  Wrong 5923173

wally-pipelined/src/fpu/FMA/tbgen/tb.c

@@ -26,7 +26,7 @@ void main() {
 		char ans[81];
 		char flags[3];
 		int rn,rz,rm,rp;
-		long stop = 6015817;
+		long stop = 5723787;
 		int debug = 1;
 		//my_string = (char *) malloc (nbytes + 1);
 		//bytes_read = getline (&my_string, &nbytes, stdin);

wally-pipelined/src/privileged/csri.sv

@@ -49,7 +49,7 @@ module csri #(parameter
   // assumes no N-mode user interrupts
 
   always_comb begin
-    IntInM     = 0;
+    IntInM     = 0; // *** does this really work
     IntInM[11] = ExtIntM & ~MIDELEG_REGW[9];   // MEIP
     IntInM[9]  = ExtIntM &  MIDELEG_REGW[9];   // SEIP
     IntInM[7]  = TimerIntM & ~MIDELEG_REGW[5]; // MTIP

wally-pipelined/src/uncore/gpio.sv

@@ -33,6 +33,8 @@ module gpio (
   input  logic [7:0]       HADDR, 
   input  logic [`XLEN-1:0] HWDATA,
   input  logic             HWRITE,
+  input  logic             HREADY,
+  input  logic [1:0]       HTRANS,
   output logic [`XLEN-1:0] HREADGPIO,
   output logic             HRESPGPIO, HREADYGPIO,
   input  logic [31:0]      GPIOPinsIn,
@@ -40,15 +42,19 @@ module gpio (
 
   logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL;
  
-  logic [7:0] entry;
-  logic            memread, memwrite;
+  logic [7:0] entry, HADDRd;
+  logic            initTrans, memread, memwrite;
 
-  assign memread  = HSELGPIO & ~HWRITE;
-  assign memwrite = HSELGPIO & HWRITE;
+  assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00);
+
+  // Control Signals
+  flopenr #(1)  memreadreg(HCLK, ~HRESETn, initTrans, ~HWRITE, memread);
+  flopenr #(1) memwritereg(HCLK, ~HRESETn, initTrans, HWRITE, memwrite);
+  flopenr #(8)    haddrreg(HCLK, ~HRESETn, initTrans, HADDR, HADDRd);
+
+  // Response Signals
   assign HRESPGPIO = 0; // OK
-  always_ff @(posedge HCLK) // delay response to data cycle
-    HREADYGPIO <= memread | memwrite;
-//  assign HREADYGPIO = 1; // Respond immediately
+  assign HREADYGPIO = 1; // never ask for wait states
   
   // word aligned reads
   generate
@@ -103,7 +109,6 @@ module gpio (
         if (~HRESETn) begin
           INPUT_EN <= 0;
           OUTPUT_EN <= 0;
-          //OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control)
         end else if (memwrite) begin
           if (entry == 8'h04) INPUT_EN <= HWDATA;
           if (entry == 8'h08) OUTPUT_EN <= HWDATA;

wally-pipelined/testbench/testbench-coremark_bare.sv

@@ -74,7 +74,7 @@ module testbench();
       memfilename = tests[0];
       $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.uncore.dtim.RAM);
-      for(j=268437829; j < 268566528; j = j+1)
+      for(j=268437702; j < 268566528; j = j+1)
         dut.uncore.dtim.RAM[j] = 64'b0;
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";

wally-pipelined/testbench/testbench-privileged.sv

@@ -40,7 +40,7 @@ module testbench();
   logic [`XLEN-1:0] meminit;
 
   string tests[] = '{                 
-    "privileged/WALLY-CAUSE-64", "0"
+    "rv64p/WALLY-CAUSE", "0"
   };
 
   logic [`AHBW-1:0] HRDATAEXT;

wally-pipelined/testgen/privileged/README.md

@@ -0,0 +1,15 @@
+# Privileged Test Generators
+
+Create a test generator in this folder with the name testgen-NAME.py. Then, to generate and compile these tests, use
+
+```bash
+sh run.sh NAME
+```
+
+For example, for `testgen-CAUSE.py`, we would run `sh run.sh CAUSE`.
+
+Provide -sim as the second argument to simulate the compiled tests using wally.
+
+```bash
+sh run.sh NAME -sim
+```

wally-pipelined/testgen/privileged/run.sh

@@ -7,8 +7,11 @@ then
 	python3 "testgen-$1.py"
 	printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n"
 
-	cd ~/riscv-wally/imperas-riscv-tests
-	make privileged
+	if [[ "$2" != "-nosim" ]]
+	then
+		cd ~/riscv-wally/imperas-riscv-tests
+		make privileged
+	fi
 fi
 
 if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
@@ -18,5 +21,5 @@ then
 	vsim -do wally-privileged.do -c
 fi
 
-cd ~/riscv-wally
+cd ~/riscv-wally/wally-pipelined
 printf "\n\n\n#####\nDone!\n#####\n\n"

wally-pipelined/testgen/privileged/testgen-CAUSE.py

@@ -61,10 +61,16 @@ def writeVectors(storecmd):
 
   #lines = 
 
+
+  # https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html
+
   lines = f"""
   j _setup
   csrrs x31, mcause, x0
-  ecall
+  csrrs x30, mepc, x0
+  addi x30, x30, 0x100
+  csrrw x0, mepc, x30
+  mret
 
   _setup:
   li x2, 0x80000004
@@ -73,23 +79,25 @@ def writeVectors(storecmd):
   """
   f.write(lines)
 
-  # User Software Interrupt
-  write(f"""
-    li x3, 0x8000000
-    {storecmd} x2, 0(x3)
-  """, storecmd, True, 0, "u")
+  # # User Software Interrupt
+  # write(f"""
+  #   li x3, 0x8000000
+  #   {storecmd} x2, 0(x3)
+  # """, storecmd, True, 0, "u")
 
-  # Supervisor Software Interrupt
-  write(f"""
-    li x3, 0x8000000
-    {storecmd} x2, 0(x3)
-  """, storecmd, True, 0, "s")
+  # # A supervisor-level software interrupt is triggered on the current hart by writing 1 to its supervisor software interrupt-pending (SSIP) bit in the sip register.
+  # # page 58 of priv spec
+  # # Supervisor Software Interrupt
+  # write(f"""
+  #   li x3, 0x8000000
+  #   {storecmd} x2, 0(x3)
+  # """, storecmd, True, 0, "s")
 
-  # Machine Software Interrupt
-  write(f"""
-    li x3, 0x8000000
-    {storecmd} x2, 0(x3)
-  """, storecmd, True, 3)
+  # # Machine Software Interrupt
+  # write(f"""
+  #   li x3, 0x8000000
+  #   {storecmd} x2, 0(x3)
+  # """, storecmd, True, 3)
 
   # User Timer Interrupt
   #write(f"""
@@ -122,8 +130,9 @@ def writeVectors(storecmd):
   # Not possible in machine mode, because we can access all memory
 
   # Illegal Instruction
+  # . fill 1, 2, 0 outputs all 0s
   write(f"""
-    .data 00000000
+      .fill 1, 2, 0
   """, storecmd, False, 2)
 
   # Breakpoint
@@ -212,7 +221,7 @@ def write(lines, storecmd, interrupt, code, mode = "m"):
 #  'Load page fault': (0, '13'),
 #  'Store/AMO page fault': (0, '15'),
 # }
-author = "dottolia@hmc.edu"
+author = "Domenico Ottolia (dottolia@hmc.edu)"
 xlens = [32, 64]
 numrand = 60;
 
@@ -231,8 +240,8 @@ for xlen in xlens:
     storecmd = "sd"
     wordsize = 8
 
-  imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/privileged/"
-  basename = "WALLY-CAUSE-" + str(xlen)
+  imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/"""
+  basename = "WALLY-CAUSE"
   fname = imperaspath + "src/" + basename + ".S"
   refname = imperaspath + "references/" + basename + ".reference_output"
   testnum = 0

wally-pipelined/testgen/privileged/testgen-RET.py

@@ -0,0 +1,157 @@
+#!/usr/bin/python3
+##################################
+# testgen-CAUSE.py
+#
+# dottolia@hmc.edu 16 Mar 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from enum import Enum
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+# def computeExpected(a, b, test):
+#   if (test == "ADD"):
+#     return a + b
+#   elif (test == "SUB"):
+#     return a - b
+#   else:
+#     die("bad test name ", test)
+#   #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,30)
+  reg2 = randint(1,30)
+  reg3 = randint(1,30)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVectors(storecmd):  
+  global testnum
+  reg1, reg2, reg3 = randRegs()
+
+  # t5 gets written with mtvec?
+
+  # lines = f"""
+
+  # li x{reg1}, 0
+  # csrwi mtvec, 80002000
+  # .data 00000000
+  # j _done{testnum}
+
+  # _trap{testnum}:
+  # csrrs x{reg1}, mcause, x0
+  # ecall
+
+  # _done{testnum}:
+  # add x0, x0, x0
+  # """
+
+  #lines = 
+
+
+  # https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html
+
+  lines = f"""
+  li x1, 100
+  li x2, 200
+  add x3, x1, x2
+  add x6, x3, x3
+
+  """
+  f.write(lines)
+
+  expected = 600
+
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+
+##################################
+# main body
+##################################
+
+author = "Domenico Ottolia (dottolia@hmc.edu)"
+xlens = [32, 64]
+numrand = 60;
+
+# setup
+seed(0xC395D19B9173AD42) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/"""
+  basename = "WALLY-RET"
+  fname = imperaspath + "src/" + basename + ".S"
+  refname = imperaspath + "references/" + basename + ".reference_output"
+  testnum = 0
+
+  # print custom header part
+  f = open(fname, "w")
+  r = open(refname, "w")
+  line = "///////////////////////////////////////////\n"
+  f.write(line)
+  lines="// "+fname+ "\n// " + author + "\n"
+  f.write(lines)
+  line ="// Created " + str(datetime.now()) 
+  f.write(line)
+
+  # insert generic header
+  # h = open("../testgen_header.S", "r")
+  # for line in h:  
+  #   f.write(line)
+
+  # print directed and random test vectors
+
+  h = open("../testgen_header.S", "r")
+  for line in h:  
+    f.write(line)
+
+  writeVectors(storecmd)
+
+  h = open("../testgen_footer.S", "r")
+  for line in h:  
+    f.write(line)
+
+  # Finish
+  lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+  lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  f.write(lines)
+
+
+  # print footer
+  # h = open("../testgen_footer.S", "r")
+  # for line in h:  
+  #   f.write(line)
+
+  # Finish
+  # lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+  # lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  # f.write(lines)
+  f.close()
+  r.close()
+