Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230

pipelined/src/cache/cache.sv

@@ -43,6 +43,9 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
   input logic [`PA_BITS-1:0]  PAdr, // physical address
   input logic [(`XLEN-1)/8:0] ByteMask,
   input logic [`XLEN-1:0]     FinalWriteData,
+  input logic [`FLEN-1:0]     FWriteDataM,
+  input logic                        FLoad2,
+  input logic                 FpLoadStoreM,
   output logic                CacheCommitted,
   output logic                CacheStall,
    // to performance counters to cpu
@@ -120,7 +123,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
   cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) 
-    CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask,
+    CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, .FLoad2,
     .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
     .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, 
     .Invalidate(InvalidateCacheM));
@@ -159,8 +162,12 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Path: Write data and address. Muxes between writes from bus and writes from CPU.
   /////////////////////////////////////////////////////////////////////////////////////////////
-  mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
+  if (`LLEN>`XLEN)
-		.d1(CacheBusWriteData),	.s(SetValid), .y(CacheWriteData));
+    mux3 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
+      .d1({WORDSPERLINE/2{FWriteDataM}}),	.d2(CacheBusWriteData),	.s({SetValid,FpLoadStoreM&~SetValid}), .y(CacheWriteData));
+  else
+    mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
+      .d1(CacheBusWriteData),	.s(SetValid), .y(CacheWriteData));
   mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 		.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 		.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),

pipelined/src/cache/cacheway.sv

@@ -38,6 +38,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   input logic [$clog2(NUMLINES)-1:0] RAdr,
   input logic [`PA_BITS-1:0]         PAdr,
   input logic [LINELEN-1:0]          CacheWriteData,
+  input logic                        FLoad2,
   input logic                        SetValidWay,
   input logic                        ClearValidWay,
   input logic                        SetDirtyWay,
@@ -74,8 +75,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Enable demux
   /////////////////////////////////////////////////////////////////////////////////////////////
-  onehotdecoder #(LOGWPL) adrdec(
+  if(`LLEN>`XLEN)begin 
-    .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
+    logic [2**LOGWPL-1:0] MemPAdrDecodedtmp;
+    onehotdecoder #(LOGWPL) adrdec(
+      .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedtmp));
+    assign MemPAdrDecoded = MemPAdrDecodedtmp|{MemPAdrDecodedtmp[2**LOGWPL-2:0]&{2**LOGWPL-1{FLoad2}}, 1'b0};
+  end else
+    onehotdecoder #(LOGWPL) adrdec(
+      .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
   // If writing the whole line set all write enables to 1, else only set the correct word.
   assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
   assign FinalByteMask = SetValidWay ? '1 : ByteMask; // OR

pipelined/src/fpu/fctrl.sv

@@ -33,8 +33,8 @@ module fctrl (
                     default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
                   endcase
       7'b0100111: case(Funct3D)
-                    3'b010:  ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsw
+                    3'b010:  ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsw
-                    3'b011:  ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsd
+                    3'b011:  ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsd
                     default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction
                   endcase
       7'b1000011:   ControlsD = `FCTRLW'b1_0_01_10_000_0_0; // fmadd
@@ -121,7 +121,7 @@ module fctrl (
       assign FmtD = 0;
     else if (`FPSIZES == 2)begin
       logic [1:0] FmtTmp;
-      assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
+      assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
       assign FmtD = (`FMT == FmtTmp);
     end
     else if (`FPSIZES == 3|`FPSIZES == 4)

pipelined/src/fpu/fpu.sv

@@ -41,10 +41,12 @@ module fpu (
   input logic [4:0] 	   RdM, RdW, // which FP register to write to (from IEU)
   input logic [1:0]        STATUS_FS, // Is floating-point enabled?
   output logic 		   FRegWriteM, // FP register write enable
-  output logic 		   FpLoadM, // Fp load instruction?
+  output logic 		   FpLoadStoreM, // Fp load instruction?
+  output logic              FLoad2,
   output logic 		   FStallD, // Stall the decode stage
   output logic 		   FWriteIntE, // integer register write enables
   output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory
+  output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory
   output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
   output logic [`XLEN-1:0] FCvtIntResW, // data to be written to integer register
   output logic [1:0]       FResSelW,
@@ -292,8 +294,19 @@ module fpu (
    // data to be stored in memory - to IEU
    //    - FP uses NaN-blocking format
    //        - if there are any unsused bits the most significant bits are filled with 1s
-   if (`FLEN>`XLEN) assign FWriteDataE = FSrcYE[`XLEN-1:0]; 
+   if (`LLEN==`XLEN) begin
-   else assign FWriteDataE = {{`XLEN-`FLEN{FSrcYE[`FLEN-1]}}, FSrcYE}; 
+      assign FWriteDataE = FSrcYE[`XLEN-1:0]; 
+   end else begin
+      logic [`FLEN-1:0] FWriteDataE;
+      if(`FMTBITS == 2) assign FLoad2 = FmtM == `FMT;
+      else assign FLoad2 = FmtM;
+
+      if (`FPSIZES==1) assign FWriteDataE = FSrcYE;
+      else if (`FPSIZES==2) assign FWriteDataE = FmtE ? FSrcYE : {2{FSrcYE[`LEN1-1:0]}};
+      else assign FWriteDataE = FmtE == `FMT ? FSrcYE : {2{FSrcYE[`LEN1-1:0]}};
+
+      flopenrc #(`FLEN) EMWriteDataReg (clk, reset, FlushM, ~StallM, FWriteDataE, FWriteDataM);
+   end
 
    // NaN Block SrcA
    generate
@@ -311,7 +324,7 @@ module fpu (
    assign PreNVE = CmpNVE&(FOpCtrlE[2]|FWriteIntE);
 
    // select the result that may be written to the integer register - to IEU
-   if (`FLEN>`XLEN) 
+   if (`FLEN>`XLEN)
       assign IntSrcXE = FSrcXE[`XLEN-1:0];
    else 
       assign IntSrcXE = {{`XLEN-`FLEN{FSrcXE[`FLEN-1:0]}}, FSrcXE};
@@ -356,7 +369,7 @@ module fpu (
    //          |||         |||
    //////////////////////////////////////////////////////////////////////////////////////////
 
-   assign FpLoadM = FResSelM[1];
+   assign FpLoadStoreM = FResSelM[1];
 
    postprocess postprocess(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .ProdExpM, .EarlyTermShiftDiv2M,
                            .AddendStickyM, .KillProdM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .Quot,

pipelined/src/ieu/datapath.sv

@@ -124,12 +124,18 @@ module datapath (
   flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
 
   // floating point interactions: fcvt, fp stores
-  if (`F_SUPPORTED) begin:fpmux
+  if (`F_SUPPORTED&(`LLEN>`XLEN)) begin:fpmux
+    logic [`XLEN-1:0] IFCvtResultW;
+    mux2  #(`XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
+    assign WriteDataE = ForwardedSrcBE;
+    mux2  #(`XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW);
+    mux5  #(`XLEN)  resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); 
+  end else if (`F_SUPPORTED) begin:fpmux
     logic [`XLEN-1:0] IFCvtResultW;
     mux2  #(`XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
     mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
     mux2  #(`XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW);
-    mux5  #(`XLEN)    resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW);	 
+    mux5  #(`XLEN)  resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); 
   end else begin:fpmux
     assign IFResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE;
     mux5  #(`XLEN)    resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW);	 

pipelined/src/ifu/ifu.sv

@@ -227,7 +227,7 @@ module ifu (
       icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0),
              .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
-             .CacheFetchLine(ICacheFetchLine),
+             .CacheFetchLine(ICacheFetchLine), .FWriteDataM(), .FpLoadStoreM(), .FLoad2(),
              .CacheWriteLine(), .ReadDataWord(FinalInstrRawF),
              .Cacheable(CacheableF),
              .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),

pipelined/src/lsu/lsu.sv

@@ -57,7 +57,9 @@ module lsu (
    input logic              BigEndianM,
    input logic              sfencevmaM,
    // fpu
-   input logic              FpLoadM,
+   input logic [`FLEN-1:0]  FWriteDataM,
+   input logic              FLoad2,
+   input logic              FpLoadStoreM,
    // faults
    output logic             LoadPageFaultM, StoreAmoPageFaultM,
    output logic             LoadMisalignedFaultM, LoadAccessFaultM,
@@ -235,7 +237,7 @@ module lsu (
               .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
         .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM),
         .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), 
-        .ByteMask(ByteMaskM), .WordCount,
+        .ByteMask(ByteMaskM), .WordCount, .FpLoadStoreM, .FWriteDataM, .FLoad2,
         .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
         .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
         .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM), 
@@ -269,7 +271,7 @@ module lsu (
   subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
     .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM);
   subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
-		.FpLoadM, .Funct3M(LSUFunct3M), .ReadDataM);
+		.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // MW Pipeline Register

pipelined/src/lsu/subwordread.sv

@@ -35,7 +35,7 @@ module subwordread
    input logic [`LLEN-1:0] 	ReadDataWordMuxM,
    input logic [2:0] 		LSUPAdrM,
    input logic [2:0] 		Funct3M,
-   input logic          FpLoadM, 
+   input logic          FpLoadStoreM, 
    output logic [`LLEN-1:0] ReadDataM
    );
 
@@ -83,16 +83,16 @@ module subwordread
     case(Funct3M)
       3'b000:  ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM};                              // lb
       3'b001:  if(`ZFH_SUPPORTED) 
-                    ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadM}}, HalfwordM[15:0]}; // lh/flh
+                    ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
                else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]};         // lh 
       3'b010:  if(`F_SUPPORTED) 
-                    ReadDataM = {{`LLEN-32{WordM[31]|FpLoadM}}, WordM[31:0]};         // lw/flw
+                    ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};         // lw/flw
                else ReadDataM = {{`LLEN-32{WordM[31]}}, WordM[31:0]};                 // lw
       3'b011:  if(`D_SUPPORTED) 
-                    ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadM}}, DblWordM[63:0]};   // ld/fld
+                    ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]};   // ld/fld
                else ReadDataM = {{`LLEN-64{DblWordM[63]}}, DblWordM[63:0]};           // ld/fld
       3'b100:    if(`Q_SUPPORTED) 
-                    ReadDataM = FpLoadM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq
+                    ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq
                  else 
                     ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]};    // lbu
       3'b101:  ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]};   // lhu
@@ -122,10 +122,10 @@ module subwordread
     case(Funct3M)
       3'b000:  ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM};                              // lb
       3'b001:  if(`ZFH_SUPPORTED) 
-                    ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadM}}, HalfwordM[15:0]}; // lh/flh
+                    ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
                else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]};         // lh 
       3'b010:  if(`F_SUPPORTED) 
-                    ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadM}}, ReadDataWordMuxM[31:0]};         // lw/flw
+                    ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]};         // lw/flw
                else ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]};                 // lw
       3'b011:  ReadDataM = ReadDataWordMuxM;                      // fld
       3'b100:  ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]};         // lbu

pipelined/src/wally/wallypipelinedcore.sv

@@ -92,13 +92,15 @@ module wallypipelinedcore (
   logic             FStallD;
   logic             FWriteIntE;
   logic [`XLEN-1:0]         FWriteDataE;
+  logic                     FLoad2;
+  logic [`FLEN-1:0]         FWriteDataM;
   logic [`XLEN-1:0]         FIntResM;  
   logic [`XLEN-1:0]         FCvtIntResW;  
   logic             FDivBusyE;
   logic             IllegalFPUInstrD, IllegalFPUInstrE;
   logic             FRegWriteM;
   logic             FPUStallD;
-  logic             FpLoadM;
+  logic             FpLoadStoreM;
   logic [1:0]       FResSelW;
   logic [4:0]             SetFflagsM;
 
@@ -253,7 +255,8 @@ module wallypipelinedcore (
   .AtomicM, .TrapM,
   .CommittedM, .DCacheMiss, .DCacheAccess,
   .SquashSCW,            
-  .FpLoadM,
+  .FpLoadStoreM,
+  .FWriteDataM, .FLoad2,
   //.DataMisalignedM(DataMisalignedM),
   .IEUAdrE, .IEUAdrM, .WriteDataE,
   .ReadDataW, .FlushDCacheM,
@@ -391,10 +394,12 @@ module wallypipelinedcore (
          .RdM, .RdW, // which FP register to write to (from IEU)
          .STATUS_FS, // is floating-point enabled?
          .FRegWriteM, // FP register write enable
-         .FpLoadM,
+         .FpLoadStoreM,
+         .FLoad2,
          .FStallD, // Stall the decode stage
          .FWriteIntE, // integer register write enable
          .FWriteDataE, // Data to be written to memory
+         .FWriteDataM, // Data to be written to memory
          .FIntResM, // data to be written to integer register
          .FCvtIntResW, // fp -> int conversion result to be stored in int register
          .FResSelW,   // fpu result selection

pipelined/srt/srt-radix4.sv

@@ -143,12 +143,13 @@ module earlytermination(
  
    logic [$clog2(`DIVLEN/2+3)-1:0]  Count;
    logic WZero;
+   logic [`DIVLEN+3:0] W;
 
-   assign WZero = (WS+WC == 0)|XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE; //*** temporary
+  assign WZero = ((WS^WC)=={WS[`DIVLEN+2:0]|WC[`DIVLEN+2:0], 1'b0})|XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE;
-   // *** rather than Counting should just be able to check if one of the two msbs of the quotent is 1 then stop???
   assign DivDone = (DivStickyE | WZero);
   assign DivStickyE = ~|Count;
-  assign DivNegStickyE = $signed(WS+WC) < 0;
+  assign W = WC+WS;
+  assign DivNegStickyE = W[`DIVLEN+3]; //*** is there a better way to do this???
   assign EarlyTermShiftDiv2E = Count;
   // +1 for setup
   // `DIVLEN/2 to get required number of bits

pipelined/testbench/testbench.sv

@@ -68,6 +68,7 @@ logic [3:0] dummy;
   integer   	ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
 
   logic 	    DCacheFlushDone, DCacheFlushStart;
+  logic riscofTest; 
     
   flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
@@ -174,6 +175,8 @@ logic [3:0] dummy;
       totalerrors = 0;
       testadr = 0;
       testadrNoBase = 0;
+      // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and  tests[0] == "2" refers to WallyRiscvArchTests 
+      riscofTest = tests[0] == "1"; // | tests[0] == "2"; 
       // fill memory with defined values to reduce Xs in simulation
       // Quick note the memory will need to be initialized.  The C library does not
       //  guarantee the  initialized reads.  For example a strcmp can read 6 byte
@@ -250,8 +253,7 @@ logic [3:0] dummy;
           for(i=0; i<SIGNATURESIZE; i=i+1) begin
             sig32[i] = 'bx;
           end
-          // riscof tests have a different signature, tests[0] == "1" refers to RISCVARCHTESTs
+          if (riscofTest) signame = {pathname, tests[test], "erence-sail_c_simulator.signature"};
-          if (tests[0] == "1") signame = {pathname, tests[test], "erence-sail_c_simulator.signature"};
           else signame = {pathname, tests[test], ".signature.output"};
           // read signature, reformat in 64 bits if necessary
           $readmemh(signame, sig32);

pipelined/testbench/tests.vh

@@ -33,8 +33,8 @@
 
 string tvpaths[] = '{
     "../../addins/imperas-riscv-tests/work/",
-    "../../tests/riscof/work/",
+    "../../tests/riscof/work/riscv-arch-test/",
-    "../../tests/wally-riscv-arch-test/work/",
+    "../../tests/wally-riscv-arch-test/work/", //"../../tests/riscof/work/wally-riscv-arch-test/",
     "../../tests/imperas-riscv-tests/work/",
     "../../benchmarks/riscv-coremark/work/",
     "../../addins/embench-iot/"
@@ -1607,3 +1607,89 @@ string wally32i[] = '{
     // "rv32i_m/privilege/WALLY-uart-01"
  };
 
+
+// riscof test paths, to replace existing paths once riscof flow is working
+// string wally64a[] = '{
+//     `WALLYTEST,
+//     "rv64i_m/privilege/src/WALLY-amo.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-lrsc.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S/ref/Ref"
+//   };
+
+//     string wally32a[] = '{
+//     `WALLYTEST,
+//     "rv32i_m/privilege/src/WALLY-amo.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-lrsc.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S/ref/Ref"
+
+//   };
+
+//   string wally64i[] = '{
+//     `WALLYTEST,
+//     "rv64i_m/I/src/WALLY-ADD.S/ref/Ref",
+//     "rv64i_m/I/src/WALLY-SLT.S/ref/Ref",
+//     "rv64i_m/I/src/WALLY-SLTU.S/ref/Ref",
+//     "rv64i_m/I/src/WALLY-SUB.S/ref/Ref",
+//     "rv64i_m/I/src/WALLY-XOR.S/ref/Ref"
+//  };
+
+//  string wally64priv[] = '{
+//     `WALLYTEST,
+//     "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-mie-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-minfo-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-misa-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-mmu-sv39.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-mmu-sv48.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-mtvec-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-pma.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-pmp.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-sie-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-status-mie-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-status-sie-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-status-tw-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-stvec-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-trap-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-trap-s-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-trap-sret-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-trap-u-01.S/ref/Ref",
+//     "rv64i_m/privilege/src/WALLY-wfi-01.S/ref/Ref"
+//  };
+
+//  string wally64periph[] = '{
+//     `WALLYTEST,
+//     "rv64i_m/privilege/src/WALLY-periph.S/ref/Ref"
+//  };
+
+//  string wally32i[] = '{
+//     `WALLYTEST,
+//     "rv32i_m/I/src/WALLY-ADD.S/ref/Ref",
+//     "rv32i_m/I/src/WALLY-SLT.S/ref/Ref",
+//     "rv32i_m/I/src/WALLY-SLTU.S/ref/Ref",
+//     "rv32i_m/I/src/WALLY-SUB.S/ref/Ref",
+//     "rv32i_m/I/src/WALLY-XOR.S/ref/Ref" 
+//  };
+
+//  string wally32priv[] = '{
+//     `WALLYTEST,
+//     "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-mie-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-minfo-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-misa-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-mmu-sv32.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-mtvec-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-pma.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-pmp.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-sie-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-status-mie-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-status-sie-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-status-tw-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-stvec-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-trap-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-trap-s-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-trap-sret-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-trap-u-01.S/ref/Ref",
+//     "rv32i_m/privilege/src/WALLY-wfi-01.S/ref/Ref"
+//  };

synthDC/Makefile

@@ -5,8 +5,8 @@ NAME := synth
 
 # defaults
 export DESIGN ?= wallypipelinedcore
-export FREQ ?= 4000
+export FREQ ?= 3402
-export CONFIG ?= rv64gc
+export CONFIG ?= rv32e
 # sky130 and sky90 presently supported
 export TECH ?= tsmc28
 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient
@@ -126,6 +126,8 @@ clean:
 	rm -f command.log
 	rm -f filenames*.log
 	rm -f power.saif
+	rm -f Synopsys_stack_trace_*.txt
+	rm -f crte_*.txt
 
 
 

synthDC/extractSummary.py

@@ -7,6 +7,7 @@ import subprocess
 from matplotlib.cbook import flatten
 import matplotlib.pyplot as plt
 import matplotlib.lines as lines
+from wallySynth import testFreq
 
 
 def synthsintocsv():
@@ -26,7 +27,7 @@ def synthsintocsv():
     writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area'])
 
     for oneSynth in allSynths:
-        descrip = specReg.findall(oneSynth)
+        descrip = specReg.findall(oneSynth) #[30:]
         width = descrip[2][:4]
         config = descrip[2][4:]
         if descrip[3][-2:] == 'nm':
@@ -46,7 +47,7 @@ def synthsintocsv():
                 nums = [float(m) for m in nums]
                 metrics += nums
             except: 
-                print(config + tech + freq + " doesn't have reports")
+                print(width + config + tech + '_' + freq + " doesn't have reports")
         if metrics == []:
             pass
         else:
@@ -56,7 +57,7 @@ def synthsintocsv():
     file.close()
 
 def synthsfromcsv(filename):
-    Synth = namedtuple("Synth", " width config special tech freq delay area")
+    Synth = namedtuple("Synth", "width config special tech freq delay area")
     with open(filename, newline='') as csvfile:
         csvreader = csv.reader(csvfile)
         global allSynths
@@ -110,23 +111,26 @@ def freqPlot(tech, width, config):
     plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png')
     # plt.show()
 
-def areaDelay(width, tech, freq, config=None, special=None):
+def areaDelay(tech, freq, width=None, config=None, special=None):
     delays, areas, labels = ([] for i in range(3))
 
     for oneSynth in allSynths:
-        if (width == oneSynth.width) & (tech == oneSynth.tech) & (freq == oneSynth.freq):
+        if (width==None) or (width == oneSynth.width):
-            if (special != None) & (oneSynth.special == special):
+            if (tech == oneSynth.tech) & (freq == oneSynth.freq):
-                delays += [oneSynth.delay]
+                if (special != None) & (oneSynth.special == special):
-                areas += [oneSynth.area]
+                    delays += [oneSynth.delay]
-                labels += [oneSynth.config]
+                    areas += [oneSynth.area]
-            elif (config != None) & (oneSynth.config == config):
+                    labels += [oneSynth.width + oneSynth.config]
-                delays += [oneSynth.delay]
+                elif (config != None) & (oneSynth.config == config):
-                areas += [oneSynth.area]
+                    delays += [oneSynth.delay]
-                labels += [oneSynth.special]
+                    areas += [oneSynth.area]
-            else:
+                    labels += [oneSynth.special]
-                delays += [oneSynth.delay]
+            # else:
-                areas += [oneSynth.area]
+            #     delays += [oneSynth.delay]
-                labels += [oneSynth.config + '_' + oneSynth.special]
+            #     areas += [oneSynth.area]
+            #     labels += [oneSynth.config + '_' + oneSynth.special]
+    if width == None:
+        width = ''
     
     f, (ax1) = plt.subplots(1, 1)
     plt.scatter(delays, areas)
@@ -154,8 +158,11 @@ def areaDelay(width, tech, freq, config=None, special=None):
 # ending freq in 42 means fpu was turned off manually
 
 if __name__ == '__main__':
-    synthsintocsv()
+    # synthsintocsv()
     synthsfromcsv('Summary.csv')
-    freqPlot('tsmc28', 'rv64', 'gc')
+    freqPlot('tsmc28', 'rv32', 'e')
-    areaDelay('rv32', 'tsmc28', 4200, config='gc')
+    freqPlot('sky90', 'rv32', 'e')
-    areaDelay('rv32', 'tsmc28', 3042, special='')
+    areaDelay('tsmc28', testFreq[1], width= 'rv64', config='gc')
+    areaDelay('tsmc28', testFreq[1], special='')
+    areaDelay('sky90', testFreq[0], width='rv64', config='gc')
+    areaDelay('sky90', testFreq[0], special='')

synthDC/runAllSynths.sh

@@ -1,5 +1,6 @@
 #!/usr/bin/bash
 
+make clean
 mv runs runArchive/$(date +"%Y_%m_%d_%I_%M_%p")
 mv newRuns runs
 mkdir newRuns

synthDC/wallySynth.py

@@ -8,20 +8,22 @@ def runCommand(config, tech, freq):
     command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT=0 MAXCORES=1".format(config, tech, freq)
     subprocess.Popen(command, shell=True)
 
+testFreq = [3000, 10000]
+
 if __name__ == '__main__':
 
     techs = ['sky90', 'tsmc28']
-    bestAchieved = [750, 3000]
+    sweepCenter = [870, 3000]
     synthsToRun = []
 
-    
     arr = [-8, -6, -4, -2, 0, 2, 4, 6, 8]
     for i in [0, 1]:
         tech = techs[i]
-        f = bestAchieved[i]
+        sc = sweepCenter[i]
-        for freq in [round(f+f*x/100) for x in arr]: # rv32e freq sweep
+        f = testFreq[i]
+        for freq in [round(sc+sc*x/100) for x in arr]: # rv32e freq sweep
             synthsToRun += [['rv32e', tech, freq]]
-        for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64i', 'rv64ic']: # configs
+        for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64i', 'rv64ic', 'rv32e']: # configs
             synthsToRun += [[config, tech, f]]
         for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations
             config = 'rv64gc_' + mod

tests/riscof/Makefile

@@ -1,20 +1,40 @@
 arch_dir = ../../addins/riscv-arch-test
+wally_dir = ../wally-riscv-arch-test
 work_dir = ./riscof_work
+work = ./work
+arch_workdir = $(work)/riscv-arch-test
+wally_workdir = $(work)/wally-riscv-arch-test
+
 current_dir = $(shell pwd)
 XLEN    ?= 64
 
-all: build
+all: root build_arch build_wally memfile
 
-build:
+root:
 	mkdir -p $(work_dir)
-	mkdir -p work
+	mkdir -p $(work)
+	mkdir -p $(arch_workdir)
+	mkdir -p $(wally_workdir)
 	sed 's,{0},$(current_dir),g;s,{1},$(XLEN)$(if $(findstring 64,$(XLEN)),gc,imc),g' config.ini > config$(XLEN).ini
+
+build_arch:
 	riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
-	rm -rf work/rv$(XLEN)i_m
+	rm -rf $(arch_workdir)/rv$(XLEN)i_m
-	mv -f $(work_dir)/rv$(XLEN)i_m work/
+	mv -f $(work_dir)/rv$(XLEN)i_m $(arch_workdir)/
+
+build_wally:
+	riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
+	rm -rf $(wally_workdir)/rv$(XLEN)i_m
+	mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/
+
+memfile: 
+	find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done
+	find $(work) -type f -name "*.elf" | grep "rv32i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
+	find $(work) -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done
 
 clean:
 	rm -f config64.ini
 	rm -f config32.ini
 	rm -rf $(work_dir)
-	rm -rf work
+	rm -rf $(wally_workdir)
+	rm -rf $(arch_workdir)

tests/riscof/sail_cSim/riscof_sail_cSim.py

@@ -101,7 +101,7 @@ class sail_cSim(pluginTemplate):
             execute += self.objdump_cmd.format(elf, self.xlen, 'Ref.elf.objdump')
             sig_file = os.path.join(test_dir, self.name[:-1] + ".signature")
 
-            execute += self.sail_exe[self.xlen] + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+            execute += self.sail_exe[self.xlen] + ' -z268435455 --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
 
             cov_str = ' '
             for label in testentry['coverage_labels']:

tests/riscof/spike/spike_rv32imc_isa.yaml

@@ -1,11 +1,11 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMFCZicsr_Zifencei
+  ISA: RV32IMAFCZicsr_Zifencei
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   misa:
-   reset-val: 0x40001124
+   reset-val: 0x40001125
    rv32:
      accessible: true
      mxl:
@@ -23,7 +23,6 @@ hart0:
            warl:
               dependency_fields: []
               legal:
-                - extensions[25:0] bitmask [0x0001124, 0x0000000]
+                - extensions[25:0] bitmask [0x0001125, 0x0000000]
               wr_illegal:
-                - Unchanged
+                - Unchanged
-