Partially working byte write enables. Works for cache, but not dtim or bus only.

pipelined/src/cache/cacheway.sv

@@ -78,8 +78,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
     .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
   // If writing the whole line set all write enables to 1, else only set the correct word.
   assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
-  //assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR
+  assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR
-  assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR  
+  //assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR  
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Tag Array

pipelined/src/lsu/lsu.sv

@@ -253,10 +253,11 @@ module lsu (
     end
   end
 
-  if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS.  Only produces byte write enable
+  if(1) begin // *** always, not just with no MEM_BUS.  Only produces byte write enable
     logic [`XLEN-1:0] ReadDataWordMaskedM;
     // ** there is definitely a sww bug with memory mapped i/o. check wally64priv.    
-    assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate
+    //assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate
+    assign ReadDataWordMaskedM = '0; // AND-gate
     // *** consider moving this AND gate into the sww.
     //assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address.
     subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]),

pipelined/src/uncore/uncore.sv

@@ -91,7 +91,7 @@ module uncore (
   assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
 
   // subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache.
-  if(`DMEM == `MEM_BUS)
+  if(0)
     subwordwrite sww(
       .HRDATA,
       .HADDRD, .HSIZED,