From 679daeedf5e25c38a0fad30cc9b773cff13f5c04 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Wed, 31 Mar 2021 13:41:40 -0400 Subject: [PATCH] busybear: clean up questa warnings --- wally-pipelined/regression/wally-busybear-batch.do | 2 +- wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/testbench/testbench-busybear.sv | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear-batch.do b/wally-pipelined/regression/wally-busybear-batch.do index 036fed326..30fea8fc0 100644 --- a/wally-pipelined/regression/wally-busybear-batch.do +++ b/wally-pipelined/regression/wally-busybear-batch.do @@ -26,7 +26,7 @@ vlib work-busybear # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index b704aba98..24fa877de 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -26,7 +26,7 @@ vlib work-busybear # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 # start and run simulation diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 8a75eb81f..acd883b47 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -145,7 +145,7 @@ module testbench_busybear(); integer regNumExpected; logic [`XLEN-1:0] PCW; - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); + flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); genvar i; generate @@ -484,7 +484,6 @@ module testbench_busybear(); // Track names of instructions string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; - flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName); instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,