mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
678f705415
@ -14,7 +14,7 @@ outDir="../linux-testvectors"
|
||||
# Uncomment this version for QEMU debugging of kernel
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||||
# - good for poking around VM if it boots up
|
||||
# - good for running QEMU commands (press "Ctrl-A" then "c" to open QEMU command prompt)
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||||
$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio
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#$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio
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# Uncomment this version for GDB debugging of kernel
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# - attempts to load in symbols from "vmlinux"
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# - good for looking at backtraces when Linux gets stuck for some reason
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@ -23,7 +23,7 @@ $customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Ima
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# Uncomment this version to generate qemu_output.txt
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# - Uses GDB script
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# - Logs raw QEMU output to qemu_output.txt
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#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
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($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
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# Uncomment this version for parse_qemu.py debugging
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||||
# - Uses qemu_output.txt
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@ -6,3 +6,5 @@ c
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file ../buildroot-image-output/vmlinux
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b plic_init
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c
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b do_idle
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c
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@ -23,15 +23,15 @@ TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr'])
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# edit this list to add more test cases
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configs = [
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TestCase(
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name="busybear",
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cmd="vsim -do wally-busybear-batch.do -c > {}",
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grepstr="loaded 100000 instructions"
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),
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#TestCase(
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# name="busybear",
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# cmd="vsim -do wally-busybear-batch.do -c > {}",
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# grepstr="loaded 100000 instructions"
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#),
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TestCase(
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name="buildroot",
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cmd="vsim -do wally-buildroot-batch.do -c > {}",
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grepstr="loaded 2500000 instructions"
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grepstr="loaded 6000 instructions"
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),
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TestCase(
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name="rv32ic",
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||||
@ -282,12 +282,13 @@ add wave -noupdate -radix hexadecimal /testbench/PCW
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||||
add wave -noupdate -radix hexadecimal /testbench/PCtextW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
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add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdW
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add wave -noupdate -divider RegFile
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add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -noupdate -radix unsigned /testbench/regNumExpected
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add wave -noupdate -radix unsigned /testbench/dut/hart/ieu/dp/RdW
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add wave -noupdate -radix hexadecimal /testbench/regExpected
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add wave -noupdate -radix hexadecimal /testbench/regNumExpected
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add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]}
|
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]}
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@ -25536,8 +25537,8 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
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add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
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add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 8} {2495 ns} 1} {{Cursor 2} {210 ns} 0}
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quietly wave cursor active 2
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WaveRestoreCursors {{Cursor 8} {203758 ns} 0} {{Cursor 2} {203765 ns} 1}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 297
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configure wave -justifyvalue left
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@ -25552,4 +25553,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {2395 ns} {2605 ns}
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WaveRestoreZoom {203642 ns} {203852 ns}
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@ -2,42 +2,41 @@ onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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||||
add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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||||
add wave -noupdate -expand -group {Memory Stage} /testbench/PCtextM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
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||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
@ -115,19 +114,19 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
|
||||
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -noupdate -expand -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
||||
@ -241,122 +240,95 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
|
||||
add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand /testbench/dut/hart/lsu/dcache/ReadTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -divider data
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
||||
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
|
||||
@ -431,7 +403,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
|
||||
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
|
||||
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {5126 ns} 0} {{Cursor 2} {40310 ns} 0} {{Cursor 3} {6427 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 4} {5126 ns} 0} {{Cursor 2} {203758 ns} 0} {{Cursor 3} {6427 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 297
|
||||
@ -447,4 +419,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {697884 ns}
|
||||
WaveRestoreZoom {203677 ns} {203893 ns}
|
||||
|
||||
52
wally-pipelined/src/cache/dcache.sv
vendored
52
wally-pipelined/src/cache/dcache.sv
vendored
@ -128,7 +128,6 @@ module dcache
|
||||
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
|
||||
logic [TAGLEN-1:0] VictimTag;
|
||||
|
||||
logic ReadDataWEn;
|
||||
|
||||
logic AnyCPUReqM;
|
||||
logic FetchCountFlag;
|
||||
@ -316,12 +315,9 @@ module dcache
|
||||
assign CPUBusy = CurrState == STATE_CPU_BUSY;
|
||||
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
|
||||
|
||||
assign ReadDataWEn = (~StallW & (~PreviousCPUBusy & (CurrState != STATE_CPU_BUSY))) |
|
||||
(NextState == STATE_CPU_BUSY & CurrState == STATE_READY) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY);
|
||||
|
||||
flopen #(`XLEN) ReadDataWReg(.clk(clk),
|
||||
.en(ReadDataWEn),
|
||||
.en(~StallW),
|
||||
.d(FinalReadDataWordM),
|
||||
.q(ReadDataW));
|
||||
|
||||
@ -467,7 +463,9 @@ module dcache
|
||||
NextState = STATE_AMO_UPDATE;
|
||||
DCacheStall = 1'b1;
|
||||
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
else NextState = STATE_AMO_UPDATE;
|
||||
end
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
@ -475,7 +473,10 @@ module dcache
|
||||
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
|
||||
DCacheStall = 1'b0;
|
||||
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
// write hit valid cached
|
||||
@ -485,7 +486,10 @@ module dcache
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirtyM = 1'b1;
|
||||
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
// read or write miss valid cached
|
||||
@ -522,7 +526,10 @@ module dcache
|
||||
end
|
||||
STATE_AMO_WRITE: begin
|
||||
SelAMOWrite = 1'b1;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
@ -578,7 +585,10 @@ module dcache
|
||||
STATE_MISS_READ_WORD_DELAY: begin
|
||||
//SelAdrM = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
@ -593,7 +603,10 @@ module dcache
|
||||
|
||||
STATE_MISS_WRITE_WORD_DELAY: begin
|
||||
CommittedM = 1'b1;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
@ -722,9 +735,12 @@ module dcache
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
|
||||
STATE_CPU_BUSY : begin
|
||||
STATE_CPU_BUSY: begin
|
||||
CommittedM = 1'b1;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
@ -752,14 +768,20 @@ module dcache
|
||||
|
||||
STATE_UNCACHED_WRITE_DONE: begin
|
||||
CommittedM = 1'b1;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
STATE_UNCACHED_READ_DONE: begin
|
||||
CommittedM = 1'b1;
|
||||
SelUncached = 1'b1;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
if(StallW) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdrM = 1'b1;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
|
||||
2
wally-pipelined/src/cache/sram1rw.sv
vendored
2
wally-pipelined/src/cache/sram1rw.sv
vendored
@ -15,7 +15,7 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
|
||||
always_ff @(posedge clk) begin
|
||||
ReadData <= StoredData[Addr];
|
||||
if (WriteEnable) begin
|
||||
StoredData[Addr] <= WriteData;
|
||||
StoredData[Addr] <= #1 WriteData;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -34,9 +34,10 @@ module pmpadrdec (
|
||||
input logic [7:0] PMPCfg,
|
||||
input logic [`XLEN-1:0] PMPAdr,
|
||||
input logic PAgePMPAdrIn,
|
||||
input logic NoLowerMatchIn,
|
||||
// input logic NoLowerMatchIn,
|
||||
input logic FirstMatch,
|
||||
output logic PAgePMPAdrOut,
|
||||
output logic NoLowerMatchOut,
|
||||
// output logic NoLowerMatchOut,
|
||||
output logic Match, Active,
|
||||
output logic L, X, W, R
|
||||
);
|
||||
@ -47,7 +48,7 @@ module pmpadrdec (
|
||||
|
||||
logic TORMatch, NAMatch;
|
||||
logic PAltPMPAdr;
|
||||
logic FirstMatch;
|
||||
// logic FirstMatch;
|
||||
logic [`PA_BITS-1:0] CurrentAdrFull;
|
||||
logic [1:0] AdrMode;
|
||||
|
||||
@ -69,16 +70,30 @@ module pmpadrdec (
|
||||
|
||||
// verilator lint_off UNOPTFLAT
|
||||
logic [`PA_BITS-1:0] Mask;
|
||||
genvar i;
|
||||
//genvar i;
|
||||
|
||||
// create a mask of which bits to ignore
|
||||
generate
|
||||
assign Mask[1:0] = 2'b11;
|
||||
assign Mask[2] = (AdrMode == NAPOT); // mask has 0s in upper bis for NA4 region
|
||||
for (i=3; i < `PA_BITS; i=i+1) begin:mask
|
||||
assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore
|
||||
end
|
||||
endgenerate
|
||||
// generate
|
||||
// assign Mask[1:0] = 2'b11;
|
||||
// assign Mask[2] = (AdrMode == NAPOT); // mask has 0s in upper bis for NA4 region
|
||||
// for (i=3; i < `PA_BITS; i=i+1) begin:mask
|
||||
// assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore
|
||||
// end
|
||||
// endgenerate
|
||||
prioritycircuit #(.ENTRIES(`PA_BITS-2), .FINAL_OP("NONE")) maskgen(.a(~PMPAdr[`PA_BITS-3:0]), .FirstPin(AdrMode==NAPOT), .y(Mask[`PA_BITS-1:2]));
|
||||
assign Mask[1:0] = 2'b11;
|
||||
|
||||
// *** possible experiments:
|
||||
/* PA < PMP addr could be in its own module,
|
||||
preeserving hierarchy so we can know if this is the culprit on the critical path
|
||||
Should take logarthmic time, so more like 6 levels than 40 should be expected
|
||||
|
||||
update mask generation
|
||||
Should be concurrent with the subtraction/comparison
|
||||
if one is the critical path, the other shouldn't be which makes us think the mask generation is the culprit.
|
||||
|
||||
Hopefully just use the priority circuit here
|
||||
*/
|
||||
// verilator lint_on UNOPTFLAT
|
||||
|
||||
assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | Mask);
|
||||
@ -87,8 +102,6 @@ module pmpadrdec (
|
||||
(AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch :
|
||||
0;
|
||||
|
||||
assign FirstMatch = NoLowerMatchIn & Match;
|
||||
assign NoLowerMatchOut = NoLowerMatchIn & ~Match;
|
||||
assign L = PMPCfg[7] & FirstMatch;
|
||||
assign X = PMPCfg[2] & FirstMatch;
|
||||
assign W = PMPCfg[1] & FirstMatch;
|
||||
|
||||
@ -55,12 +55,9 @@ module pmpchecker (
|
||||
// Bit i is high when the address falls in PMP region i
|
||||
logic EnforcePMP;
|
||||
logic [7:0] PMPCfg[`PMP_ENTRIES-1:0];
|
||||
logic [`PMP_ENTRIES-1:0] Match; // PMP Entry matches
|
||||
logic [`PMP_ENTRIES-1:0] Match, FirstMatch; // PMP Entry matches
|
||||
logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null
|
||||
logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
|
||||
// verilator lint_off UNOPTFLAT
|
||||
logic [`PMP_ENTRIES-1:0] NoLowerMatch; // None of the lower PMP entries match
|
||||
// verilator lint_on UNOPTFLAT
|
||||
logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
|
||||
genvar i,j;
|
||||
|
||||
@ -70,9 +67,9 @@ module pmpchecker (
|
||||
.PMPAdr(PMPADDR_ARRAY_REGW),
|
||||
.PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
|
||||
.PAgePMPAdrOut(PAgePMPAdr),
|
||||
.NoLowerMatchIn({NoLowerMatch[`PMP_ENTRIES-2:0], 1'b1}),
|
||||
.NoLowerMatchOut(NoLowerMatch),
|
||||
.Match, .Active, .L, .X, .W, .R);
|
||||
.FirstMatch, .Match, .Active, .L, .X, .W, .R);
|
||||
|
||||
prioritycircuit #(.ENTRIES(`PMP_ENTRIES), .FINAL_OP("AND")) pmppriority(.a(Match), .FirstPin(1'b1), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit.
|
||||
|
||||
// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
|
||||
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
///////////////////////////////////////////
|
||||
// tlbpriority.sv
|
||||
// prioritycircuit.sv
|
||||
//
|
||||
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
|
||||
// Modified: Teo Ene 15 Apr 2021:
|
||||
@ -30,8 +30,10 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module tlbpriority #(parameter ENTRIES = 8) (
|
||||
module prioritycircuit #(parameter ENTRIES = 8,
|
||||
parameter FINAL_OP = "AND") (
|
||||
input logic [ENTRIES-1:0] a,
|
||||
input logic FirstPin,
|
||||
output logic [ENTRIES-1:0] y
|
||||
);
|
||||
// verilator lint_off UNOPTFLAT
|
||||
@ -40,11 +42,19 @@ module tlbpriority #(parameter ENTRIES = 8) (
|
||||
// generate thermometer code mask
|
||||
genvar i;
|
||||
generate
|
||||
assign nolower[0] = 1;
|
||||
assign nolower[0] = FirstPin;
|
||||
for (i=1; i<ENTRIES; i++) begin:therm
|
||||
assign nolower[i] = nolower[i-1] & ~a[i-1];
|
||||
end
|
||||
endgenerate
|
||||
// verilator lint_on UNOPTFLAT
|
||||
assign y = a & nolower;
|
||||
|
||||
generate
|
||||
if (FINAL_OP=="AND") begin
|
||||
assign y = a & nolower;
|
||||
end else if (FINAL_OP=="NONE") begin
|
||||
assign y = nolower;
|
||||
end // *** So far these are the only two operations I need to do at the end, but feel free to add more as needed.
|
||||
endgenerate
|
||||
// assign y = a & nolower;
|
||||
endmodule
|
||||
@ -39,7 +39,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
|
||||
logic AllUsed; // High if the next access causes all RU bits to be 1
|
||||
|
||||
// Find the first line not recently used
|
||||
tlbpriority #(TLB_ENTRIES) nru(~RUBits, WriteLines);
|
||||
prioritycircuit #(.ENTRIES(TLB_ENTRIES), .FINAL_OP("AND")) nru(.a(~RUBits), .FirstPin(1'b1), .y(WriteLines));
|
||||
|
||||
// Track recently used lines, updating on a CAM Hit or TLB write
|
||||
assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
|
||||
|
||||
@ -82,7 +82,7 @@ module csrm #(parameter
|
||||
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] MISA_REGW;
|
||||
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
|
||||
logic [`XLEN-1:0] MSCRATCH_REGW, MCAUSE_REGW, MTVAL_REGW;
|
||||
|
||||
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
|
||||
@ -97,6 +97,9 @@ module csrm #(parameter
|
||||
// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
|
||||
assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]};
|
||||
|
||||
// MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it.
|
||||
assign MHARTID_REGW = 0;
|
||||
|
||||
// Write machine Mode CSRs
|
||||
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS) && ~StallW;
|
||||
assign WriteMTVECM = CSRMWriteM && (CSRAdrM == MTVEC) && ~StallW;
|
||||
@ -195,7 +198,7 @@ module csrm #(parameter
|
||||
MVENDORID: CSRMReadValM = 0;
|
||||
MARCHID: CSRMReadValM = 0;
|
||||
MIMPID: CSRMReadValM = `XLEN'h100; // pipelined implementation
|
||||
MHARTID: CSRMReadValM = 0;
|
||||
MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0
|
||||
MSTATUS: CSRMReadValM = MSTATUS_REGW;
|
||||
MSTATUSH: CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
|
||||
MTVEC: CSRMReadValM = MTVEC_REGW;
|
||||
|
||||
@ -82,7 +82,7 @@ module clint (
|
||||
always_ff @(posedge HCLK or negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
MSIP <= 0;
|
||||
MTIMECMP <= 0;
|
||||
MTIMECMP <= (64)'(0);
|
||||
// MTIMECMP is not reset
|
||||
end else if (memwrite) begin
|
||||
if (entryd == 16'h0000) MSIP <= HWDATA[0];
|
||||
@ -112,7 +112,7 @@ module clint (
|
||||
always_ff @(posedge HCLK or negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
MSIP <= 0;
|
||||
MTIMECMP <= 0;
|
||||
MTIMECMP <= (64)'(0);
|
||||
// MTIMECMP is not reset
|
||||
end else if (memwrite) begin
|
||||
if (entryd == 16'h0000) MSIP <= HWDATA[0];
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
|
||||
module testbench();
|
||||
|
||||
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0000000; // # of instructions at which to turn on waves in graphical sim
|
||||
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0459700; // # of instructions at which to turn on waves in graphical sim
|
||||
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
@ -194,120 +194,118 @@ module testbench();
|
||||
// Big Chunky Block
|
||||
// ----------------
|
||||
always @(reset or dut.hart.ifu.InstrRawD or dut.hart.ifu.PCD) begin// or negedge dut.hart.ifu.StallE) begin // Why do we care about StallE? Everything seems to run fine without it.
|
||||
if(~dut.hart.lsu.dcache.MemRWM) begin // *** Should this need to consider dut.hart.lsu.dcache.MemRWM?
|
||||
#2;
|
||||
// If PCD/InstrD aren't garbage
|
||||
if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0) begin // && ~dut.hart.ifu.StallE) begin
|
||||
// If Wally's PCD has updated
|
||||
if (dut.hart.ifu.PCD !== lastPCD) begin
|
||||
lastInstrDExpected = InstrDExpected;
|
||||
lastPC <= dut.hart.ifu.PCD;
|
||||
lastPC2 <= lastPC;
|
||||
// If PCD isn't going to be flushed
|
||||
if (~PCDwrong || lastPC == PCDexpected) begin
|
||||
#2;
|
||||
// If PCD/InstrD aren't garbage
|
||||
if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0) begin // && ~dut.hart.ifu.StallE) begin
|
||||
// If Wally's PCD has updated
|
||||
if (dut.hart.ifu.PCD !== lastPCD) begin
|
||||
lastInstrDExpected = InstrDExpected;
|
||||
lastPC <= dut.hart.ifu.PCD;
|
||||
lastPC2 <= lastPC;
|
||||
// If PCD isn't going to be flushed
|
||||
if (~PCDwrong || lastPC == PCDexpected) begin
|
||||
|
||||
// Stop if we've reached the end
|
||||
if($feof(data_file_PCF)) begin
|
||||
$display("no more PC data to read... CONGRATULATIONS!!!");
|
||||
`ERROR
|
||||
end
|
||||
// Stop if we've reached the end
|
||||
if($feof(data_file_PCF)) begin
|
||||
$display("no more PC data to read... CONGRATULATIONS!!!");
|
||||
`ERROR
|
||||
end
|
||||
|
||||
// Increment PC
|
||||
`SCAN_PC(data_file_PCF, scan_file_PCF, PCtextF, PCtextF2, InstrFExpected, PCFexpected);
|
||||
`SCAN_PC(data_file_PCD, scan_file_PCD, PCtextD, PCtextD2, InstrDExpected, PCDexpected);
|
||||
// Increment PC
|
||||
`SCAN_PC(data_file_PCF, scan_file_PCF, PCtextF, PCtextF2, InstrFExpected, PCFexpected);
|
||||
`SCAN_PC(data_file_PCD, scan_file_PCD, PCtextD, PCtextD2, InstrDExpected, PCDexpected);
|
||||
|
||||
// NOP out certain instructions
|
||||
if(dut.hart.ifu.PCD===PCDexpected) begin
|
||||
if((dut.hart.ifu.PCD == 32'h80001dc6) || // for now, NOP out any stores to PLIC
|
||||
(dut.hart.ifu.PCD == 32'h80001de0) ||
|
||||
(dut.hart.ifu.PCD == 32'h80001de2)) begin
|
||||
$display("warning: NOPing out %s at PCD=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
|
||||
force InstrDExpected = 32'b0010011;
|
||||
force dut.hart.ifu.InstrRawD = 32'b0010011;
|
||||
while (clk != 0) #1;
|
||||
while (clk != 1) #1;
|
||||
release dut.hart.ifu.InstrRawD;
|
||||
release InstrDExpected;
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end else begin
|
||||
forcedInstr = 0;
|
||||
end
|
||||
end
|
||||
|
||||
// Increment instruction count
|
||||
if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
|
||||
(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
|
||||
(instrs <= 100000 && instrs % 10000 == 0) || (instrs % 100000 == 0)) begin
|
||||
$display("loaded %0d instructions", instrs);
|
||||
end
|
||||
instrs += 1;
|
||||
|
||||
// Stop before bugs so "do" file can turn on waves
|
||||
if (instrs == waveOnICount) begin
|
||||
$display("turning on waves at %0d instructions", instrs);
|
||||
$stop;
|
||||
end else if (instrs == stopICount && stopICount != 0) begin
|
||||
$display("Ending sim at %0d instructions (set stopICount to 0 to let the sim go on)", instrs);
|
||||
$stop;
|
||||
end
|
||||
|
||||
// Check if PCD is going to be flushed due to a branch or jump
|
||||
if (`BPRED_ENABLED) begin
|
||||
PCDwrong = dut.hart.hzu.FlushD; //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET.
|
||||
end else begin
|
||||
casex (lastInstrDExpected[31:0])
|
||||
32'b00000000001000000000000001110011, // URET
|
||||
32'b00010000001000000000000001110011, // SRET
|
||||
32'b00110000001000000000000001110011, // MRET
|
||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
|
||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
|
||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
|
||||
32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
|
||||
32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
|
||||
32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
|
||||
PCDwrong = 1;
|
||||
32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK:
|
||||
32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR*
|
||||
PCDwrong = 0; // tbh don't really know what should happen here
|
||||
32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, *
|
||||
32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
|
||||
32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
|
||||
PCDwrong = 1;
|
||||
default:
|
||||
PCDwrong = 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Check PCD, InstrD
|
||||
if (~PCDwrong && ~(dut.hart.ifu.PCD === PCDexpected)) begin
|
||||
$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, PCDexpected);
|
||||
`ERROR
|
||||
end
|
||||
InstrMask = InstrDExpected[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
|
||||
if ((~forcedInstr) && (~PCDwrong) && ((InstrMask & dut.hart.ifu.InstrRawD) !== (InstrMask & InstrDExpected))) begin
|
||||
$display("%0t ps, PCD %x, instr %0d: InstrD %x %s does not equal InstrDExpected %x %s", $time, dut.hart.ifu.PCD, instrs, dut.hart.ifu.InstrRawD, InstrDName, InstrDExpected, PCtextD);
|
||||
`ERROR
|
||||
end
|
||||
|
||||
// Repeated instruction means QEMU had an interrupt which we need to spoof
|
||||
if (PCFexpected == PCDexpected) begin
|
||||
$display("Note at %0t ps, PCM %x %s, instr %0d: spoofing an interrupt", $time, dut.hart.ifu.PCM, PCtextM, instrs);
|
||||
// Increment file pointers past the repeated instruction.
|
||||
`SCAN_PC(data_file_PCF, scan_file_PCF, PCtextF, PCtextF2, InstrFExpected, PCFexpected);
|
||||
`SCAN_PC(data_file_PCD, scan_file_PCD, PCtextD, PCtextD2, InstrDExpected, PCDexpected);
|
||||
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
|
||||
scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
|
||||
// Next force a timer interrupt (*** this may later need generalizing)
|
||||
force dut.uncore.genblk1.clint.MTIME = dut.uncore.genblk1.clint.MTIMECMP + 1;
|
||||
// NOP out certain instructions
|
||||
if(dut.hart.ifu.PCD===PCDexpected) begin
|
||||
if((dut.hart.ifu.PCD == 32'h80001dc6) || // for now, NOP out any stores to PLIC
|
||||
(dut.hart.ifu.PCD == 32'h80001de0) ||
|
||||
(dut.hart.ifu.PCD == 32'h80001de2)) begin
|
||||
$display("warning: NOPing out %s at PCD=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
|
||||
force InstrDExpected = 32'b0010011;
|
||||
force dut.hart.ifu.InstrRawD = 32'b0010011;
|
||||
while (clk != 0) #1;
|
||||
while (clk != 1) #1;
|
||||
release dut.uncore.genblk1.clint.MTIME;
|
||||
release dut.hart.ifu.InstrRawD;
|
||||
release InstrDExpected;
|
||||
warningCount += 1;
|
||||
forcedInstr = 1;
|
||||
end else begin
|
||||
forcedInstr = 0;
|
||||
end
|
||||
end
|
||||
|
||||
// Increment instruction count
|
||||
if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
|
||||
(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
|
||||
(instrs <= 100000 && instrs % 10000 == 0) || (instrs % 100000 == 0)) begin
|
||||
$display("loaded %0d instructions", instrs);
|
||||
end
|
||||
instrs += 1;
|
||||
|
||||
// Stop before bugs so "do" file can turn on waves
|
||||
if (instrs == waveOnICount) begin
|
||||
$display("turning on waves at %0d instructions", instrs);
|
||||
$stop;
|
||||
end else if (instrs == stopICount && stopICount != 0) begin
|
||||
$display("Ending sim at %0d instructions (set stopICount to 0 to let the sim go on)", instrs);
|
||||
$stop;
|
||||
end
|
||||
|
||||
// Check if PCD is going to be flushed due to a branch or jump
|
||||
if (`BPRED_ENABLED) begin
|
||||
PCDwrong = dut.hart.hzu.FlushD; //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET.
|
||||
end else begin
|
||||
casex (lastInstrDExpected[31:0])
|
||||
32'b00000000001000000000000001110011, // URET
|
||||
32'b00010000001000000000000001110011, // SRET
|
||||
32'b00110000001000000000000001110011, // MRET
|
||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
|
||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
|
||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
|
||||
32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
|
||||
32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
|
||||
32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
|
||||
PCDwrong = 1;
|
||||
32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK:
|
||||
32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR*
|
||||
PCDwrong = 0; // tbh don't really know what should happen here
|
||||
32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, *
|
||||
32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
|
||||
32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
|
||||
PCDwrong = 1;
|
||||
default:
|
||||
PCDwrong = 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Check PCD, InstrD
|
||||
if (~PCDwrong && ~(dut.hart.ifu.PCD === PCDexpected)) begin
|
||||
$display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, PCDexpected);
|
||||
`ERROR
|
||||
end
|
||||
InstrMask = InstrDExpected[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
|
||||
if ((~forcedInstr) && (~PCDwrong) && ((InstrMask & dut.hart.ifu.InstrRawD) !== (InstrMask & InstrDExpected))) begin
|
||||
$display("%0t ps, PCD %x, instr %0d: InstrD %x %s does not equal InstrDExpected %x %s", $time, dut.hart.ifu.PCD, instrs, dut.hart.ifu.InstrRawD, InstrDName, InstrDExpected, PCtextD);
|
||||
`ERROR
|
||||
end
|
||||
|
||||
// Repeated instruction means QEMU had an interrupt which we need to spoof
|
||||
if (PCFexpected == PCDexpected) begin
|
||||
$display("Note at %0t ps, PCM %x %s, instr %0d: spoofing an interrupt", $time, dut.hart.ifu.PCM, PCtextM, instrs);
|
||||
// Increment file pointers past the repeated instruction.
|
||||
`SCAN_PC(data_file_PCF, scan_file_PCF, PCtextF, PCtextF2, InstrFExpected, PCFexpected);
|
||||
`SCAN_PC(data_file_PCD, scan_file_PCD, PCtextD, PCtextD2, InstrDExpected, PCDexpected);
|
||||
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
|
||||
scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
|
||||
// Next force a timer interrupt (*** this may later need generalizing)
|
||||
force dut.uncore.genblk1.clint.MTIME = dut.uncore.genblk1.clint.MTIMECMP + 1;
|
||||
while (clk != 0) #1;
|
||||
while (clk != 1) #1;
|
||||
release dut.uncore.genblk1.clint.MTIME;
|
||||
end
|
||||
end
|
||||
lastPCD = dut.hart.ifu.PCD;
|
||||
end
|
||||
lastPCD = dut.hart.ifu.PCD;
|
||||
end
|
||||
end
|
||||
|
||||
@ -453,8 +451,7 @@ module testbench();
|
||||
// Read Checker
|
||||
// ------------
|
||||
always @(negedge clk) begin
|
||||
//if (dut.hart.MemRWM[1] && ~dut.hart.StallM && ~dut.hart.FlushM && dut.hart.ieu.InstrValidM) begin <-- This doesn't work because ReadDataM can be used for other things (namely page table walking) while the pipeline is stalled, leaving it in a different state when the pipeline unstalls
|
||||
if (dut.hart.MemRWM[1] && dut.hart.lsu.dcache.ReadDataWEn) begin // <-- ReadDataWEn is a good indicator that the pipeline is using the current contents of ReadDataM
|
||||
if (dut.hart.MemRWM[1] && ~dut.hart.StallM && ~dut.hart.FlushM && dut.hart.ieu.InstrValidM) begin
|
||||
if($feof(data_file_memR)) begin
|
||||
$display("no more memR data to read");
|
||||
`ERROR
|
||||
@ -530,7 +527,8 @@ module testbench();
|
||||
// --------------
|
||||
// Checker Macros
|
||||
// --------------
|
||||
string MSTATUSstring = "MSTATUS"; //string variables seem to compare more reliably than string literals
|
||||
string MSTATUSstring = "MSTATUS"; // string variables seem to compare more reliably than string literals (they gave me a lot of hassle), but *** there's probably a better way to do this
|
||||
string MIPstring = "MIP";
|
||||
string SEPCstring = "SEPC";
|
||||
string SCAUSEstring = "SCAUSE";
|
||||
string SSTATUSstring = "SSTATUS";
|
||||
@ -540,10 +538,13 @@ module testbench();
|
||||
string ``CSR``name = `"CSR`"; \
|
||||
string expected``CSR``name; \
|
||||
always @(``PATH``.``CSR``_REGW) begin \
|
||||
if ($time > 1 && (`BUILDROOT != 1 || ``CSR``name != SSTATUSstring)) begin \
|
||||
if (``CSR``name == SEPCstring) begin #1; end \
|
||||
if (``CSR``name == SCAUSEstring) begin #2; end \
|
||||
if (``CSR``name == SSTATUSstring) begin #3; end \
|
||||
// MIP is not checked because QEMU bodges it (MTIP in particular), and even if QEMU reported it correctly, the timing would still be off \
|
||||
if ($time > 1 && (``CSR``name != MIPstring)) begin \
|
||||
// This is some feeble hackery designed to control the order in which CSRs are checked \
|
||||
// when multiple change at the same time. \
|
||||
if (``CSR``name == SEPCstring) #1; \
|
||||
if (``CSR``name == SCAUSEstring) #2; \
|
||||
if (``CSR``name == SSTATUSstring) #3; \
|
||||
scan_file_csr = $fscanf(data_file_csr, "%s\n", expected``CSR``name); \
|
||||
scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
|
||||
if(expected``CSR``name.icompare(``CSR``name)) begin \
|
||||
@ -581,31 +582,36 @@ module testbench();
|
||||
// --------
|
||||
// Checking
|
||||
// --------
|
||||
//`CHECK_CSR(FCSR)
|
||||
`CHECK_CSR2(MCAUSE, `CSRM)
|
||||
`CHECK_CSR(MCOUNTEREN)
|
||||
`CHECK_CSR(MEDELEG)
|
||||
`CHECK_CSR(MEPC)
|
||||
//`CHECK_CSR(MHARTID)
|
||||
`CHECK_CSR(MIDELEG)
|
||||
`CHECK_CSR(MIE)
|
||||
//`CHECK_CSR(MIP)
|
||||
`CHECK_CSR2(MISA, `CSRM)
|
||||
`CHECK_CSR2(MSCRATCH, `CSRM)
|
||||
// Which CSRs we check depends upon which ones QEMU outputs
|
||||
// *** can we fix QEMU to output a defined set of CSRs?
|
||||
`CHECK_CSR2(MHARTID, `CSRM)
|
||||
`CHECK_CSR(MSTATUS)
|
||||
`CHECK_CSR2(MTVAL, `CSRM)
|
||||
`CHECK_CSR(MIP)
|
||||
`CHECK_CSR(MIE)
|
||||
`CHECK_CSR(MIDELEG)
|
||||
`CHECK_CSR(MEDELEG)
|
||||
`CHECK_CSR(MTVEC)
|
||||
`CHECK_CSR(STVEC)
|
||||
`CHECK_CSR(MEPC)
|
||||
`CHECK_CSR(SEPC)
|
||||
`CHECK_CSR2(MCAUSE, `CSRM)
|
||||
`CHECK_CSR2(SCAUSE, `CSRS)
|
||||
`CHECK_CSR2(MTVAL, `CSRM)
|
||||
`CHECK_CSR2(STVAL, `CSRS)
|
||||
|
||||
//`CHECK_CSR(FCSR)
|
||||
//`CHECK_CSR(MCOUNTEREN)
|
||||
//`CHECK_CSR2(MISA, `CSRM)
|
||||
//`CHECK_CSR2(MSCRATCH, `CSRM)
|
||||
//`CHECK_CSR2(PMPADDR0, `CSRM)
|
||||
//`CHECK_CSR2(PMdut.PCFG0, `CSRM)
|
||||
`CHECK_CSR(SATP)
|
||||
`CHECK_CSR2(SCAUSE, `CSRS)
|
||||
`CHECK_CSR(SCOUNTEREN)
|
||||
`CHECK_CSR(SEPC)
|
||||
`CHECK_CSR(SIE)
|
||||
`CHECK_CSR2(SSCRATCH, `CSRS)
|
||||
`CHECK_CSR(SSTATUS)
|
||||
`CHECK_CSR2(STVAL, `CSRS)
|
||||
`CHECK_CSR(STVEC)
|
||||
//`CHECK_CSR(SATP)
|
||||
//`CHECK_CSR(SCOUNTEREN)
|
||||
//`CHECK_CSR(SIE)
|
||||
//`CHECK_CSR2(SSCRATCH, `CSRS)
|
||||
//`CHECK_CSR(SSTATUS)
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////// Miscellaneous ///////////////////////////////
|
||||
|
||||
Loading…
Reference in New Issue
Block a user