Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/openhwgroup/cvw

Browse Source
This commit is contained in:
Ross Thompson 2023-04-30 23:30:13 -05:00
commit 67539a4af1
15 changed files with 240 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -115,3 +115,4 @@ tests/coverage/*.elf
*.elf.memfile
sim/*Cache.log
sim/branch
tests/fp/combined_IF_vectors/IF_vectors/*.tv

53
sim/coverage-exclusions-rv64gc.do
View File

@ -97,6 +97,9 @@ for {set i 0} {$i < $numcacheways} {incr i} {
# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
####################
# Unused / illegal peripheral accesses
####################
# Excluding peripherals as sources of instructions for the ifu
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec
@ -104,53 +107,63 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec
# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
# Excluding so far un-used instruction sources for the ifu
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
#Excluding the bootrom, uncoreran, and clint as sources for the lsu
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
## Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccessF' will never be 1
# in pmachecker.sv
####################
# Unused access types due to sharing IFU and LSU logic
####################
## The lsu never executes instructions so 'ExecuteAccessF' will never be 1
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
# in mmu.sv
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
# in pmpchecker.sv
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3
## Excluding ReadAccessM_1 and WriteAccessM_1 signals in the ifu pmachecker, mmu, pmpchecker because they will never be high
## and Excluding ExecuteAccessF_0 because it is always true/high in the ifu
# in pmachecker.sv
## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"]
@ -159,8 +172,6 @@ set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM & PMAAccessFault"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
# in mmu.sv
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
@ -175,21 +186,14 @@ set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
# in pmpchecker.sv
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"]
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
## Executing any LoadAccess or StoreAccess signal in the ifu - depend on Read and Write Access that the ifu will never have
# in /mmu/mmu.sv
set line [GetLineNum ../src/mmu/mmu.sv "PMALoadAccessFaultM \\| PMPLoadAccessFaultM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
set line [GetLineNum ../src/mmu/mmu.sv "PMAStoreAmoAccessFaultM \\| PMPStoreAmoAccessFaultM"]
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
## Excluding ReadAccess_0, WriteAcess_1 in the TLB because the itlb only reads, and does not write
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"]
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"]
@ -201,3 +205,10 @@ coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $l
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
# TLB not recently used never has all RU bits = 1 because it will then clear all to 0
# This is a blunt instrument; perhaps there is a more graceful exclusion
coverage exclude -srcfile priorityonehot.sv
# Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1

4
src/ieu/bmu/byte.sv → src/ieu/bmu/byteop.sv
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////
// byte.sv
// byteop.sv
//
// Written: Kevin Kim <kekim@hmc.edu>
// Created: 1 February 2023
@ -29,7 +29,7 @@
`include "wally-config.vh"
module byteUnit #(parameter WIDTH=32) (
module byteop #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, // Operands
input logic ByteSelect, // LSB of Immediate
output logic [WIDTH-1:0] ByteResult); // rev8, orcb result

2
src/ieu/bmu/zbb.sv
View File

@ -47,7 +47,7 @@ module zbb #(parameter WIDTH=32) (
mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
// ZBBSelect[2] differentiates between min(u) vs max(u) instruction

8
src/lsu/amoalu.sv
View File

@ -34,7 +34,7 @@ module amoalu (
input logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
input logic [6:0] LSUFunct7M, // ALU Operation
input logic [2:0] LSUFunct3M, // Memoy access width
output logic [`XLEN-1:0] AMOResult // ALU output
output logic [`XLEN-1:0] AMOResultM // ALU output
);
logic [`XLEN-1:0] a, b, y;
@ -60,17 +60,17 @@ module amoalu (
if (`XLEN == 32) begin:sext
assign a = ReadDataM;
assign b = IHWriteDataM;
assign AMOResult = y;
assign AMOResultM = y;
end else begin:sext // `XLEN = 64
always_comb
if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
AMOResult = {{32{y[31]}}, y[31:0]};
AMOResultM = {{32{y[31]}}, y[31:0]};
end else begin
a = ReadDataM;
b = IHWriteDataM;
AMOResult = y;
AMOResultM = y;
end
end
endmodule

8
src/lsu/atomic.sv
View File

@ -38,7 +38,7 @@ module atomic (
input logic [`PA_BITS-1:0] PAdrM, // Physical memory address
input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW
input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size
input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation
input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal
input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation
output logic [`XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data
@ -46,12 +46,12 @@ module atomic (
output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC
);
logic [`XLEN-1:0] AMOResult;
logic [`XLEN-1:0] AMOResultM;
logic MemReadM;
amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult);
amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);

2
src/mmu/hptw.sv
View File

@ -175,7 +175,7 @@ module hptw (
.SV39Mode(), .UpperBitsUnequal);
assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
assign InvalidWrite = WriteAccess & ~Writable;
assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable;
assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable;
assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequal | Misaligned | ~Valid;
// hptw needs to know if there is a Dirty or Access fault occuring on this

8
src/mmu/pmachecker.sv
View File

@ -57,14 +57,14 @@ module pmachecker (
adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
// Only non-core RAM/ROM memory regions are cacheable
assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6];
assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-cachable
// Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
// I/O is nonidempotent.
assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6];
assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-idempotent
// Atomic operations are only allowed on RAM
assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6];
assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6]; // exclusion-tag: unused-atomic
// Check if tightly integrated memories are selected
assign SelTIM = SelRegions[10] | SelRegions[9];
assign SelTIM = SelRegions[10] | SelRegions[9]; // exclusion-tag: unused-tim
// Detect access faults
assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;

2
src/mmu/pmpadrdec.sv
View File

@ -63,7 +63,7 @@ module pmpadrdec (
assign CurrentAdrFull = {PMPAdr, 2'b00};
assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison
assign PAgePMPAdrOut = ~PAltPMPAdr;
assign TORMatch = PAgePMPAdrIn & PAltPMPAdr;
assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; // exclusion-tag: PAgePMPAdrIn
// Naturally aligned regions
logic [`PA_BITS-1:0] NAMask, NABase;

4
src/mmu/tlb/tlblru.sv
View File

@ -50,7 +50,5 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
assign RUBitsAccessed = AccessLines | RUBits;
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
// enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
flopenr #(TLB_ENTRIES) lrustate(clk, reset, (CAMHit | TLBWrite), RUBitsNext, RUBits);
endmodule

2
src/privileged/csr.sv
View File

@ -158,7 +158,7 @@ module csr #(parameter
assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition
mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
end else
assign TrapVectorM = TVecAlignedM;
assign TrapVectorM = TVecAlignedM; // unvectored interrupt handler can be at any word-aligned address. This is called Sstvecd
// Trap Returns
// A trap sets the PC to TrapVector

3
src/privileged/csrsr.sv
View File

@ -177,8 +177,7 @@ module csrsr (
STATUS_MIE <= #1 STATUS_MPIE; // restore global interrupt enable
STATUS_MPIE <= #1 1; //
STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // set MPP to lowest supported privilege level
// STATUS_MPRV_INT <= #1 0; // changed to this by Ross to solve Linux bug; might have been s spurious disagreement with QEMU
STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // Seems to be given by page 21 of spec.
STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // page 21 of privileged spec.
end else if (sretM) begin
STATUS_SIE <= #1 STATUS_SPIE; // restore global interrupt enable
STATUS_SPIE <= #1 `S_SUPPORTED;

4
testbench/tests.vh
View File

@ -63,7 +63,9 @@ string tvpaths[] = '{
"pmp",
"pmpcfg",
"pmpcfg1",
"pmpcfg2"
"pmpcfg2",
"pmppriority",
"pmpadrdecs"
};
string coremark[] = '{

22
tests/coverage/pmpadrdecs.S Normal file
View File

@ -0,0 +1,22 @@
// pmpadrdecs
// Liam Chalk, lchalk@hmc.edu, 4/27/2023
// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4]
#include "WALLY-init-lib.h"
main:
# Writing values to pmpcfg0 to change AdrMode to 2 or 3
# pmpadrdec[0]
li t0, 0x0000000010
csrw pmpcfg0, t0
# pmpadrdec[1]
li t0, 0x0000001800
csrw pmpcfg0, t0
# pmpadrdec[2]
li t0, 0x0000180000
csrw pmpcfg0, t0
# pmpadrdec[4]
li t0, 0x1000000000
csrw pmpcfg0, t0
j done

161
tests/coverage/pmppriority.S Normal file
View File

@ -0,0 +1,161 @@
// pmppriority test cases
// Kevin Wan kewan@hmc.edu 4/27/2023
// want memory ranges to match:
// 1. only the most significant address and none of the lower ones,
// 2. the most significant address and ANY of the lower ones.
#include "WALLY-init-lib.h"
main:
li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg.
csrw pmpaddr0, t1
csrw pmpaddr1, t1
csrw pmpaddr2, t1
csrw pmpaddr3, t1
csrw pmpaddr4, t1
csrw pmpaddr5, t1
csrw pmpaddr6, t1
csrw pmpaddr7, t1
csrw pmpaddr8, t1
csrw pmpaddr9, t1
csrw pmpaddr10, t1
csrw pmpaddr11, t1
csrw pmpaddr12, t1
csrw pmpaddr13, t1
csrw pmpaddr14, t1
csrw pmpaddr15, t1
li t0, 0x1F
csrw pmpcfg0, t0 //set to XWR and NAPOT
sw zero, 0(sp)
li t0, 0x1F00
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F1F
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F0000
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F1F1F
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F000000
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F00000000
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F0000000000
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F1F
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F000000000000
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F1F1F
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F00000000000000
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F1F1F1F
csrw pmpcfg0, t0
sw zero, 0(sp)
li t0, 0x0
csrw pmpcfg0, t0
li t0, 0x1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F00
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F0000
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F00000000
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F0000000000
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F000000000000
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F00000000000000
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F1F1F1F
csrw pmpcfg0, t0
li t0, 0x1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F1F1F
csrw pmpcfg2, t0
sw zero, 0(sp)
li t0, 0x1F1F1F1F1F1F1F1F
csrw pmpcfg2, t0
sw zero, 0(sp)
j done