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Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough

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This commit is contained in:
David Harris 2024-01-06 07:11:25 -08:00
parent 0781cd4a44
commit 67124b0c7f
4 changed files with 6 additions and 4 deletions
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2
bin/wally-tool-chain-install.sh
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@ -113,7 +113,7 @@ cd ../arch_test_target/spike/device
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
# Wally needs Verilator 5.0 or later.
# Wally needs Verilator 5.021 or later.
# Verilator needs to be built from scratch to get the latest version
# apt-get install verilator installs version 4.028 as of 6/8/23
sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g

2
setup.sh
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@ -54,5 +54,7 @@ if [ -e "$IDV" ]; then
export PATH=$IDV/scripts/cvw:$PATH
fi
# Verilator needs a larger stack to simulate CORE-V Wally
ulimit -s 100000
echo "setup done"

4
sim/verilate
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@ -2,7 +2,7 @@
# simulate with Verilator
# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
# verilator -GTEST="arch64i" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`
@ -12,7 +12,7 @@ basepath=$(dirname $0)/..
for config in rv64gc; do
echo "$config simulating..."
# not working: -GTEST="arch64i"
if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="arch64i" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"arch64i\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi

2
src/mmu/tlb/tlbcontrol.sv
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@ -97,7 +97,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
assign PreUpdateDA = ~PTE_A;
assign InvalidAccess = ~PTE_X;
end else begin:dtlb // Data TLB fault checking
logic InvalidRead, InvalidWrite, ReservtedEncoding;
logic InvalidRead, InvalidWrite, ReservedEncoding;
logic InvalidCBOM, InvalidCBOZ;
// User mode may only load/store from user mode pages, and supervisor mode