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Partial fix to allow byte write enables with fpga and still get a preload to work.

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This commit is contained in:
Ross Thompson 2022-03-29 19:12:29 -05:00
parent fe896bff8e
commit 66e9380cfb
4 changed files with 165 additions and 13 deletions
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47
pipelined/src/generic/flop/bram.sv Normal file
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@ -0,0 +1,47 @@
// This model actually works correctly with vivado.
module bram2p1r1w
#(
//--------------------------------------------------------------------------
parameter NUM_COL = 8,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input logic clk,
input logic enaA,
input logic [ADDR_WIDTH-1:0] addrA,
output logic [DATA_WIDTH-1:0] doutA,
input logic enaB,
input logic [NUM_COL-1:0] weB,
input logic [ADDR_WIDTH-1:0] addrB,
input logic [DATA_WIDTH-1:0] dinB
);
// Core Memory
logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0];
integer i;
initial begin
$readmemh("big64.txt", RAM);
end
// Port-A Operation
always @ (posedge clk) begin
if(enaA) begin
doutA <= RAM[addrA];
end
end
// Port-B Operation:
always @ (posedge clk) begin
if(enaB) begin
for(i=0;i<NUM_COL;i=i+1) begin
if(weB[i]) begin
RAM[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +:COL_WIDTH];
end
end
end
end
endmodule // bytewrite_tdp_ram_rf

2
pipelined/src/uncore/ram.sv
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@ -30,7 +30,7 @@
`include "wally-config.vh"
module ram #(parameter BASE=0, RANGE = 65535) (
module ramOld #(parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn,
input logic HSELRam,
input logic [31:0] HADDR,

105
pipelined/src/uncore/ram3.sv Normal file
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@ -0,0 +1,105 @@
///////////////////////////////////////////
// ram.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: On-chip RAM, external to core
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
// True-Dual-Port BRAM with Byte-wide Write Enable
// Read-First mode
// bytewrite_tdp_ram_rf.v
//
`include "wally-config.vh"
module ram #(parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn,
input logic HSELRam,
input logic [31:0] HADDR,
input logic HWRITE,
input logic HREADY,
input logic [1:0] HTRANS,
input logic [`XLEN-1:0] HWDATA,
input logic [3:0] HSIZED,
output logic [`XLEN-1:0] HREADRam,
output logic HRESPRam, HREADYRam
);
logic [`XLEN/8-1:0] ByteMaskM;
logic [31:0] HWADDR, A;
logic prevHREADYRam, risingHREADYRam;
logic initTrans;
logic memwrite;
logic [3:0] busycount;
swbytemask swbytemask(.HSIZED, .HADDRD(A[2:0]), .ByteMask(ByteMaskM));
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
// *** this seems like a weird way to use reset
flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELRam & HWRITE, memwrite);
flopenr #(32) haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A);
// busy FSM to extend READY signal
always @(posedge HCLK, negedge HRESETn)
if (~HRESETn) begin
busycount <= 0;
HREADYRam <= #1 0;
end else begin
if (initTrans) begin
busycount <= 0;
HREADYRam <= #1 0;
end else if (~HREADYRam) begin
if (busycount == 0) begin // Ram latency, for testing purposes. *** test with different values such as 2
HREADYRam <= #1 1;
end else begin
busycount <= busycount + 1;
end
end
end
assign HRESPRam = 0; // OK
localparam ADDR_WDITH = $clog2(RANGE/8);
// Rising HREADY edge detector
// Indicates when ram is finishing up
// Needed because HREADY may go high for other reasons,
// and we only want to write data when finishing up.
flopenr #(1) prevhreadyRamreg(HCLK,~HRESETn, 1'b1, HREADYRam,prevHREADYRam);
assign risingHREADYRam = HREADYRam & ~prevHREADYRam;
always @(posedge HCLK)
HWADDR <= #1 A;
bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH)
memory(.clk(HCLK), .enaA(1'b1),
.addrA(A[ADDR_WDITH+2:3]), .doutA(HREADRam),
.enaB(memwrite & risingHREADYRam), .weB(ByteMaskM),
.addrB(HWADDR[ADDR_WDITH+2:3]), .dinB(HWDATA));
endmodule

24
pipelined/testbench/testbench.sv
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@ -178,7 +178,7 @@ logic [3:0] dummy;
// the design.
if (TEST == "coremark")
for (i=MemStartAddr; i<MemEndAddr; i = i+1)
dut.uncore.ram.ram.RAM[i] = 64'h0;
dut.uncore.ram.ram.memory.RAM[i] = 64'h0;
// read test vectors into memory
pathname = tvpaths[tests[0].atoi()];
@ -186,9 +186,9 @@ logic [3:0] dummy;
pathname = tvpaths[0];
else pathname = tvpaths[1]; */
memfilename = {pathname, tests[test], ".elf.memfile"};
if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
else $readmemh(memfilename, dut.uncore.ram.ram.RAM);
if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
@ -246,11 +246,11 @@ logic [3:0] dummy;
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
logic [`XLEN-1:0] sig;
if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadr+i];
else sig = dut.uncore.ram.ram.RAM[testadr+i];
if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadr+i];
else sig = dut.uncore.ram.ram.memory.RAM[testadr+i];
// $display("signature[%h] = %h sig = %h", i, signature[i], sig);
if (signature[i] !== sig &
//if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] &
//if (signature[i] !== dut.core.lsu.dtim.ram.memory.RAM[testadr+i] &
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1?
if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin
// if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin
@ -260,7 +260,7 @@ logic [3:0] dummy;
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DMEM) = %h, signature = %h",
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
// tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.RAM[testadr+i], signature[i]);
// tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.memory.RAM[testadr+i], signature[i]);
$stop;//***debug
end
end
@ -283,10 +283,10 @@ logic [3:0] dummy;
else begin
//pathname = tvpaths[tests[0]];
memfilename = {pathname, tests[test], ".elf.memfile"};
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
else $readmemh(memfilename, dut.uncore.ram.ram.RAM);
if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
//$readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};