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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed wave file after signal name changes
This commit is contained in:
David Harris
parent
f4ee05e1ea
commit
66dce731a0
53
sim/wave.do
53
sim/wave.do
@ -8,11 +8,11 @@ add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/dut/core/InstrValidM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/BPWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ieu/c/MDUStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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@ -59,14 +59,13 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSrcE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PC1NextF
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add wave -noupdate -group {PCNext Generation} -label {NextValidPCE (from bpred)} /testbench/dut/core/ifu/NextValidPCE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/CSRWriteFenceM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/PC2NextF
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/mretM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/EPC
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/EPCM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/TrapVectorM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/TrapM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/RetM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/RetM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/ifu/UnalignedPCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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@ -195,9 +194,9 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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@ -251,13 +250,12 @@ add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE
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add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM
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add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelWay
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add wave -noupdate -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE
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add wave -noupdate -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
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@ -291,7 +289,6 @@ add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
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@ -626,24 +623,24 @@ add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/BALUControl
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs2D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs2E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdW
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/MemReadE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RegWriteM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RegWriteW
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/ForwardAE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/ForwardBE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -group Forward /testbench/dut/core/ieu/dp/IFResultM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/ForwardAE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/ForwardAE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdW
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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