mirror of
				https://github.com/openhwgroup/cvw
				synced 2025-02-11 06:05:49 +00:00 
			
		
		
		
	Update README.md
This commit is contained in:
		
							parent
							
								
									f08cb71b87
								
							
						
					
					
						commit
						66adcaa9f5
					
				
							
								
								
									
										12
									
								
								README.md
									
									
									
									
									
								
							
							
						
						
									
										12
									
								
								README.md
									
									
									
									
									
								
							@ -3,5 +3,17 @@ Configurable RISC-V Processor
 | 
			
		||||
 | 
			
		||||
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and Imperas tests.  As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
 | 
			
		||||
 | 
			
		||||
To use Wally on Linux:
 | 
			
		||||
 | 
			
		||||
git clone https://github.com/davidharrishmc/riscv-wally
 | 
			
		||||
cd riscv-wally
 | 
			
		||||
cd imperas-riscv-tests
 | 
			
		||||
make
 | 
			
		||||
cd ../addins
 | 
			
		||||
git clone https://github.com/riscv-non-isa/riscv-arch-test
 | 
			
		||||
 | 
			
		||||
 | 
			
		||||
Notes:
 | 
			
		||||
Eventually download imperas-riscv-tests separately
 | 
			
		||||
Move our custom tests to another directory
 | 
			
		||||
Handle exe2memfile separately.
 | 
			
		||||
 | 
			
		||||
		Loading…
	
		Reference in New Issue
	
	Block a user