From dcb5d0f6a9209e269bfa68b92bba9e1da3eb64a3 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 18 Feb 2022 19:41:50 +0000 Subject: [PATCH 001/199] Added misa test for both 32 and 64 bits --- pipelined/testbench/tests.vh | 6 +- .../rv32i_m/privilege/Makefrag | 3 +- .../references/WALLY-misa-01.reference_output | 1024 +++++++++++++++++ .../rv32i_m/privilege/src/WALLY-misa-01.S | 44 + .../rv64i_m/privilege/Makefrag | 3 +- .../references/WALLY-misa-01.reference_output | 1024 +++++++++++++++++ .../rv64i_m/privilege/src/WALLY-misa-01.S | 44 + 7 files changed, 2144 insertions(+), 4 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 0a2aa706d..514f9e35b 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1489,7 +1489,8 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-PMA", "40A0", "rv64i_m/privilege/WALLY-minfo-01", "40A0", "rv64i_m/privilege/WALLY-CSR-permission-s-01", "50A0", - "rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0" + "rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0", + "rv64i_m/privilege/WALLY-misa-01", "40A0" }; string wally64periph[] = '{ @@ -1552,7 +1553,8 @@ string wally32i[] = '{ "rv32i_m/privilege/WALLY-PMP", "4080", "rv32i_m/privilege/WALLY-CSR-permission-s-01", "5080", "rv32i_m/privilege/WALLY-CSR-permission-u-01", "5080", - "rv32i_m/privilege/WALLY-minfo-01", "4080" + "rv32i_m/privilege/WALLY-minfo-01", "4080", + "rv32i_m/privilege/WALLY-misa-01", "4080" }; string wally32periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index abd1d1211..a3e211f03 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -32,7 +32,8 @@ rv32i_sc_tests = \ WALLY-PMP \ WALLY-CSR-permission-s-01 \ WALLY-CSR-permission-u-01 \ - WALLY-minfo-01 + WALLY-minfo-01 \ + WALLY-misa-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output new file mode 100644 index 000000000..63f51669e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output @@ -0,0 +1,1024 @@ +00000111 # Test 5.3.2.2: successful read of nonzero misa +0000000b # ecall from terminating tests in machine mode +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S new file mode 100644 index 000000000..6bbc3a82a --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// +// WALLY-MMU +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-18 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +s_file_begin: +// Test 5.3.2.2: Machine ISA register test + +// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs. +csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs. +li x7, 0x111 // success value for read of nonzero misa +bnez x30, misa_nonzero +li x7, 0xbad // misa was zero, store bad value + +misa_nonzero: +sw x7, 0(x6) +addi x6, x6, 4 +addi x16, x16, 4 + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index e8c000283..2853b220a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -33,7 +33,8 @@ rv64i_sc_tests = \ WALLY-PMP \ WALLY-minfo-01 \ WALLY-CSR-permission-s-01 \ - WALLY-CSR-permission-u-01 + WALLY-CSR-permission-u-01 \ + WALLY-misa-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output new file mode 100644 index 000000000..f5a34cb06 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output @@ -0,0 +1,1024 @@ +00000111 # Test 5.3.2.2: successful read of nonzero misa +00000000 +0000000b # ecall from terminating tests in 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S new file mode 100644 index 000000000..d9a45556f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// +// WALLY-MMU +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-18 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +s_file_begin: +// Test 5.3.2.2: Machine ISA register test + +// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs. +csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs. +li x7, 0x111 // success value for read of nonzero misa +bnez x30, misa_nonzero +li x7, 0xbad // misa was zero, store bad value + +misa_nonzero: +sd x7, 0(x6) +addi x6, x6, 8 +addi x16, x16, 8 + +END_TESTS + +TEST_STACK_AND_DATA From 324efa7d422e614700900b57b063fe5fd911332e Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 18 Feb 2022 19:43:24 +0000 Subject: [PATCH 002/199] added 32 bit pma tests to regression even though they've been working fo a while --- pipelined/testbench/tests.vh | 1 + 1 file changed, 1 insertion(+) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 514f9e35b..87ef92148 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1551,6 +1551,7 @@ string wally32i[] = '{ `WALLYTEST, "rv32i_m/privilege/WALLY-MMU-SV32", "4080", "rv32i_m/privilege/WALLY-PMP", "4080", + "rv32i_m/privilege/WALLY-PMA", "4080", "rv32i_m/privilege/WALLY-CSR-permission-s-01", "5080", "rv32i_m/privilege/WALLY-CSR-permission-u-01", "5080", "rv32i_m/privilege/WALLY-minfo-01", "4080", From a88302f0d7f55385cd5e81d152671c13d9d7d5df Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Feb 2022 23:08:40 +0000 Subject: [PATCH 003/199] Removed problematic warning about reaching default state in HPTW --- pipelined/src/mmu/hptw.sv | 4 ---- 1 file changed, 4 deletions(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 2700cf4ef..b7f9a16d4 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -190,10 +190,6 @@ module hptw // else NextWalkerState = FAULT; LEAF: NextWalkerState = IDLE; // updates TLB default: begin - // synthesis translate_off - if (WalkerState !== 'x) - $error("Default state in HPTW should be unreachable; was %d", WalkerState); - // synthesis translate_on NextWalkerState = IDLE; // should never be reached end endcase From a60332b455df36bc7db7924e8ddc882fed596ea0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 19 Feb 2022 14:38:17 -0600 Subject: [PATCH 004/199] Minor changes to LSU. --- pipelined/src/lsu/lsu.sv | 38 ++++++++++++++++++++------------- pipelined/src/lsu/lsuvirtmen.sv | 2 +- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 86dfd3a04..ce12e0283 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -140,10 +140,11 @@ module lsu ( // MMU and Misalignment fault logic required if privileged unit exists if(`ZICSR_SUPPORTED == 1) begin : dmmu - + logic DisableTranslation; + assign DisableTranslation = SelHPTW | FlushDCacheM; mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .DisableTranslation(SelHPTW | FlushDCacheM), + .PrivilegeModeW, .DisableTranslation, .PAdr(PreLSUPAdrM), .VAdr(IEUAdrM), .Size(LSUFunct3M[1:0]), @@ -158,7 +159,9 @@ module lsu ( .InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .DAPageFault(DataDAPageFaultM), - .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), // **** change this to just use PreLSURWM + // *** should use LSURWM as this is includes the lr/sc squash. However this introduces a combo loop + // from squash, depends on LSUPAdrM, depends on TLBHit, depends on these *AccessM inputs. + .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), .WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); @@ -177,6 +180,7 @@ module lsu ( logic [`XLEN-1:0] ReadDataWordM; logic [`XLEN-1:0] ReadDataWordMuxM; logic IgnoreRequest; + logic SelUncachedAdr; assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; if (`DMEM == `MEM_TIM) begin : dtim @@ -184,7 +188,7 @@ module lsu ( .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .DCacheMiss, .DCacheAccess); - + assign SelUncachedAdr = '0; // value does not matter. end else begin : bus localparam integer WORDSPERLINE = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN; @@ -199,7 +203,6 @@ module lsu ( logic [`PA_BITS-1:0] WordOffsetAddr; logic SelBus; logic [LOGWPL-1:0] WordCount; - logic SelUncachedAdr; busdp #(WORDSPERLINE, LINELEN, LOGWPL, 1) busdp( .clk, .reset, @@ -212,10 +215,13 @@ module lsu ( mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheBusWriteData[`XLEN-1:0]), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - mux2 #(`XLEN) lsubushwdatamux( .d0(ReadDataWordM), .d1(FinalWriteDataM), + mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA)); - assign WordOffsetAddr = LSUBusWriteCrit ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM; + mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM), + .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), + .y(WordOffsetAddr)); + if(`DMEM == `MEM_CACHE) begin : dcache logic [1:0] RW, Atomic; assign RW = CacheableM ? LSURWM : 2'b00; // AND gate @@ -241,17 +247,18 @@ module lsu ( end end + if(`DMEM != `MEM_BUS) begin + logic [`XLEN-1:0] ReadDataWordMaskedM; + assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate + subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), + .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(PostSWWWriteDataM)); + end else + assign PostSWWWriteDataM = FinalAMOWriteDataM; + subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); - if(`DMEM != `MEM_BUS) begin - logic [`XLEN-1:0] ReadDataWordMaskedM; - assign ReadDataWordMaskedM = CacheableM ? ReadDataWordM : '0; // AND-gate - subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), - .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(PostSWWWriteDataM)); - end else - assign PostSWWWriteDataM = FinalAMOWriteDataM; assign FinalWriteDataM = SelHPTW ? PTE : PostSWWWriteDataM; @@ -259,6 +266,7 @@ module lsu ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// + // *** why does this need DTLBMissM? if (`A_SUPPORTED) begin:atomic atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 51ca4e51f..735fc0df5 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -59,7 +59,7 @@ module lsuvirtmem( output logic [1:0] LSUAtomicM, output logic [11:0] LSUAdrE, output logic [`PA_BITS-1:0] PreLSUPAdrM, - input logic [`XLEN+1:0] IEUAdrExtM, + input logic [`XLEN+1:0] IEUAdrExtM, // *** can move internally. output logic InterlockStall, output logic CPUBusy, From c4ad200ea71aebbf9dadbc016af098afe891d25e Mon Sep 17 00:00:00 2001 From: kaveh Pezeshki Date: Sun, 20 Feb 2022 09:08:38 +0000 Subject: [PATCH 005/199] added Makefile for automated disassembly generation --- linux/buildroot-scripts/Makefile | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 linux/buildroot-scripts/Makefile diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile new file mode 100644 index 000000000..b0e3bdf9b --- /dev/null +++ b/linux/buildroot-scripts/Makefile @@ -0,0 +1,21 @@ +all: + make disassemble + make generate + +generate: + # generating device tree binary + dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb + +disassemble: + mkdir ${RISCV}/buildroot/output/images/disassembly + # fw_jump + riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/fw_jump.elf >> ${RISCV}/buildroot/output/images/disassembly/fw_jump.objdump + # vmlinux + riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/vmlinux >> ${RISCV}/buildroot/output/images/disassembly/vmlinux.objdump + # filesystem + mkdir ${RISCV}/buildroot/output/images/disassembly/rootfs + -cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -idv < ../../rootfs.cpio + +clean: + rm ${RISCV}/buildroot/output/images/wally-virt.dtb + rm -rf ${RISCV}/buildroot/output/images/disassembly From 04892c5d3847041849ca53c63cecd148c67c1698 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 21 Feb 2022 07:03:12 +0000 Subject: [PATCH 006/199] added scratch register tests for 64 and 32 bits --- pipelined/testbench/tests.vh | 8 +- .../rv32i_m/privilege/Makefrag | 4 +- .../WALLY-scratch-01.reference_output | 1024 +++++++++++++++++ .../WALLY-sscratch-s-01.reference_output | 1024 +++++++++++++++++ .../rv32i_m/privilege/src/WALLY-scratch-01.S | 35 + .../privilege/src/WALLY-sscratch-s-01.S | 39 + .../rv64i_m/privilege/Makefrag | 4 +- .../WALLY-scratch-01.reference_output | 1024 +++++++++++++++++ .../WALLY-sscratch-s-01.reference_output | 1024 +++++++++++++++++ .../rv64i_m/privilege/src/WALLY-scratch-01.S | 35 + .../privilege/src/WALLY-sscratch-s-01.S | 39 + 11 files changed, 4256 insertions(+), 4 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-scratch-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sscratch-s-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 87ef92148..8cd3d6aec 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1490,7 +1490,9 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-minfo-01", "40A0", "rv64i_m/privilege/WALLY-CSR-permission-s-01", "50A0", "rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0", - "rv64i_m/privilege/WALLY-misa-01", "40A0" + "rv64i_m/privilege/WALLY-misa-01", "40A0", + "rv64i_m/privilege/WALLY-scratch-01", "40A0", + "rv64i_m/privilege/WALLY-sscratch-s-01", "40A0" }; string wally64periph[] = '{ @@ -1555,7 +1557,9 @@ string wally32i[] = '{ "rv32i_m/privilege/WALLY-CSR-permission-s-01", "5080", "rv32i_m/privilege/WALLY-CSR-permission-u-01", "5080", "rv32i_m/privilege/WALLY-minfo-01", "4080", - "rv32i_m/privilege/WALLY-misa-01", "4080" + "rv32i_m/privilege/WALLY-misa-01", "4080", + "rv32i_m/privilege/WALLY-scratch-01", "4080", + "rv32i_m/privilege/WALLY-sscratch-s-01", "4080" }; string wally32periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index a3e211f03..0b9dd696f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -33,7 +33,9 @@ rv32i_sc_tests = \ WALLY-CSR-permission-s-01 \ WALLY-CSR-permission-u-01 \ WALLY-minfo-01 \ - WALLY-misa-01 + WALLY-misa-01 \ + WALLY-scratch-01 \ + WALLY-sscratch-s-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output new file mode 100644 index 000000000..1e15db105 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output @@ -0,0 +1,1024 @@ +00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch +0000000b # ecall from ending tests in machine mode +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S new file mode 100644 index 000000000..4cb24cd18 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S @@ -0,0 +1,35 @@ +/////////////////////////////////////////// +// +// WALLY-scratch +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-20 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +s_file_begin: +// Test 5.3.2.3: Scratch registers test + +WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S new file mode 100644 index 000000000..f42a61ef1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// +// WALLY-sscratch +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-20 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +s_file_begin: + +// Test 5.3.2.3: Scratch registers test +WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode + +GOTO_S_MODE 0x0, 0x0 + +WRITE_READ_CSR sscratch, 0xAAA // check that sscratch is readable and writeable in supervisor mode + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 2853b220a..5077e0bae 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -34,7 +34,9 @@ rv64i_sc_tests = \ WALLY-minfo-01 \ WALLY-CSR-permission-s-01 \ WALLY-CSR-permission-u-01 \ - WALLY-misa-01 + WALLY-misa-01 \ + WALLY-scratch-01 \ + WALLY-sscratch-s-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-scratch-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-scratch-01.reference_output new file mode 100644 index 000000000..fd5eefd64 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-scratch-01.reference_output @@ -0,0 +1,1024 @@ +00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch +00000000 +0000000b # ecall from ending tests in machine mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sscratch-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sscratch-s-01.reference_output new file mode 100644 index 000000000..e44b95848 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sscratch-s-01.reference_output @@ -0,0 +1,1024 @@ +00000111 # Test 5.3.2.3: successful read of the 0x111 written to sscratch +00000000 +0000000b # ecall from going to s mode from m mode +00000000 +00000aaa # successful read of 0xAAA written to sscratch +00000000 +00000009 # ecall from ending tests in supervisor mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S new file mode 100644 index 000000000..a5b2d4e0d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S @@ -0,0 +1,35 @@ +/////////////////////////////////////////// +// +// WALLY-scratch +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-20 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +s_file_begin: +// Test 5.3.2.3: Scratch registers test + +WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S new file mode 100644 index 000000000..091e50cb1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// +// WALLY-sscratch +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-20 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +s_file_begin: + +// Test 5.3.2.3: Scratch registers test +WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode + +GOTO_S_MODE 0x0, 0x0 + +WRITE_READ_CSR sscratch, 0xAAA // check that sscratch is readable and writeable in supervisor mode + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file From 4a17b2e4ed857bc562f12d848e7abcfd44bfb346 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 21 Feb 2022 07:14:42 +0000 Subject: [PATCH 007/199] made sure program isn't passing the testwith a false posistive --- .../privilege/src/WALLY-CSR-permission-s-01.S | 274 +++++++++--------- .../privilege/src/WALLY-CSR-permission-u-01.S | 224 +++++++------- .../privilege/src/WALLY-CSR-permission-s-01.S | 202 ++++++------- .../privilege/src/WALLY-CSR-permission-u-01.S | 224 +++++++------- .../rv64i_m/privilege/src/WALLY-minfo-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-misa-01.S | 2 +- 6 files changed, 464 insertions(+), 464 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S index 2464e9289..522fb6d0f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S @@ -34,161 +34,161 @@ s_file_begin: GOTO_S_MODE 0x0, 0x0 -# Attempt to write 0xbad to each of these CSRs and read the value back +# Attempt to write 0x111 to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # High-bit versions storing the upper 32 bits of some CSRs for RV32 -# WRITE_READ_CSR mstatush 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR menvcfgh 0xbad -# WRITE_READ_CSR mseccfgh 0xbad -WRITE_READ_CSR pmpcfg1 0xbad -WRITE_READ_CSR pmpcfg3 0xbad -WRITE_READ_CSR mcycleh 0xbad -WRITE_READ_CSR minstreth 0xbad -WRITE_READ_CSR mhpmcounter3h 0xbad -WRITE_READ_CSR mhpmcounter4h 0xbad -WRITE_READ_CSR mhpmcounter5h 0xbad -WRITE_READ_CSR mhpmcounter6h 0xbad -WRITE_READ_CSR mhpmcounter7h 0xbad -WRITE_READ_CSR mhpmcounter8h 0xbad -WRITE_READ_CSR mhpmcounter9h 0xbad -WRITE_READ_CSR mhpmcounter10h 0xbad -WRITE_READ_CSR mhpmcounter11h 0xbad -WRITE_READ_CSR mhpmcounter12h 0xbad -WRITE_READ_CSR mhpmcounter13h 0xbad -WRITE_READ_CSR mhpmcounter14h 0xbad -WRITE_READ_CSR mhpmcounter15h 0xbad -WRITE_READ_CSR mhpmcounter16h 0xbad -WRITE_READ_CSR mhpmcounter17h 0xbad -WRITE_READ_CSR mhpmcounter18h 0xbad -WRITE_READ_CSR mhpmcounter19h 0xbad -WRITE_READ_CSR mhpmcounter20h 0xbad -WRITE_READ_CSR mhpmcounter21h 0xbad -WRITE_READ_CSR mhpmcounter22h 0xbad -WRITE_READ_CSR mhpmcounter23h 0xbad -WRITE_READ_CSR mhpmcounter24h 0xbad -WRITE_READ_CSR mhpmcounter25h 0xbad -WRITE_READ_CSR mhpmcounter26h 0xbad -WRITE_READ_CSR mhpmcounter27h 0xbad -WRITE_READ_CSR mhpmcounter28h 0xbad -WRITE_READ_CSR mhpmcounter29h 0xbad -WRITE_READ_CSR mhpmcounter30h 0xbad -WRITE_READ_CSR mhpmcounter31h 0xbad +# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC +# WRITE_READ_CSR menvcfgh 0x111 +# WRITE_READ_CSR mseccfgh 0x111 +WRITE_READ_CSR pmpcfg1 0x111 +WRITE_READ_CSR pmpcfg3 0x111 +WRITE_READ_CSR mcycleh 0x111 +WRITE_READ_CSR minstreth 0x111 +WRITE_READ_CSR mhpmcounter3h 0x111 +WRITE_READ_CSR mhpmcounter4h 0x111 +WRITE_READ_CSR mhpmcounter5h 0x111 +WRITE_READ_CSR mhpmcounter6h 0x111 +WRITE_READ_CSR mhpmcounter7h 0x111 +WRITE_READ_CSR mhpmcounter8h 0x111 +WRITE_READ_CSR mhpmcounter9h 0x111 +WRITE_READ_CSR mhpmcounter10h 0x111 +WRITE_READ_CSR mhpmcounter11h 0x111 +WRITE_READ_CSR mhpmcounter12h 0x111 +WRITE_READ_CSR mhpmcounter13h 0x111 +WRITE_READ_CSR mhpmcounter14h 0x111 +WRITE_READ_CSR mhpmcounter15h 0x111 +WRITE_READ_CSR mhpmcounter16h 0x111 +WRITE_READ_CSR mhpmcounter17h 0x111 +WRITE_READ_CSR mhpmcounter18h 0x111 +WRITE_READ_CSR mhpmcounter19h 0x111 +WRITE_READ_CSR mhpmcounter20h 0x111 +WRITE_READ_CSR mhpmcounter21h 0x111 +WRITE_READ_CSR mhpmcounter22h 0x111 +WRITE_READ_CSR mhpmcounter23h 0x111 +WRITE_READ_CSR mhpmcounter24h 0x111 +WRITE_READ_CSR mhpmcounter25h 0x111 +WRITE_READ_CSR mhpmcounter26h 0x111 +WRITE_READ_CSR mhpmcounter27h 0x111 +WRITE_READ_CSR mhpmcounter28h 0x111 +WRITE_READ_CSR mhpmcounter29h 0x111 +WRITE_READ_CSR mhpmcounter30h 0x111 +WRITE_READ_CSR mhpmcounter31h 0x111 # Machine information Registers -WRITE_READ_CSR mvendorid, 0xbad -WRITE_READ_CSR marchid, 0xbad -WRITE_READ_CSR mimpid, 0xbad -WRITE_READ_CSR mhartid, 0xbad -# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 +WRITE_READ_CSR mvendorid, 0x111 +WRITE_READ_CSR marchid, 0x111 +WRITE_READ_CSR mimpid, 0x111 +WRITE_READ_CSR mhartid, 0x111 +# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22 # Machine Trap Setup -WRITE_READ_CSR mstatus, 0xbad -WRITE_READ_CSR misa, 0xbad -WRITE_READ_CSR medeleg, 0xbad -WRITE_READ_CSR mideleg, 0xbad -WRITE_READ_CSR mie, 0xbad -WRITE_READ_CSR mtvec, 0xbad -WRITE_READ_CSR mcounteren, 0xbad +WRITE_READ_CSR mstatus, 0x111 +WRITE_READ_CSR misa, 0x111 +WRITE_READ_CSR medeleg, 0x111 +WRITE_READ_CSR mideleg, 0x111 +WRITE_READ_CSR mie, 0x111 +WRITE_READ_CSR mtvec, 0x111 +WRITE_READ_CSR mcounteren, 0x111 # Machine Trap Handling -WRITE_READ_CSR mscratch, 0xbad -WRITE_READ_CSR mepc, 0xbad -WRITE_READ_CSR mcause, 0xbad -WRITE_READ_CSR mtval, 0xbad -WRITE_READ_CSR mip, 0xbad -# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mtval2, 0xbad +WRITE_READ_CSR mscratch, 0x111 +WRITE_READ_CSR mepc, 0x111 +WRITE_READ_CSR mcause, 0x111 +WRITE_READ_CSR mtval, 0x111 +WRITE_READ_CSR mip, 0x111 +# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0x111 # Machine Configuration -# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mseccgf, 0xbad +# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0x111 # Machine Memory Protection -WRITE_READ_CSR pmpcfg0, 0xbad -WRITE_READ_CSR pmpcfg2, 0xbad # there's 1 pmpcfg reg per 8 pmpaddr regs +WRITE_READ_CSR pmpcfg0, 0x111 +WRITE_READ_CSR pmpcfg2, 0x111 # there's 1 pmpcfg reg per 8 pmpaddr regs -WRITE_READ_CSR pmpaddr0, 0xbad -WRITE_READ_CSR pmpaddr1, 0xbad -WRITE_READ_CSR pmpaddr2, 0xbad -WRITE_READ_CSR pmpaddr3, 0xbad -WRITE_READ_CSR pmpaddr4, 0xbad -WRITE_READ_CSR pmpaddr5, 0xbad -WRITE_READ_CSR pmpaddr6, 0xbad -WRITE_READ_CSR pmpaddr7, 0xbad -WRITE_READ_CSR pmpaddr8, 0xbad -WRITE_READ_CSR pmpaddr9, 0xbad -WRITE_READ_CSR pmpaddr10, 0xbad -WRITE_READ_CSR pmpaddr11, 0xbad -WRITE_READ_CSR pmpaddr12, 0xbad -WRITE_READ_CSR pmpaddr13, 0xbad -WRITE_READ_CSR pmpaddr14, 0xbad -WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config +WRITE_READ_CSR pmpaddr0, 0x111 +WRITE_READ_CSR pmpaddr1, 0x111 +WRITE_READ_CSR pmpaddr2, 0x111 +WRITE_READ_CSR pmpaddr3, 0x111 +WRITE_READ_CSR pmpaddr4, 0x111 +WRITE_READ_CSR pmpaddr5, 0x111 +WRITE_READ_CSR pmpaddr6, 0x111 +WRITE_READ_CSR pmpaddr7, 0x111 +WRITE_READ_CSR pmpaddr8, 0x111 +WRITE_READ_CSR pmpaddr9, 0x111 +WRITE_READ_CSR pmpaddr10, 0x111 +WRITE_READ_CSR pmpaddr11, 0x111 +WRITE_READ_CSR pmpaddr12, 0x111 +WRITE_READ_CSR pmpaddr13, 0x111 +WRITE_READ_CSR pmpaddr14, 0x111 +WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config # Machine Counter/Timers -WRITE_READ_CSR mcycle, 0xbad -WRITE_READ_CSR minstret, 0xbad -WRITE_READ_CSR mhpmcounter3, 0xbad -WRITE_READ_CSR mhpmcounter4, 0xbad -WRITE_READ_CSR mhpmcounter5, 0xbad -WRITE_READ_CSR mhpmcounter6, 0xbad -WRITE_READ_CSR mhpmcounter7, 0xbad -WRITE_READ_CSR mhpmcounter8, 0xbad -WRITE_READ_CSR mhpmcounter9, 0xbad -WRITE_READ_CSR mhpmcounter10, 0xbad -WRITE_READ_CSR mhpmcounter11, 0xbad -WRITE_READ_CSR mhpmcounter12, 0xbad -WRITE_READ_CSR mhpmcounter13, 0xbad -WRITE_READ_CSR mhpmcounter14, 0xbad -WRITE_READ_CSR mhpmcounter15, 0xbad -WRITE_READ_CSR mhpmcounter16, 0xbad -WRITE_READ_CSR mhpmcounter17, 0xbad -WRITE_READ_CSR mhpmcounter18, 0xbad -WRITE_READ_CSR mhpmcounter19, 0xbad -WRITE_READ_CSR mhpmcounter20, 0xbad -WRITE_READ_CSR mhpmcounter21, 0xbad -WRITE_READ_CSR mhpmcounter22, 0xbad -WRITE_READ_CSR mhpmcounter23, 0xbad -WRITE_READ_CSR mhpmcounter24, 0xbad -WRITE_READ_CSR mhpmcounter25, 0xbad -WRITE_READ_CSR mhpmcounter26, 0xbad -WRITE_READ_CSR mhpmcounter27, 0xbad -WRITE_READ_CSR mhpmcounter28, 0xbad -WRITE_READ_CSR mhpmcounter29, 0xbad -WRITE_READ_CSR mhpmcounter30, 0xbad -WRITE_READ_CSR mhpmcounter31, 0xbad +WRITE_READ_CSR mcycle, 0x111 +WRITE_READ_CSR minstret, 0x111 +WRITE_READ_CSR mhpmcounter3, 0x111 +WRITE_READ_CSR mhpmcounter4, 0x111 +WRITE_READ_CSR mhpmcounter5, 0x111 +WRITE_READ_CSR mhpmcounter6, 0x111 +WRITE_READ_CSR mhpmcounter7, 0x111 +WRITE_READ_CSR mhpmcounter8, 0x111 +WRITE_READ_CSR mhpmcounter9, 0x111 +WRITE_READ_CSR mhpmcounter10, 0x111 +WRITE_READ_CSR mhpmcounter11, 0x111 +WRITE_READ_CSR mhpmcounter12, 0x111 +WRITE_READ_CSR mhpmcounter13, 0x111 +WRITE_READ_CSR mhpmcounter14, 0x111 +WRITE_READ_CSR mhpmcounter15, 0x111 +WRITE_READ_CSR mhpmcounter16, 0x111 +WRITE_READ_CSR mhpmcounter17, 0x111 +WRITE_READ_CSR mhpmcounter18, 0x111 +WRITE_READ_CSR mhpmcounter19, 0x111 +WRITE_READ_CSR mhpmcounter20, 0x111 +WRITE_READ_CSR mhpmcounter21, 0x111 +WRITE_READ_CSR mhpmcounter22, 0x111 +WRITE_READ_CSR mhpmcounter23, 0x111 +WRITE_READ_CSR mhpmcounter24, 0x111 +WRITE_READ_CSR mhpmcounter25, 0x111 +WRITE_READ_CSR mhpmcounter26, 0x111 +WRITE_READ_CSR mhpmcounter27, 0x111 +WRITE_READ_CSR mhpmcounter28, 0x111 +WRITE_READ_CSR mhpmcounter29, 0x111 +WRITE_READ_CSR mhpmcounter30, 0x111 +WRITE_READ_CSR mhpmcounter31, 0x111 # Machine Counter Setup -WRITE_READ_CSR mcountinhibit, 0xbad -WRITE_READ_CSR mhpmevent3, 0xbad -WRITE_READ_CSR mhpmevent4, 0xbad -WRITE_READ_CSR mhpmevent5, 0xbad -WRITE_READ_CSR mhpmevent6, 0xbad -WRITE_READ_CSR mhpmevent7, 0xbad -WRITE_READ_CSR mhpmevent8, 0xbad -WRITE_READ_CSR mhpmevent9, 0xbad -WRITE_READ_CSR mhpmevent10, 0xbad -WRITE_READ_CSR mhpmevent11, 0xbad -WRITE_READ_CSR mhpmevent12, 0xbad -WRITE_READ_CSR mhpmevent13, 0xbad -WRITE_READ_CSR mhpmevent14, 0xbad -WRITE_READ_CSR mhpmevent15, 0xbad -WRITE_READ_CSR mhpmevent16, 0xbad -WRITE_READ_CSR mhpmevent17, 0xbad -WRITE_READ_CSR mhpmevent18, 0xbad -WRITE_READ_CSR mhpmevent19, 0xbad -WRITE_READ_CSR mhpmevent20, 0xbad -WRITE_READ_CSR mhpmevent21, 0xbad -WRITE_READ_CSR mhpmevent22, 0xbad -WRITE_READ_CSR mhpmevent23, 0xbad -WRITE_READ_CSR mhpmevent24, 0xbad -WRITE_READ_CSR mhpmevent25, 0xbad -WRITE_READ_CSR mhpmevent26, 0xbad -WRITE_READ_CSR mhpmevent27, 0xbad -WRITE_READ_CSR mhpmevent28, 0xbad -WRITE_READ_CSR mhpmevent29, 0xbad -WRITE_READ_CSR mhpmevent30, 0xbad -WRITE_READ_CSR mhpmevent31, 0xbad +WRITE_READ_CSR mcountinhibit, 0x111 +WRITE_READ_CSR mhpmevent3, 0x111 +WRITE_READ_CSR mhpmevent4, 0x111 +WRITE_READ_CSR mhpmevent5, 0x111 +WRITE_READ_CSR mhpmevent6, 0x111 +WRITE_READ_CSR mhpmevent7, 0x111 +WRITE_READ_CSR mhpmevent8, 0x111 +WRITE_READ_CSR mhpmevent9, 0x111 +WRITE_READ_CSR mhpmevent10, 0x111 +WRITE_READ_CSR mhpmevent11, 0x111 +WRITE_READ_CSR mhpmevent12, 0x111 +WRITE_READ_CSR mhpmevent13, 0x111 +WRITE_READ_CSR mhpmevent14, 0x111 +WRITE_READ_CSR mhpmevent15, 0x111 +WRITE_READ_CSR mhpmevent16, 0x111 +WRITE_READ_CSR mhpmevent17, 0x111 +WRITE_READ_CSR mhpmevent18, 0x111 +WRITE_READ_CSR mhpmevent19, 0x111 +WRITE_READ_CSR mhpmevent20, 0x111 +WRITE_READ_CSR mhpmevent21, 0x111 +WRITE_READ_CSR mhpmevent22, 0x111 +WRITE_READ_CSR mhpmevent23, 0x111 +WRITE_READ_CSR mhpmevent24, 0x111 +WRITE_READ_CSR mhpmevent25, 0x111 +WRITE_READ_CSR mhpmevent26, 0x111 +WRITE_READ_CSR mhpmevent27, 0x111 +WRITE_READ_CSR mhpmevent28, 0x111 +WRITE_READ_CSR mhpmevent29, 0x111 +WRITE_READ_CSR mhpmevent30, 0x111 +WRITE_READ_CSR mhpmevent31, 0x111 END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S index 190b6ed24..9e40fd18e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -31,142 +31,142 @@ s_file_begin: GOTO_U_MODE 0x0, 0x0 -# Attempt to write 0xbad to each of these CSRs and read the value back +# Attempt to write 0xAAA to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # Supervisor Trap Setup -WRITE_READ_CSR sstatus, 0xbad -WRITE_READ_CSR sie, 0xbad -WRITE_READ_CSR stvec, 0xbad -WRITE_READ_CSR scounteren, 0xbad +WRITE_READ_CSR sstatus, 0xAAA +WRITE_READ_CSR sie, 0xAAA +WRITE_READ_CSR stvec, 0xAAA +WRITE_READ_CSR scounteren, 0xAAA # Supervisor Configuration -# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# WRITE_READ_CSR senvcfg, 0xAAA # *** these appear not to be implemented in the compile step of make??? # Supervisor Trap Handling -WRITE_READ_CSR sscratch, 0xbad -WRITE_READ_CSR sepc, 0xbad -WRITE_READ_CSR scause, 0xbad -WRITE_READ_CSR stval, 0xbad -WRITE_READ_CSR sip, 0xbad +WRITE_READ_CSR sscratch, 0xAAA +WRITE_READ_CSR sepc, 0xAAA +WRITE_READ_CSR scause, 0xAAA +WRITE_READ_CSR stval, 0xAAA +WRITE_READ_CSR sip, 0xAAA # Supervisor Protection and Translation -WRITE_READ_CSR satp, 0xbad +WRITE_READ_CSR satp, 0xAAA # Machine information Registers -WRITE_READ_CSR mvendorid, 0xbad -WRITE_READ_CSR marchid, 0xbad -WRITE_READ_CSR mimpid, 0xbad -WRITE_READ_CSR mhartid, 0xbad -# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 +WRITE_READ_CSR mvendorid, 0xAAA +WRITE_READ_CSR marchid, 0xAAA +WRITE_READ_CSR mimpid, 0xAAA +WRITE_READ_CSR mhartid, 0xAAA +# WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22 # Machine Trap Setup -WRITE_READ_CSR mstatus, 0xbad -WRITE_READ_CSR misa, 0xbad -WRITE_READ_CSR medeleg, 0xbad -WRITE_READ_CSR mideleg, 0xbad -WRITE_READ_CSR mie, 0xbad -WRITE_READ_CSR mtvec, 0xbad -WRITE_READ_CSR mcounteren, 0xbad +WRITE_READ_CSR mstatus, 0xAAA +WRITE_READ_CSR misa, 0xAAA +WRITE_READ_CSR medeleg, 0xAAA +WRITE_READ_CSR mideleg, 0xAAA +WRITE_READ_CSR mie, 0xAAA +WRITE_READ_CSR mtvec, 0xAAA +WRITE_READ_CSR mcounteren, 0xAAA # Machine Trap Handling -WRITE_READ_CSR mscratch, 0xbad -WRITE_READ_CSR mepc, 0xbad -WRITE_READ_CSR mcause, 0xbad -WRITE_READ_CSR mtval, 0xbad -WRITE_READ_CSR mip, 0xbad -# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mtval2, 0xbad +WRITE_READ_CSR mscratch, 0xAAA +WRITE_READ_CSR mepc, 0xAAA +WRITE_READ_CSR mcause, 0xAAA +WRITE_READ_CSR mtval, 0xAAA +WRITE_READ_CSR mip, 0xAAA +# WRITE_READ_CSR mtinst, 0xAAA # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0xAAA # Machine Configuration -# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mseccgf, 0xbad +# WRITE_READ_CSR menvcfg, 0xAAA # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0xAAA # Machine Memory Protection -WRITE_READ_CSR pmpcfg0, 0xbad -WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs +WRITE_READ_CSR pmpcfg0, 0xAAA +WRITE_READ_CSR pmpcfg2, 0xAAA # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs -WRITE_READ_CSR pmpaddr0, 0xbad -WRITE_READ_CSR pmpaddr1, 0xbad -WRITE_READ_CSR pmpaddr2, 0xbad -WRITE_READ_CSR pmpaddr3, 0xbad -WRITE_READ_CSR pmpaddr4, 0xbad -WRITE_READ_CSR pmpaddr5, 0xbad -WRITE_READ_CSR pmpaddr6, 0xbad -WRITE_READ_CSR pmpaddr7, 0xbad -WRITE_READ_CSR pmpaddr8, 0xbad -WRITE_READ_CSR pmpaddr9, 0xbad -WRITE_READ_CSR pmpaddr10, 0xbad -WRITE_READ_CSR pmpaddr11, 0xbad -WRITE_READ_CSR pmpaddr12, 0xbad -WRITE_READ_CSR pmpaddr13, 0xbad -WRITE_READ_CSR pmpaddr14, 0xbad -WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config +WRITE_READ_CSR pmpaddr0, 0xAAA +WRITE_READ_CSR pmpaddr1, 0xAAA +WRITE_READ_CSR pmpaddr2, 0xAAA +WRITE_READ_CSR pmpaddr3, 0xAAA +WRITE_READ_CSR pmpaddr4, 0xAAA +WRITE_READ_CSR pmpaddr5, 0xAAA +WRITE_READ_CSR pmpaddr6, 0xAAA +WRITE_READ_CSR pmpaddr7, 0xAAA +WRITE_READ_CSR pmpaddr8, 0xAAA +WRITE_READ_CSR pmpaddr9, 0xAAA +WRITE_READ_CSR pmpaddr10, 0xAAA +WRITE_READ_CSR pmpaddr11, 0xAAA +WRITE_READ_CSR pmpaddr12, 0xAAA +WRITE_READ_CSR pmpaddr13, 0xAAA +WRITE_READ_CSR pmpaddr14, 0xAAA +WRITE_READ_CSR pmpaddr15, 0xAAA # only pmpcfg0...15 are enabled in our config # Machine Counter/Timers -WRITE_READ_CSR mcycle, 0xbad -WRITE_READ_CSR minstret, 0xbad -WRITE_READ_CSR mhpmcounter3, 0xbad -WRITE_READ_CSR mhpmcounter4, 0xbad -WRITE_READ_CSR mhpmcounter5, 0xbad -WRITE_READ_CSR mhpmcounter6, 0xbad -WRITE_READ_CSR mhpmcounter7, 0xbad -WRITE_READ_CSR mhpmcounter8, 0xbad -WRITE_READ_CSR mhpmcounter9, 0xbad -WRITE_READ_CSR mhpmcounter10, 0xbad -WRITE_READ_CSR mhpmcounter11, 0xbad -WRITE_READ_CSR mhpmcounter12, 0xbad -WRITE_READ_CSR mhpmcounter13, 0xbad -WRITE_READ_CSR mhpmcounter14, 0xbad -WRITE_READ_CSR mhpmcounter15, 0xbad -WRITE_READ_CSR mhpmcounter16, 0xbad -WRITE_READ_CSR mhpmcounter17, 0xbad -WRITE_READ_CSR mhpmcounter18, 0xbad -WRITE_READ_CSR mhpmcounter19, 0xbad -WRITE_READ_CSR mhpmcounter20, 0xbad -WRITE_READ_CSR mhpmcounter21, 0xbad -WRITE_READ_CSR mhpmcounter22, 0xbad -WRITE_READ_CSR mhpmcounter23, 0xbad -WRITE_READ_CSR mhpmcounter24, 0xbad -WRITE_READ_CSR mhpmcounter25, 0xbad -WRITE_READ_CSR mhpmcounter26, 0xbad -WRITE_READ_CSR mhpmcounter27, 0xbad -WRITE_READ_CSR mhpmcounter28, 0xbad -WRITE_READ_CSR mhpmcounter29, 0xbad -WRITE_READ_CSR mhpmcounter30, 0xbad -WRITE_READ_CSR mhpmcounter31, 0xbad +WRITE_READ_CSR mcycle, 0xAAA +WRITE_READ_CSR minstret, 0xAAA +WRITE_READ_CSR mhpmcounter3, 0xAAA +WRITE_READ_CSR mhpmcounter4, 0xAAA +WRITE_READ_CSR mhpmcounter5, 0xAAA +WRITE_READ_CSR mhpmcounter6, 0xAAA +WRITE_READ_CSR mhpmcounter7, 0xAAA +WRITE_READ_CSR mhpmcounter8, 0xAAA +WRITE_READ_CSR mhpmcounter9, 0xAAA +WRITE_READ_CSR mhpmcounter10, 0xAAA +WRITE_READ_CSR mhpmcounter11, 0xAAA +WRITE_READ_CSR mhpmcounter12, 0xAAA +WRITE_READ_CSR mhpmcounter13, 0xAAA +WRITE_READ_CSR mhpmcounter14, 0xAAA +WRITE_READ_CSR mhpmcounter15, 0xAAA +WRITE_READ_CSR mhpmcounter16, 0xAAA +WRITE_READ_CSR mhpmcounter17, 0xAAA +WRITE_READ_CSR mhpmcounter18, 0xAAA +WRITE_READ_CSR mhpmcounter19, 0xAAA +WRITE_READ_CSR mhpmcounter20, 0xAAA +WRITE_READ_CSR mhpmcounter21, 0xAAA +WRITE_READ_CSR mhpmcounter22, 0xAAA +WRITE_READ_CSR mhpmcounter23, 0xAAA +WRITE_READ_CSR mhpmcounter24, 0xAAA +WRITE_READ_CSR mhpmcounter25, 0xAAA +WRITE_READ_CSR mhpmcounter26, 0xAAA +WRITE_READ_CSR mhpmcounter27, 0xAAA +WRITE_READ_CSR mhpmcounter28, 0xAAA +WRITE_READ_CSR mhpmcounter29, 0xAAA +WRITE_READ_CSR mhpmcounter30, 0xAAA +WRITE_READ_CSR mhpmcounter31, 0xAAA # Machine Counter Setup -WRITE_READ_CSR mcountinhibit, 0xbad -WRITE_READ_CSR mhpmevent3, 0xbad -WRITE_READ_CSR mhpmevent4, 0xbad -WRITE_READ_CSR mhpmevent5, 0xbad -WRITE_READ_CSR mhpmevent6, 0xbad -WRITE_READ_CSR mhpmevent7, 0xbad -WRITE_READ_CSR mhpmevent8, 0xbad -WRITE_READ_CSR mhpmevent9, 0xbad -WRITE_READ_CSR mhpmevent10, 0xbad -WRITE_READ_CSR mhpmevent11, 0xbad -WRITE_READ_CSR mhpmevent12, 0xbad -WRITE_READ_CSR mhpmevent13, 0xbad -WRITE_READ_CSR mhpmevent14, 0xbad -WRITE_READ_CSR mhpmevent15, 0xbad -WRITE_READ_CSR mhpmevent16, 0xbad -WRITE_READ_CSR mhpmevent17, 0xbad -WRITE_READ_CSR mhpmevent18, 0xbad -WRITE_READ_CSR mhpmevent19, 0xbad -WRITE_READ_CSR mhpmevent20, 0xbad -WRITE_READ_CSR mhpmevent21, 0xbad -WRITE_READ_CSR mhpmevent22, 0xbad -WRITE_READ_CSR mhpmevent23, 0xbad -WRITE_READ_CSR mhpmevent24, 0xbad -WRITE_READ_CSR mhpmevent25, 0xbad -WRITE_READ_CSR mhpmevent26, 0xbad -WRITE_READ_CSR mhpmevent27, 0xbad -WRITE_READ_CSR mhpmevent28, 0xbad -WRITE_READ_CSR mhpmevent29, 0xbad -WRITE_READ_CSR mhpmevent30, 0xbad -WRITE_READ_CSR mhpmevent31, 0xbad +WRITE_READ_CSR mcountinhibit, 0xAAA +WRITE_READ_CSR mhpmevent3, 0xAAA +WRITE_READ_CSR mhpmevent4, 0xAAA +WRITE_READ_CSR mhpmevent5, 0xAAA +WRITE_READ_CSR mhpmevent6, 0xAAA +WRITE_READ_CSR mhpmevent7, 0xAAA +WRITE_READ_CSR mhpmevent8, 0xAAA +WRITE_READ_CSR mhpmevent9, 0xAAA +WRITE_READ_CSR mhpmevent10, 0xAAA +WRITE_READ_CSR mhpmevent11, 0xAAA +WRITE_READ_CSR mhpmevent12, 0xAAA +WRITE_READ_CSR mhpmevent13, 0xAAA +WRITE_READ_CSR mhpmevent14, 0xAAA +WRITE_READ_CSR mhpmevent15, 0xAAA +WRITE_READ_CSR mhpmevent16, 0xAAA +WRITE_READ_CSR mhpmevent17, 0xAAA +WRITE_READ_CSR mhpmevent18, 0xAAA +WRITE_READ_CSR mhpmevent19, 0xAAA +WRITE_READ_CSR mhpmevent20, 0xAAA +WRITE_READ_CSR mhpmevent21, 0xAAA +WRITE_READ_CSR mhpmevent22, 0xAAA +WRITE_READ_CSR mhpmevent23, 0xAAA +WRITE_READ_CSR mhpmevent24, 0xAAA +WRITE_READ_CSR mhpmevent25, 0xAAA +WRITE_READ_CSR mhpmevent26, 0xAAA +WRITE_READ_CSR mhpmevent27, 0xAAA +WRITE_READ_CSR mhpmevent28, 0xAAA +WRITE_READ_CSR mhpmevent29, 0xAAA +WRITE_READ_CSR mhpmevent30, 0xAAA +WRITE_READ_CSR mhpmevent31, 0xAAA END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S index 927e8653c..4336a510a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S @@ -34,123 +34,123 @@ s_file_begin: GOTO_S_MODE 0x0, 0x0 -# Attempt to write 0xbad to each of these CSRs and read the value back +# Attempt to write 0x111 to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # Machine information Registers -WRITE_READ_CSR mvendorid, 0xbad -WRITE_READ_CSR marchid, 0xbad -WRITE_READ_CSR mimpid, 0xbad -WRITE_READ_CSR mhartid, 0xbad -# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 +WRITE_READ_CSR mvendorid, 0x111 +WRITE_READ_CSR marchid, 0x111 +WRITE_READ_CSR mimpid, 0x111 +WRITE_READ_CSR mhartid, 0x111 +# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22 # Machine Trap Setup -WRITE_READ_CSR mstatus, 0xbad -WRITE_READ_CSR misa, 0xbad -WRITE_READ_CSR medeleg, 0xbad -WRITE_READ_CSR mideleg, 0xbad -WRITE_READ_CSR mie, 0xbad -WRITE_READ_CSR mtvec, 0xbad -WRITE_READ_CSR mcounteren, 0xbad +WRITE_READ_CSR mstatus, 0x111 +WRITE_READ_CSR misa, 0x111 +WRITE_READ_CSR medeleg, 0x111 +WRITE_READ_CSR mideleg, 0x111 +WRITE_READ_CSR mie, 0x111 +WRITE_READ_CSR mtvec, 0x111 +WRITE_READ_CSR mcounteren, 0x111 # Machine Trap Handling -WRITE_READ_CSR mscratch, 0xbad -WRITE_READ_CSR mepc, 0xbad -WRITE_READ_CSR mcause, 0xbad -WRITE_READ_CSR mtval, 0xbad -WRITE_READ_CSR mip, 0xbad -# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mtval2, 0xbad +WRITE_READ_CSR mscratch, 0x111 +WRITE_READ_CSR mepc, 0x111 +WRITE_READ_CSR mcause, 0x111 +WRITE_READ_CSR mtval, 0x111 +WRITE_READ_CSR mip, 0x111 +# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0x111 # Machine Configuration -# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mseccgf, 0xbad +# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0x111 # Machine Memory Protection -WRITE_READ_CSR pmpcfg0, 0xbad -WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs +WRITE_READ_CSR pmpcfg0, 0x111 +WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs -WRITE_READ_CSR pmpaddr0, 0xbad -WRITE_READ_CSR pmpaddr1, 0xbad -WRITE_READ_CSR pmpaddr2, 0xbad -WRITE_READ_CSR pmpaddr3, 0xbad -WRITE_READ_CSR pmpaddr4, 0xbad -WRITE_READ_CSR pmpaddr5, 0xbad -WRITE_READ_CSR pmpaddr6, 0xbad -WRITE_READ_CSR pmpaddr7, 0xbad -WRITE_READ_CSR pmpaddr8, 0xbad -WRITE_READ_CSR pmpaddr9, 0xbad -WRITE_READ_CSR pmpaddr10, 0xbad -WRITE_READ_CSR pmpaddr11, 0xbad -WRITE_READ_CSR pmpaddr12, 0xbad -WRITE_READ_CSR pmpaddr13, 0xbad -WRITE_READ_CSR pmpaddr14, 0xbad -WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config +WRITE_READ_CSR pmpaddr0, 0x111 +WRITE_READ_CSR pmpaddr1, 0x111 +WRITE_READ_CSR pmpaddr2, 0x111 +WRITE_READ_CSR pmpaddr3, 0x111 +WRITE_READ_CSR pmpaddr4, 0x111 +WRITE_READ_CSR pmpaddr5, 0x111 +WRITE_READ_CSR pmpaddr6, 0x111 +WRITE_READ_CSR pmpaddr7, 0x111 +WRITE_READ_CSR pmpaddr8, 0x111 +WRITE_READ_CSR pmpaddr9, 0x111 +WRITE_READ_CSR pmpaddr10, 0x111 +WRITE_READ_CSR pmpaddr11, 0x111 +WRITE_READ_CSR pmpaddr12, 0x111 +WRITE_READ_CSR pmpaddr13, 0x111 +WRITE_READ_CSR pmpaddr14, 0x111 +WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config # Machine Counter/Timers -WRITE_READ_CSR mcycle, 0xbad -WRITE_READ_CSR minstret, 0xbad -WRITE_READ_CSR mhpmcounter3, 0xbad -WRITE_READ_CSR mhpmcounter4, 0xbad -WRITE_READ_CSR mhpmcounter5, 0xbad -WRITE_READ_CSR mhpmcounter6, 0xbad -WRITE_READ_CSR mhpmcounter7, 0xbad -WRITE_READ_CSR mhpmcounter8, 0xbad -WRITE_READ_CSR mhpmcounter9, 0xbad -WRITE_READ_CSR mhpmcounter10, 0xbad -WRITE_READ_CSR mhpmcounter11, 0xbad -WRITE_READ_CSR mhpmcounter12, 0xbad -WRITE_READ_CSR mhpmcounter13, 0xbad -WRITE_READ_CSR mhpmcounter14, 0xbad -WRITE_READ_CSR mhpmcounter15, 0xbad -WRITE_READ_CSR mhpmcounter16, 0xbad -WRITE_READ_CSR mhpmcounter17, 0xbad -WRITE_READ_CSR mhpmcounter18, 0xbad -WRITE_READ_CSR mhpmcounter19, 0xbad -WRITE_READ_CSR mhpmcounter20, 0xbad -WRITE_READ_CSR mhpmcounter21, 0xbad -WRITE_READ_CSR mhpmcounter22, 0xbad -WRITE_READ_CSR mhpmcounter23, 0xbad -WRITE_READ_CSR mhpmcounter24, 0xbad -WRITE_READ_CSR mhpmcounter25, 0xbad -WRITE_READ_CSR mhpmcounter26, 0xbad -WRITE_READ_CSR mhpmcounter27, 0xbad -WRITE_READ_CSR mhpmcounter28, 0xbad -WRITE_READ_CSR mhpmcounter29, 0xbad -WRITE_READ_CSR mhpmcounter30, 0xbad -WRITE_READ_CSR mhpmcounter31, 0xbad +WRITE_READ_CSR mcycle, 0x111 +WRITE_READ_CSR minstret, 0x111 +WRITE_READ_CSR mhpmcounter3, 0x111 +WRITE_READ_CSR mhpmcounter4, 0x111 +WRITE_READ_CSR mhpmcounter5, 0x111 +WRITE_READ_CSR mhpmcounter6, 0x111 +WRITE_READ_CSR mhpmcounter7, 0x111 +WRITE_READ_CSR mhpmcounter8, 0x111 +WRITE_READ_CSR mhpmcounter9, 0x111 +WRITE_READ_CSR mhpmcounter10, 0x111 +WRITE_READ_CSR mhpmcounter11, 0x111 +WRITE_READ_CSR mhpmcounter12, 0x111 +WRITE_READ_CSR mhpmcounter13, 0x111 +WRITE_READ_CSR mhpmcounter14, 0x111 +WRITE_READ_CSR mhpmcounter15, 0x111 +WRITE_READ_CSR mhpmcounter16, 0x111 +WRITE_READ_CSR mhpmcounter17, 0x111 +WRITE_READ_CSR mhpmcounter18, 0x111 +WRITE_READ_CSR mhpmcounter19, 0x111 +WRITE_READ_CSR mhpmcounter20, 0x111 +WRITE_READ_CSR mhpmcounter21, 0x111 +WRITE_READ_CSR mhpmcounter22, 0x111 +WRITE_READ_CSR mhpmcounter23, 0x111 +WRITE_READ_CSR mhpmcounter24, 0x111 +WRITE_READ_CSR mhpmcounter25, 0x111 +WRITE_READ_CSR mhpmcounter26, 0x111 +WRITE_READ_CSR mhpmcounter27, 0x111 +WRITE_READ_CSR mhpmcounter28, 0x111 +WRITE_READ_CSR mhpmcounter29, 0x111 +WRITE_READ_CSR mhpmcounter30, 0x111 +WRITE_READ_CSR mhpmcounter31, 0x111 # Machine Counter Setup -WRITE_READ_CSR mcountinhibit, 0xbad -WRITE_READ_CSR mhpmevent3, 0xbad -WRITE_READ_CSR mhpmevent4, 0xbad -WRITE_READ_CSR mhpmevent5, 0xbad -WRITE_READ_CSR mhpmevent6, 0xbad -WRITE_READ_CSR mhpmevent7, 0xbad -WRITE_READ_CSR mhpmevent8, 0xbad -WRITE_READ_CSR mhpmevent9, 0xbad -WRITE_READ_CSR mhpmevent10, 0xbad -WRITE_READ_CSR mhpmevent11, 0xbad -WRITE_READ_CSR mhpmevent12, 0xbad -WRITE_READ_CSR mhpmevent13, 0xbad -WRITE_READ_CSR mhpmevent14, 0xbad -WRITE_READ_CSR mhpmevent15, 0xbad -WRITE_READ_CSR mhpmevent16, 0xbad -WRITE_READ_CSR mhpmevent17, 0xbad -WRITE_READ_CSR mhpmevent18, 0xbad -WRITE_READ_CSR mhpmevent19, 0xbad -WRITE_READ_CSR mhpmevent20, 0xbad -WRITE_READ_CSR mhpmevent21, 0xbad -WRITE_READ_CSR mhpmevent22, 0xbad -WRITE_READ_CSR mhpmevent23, 0xbad -WRITE_READ_CSR mhpmevent24, 0xbad -WRITE_READ_CSR mhpmevent25, 0xbad -WRITE_READ_CSR mhpmevent26, 0xbad -WRITE_READ_CSR mhpmevent27, 0xbad -WRITE_READ_CSR mhpmevent28, 0xbad -WRITE_READ_CSR mhpmevent29, 0xbad -WRITE_READ_CSR mhpmevent30, 0xbad -WRITE_READ_CSR mhpmevent31, 0xbad +WRITE_READ_CSR mcountinhibit, 0x111 +WRITE_READ_CSR mhpmevent3, 0x111 +WRITE_READ_CSR mhpmevent4, 0x111 +WRITE_READ_CSR mhpmevent5, 0x111 +WRITE_READ_CSR mhpmevent6, 0x111 +WRITE_READ_CSR mhpmevent7, 0x111 +WRITE_READ_CSR mhpmevent8, 0x111 +WRITE_READ_CSR mhpmevent9, 0x111 +WRITE_READ_CSR mhpmevent10, 0x111 +WRITE_READ_CSR mhpmevent11, 0x111 +WRITE_READ_CSR mhpmevent12, 0x111 +WRITE_READ_CSR mhpmevent13, 0x111 +WRITE_READ_CSR mhpmevent14, 0x111 +WRITE_READ_CSR mhpmevent15, 0x111 +WRITE_READ_CSR mhpmevent16, 0x111 +WRITE_READ_CSR mhpmevent17, 0x111 +WRITE_READ_CSR mhpmevent18, 0x111 +WRITE_READ_CSR mhpmevent19, 0x111 +WRITE_READ_CSR mhpmevent20, 0x111 +WRITE_READ_CSR mhpmevent21, 0x111 +WRITE_READ_CSR mhpmevent22, 0x111 +WRITE_READ_CSR mhpmevent23, 0x111 +WRITE_READ_CSR mhpmevent24, 0x111 +WRITE_READ_CSR mhpmevent25, 0x111 +WRITE_READ_CSR mhpmevent26, 0x111 +WRITE_READ_CSR mhpmevent27, 0x111 +WRITE_READ_CSR mhpmevent28, 0x111 +WRITE_READ_CSR mhpmevent29, 0x111 +WRITE_READ_CSR mhpmevent30, 0x111 +WRITE_READ_CSR mhpmevent31, 0x111 END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S index f68191417..21fdc1d7d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -31,142 +31,142 @@ s_file_begin: GOTO_U_MODE 0x0, 0x0 -# Attempt to write 0xbad to each of these CSRs and read the value back +# Attempt to write 0x111 to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # Supervisor Trap Setup -WRITE_READ_CSR sstatus, 0xbad -WRITE_READ_CSR sie, 0xbad -WRITE_READ_CSR stvec, 0xbad -WRITE_READ_CSR scounteren, 0xbad +WRITE_READ_CSR sstatus, 0x111 +WRITE_READ_CSR sie, 0x111 +WRITE_READ_CSR stvec, 0x111 +WRITE_READ_CSR scounteren, 0x111 # Supervisor Configuration -# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR senvcfg, 0x111 # *** these appear not to be implemented in GCC # Supervisor Trap Handling -WRITE_READ_CSR sscratch, 0xbad -WRITE_READ_CSR sepc, 0xbad -WRITE_READ_CSR scause, 0xbad -WRITE_READ_CSR stval, 0xbad -WRITE_READ_CSR sip, 0xbad +WRITE_READ_CSR sscratch, 0x111 +WRITE_READ_CSR sepc, 0x111 +WRITE_READ_CSR scause, 0x111 +WRITE_READ_CSR stval, 0x111 +WRITE_READ_CSR sip, 0x111 # Supervisor Protection and Translation -WRITE_READ_CSR satp, 0xbad +WRITE_READ_CSR satp, 0x111 # Machine information Registers -WRITE_READ_CSR mvendorid, 0xbad -WRITE_READ_CSR marchid, 0xbad -WRITE_READ_CSR mimpid, 0xbad -WRITE_READ_CSR mhartid, 0xbad -# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 +WRITE_READ_CSR mvendorid, 0x111 +WRITE_READ_CSR marchid, 0x111 +WRITE_READ_CSR mimpid, 0x111 +WRITE_READ_CSR mhartid, 0x111 +# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22 # Machine Trap Setup -WRITE_READ_CSR mstatus, 0xbad -WRITE_READ_CSR misa, 0xbad -WRITE_READ_CSR medeleg, 0xbad -WRITE_READ_CSR mideleg, 0xbad -WRITE_READ_CSR mie, 0xbad -WRITE_READ_CSR mtvec, 0xbad -WRITE_READ_CSR mcounteren, 0xbad +WRITE_READ_CSR mstatus, 0x111 +WRITE_READ_CSR misa, 0x111 +WRITE_READ_CSR medeleg, 0x111 +WRITE_READ_CSR mideleg, 0x111 +WRITE_READ_CSR mie, 0x111 +WRITE_READ_CSR mtvec, 0x111 +WRITE_READ_CSR mcounteren, 0x111 # Machine Trap Handling -WRITE_READ_CSR mscratch, 0xbad -WRITE_READ_CSR mepc, 0xbad -WRITE_READ_CSR mcause, 0xbad -WRITE_READ_CSR mtval, 0xbad -WRITE_READ_CSR mip, 0xbad -# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mtval2, 0xbad +WRITE_READ_CSR mscratch, 0x111 +WRITE_READ_CSR mepc, 0x111 +WRITE_READ_CSR mcause, 0x111 +WRITE_READ_CSR mtval, 0x111 +WRITE_READ_CSR mip, 0x111 +# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0x111 # Machine Configuration -# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC -# WRITE_READ_CSR mseccgf, 0xbad +# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0x111 # Machine Memory Protection -WRITE_READ_CSR pmpcfg0, 0xbad -WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs +WRITE_READ_CSR pmpcfg0, 0x111 +WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs -WRITE_READ_CSR pmpaddr0, 0xbad -WRITE_READ_CSR pmpaddr1, 0xbad -WRITE_READ_CSR pmpaddr2, 0xbad -WRITE_READ_CSR pmpaddr3, 0xbad -WRITE_READ_CSR pmpaddr4, 0xbad -WRITE_READ_CSR pmpaddr5, 0xbad -WRITE_READ_CSR pmpaddr6, 0xbad -WRITE_READ_CSR pmpaddr7, 0xbad -WRITE_READ_CSR pmpaddr8, 0xbad -WRITE_READ_CSR pmpaddr9, 0xbad -WRITE_READ_CSR pmpaddr10, 0xbad -WRITE_READ_CSR pmpaddr11, 0xbad -WRITE_READ_CSR pmpaddr12, 0xbad -WRITE_READ_CSR pmpaddr13, 0xbad -WRITE_READ_CSR pmpaddr14, 0xbad -WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config +WRITE_READ_CSR pmpaddr0, 0x111 +WRITE_READ_CSR pmpaddr1, 0x111 +WRITE_READ_CSR pmpaddr2, 0x111 +WRITE_READ_CSR pmpaddr3, 0x111 +WRITE_READ_CSR pmpaddr4, 0x111 +WRITE_READ_CSR pmpaddr5, 0x111 +WRITE_READ_CSR pmpaddr6, 0x111 +WRITE_READ_CSR pmpaddr7, 0x111 +WRITE_READ_CSR pmpaddr8, 0x111 +WRITE_READ_CSR pmpaddr9, 0x111 +WRITE_READ_CSR pmpaddr10, 0x111 +WRITE_READ_CSR pmpaddr11, 0x111 +WRITE_READ_CSR pmpaddr12, 0x111 +WRITE_READ_CSR pmpaddr13, 0x111 +WRITE_READ_CSR pmpaddr14, 0x111 +WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config # Machine Counter/Timers -WRITE_READ_CSR mcycle, 0xbad -WRITE_READ_CSR minstret, 0xbad -WRITE_READ_CSR mhpmcounter3, 0xbad -WRITE_READ_CSR mhpmcounter4, 0xbad -WRITE_READ_CSR mhpmcounter5, 0xbad -WRITE_READ_CSR mhpmcounter6, 0xbad -WRITE_READ_CSR mhpmcounter7, 0xbad -WRITE_READ_CSR mhpmcounter8, 0xbad -WRITE_READ_CSR mhpmcounter9, 0xbad -WRITE_READ_CSR mhpmcounter10, 0xbad -WRITE_READ_CSR mhpmcounter11, 0xbad -WRITE_READ_CSR mhpmcounter12, 0xbad -WRITE_READ_CSR mhpmcounter13, 0xbad -WRITE_READ_CSR mhpmcounter14, 0xbad -WRITE_READ_CSR mhpmcounter15, 0xbad -WRITE_READ_CSR mhpmcounter16, 0xbad -WRITE_READ_CSR mhpmcounter17, 0xbad -WRITE_READ_CSR mhpmcounter18, 0xbad -WRITE_READ_CSR mhpmcounter19, 0xbad -WRITE_READ_CSR mhpmcounter20, 0xbad -WRITE_READ_CSR mhpmcounter21, 0xbad -WRITE_READ_CSR mhpmcounter22, 0xbad -WRITE_READ_CSR mhpmcounter23, 0xbad -WRITE_READ_CSR mhpmcounter24, 0xbad -WRITE_READ_CSR mhpmcounter25, 0xbad -WRITE_READ_CSR mhpmcounter26, 0xbad -WRITE_READ_CSR mhpmcounter27, 0xbad -WRITE_READ_CSR mhpmcounter28, 0xbad -WRITE_READ_CSR mhpmcounter29, 0xbad -WRITE_READ_CSR mhpmcounter30, 0xbad -WRITE_READ_CSR mhpmcounter31, 0xbad +WRITE_READ_CSR mcycle, 0x111 +WRITE_READ_CSR minstret, 0x111 +WRITE_READ_CSR mhpmcounter3, 0x111 +WRITE_READ_CSR mhpmcounter4, 0x111 +WRITE_READ_CSR mhpmcounter5, 0x111 +WRITE_READ_CSR mhpmcounter6, 0x111 +WRITE_READ_CSR mhpmcounter7, 0x111 +WRITE_READ_CSR mhpmcounter8, 0x111 +WRITE_READ_CSR mhpmcounter9, 0x111 +WRITE_READ_CSR mhpmcounter10, 0x111 +WRITE_READ_CSR mhpmcounter11, 0x111 +WRITE_READ_CSR mhpmcounter12, 0x111 +WRITE_READ_CSR mhpmcounter13, 0x111 +WRITE_READ_CSR mhpmcounter14, 0x111 +WRITE_READ_CSR mhpmcounter15, 0x111 +WRITE_READ_CSR mhpmcounter16, 0x111 +WRITE_READ_CSR mhpmcounter17, 0x111 +WRITE_READ_CSR mhpmcounter18, 0x111 +WRITE_READ_CSR mhpmcounter19, 0x111 +WRITE_READ_CSR mhpmcounter20, 0x111 +WRITE_READ_CSR mhpmcounter21, 0x111 +WRITE_READ_CSR mhpmcounter22, 0x111 +WRITE_READ_CSR mhpmcounter23, 0x111 +WRITE_READ_CSR mhpmcounter24, 0x111 +WRITE_READ_CSR mhpmcounter25, 0x111 +WRITE_READ_CSR mhpmcounter26, 0x111 +WRITE_READ_CSR mhpmcounter27, 0x111 +WRITE_READ_CSR mhpmcounter28, 0x111 +WRITE_READ_CSR mhpmcounter29, 0x111 +WRITE_READ_CSR mhpmcounter30, 0x111 +WRITE_READ_CSR mhpmcounter31, 0x111 # Machine Counter Setup -WRITE_READ_CSR mcountinhibit, 0xbad -WRITE_READ_CSR mhpmevent3, 0xbad -WRITE_READ_CSR mhpmevent4, 0xbad -WRITE_READ_CSR mhpmevent5, 0xbad -WRITE_READ_CSR mhpmevent6, 0xbad -WRITE_READ_CSR mhpmevent7, 0xbad -WRITE_READ_CSR mhpmevent8, 0xbad -WRITE_READ_CSR mhpmevent9, 0xbad -WRITE_READ_CSR mhpmevent10, 0xbad -WRITE_READ_CSR mhpmevent11, 0xbad -WRITE_READ_CSR mhpmevent12, 0xbad -WRITE_READ_CSR mhpmevent13, 0xbad -WRITE_READ_CSR mhpmevent14, 0xbad -WRITE_READ_CSR mhpmevent15, 0xbad -WRITE_READ_CSR mhpmevent16, 0xbad -WRITE_READ_CSR mhpmevent17, 0xbad -WRITE_READ_CSR mhpmevent18, 0xbad -WRITE_READ_CSR mhpmevent19, 0xbad -WRITE_READ_CSR mhpmevent20, 0xbad -WRITE_READ_CSR mhpmevent21, 0xbad -WRITE_READ_CSR mhpmevent22, 0xbad -WRITE_READ_CSR mhpmevent23, 0xbad -WRITE_READ_CSR mhpmevent24, 0xbad -WRITE_READ_CSR mhpmevent25, 0xbad -WRITE_READ_CSR mhpmevent26, 0xbad -WRITE_READ_CSR mhpmevent27, 0xbad -WRITE_READ_CSR mhpmevent28, 0xbad -WRITE_READ_CSR mhpmevent29, 0xbad -WRITE_READ_CSR mhpmevent30, 0xbad -WRITE_READ_CSR mhpmevent31, 0xbad +WRITE_READ_CSR mcountinhibit, 0x111 +WRITE_READ_CSR mhpmevent3, 0x111 +WRITE_READ_CSR mhpmevent4, 0x111 +WRITE_READ_CSR mhpmevent5, 0x111 +WRITE_READ_CSR mhpmevent6, 0x111 +WRITE_READ_CSR mhpmevent7, 0x111 +WRITE_READ_CSR mhpmevent8, 0x111 +WRITE_READ_CSR mhpmevent9, 0x111 +WRITE_READ_CSR mhpmevent10, 0x111 +WRITE_READ_CSR mhpmevent11, 0x111 +WRITE_READ_CSR mhpmevent12, 0x111 +WRITE_READ_CSR mhpmevent13, 0x111 +WRITE_READ_CSR mhpmevent14, 0x111 +WRITE_READ_CSR mhpmevent15, 0x111 +WRITE_READ_CSR mhpmevent16, 0x111 +WRITE_READ_CSR mhpmevent17, 0x111 +WRITE_READ_CSR mhpmevent18, 0x111 +WRITE_READ_CSR mhpmevent19, 0x111 +WRITE_READ_CSR mhpmevent20, 0x111 +WRITE_READ_CSR mhpmevent21, 0x111 +WRITE_READ_CSR mhpmevent22, 0x111 +WRITE_READ_CSR mhpmevent23, 0x111 +WRITE_READ_CSR mhpmevent24, 0x111 +WRITE_READ_CSR mhpmevent25, 0x111 +WRITE_READ_CSR mhpmevent26, 0x111 +WRITE_READ_CSR mhpmevent27, 0x111 +WRITE_READ_CSR mhpmevent28, 0x111 +WRITE_READ_CSR mhpmevent29, 0x111 +WRITE_READ_CSR mhpmevent30, 0x111 +WRITE_READ_CSR mhpmevent31, 0x111 END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index 1eeaed0bd..850d0c2a4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -1,6 +1,6 @@ /////////////////////////////////////////// // -// WALLY-MMU +// WALLY-minfo // // Author: Kip Macsai-Goren // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S index d9a45556f..7ea1e7827 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S @@ -1,6 +1,6 @@ /////////////////////////////////////////// // -// WALLY-MMU +// WALLY-misa // // Author: Kip Macsai-Goren // From adb9134c64b0fced233853e757bd5a7426aba579 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 21 Feb 2022 07:15:00 +0000 Subject: [PATCH 008/199] removed macro-only file. no longer used --- .../privilege/src/WALLY-TEST-MACROS-64.h | 560 ------------------ 1 file changed, 560 deletions(-) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h deleted file mode 100644 index de54815e8..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h +++ /dev/null @@ -1,560 +0,0 @@ -/////////////////////////////////////////// -// -// WALLY-TEST-LIB-64.h -// -// Author: Kip Macsai-Goren -// -// Created 2022-01-30 -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - - -.macro INIT_TESTS - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - - - // --------------------------------------------------------------------------------------------- - // Initialization Overview: - // - // Initialize x6 as a virtual pointer to the test results - // Initialize x16 as a physical pointer to the test results - // Set up stack pointer (sp = x2) - // Set up the exception Handler, keeping the original handler in x4. - // - // --------------------------------------------------------------------------------------------- - - // address for test results - la x6, test_1_res - la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers - // any time either is used, both must be updated. - - // address for stack - la sp, top_of_stack - - // trap handler setup - la x1, machine_trap_handler - csrrw x4, mtvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test. - li a0, 0 - li a1, 0 - li a2, 0 // reset trap handler inputs to zero - - // go to first test! - j begin_test - - - // --------------------------------------------------------------------------------------------- - // General traps Handler - // - // Handles traps by branching to different behaviors based on mcause. - // - // Note that allowing the exception handler to change mode for a program is a huge security - // hole, but this is an expedient way of writing tests that need different modes - // - // input parameters: - // - // a0 (x10): - // 0: halt program with no failures - // 1: halt program with failure in x11 = a1 - // 2: go to machine mode - // 3: go to supervisor mode - // 4: go to user mode - // others: do nothing - // - // a1 (x11): - // VPN for return address after changing privilege mode. - // This should be the base VPN with no offset. - // 0x0 : defaults to next instruction on the same page the trap was called on. - // - // a2 (x12): - // Pagetype of the current address VPN before changing privilge mode - // Used so that we can know how many bits of the adress are the offset. - // Ignored if a1 == 0x0 - // 0: Kilopage - // 1: Megapage - // 2: Gigapage - // 3: Terapage - // - // -------------------------------------------------------------------------------------------- - - -machine_trap_handler: - // The processor is always in machine mode when a trap takes us here - // save registers on stack before using - sd x1, -8(sp) - sd x5, -16(sp) - - // Record trap - csrr x1, mcause // record the mcause - sd x1, 0(x16) - addi x6, x6, 8 - addi x16, x16, 8 // update pointers for logging results - - // Respond to trap based on cause - // All interrupts should return after being logged - li x5, 0x8000000000000000 // if msb is set, it is an interrupt - and x5, x5, x1 - bnez x5, trapreturn // return from interrupt - // Other trap handling is specified in the vector Table - slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table - la x5, trap_handler_vector_table - add x5, x5, x1 // compute address of vector in Table - ld x5, 0(x5) // fectch address of handler from vector Table - jr x5 // and jump to the handler - -segfault: - ld x5, -16(sp) // restore registers from stack before faulting - ld x1, -8(sp) - j terminate_test // halt program. - -trapreturn: - // look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1 - csrr x1, mepc // get the mepc - addi x1, x1, 4 // *** should be 2 for compressed instructions, see note. - - -// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction, -// ******** but in the handler, we work in M mode with physical addresses -// This means the address in mepc is suddenly pointing somewhere else. -// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible) -// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed. - -// lw x5, 0(x1) // read the faulting instruction -// li x1, 3 // check bottom 2 bits of instruction to see if compressed -// and x5, x5, x1 // mask the other bits -// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed - -// trapreturn_compressed: -// csrr x1, mepc // get the mepc again -// addi x1, x1, 2 // add 2 to find the next instruction -// j trapreturn_specified // and return - -// trapreturn_uncompressed: -// csrr x1, mepc // get the mepc again -// addi x1, x1, 4 // add 4 to find the next instruction - -trapreturn_specified: - // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc) - // so that when we return to a new virtual address, they're all in the right spot as well. - - beqz a1, trapreturn_finished // either update values, of go to default return address. - - la x5, trap_return_pagetype_table - slli a2, a2, 3 - add x5, x5, a2 - ld a2, 0(x5) // a2 = number of offset bits in current page type - - li x5, 1 - sll x5, x5, a2 - addi x5, x5, -1 // x5 = mask bits for offset into current pagetype - - // reset the top of the stack, x1 - ld x7, -8(sp) - and x7, x5, x7 // x7 = offset for x1 - add x7, x7, a1 // x7 = new address for x1 - sd x7, -8(sp) - - // reset the second spot in the stack, x5 - ld x7, -16(sp) - and x7, x5, x7 // x7 = offset for x5 - add x7, x7, a1 // x7 = new address for x5 - sd x7, -16(sp) - - // reset x6, the pointer for the virtual address of the output of the tests - and x7, x5, x6 // x7 = offset for x6 - add x6, x7, a1 // x6 = new address for the result pointer - - // set return address, stored temporarily in x1, to the next instruction, but in the new virtual page. - and x1, x5, x1 // x1 = offset for the return address - add x1, x1, a1 // x1 = new return address. - - li a1, 0 - li a2, 0 // reset trapreturn inputs to the trap handler - -trapreturn_finished: - csrw mepc, x1 // update the mepc with address of next instruction - ld x5, -16(sp) // restore registers from stack before returning - ld x1, -8(sp) - mret // return from trap - -ecallhandler: - // Check input parameter a0. encoding above. - // *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs. - li x5, 2 // case 2: change to machine mode - beq a0, x5, ecallhandler_changetomachinemode - li x5, 3 // case 3: change to supervisor mode - beq a0, x5, ecallhandler_changetosupervisormode - li x5, 4 // case 4: change to user mode - beq a0, x5, ecallhandler_changetousermode - // unsupported ecalls should segfault - j segfault - -ecallhandler_changetomachinemode: - // Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret - li x1, 0b1100000000000 - csrs mstatus, x1 - j trapreturn - -ecallhandler_changetosupervisormode: - // Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret - li x1, 0b1100000000000 - csrc mstatus, x1 - li x1, 0b0100000000000 - csrs mstatus, x1 - j trapreturn - -ecallhandler_changetousermode: - // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret - li x1, 0b1100000000000 - csrc mstatus, x1 - j trapreturn - -instrfault: - ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page) - j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page) - -illegalinstr: - j trapreturn // return to the code after recording the mcause - -accessfault: - // *** What do I have to do here? - j trapreturn - - // Table of trap behavior - // lists what to do on each exception (not interrupts) - // unexpected exceptions should cause segfaults for easy detection - // Expected exceptions should increment the EPC to the next instruction and return - - .align 3 // aligns this data table to an 8 byte boundary -trap_handler_vector_table: - .8byte segfault // 0: instruction address misaligned - .8byte instrfault // 1: instruction access fault - .8byte illegalinstr // 2: illegal instruction - .8byte segfault // 3: breakpoint - .8byte segfault // 4: load address misaligned - .8byte accessfault // 5: load access fault - .8byte segfault // 6: store address misaligned - .8byte accessfault // 7: store access fault - .8byte ecallhandler // 8: ecall from U-mode - .8byte ecallhandler // 9: ecall from S-mode - .8byte segfault // 10: reserved - .8byte ecallhandler // 11: ecall from M-mode - .8byte instrfault // 12: instruction page fault - .8byte trapreturn // 13: load page fault - .8byte segfault // 14: reserved - .8byte trapreturn // 15: store page fault - -.align 3 -trap_return_pagetype_table: - .8byte 0xC // 0: kilopage has 12 offset bits - .8byte 0x15 // 1: megapage has 21 offset bits - .8byte 0x1E // 2: gigapage has 30 offset bits - .8byte 0x27 // 3: terapage has 39 offset bits - -begin_test: // label here to jump to so we dont go through the trap handler before starting the test - -.endm // Ends the initialization macro that set up the begginnning of the tests and the trap handler. - - -// Test Summary table! - -// Test Name : Description : Fault output value : Normal output values -// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------ -// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None -// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None -// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None -// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None -// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) -// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_baremetal : satp.MODE = bare metal : None : None -// goto_sv39 : satp.MODE = sv39 : None : None -// goto_sv48 : satp.MODE = sv48 : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR -// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11 - -// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value - -.macro write64_test ADDR VAL - // attempt to write VAL to ADDR - // Success outputs: - // None - // Fault outputs: - // 0x6: misaligned address - // 0x7: access fault - // 0xf: page fault - li x29, \VAL - li x30, \ADDR - sd x29, 0(x30) -.endm - -.macro write32_test ADDR VAL - // all write tests have the same description/outputs as write64 - li x29, \VAL - li x30, \ADDR - sw x29, 0(x30) -.endm - -.macro write16_test ADDR VAL - // all write tests have the same description/outputs as write64 - li x29, \VAL - li x30, \ADDR - sh x29, 0(x30) -.endm - -.macro write08_test ADDR VAL - // all write tests have the same description/outputs as write64 - li x29, \VAL - li x30, \ADDR - sb x29, 0(x30) -.endm - -.macro read64_test ADDR - // Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value - // Success outputs: - // value read out from ADDR - // Fault outputs: - // One of the following followed by 0xBAD - // 0x4: misaligned address - // 0x5: access fault - // 0xD: page fault - li x7, 0xBAD // bad value that will be overwritten on good reads. - li x29, \ADDR - ld x7, 0(x29) - sd x7, 0(x6) - addi x6, x6, 8 - addi x16, x16, 8 -.endm - -.macro read32_test ADDR - // All reads have the same description/outputs as read64. - // They will store the sign extended value of what was read out at ADDR - li x7, 0xBAD // bad value that will be overwritten on good reads. - li x29, \ADDR - lw x7, 0(x29) - sd x7, 0(x6) - addi x6, x6, 8 - addi x16, x16, 8 -.endm - -.macro read16_test ADDR - // All reads have the same description/outputs as read64. - // They will store the sign extended value of what was read out at ADDR - li x7, 0xBAD // bad value that will be overwritten on good reads. - li x29, \ADDR - lh x7, 0(x29) - sd x7, 0(x6) - addi x6, x6, 8 - addi x16, x16, 8 -.endm - -.macro read08_test ADDR - // All reads have the same description/outputs as read64. - // They will store the sign extended value of what was read out at ADDR - li x7, 0xBAD // bad value that will be overwritten on good reads. - li x29, \ADDR - lb x7, 0(x29) - sd x7, 0(x6) - addi x6, x6, 8 - addi x16, x16, 8 -.endm - -// These goto_x_mode tests all involve invoking the trap handler, -// So their outputs are inevitably: -// 0x8: test called from U mode -// 0x9: test called from S mode -// 0xB: test called from M mode -// they generally do not fault or cause issues as long as these modes are enabled -// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not? - -.macro goto_m_mode RETURN_VPN RETURN_PAGETYPE - li a0, 2 // determine trap handler behavior (go to supervisor mode) - li a1, \RETURN_VPN // return VPN - li a2, \RETURN_PAGETYPE // return page types - ecall // writes mcause to the output. - // now in S mode -.endm - -.macro goto_s_mode RETURN_VPN RETURN_PAGETYPE - li a0, 3 // determine trap handler behavior (go to supervisor mode) - li a1, \RETURN_VPN // return VPN - li a2, \RETURN_PAGETYPE // return page types - ecall // writes mcause to the output. - // now in S mode -.endm - -.macro goto_u_mode RETURN_VPN RETURN_PAGETYPE - li a0, 4 // determine trap handler behavior (go to supervisor mode) - li a1, \RETURN_VPN // return VPN - li a2, \RETURN_PAGETYPE // return page types - ecall // writes mcause to the output. - // now in S mode -.endm - -// These tests change virtual memory settings, turning it on/off and changing between types. -// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy? - -.macro goto_baremetal - // Turn translation off - li x7, 0 // satp.MODE value for bare metal (0) - slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well -.endm - -.macro goto_sv39 - // Turn on sv39 virtual memory - li x7, 8 // satp.MODE value for Sv39 (8) - slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well -.endm - -.macro goto_sv48 - // Turn on sv48 virtual memory - li x7, 9 // satp.MODE value for Sv39 (8) - slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well -.endm - -.macro write_read_csr CSR VAL - // attempt to write CSR with VAL. Note: this also tests read access to CSR - // Success outputs: - // value read back out from CSR after writing - // Fault outputs: - // The previous CSR value before write attempt - // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access - li x30, 0xbad // load bad value to be overwritten by csrr - li x29, \VAL - csrw \CSR\(), x29 - csrr x30, \CSR - sd x30, 0(x6) - addi x6, x6, 8 - addi x16, x16, 8 -.endm - -.macro csr_r_access CSR - // verify that a csr is accessible to read but not to write - // Success outputs: - // 0x2, then - // 0x11 *** consider changing to something more meaningful - // Fault outputs: - // 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault? - csrr x29, \CSR - csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR - csrr x30, \CSR - bne x30, x29, 1f // 1f represents write_access - li x30, 0x11 // Write failed, confirming read only permissions. - j 2f // j r_access_end -1: // w_access (write succeeded, violating read-only) - li x30, 0xBAD -2: // r_access end - sd x30, 0(x6) - addi x6, x6, 8 - addi x16, x16, 8 -.endm - -.macro execute_at_address ADDR - // Execute the code already written to ADDR, returning the value in x7. - // *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR - // Assumes the code modifies x7, usually to become 0x111. - // Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret) - // Success outputs: - // modified value of x7. (0x111 if you use the sample code) - // Fault outputs: - // One of the following followed by 0xBAD - // 0x0: misaligned address - // 0x1: access fault - // 0xC: page fault - fence.i // forces caches and main memory to sync so execution code written to ADDR can run. - li x7, 0xBAD - li x28, \ADDR - jalr x28 // jump to executable test code - sd x7, 0(x6) - addi x6, x6, 8 - addi x16, x16, 8 -.endm - -.macro END_TESTS -// invokes one final ecall to return to machine mode then terminates this program, so the output is -// 0x8: termination called from U mode -// 0x9: termination called from S mode -// 0xB: termination called from M mode - -terminate_test: - - li a0, 2 // Trap handler behavior (go to machine mode) - ecall // writes mcause to the output. - csrw mtvec, x4 // restore original trap handler to halt program - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -RVTEST_DATA_END - -.align 3 // align stack to 8 byte boundary -bottom_of_stack: - .fill 1024, 4, 0xdeadbeef -top_of_stack: - - -RVMODEL_DATA_BEGIN - -test_1_res: - .fill 1024, 4, 0xdeadbeef - -RVMODEL_DATA_END - -#ifdef rvtest_mtrap_routine - -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -.endm // ends the macro that terminates this test program. \ No newline at end of file From 5d9ad011d249e4ef841f1609b8b9976a8ca32d9e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Feb 2022 09:31:29 -0600 Subject: [PATCH 009/199] Moved mux into lsuvirtmem. --- pipelined/src/lsu/atomic.sv | 6 +++--- pipelined/src/lsu/lsu.sv | 21 ++++++++++----------- pipelined/src/lsu/lsuvirtmen.sv | 3 +++ 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index 77db25e1c..1191df350 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -34,7 +34,7 @@ module atomic ( input logic clk, input logic reset, FlushW, CPUBusy, input logic [`XLEN-1:0] ReadDataM, - input logic [`XLEN-1:0] WriteDataM, + input logic [`XLEN-1:0] LSUWriteDataM, input logic [`PA_BITS-1:0] LSUPAdrM, input logic [6:0] LSUFunct7M, input logic [2:0] LSUFunct3M, @@ -49,9 +49,9 @@ module atomic ( logic [`XLEN-1:0] AMOResult; logic MemReadM; - amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), + amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), .result(AMOResult)); - mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); + mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, .SquashSCW, .LSURWM); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index ce12e0283..2c49e9c90 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -103,7 +103,8 @@ module lsu ( logic BusCommittedM, DCacheCommittedM; logic LSUBusWriteCrit; logic DataDAPageFaultM; - + logic [`XLEN-1:0] LSUWriteDataM; + flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); assign IEUAdrExtM = {2'b00, IEUAdrM}; assign LSUStallM = DCacheStallM | InterlockStall | BusStall; @@ -118,8 +119,8 @@ module lsu ( .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, - .ReadDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM, - .IEUAdrExtM, .PTE, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, + .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM, + .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); @@ -129,6 +130,7 @@ module lsu ( assign LSUAdrE = PreLSUAdrE; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM[`PA_BITS-1:0]; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; + assign LSUWriteDataM = WriteDataM; end // CommittedM tells the CPU's privilege unit the current instruction @@ -176,7 +178,7 @@ module lsu ( // Memory System // Either Data Cache or Data Tightly Integrated Memory or just bus interface ///////////////////////////////////////////////////////////////////////////////////////////// - logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM, PostSWWWriteDataM; + logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; logic [`XLEN-1:0] ReadDataWordM; logic [`XLEN-1:0] ReadDataWordMuxM; logic IgnoreRequest; @@ -252,26 +254,23 @@ module lsu ( assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(PostSWWWriteDataM)); + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); end else - assign PostSWWWriteDataM = FinalAMOWriteDataM; + assign FinalWriteDataM = FinalAMOWriteDataM; subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); - - assign FinalWriteDataM = SelHPTW ? PTE : PostSWWWriteDataM; - ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// // *** why does this need DTLBMissM? if (`A_SUPPORTED) begin:atomic - atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM, + atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc - assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = WriteDataM; + assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM; end endmodule diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 735fc0df5..34c645b51 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -47,6 +47,7 @@ module lsuvirtmem( input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] PCF, input logic [`XLEN-1:0] ReadDataM, + input logic [`XLEN-1:0] WriteDataM, input logic [2:0] Funct3M, output logic [2:0] LSUFunct3M, input logic [6:0] Funct7M, @@ -54,6 +55,7 @@ module lsuvirtmem( input logic [`XLEN-1:0] IEUAdrE, input logic [`XLEN-1:0] IEUAdrM, output logic [`XLEN-1:0] PTE, + output logic [`XLEN-1:0] LSUWriteDataM, output logic [1:0] PageType, output logic [1:0] PreLSURWM, output logic [1:0] LSUAtomicM, @@ -100,6 +102,7 @@ module lsuvirtmem( mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE); mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM); + mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM); // always block interrupts when using the hardware page table walker. assign CPUBusy = StallW & ~SelHPTW; From a3a572fe5f86ef1740a1cb6721f34db09f7ab50f Mon Sep 17 00:00:00 2001 From: ushakya22 Date: Mon, 21 Feb 2022 16:04:41 +0000 Subject: [PATCH 010/199] Created test vector generation file for exponent and mantissa division --- pipelined/srt/exptestgen | Bin 0 -> 22128 bytes pipelined/srt/exptestgen.c | 121 +++++++++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100755 pipelined/srt/exptestgen create mode 100644 pipelined/srt/exptestgen.c diff --git a/pipelined/srt/exptestgen b/pipelined/srt/exptestgen new file mode 100755 index 0000000000000000000000000000000000000000..0b5085bcb6c9ec2f476716fba8fec66a0110e49f GIT binary patch literal 22128 zcmeHP4{#LMd4IY?APk%i#~9gQYu%W!1m-0EM%1x&CphWkAfO;6vIAZn(n-4bbSK~K z8Nt-G5~0)=1)GV}lw_tY(@s*{WLkG7_As4{k)Ywo)a}S=CUpy)%Bh_>3?2(2V+CWb z-}mRwg((#6to(_dKtJ^lu@i zw@H?;1~FfF#ogjAF&B_I@bO9sQa#6XmRvKfAU!8gv}bAGfGhB^rVs$dj=RGK@3O%U+Ta@jSKwn!LjV*z?o)s-7FD84>5?Yg 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z&o>?+gK>jBu60`Np9Ks%@9MHuEWB@u^plKYm= z9RSDln~*o!^E`>0UX<~3!N>#KvBU3J?0G)46BmIY5z!g=re?|UM*SN!CU}437 E0R>#^_W%F@ literal 0 HcmV?d00001 diff --git a/pipelined/srt/exptestgen.c b/pipelined/srt/exptestgen.c new file mode 100644 index 000000000..2d5cfb861 --- /dev/null +++ b/pipelined/srt/exptestgen.c @@ -0,0 +1,121 @@ +/* testgen.c */ + +/* Written 2/19/2022 by David Harris + + This program creates test vectors for mantissa and exponent components + of an IEEE floating point divider. + Builds upon program that creates test vectors for mantissa component only. + */ + +/* #includes */ + +#include +#include +#include + +/* Constants */ + +#define ENTRIES 17 +#define RANDOM_VECS 500 +// #define BIAS 1023 // Bias is for double precision + +/* Prototypes */ + +void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa); +void printhex(FILE *fptr, double x); +double random_input(void); +double random_input_e(void); + +/* Main */ + +void main(void) +{ + FILE *fptr; + // e1 & e2 are exponents + // a & b are mantissas + // r_mantissa is result of mantissa divsion + // r_exp is result of exponent division + double a, b, r_mantissa, r_exp; + int e1, e2; + double mantissa[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, + 1.75, 1.875, 1.99999, + 1.1, 1.2, 1.01, 1.001, 1.0001, + 1/1.1, 1/1.5, 1/1.25, 1/1.125}; + int exponent[ENTRIES] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17}; + int i, j; + int bias = 1023; + + if ((fptr = fopen("testvectors","w")) == NULL) { + fprintf(stderr, "Couldn't write testvectors file\n"); + exit(1); + } + + for (i=0; i2) m /= 2; + for (i=0; i Date: Mon, 21 Feb 2022 16:05:43 +0000 Subject: [PATCH 011/199] verilator lint for srt --- pipelined/srt/lint-srt | 1 + 1 file changed, 1 insertion(+) diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 399201be0..8fba602e8 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1 +1,2 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv +verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv From ec3fa45f8664b59aff29a3c20e2b10a9e1273e3c Mon Sep 17 00:00:00 2001 From: ushakya22 Date: Mon, 21 Feb 2022 16:08:09 +0000 Subject: [PATCH 012/199] reverted srt_standford back to original file pre modifications by Udeema --- pipelined/srt/srt_stanford.sv | 92 +++++------------------------------ 1 file changed, 12 insertions(+), 80 deletions(-) diff --git a/pipelined/srt/srt_stanford.sv b/pipelined/srt/srt_stanford.sv index e66cfa3c3..23ab683d5 100644 --- a/pipelined/srt/srt_stanford.sv +++ b/pipelined/srt/srt_stanford.sv @@ -14,49 +14,6 @@ `include "wally-config.vh" -// will also be used for integer division so keep in mind when naming modules/signals - -///////////////// -// srt_divide // -//////////////// -module srt_divide(input logic clk, - input logic req, - input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b - input logic [63:0] a, b, // input numbers - output logic [54:0] rp, rm, - output logic [10:0] expE); - - // output logic from Unpackers - logic XSgnE, YSgnE, ZSgnE; - logic [10:0] XExpE, YExpE, ZExpE; // exponent - logic [52:0] XManE, YManE, ZManE; - logic XNormE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; // denormals - logic XZeroE, YZeroE, ZZeroE; - logic [10:0] BiasE; // currrently hardcoded, will probs be removed - logic XInfE, YInfE, ZInfE; - logic XExpMaxE; // says exponent is all ones, can ignore - - // have Unpackers - // have mantissa divider - // exponent divider - - // hopefully having the .* here works for unpacker --- nope it doesn't - unpack unpacking(a, b, 0, 1'b1, 0, XSgnE, YSgnE, ZSgnE, XExpE, YExpE, ZExpE, XManE, YManE, ZManE, XNormE,XNaNE, YNaNE, ZNaNE,XSNaNE, YSNaNE, ZSNaNE,XDenormE, YDenormE, ZDenormE,XZeroE, YZeroE, ZZeroE,BiasE,XInfE, YInfE, ZInfE,XExpMaxE); - srt srt(clk, req, XManE[51:0], YManE[51:0], rp, rm); - exp exp(XexpE, YExpE, expE); -endmodule - -// exponent module -// first iteration -module exp(input [10:0] e1, e2, - output [10:0] e); // for a 64 bit number, exponent section is 11 bits - assign e = (e1 - e2) + 11'd1023; // bias is hardcoded -endmodule - - ///////// // srt // ///////// @@ -84,12 +41,12 @@ module srt(input logic clk, // When start is asserted, the inputs are loaded into the divider. // Otherwise, the divisor is retained and the partial remainder // is fed back for the next iteration. - mux2_special psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn); - flop_special psflop(clk, psn, ps); - mux2_special pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn); - flop_special pcflop(clk, pcn, pc); - mux2_special dmux(d, {4'b0001, b}, req, dn); - flop_special dflop(clk, dn, d); + mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn); + flop psflop(clk, psn, ps); + mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn); + flop pcflop(clk, pcn, pc); + mux2 dmux(d, {4'b0001, b}, req, dn); + flop dflop(clk, dn, d); // Quotient Selection logic // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) @@ -99,7 +56,7 @@ module srt(input logic clk, // Divisor Selection logic inv dinv(d, d_b); - mux3_special divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel); + mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel); // Partial Product Generation csa csa(ps, pc, dsel, qp, psa, pca); @@ -108,7 +65,7 @@ endmodule ////////// // mux2 // ////////// -module mux2_special(input logic [55:0] in0, in1, +module mux2(input logic [55:0] in0, in1, input logic sel, output logic [55:0] out); @@ -118,7 +75,7 @@ endmodule ////////// // flop // ////////// -module flop_special(clk, in, out); +module flop(clk, in, out); input clk; input [55:0] in; output [55:0] out; @@ -204,9 +161,9 @@ module inv(input logic [55:0] in, endmodule ////////// -// mux3_special // +// mux3 // ////////// -module mux3_special(in0, in1, in2, sel0, sel1, sel2, out); +module mux3(in0, in1, in2, sel0, sel1, sel2, out); input [55:0] in0; input [55:0] in1; input [55:0] in2; @@ -316,24 +273,6 @@ module testbench; logic [51:0] b; logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits - - //input logic [63:0] X, Y, Z, - numbers - //input logic FmtE, ---- format, 1 is for double precision, 0 is single - //input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide - // all variables are commented in fpu.sv - - // output logic from Unpackers - logic XSgnE, YSgnE, ZSgnE; - logic [10:0] XExpE, YExpE, ZExpE; // exponent - logic [52:0] XManE, YManE, ZManE; - logic XNormE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; // denormals - logic XZeroE, YZeroE, ZZeroE; - logic [10:0] BiasE; // currrently hardcoded, will probs be removed - logic XInfE, YInfE, ZInfE; - logic XExpMaxE; // says exponent is all ones, can ignore // Test parameters parameter MEM_SIZE = 40000; @@ -350,15 +289,8 @@ module testbench; logic [51:0] correctr, nextr; integer testnum, errors; - // Unpackers - unpacking unpack(.X({12'b100010000010,a}), .Y({12'b100010000001,b}), .Z(0), .FmtE(1'b1), .FOpCtrlE(0), .*); - // Divider - srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(XManE[51:0]), .b(YManE[51:0]), .rp(rp),.rm(rm)); - - //srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(a), .b(b), .rp(rp),.rm(rm)); - - // Divider + unpacker + srt srt(clk, req, a, b, rp, rm); // Final adder converts quotient digits to 2's complement & normalizes finaladd finaladd(rp, rm, r); From 3d5b40775541a1112fe19efbf74dcb06897ddd69 Mon Sep 17 00:00:00 2001 From: ushakya22 Date: Mon, 21 Feb 2022 16:08:45 +0000 Subject: [PATCH 013/199] Changed Makefile to compile exptestgen instead of testgen --- pipelined/srt/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index 73a0b75fa..db5a11f86 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -3,5 +3,5 @@ all: sqrttestgen testgen sqrttestgen: sqrttestgen.c gcc sqrttestgen.c -lm -o sqrttestgen -testgen: testgen.c - gcc testgen.c -lm -o testgen +testgen: exptestgen.c + gcc exptestgen.c -lm -o exptestgen From 1ea3e8120abe93558c3eb3e304fb82aec4d30f54 Mon Sep 17 00:00:00 2001 From: ushakya22 Date: Mon, 21 Feb 2022 16:13:30 +0000 Subject: [PATCH 014/199] - Created exponent divsion module - top module includes exponent module now Notes: - may be a better implementation of the exponent module rather than having what I believe are two adders currently --- pipelined/srt/srt.sv | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 044bac9c1..bc272b011 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -37,6 +37,8 @@ module srt #(parameter Nf=52) ( input logic Flush, // *** multiple pipe stages // Floating Point Inputs // later add exponents, signs, special cases + input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits + // end of floating point inputs input logic [Nf-1:0] SrcXFrac, SrcYFrac, input logic [`XLEN-1:0] SrcA, SrcB, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit @@ -45,6 +47,7 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputss input logic Sqrt, // perform square root, not divide output logic [Nf-1:0] Quot, Rem, // *** later handle integers + output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision output logic [3:0] Flags ); @@ -78,6 +81,9 @@ module srt #(parameter Nf=52) ( // Partial Product Generation csa csa(WS, WC, Dsel, qp, WSA, WCA); + // Exponent division + exp exp(SrcXExpE, SrcYExpE, Exp); + srtpostproc postproc(rp, rm, Quot); endmodule @@ -247,6 +253,14 @@ module csa #(parameter N=56) ( (in2[54:0] & in3[54:0]), cin}; endmodule +////////////// +// exponent // +////////////// +module exp(input [10:0] e1, e2, + output [10:0] e); // for double precision, exponent is 11 bits + assign e = (e1 - e2) + 11'd1023; // bias is hardcoded +endmodule + ////////////// // finaladd // ////////////// From 3abc2c0592e20a1c5acd3a351645a51417e1ce9e Mon Sep 17 00:00:00 2001 From: ushakya22 Date: Mon, 21 Feb 2022 16:24:50 +0000 Subject: [PATCH 015/199] - created new testbench file instead of having it at the bottom of the srt file - uses unpacker to parse 64 bit floating point numbers - updated testbench to read from new testvectors generated by exptestbench Notes: MEM_WIDTH updated to be 64*3 Input numbers and output result is 64 bit number MEM_SIZE set to 60000 --- pipelined/srt/testbench.sv | 66 ++- pipelined/srt/testvectors | 1078 ++++++++++-------------------------- 2 files changed, 339 insertions(+), 805 deletions(-) diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 0af3821ec..971a3f997 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -40,33 +40,66 @@ module testbench; logic clk; logic req; logic done; - logic [51:0] a; - logic [51:0] b; - logic [51:0] r; + logic [63:0] a; + logic [63:0] b; + logic [63:0] result; + logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits + logic [10:0] e; // output exponent + // input logic for Unpacker + // input logic [63:0] X, Y, Z, - numbers + // input logic FmtE, ---- format, 1 is for double precision, 0 is single + // input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide + // all variables are commented in fpu.sv + + // output logic from Unpacker + logic XSgnE, YSgnE, ZSgnE; + logic [10:0] XExpE, YExpE, ZExpE; // exponent + logic [52:0] XManE, YManE, ZManE; + logic XNormE; + logic XNaNE, YNaNE, ZNaNE; + logic XSNaNE, YSNaNE, ZSNaNE; + logic XDenormE, YDenormE, ZDenormE; // denormals + logic XZeroE, YZeroE, ZZeroE; + logic [10:0] BiasE; // currrently hardcoded, will probs be removed + logic XInfE, YInfE, ZInfE; + logic XExpMaxE; // says exponent is all ones, can ignore + // Test parameters - parameter MEM_SIZE = 40000; - parameter MEM_WIDTH = 52+52+52; + parameter MEM_SIZE = 60000; + parameter MEM_WIDTH = 64+64+64; - `define memr 51:0 - `define memb 103:52 - `define mema 155:104 + `define memr 63:0 + `define memb 127:64 + `define mema 191:128 // Test logicisters logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [51:0] correctr, nextr, diffn, diffp; + logic [63:0] correctr, nextr, diffn, diffp; integer testnum, errors; + // Unpacker + // Note: BiasE will probably get taken out eventually + unpacking unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), + .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), + .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), + .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), + .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE), + .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); + // Divider srt #(52) srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXFrac(a), .SrcYFrac(b), + .SrcXExpE(XExpE), .SrcYExpE(YExpE), + .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Flags()); + .Quot(r), .Rem(), .Exp(e), .Flags()); + + assign result = {1'b0, e, r}; // Counter counter counter(clk, req, done); @@ -100,16 +133,17 @@ module testbench; if (done) begin req <= #5 1; - diffp = correctr - r; - diffn = r - correctr; + diffp = correctr - result; + diffn = result - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; - $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); + $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); $display("failed\n"); + $display(testnum); $stop; end - if (a === 52'hxxxxxxxxxxxxx) + if (a === 64'hxxxxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); $stop; @@ -121,7 +155,7 @@ module testbench; correctr = nextr; testnum = testnum+1; Vec = Tests[testnum]; - $display("a = %h b = %h",a,b); + $display("a = %h b = %h result = %h",a,b,nextr); a = Vec[`mema]; b = Vec[`memb]; nextr = Vec[`memr]; diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors index 112803fe9..c6412a9e6 100644 --- a/pipelined/srt/testvectors +++ b/pipelined/srt/testvectors @@ -1,789 +1,289 @@ -0000000000000_0000000000000_0000000000000 -8000000000000_0000000000000_8000000000000 -4000000000000_0000000000000_4000000000000 -2000000000000_0000000000000_2000000000000 -1000000000000_0000000000000_1000000000000 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+40b004189374bc6a_410c71c71c71c71c_3fa2049ba5e353f8 +40c00068db8bac71_410c71c71c71c71c_3fb20075f6fd21ff +40dd1745d1745d17_410c71c71c71c71c_3fc05d1745d1745d +40e5555555555555_410c71c71c71c71c_3fd8000000000000 +40f999999999999a_410c71c71c71c71c_3fecccccccccccce +410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000 From 5f916d17d259806dfa4bad28a2788b6d09c6bdd8 Mon Sep 17 00:00:00 2001 From: ushakya22 Date: Mon, 21 Feb 2022 17:28:11 +0000 Subject: [PATCH 016/199] Moved order of reading a, b, and result from test vectors file so that result matches up with inputs a and b --- pipelined/srt/testbench.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 971a3f997..c9cf72bdd 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -138,9 +138,10 @@ module testbench; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; + $display("a = %h b = %h result = %h",a,b,correctr); $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); + $display("at fail"); $display("failed\n"); - $display(testnum); $stop; end if (a === 64'hxxxxxxxxxxxxxxxx) @@ -153,12 +154,14 @@ module testbench; begin req <= #5 0; correctr = nextr; + $display("pre increment"); testnum = testnum+1; + a = Vec[`mema]; + b = Vec[`memb]; Vec = Tests[testnum]; $display("a = %h b = %h result = %h",a,b,nextr); - a = Vec[`mema]; - b = Vec[`memb]; nextr = Vec[`memr]; + $display("after increment"); end end From 456a54166a6085620002247f295ac018deef2755 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Feb 2022 12:46:06 -0600 Subject: [PATCH 017/199] Minor cleanup of lsu. --- pipelined/src/lsu/lsu.sv | 4 ++-- pipelined/src/lsu/lsuvirtmen.sv | 9 +++++---- pipelined/src/mmu/hptw.sv | 14 +++++++------- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2c49e9c90..48ca50a7d 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -119,7 +119,7 @@ module lsu ( .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, - .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM, + .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); @@ -221,7 +221,7 @@ module lsu ( .s(SelUncachedAdr), .y(LSUBusHWDATA)); mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM), .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); + .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. if(`DMEM == `MEM_CACHE) begin : dcache diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 34c645b51..c7aa798a7 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -53,7 +53,6 @@ module lsuvirtmem( input logic [6:0] Funct7M, output logic [6:0] LSUFunct7M, input logic [`XLEN-1:0] IEUAdrE, - input logic [`XLEN-1:0] IEUAdrM, output logic [`XLEN-1:0] PTE, output logic [`XLEN-1:0] LSUWriteDataM, output logic [1:0] PageType, @@ -88,7 +87,7 @@ module lsuvirtmem( .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, .InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); hptw hptw( // *** remove logic from (), mention this in style guide CH3 - .clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, .MemRWM, .AtomicM, + .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ITLBMissF(ITLBMissOrDAFaultF & ~TrapM), .DTLBMissM(DTLBMissOrDAFaultM & ~TrapM), // *** Fix me. *** I'm not sure ITLBMiss should be suppressed on TrapM. .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), @@ -100,9 +99,11 @@ module lsuvirtmem( mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE); - mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. + mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache. mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM); - mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM); + if(`HPTW_WRITES_SUPPORTED) + mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM); + else assign LSUWriteDataM = WriteDataM; // always block interrupts when using the hardware page table walker. assign CPUBusy = StallW & ~SelHPTW; diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 117f2a577..b34193588 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -34,7 +34,8 @@ module hptw ( input logic clk, reset, input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table - input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate + input logic [`XLEN-1:0] PCF, // addresses to translate + input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate input logic [1:0] MemRWM, AtomicM, // system status input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -84,7 +85,7 @@ module hptw assign TLBMiss = (DTLBMissM | ITLBMissF); // Determine which address to translate - assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF; + assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF; assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops @@ -116,11 +117,11 @@ module hptw logic SetDirty; logic Dirty, Accessed; - assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE; // This will be HPTWReadPTE if not handling DAPageFault. + assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE; flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); assign SaveHPTWAdr = WalkerState == L0_ADR; assign SelHPTWWriteAdr = UpdatePTE | HPTWWrite; - mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); // HPTWAdr = HPTWReadAdr if not handling DAPageFault. + mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); assign {Dirty, Accessed} = PTE[7:6]; @@ -132,7 +133,7 @@ module hptw assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | ((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk)); - // *** turn into module + // *** turn into module common with code in tlbcontrol. if (`XLEN==64) begin:rv64 assign SV39Mode = (SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS] == `SV39); // page fault if upper bits aren't all the same @@ -150,12 +151,11 @@ module hptw assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid : ImproperPrivilege | ~Executable | UpperBitsUnequalPageFault | Misaligned | ~Valid; - // hptw needs to know if there is a Dirty or Access fault occuring on this // memory access. If there is the PTE needs to be updated seting Access // and possibly also Dirty. Dirty is set if the operation is a store/amo. // However any other fault should not cause the update. - assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault; // set to 0 if not handling DAPageFault. + assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault; assign HPTWWrite = (WalkerState == UPDATE_PTE); assign UpdatePTE = WalkerState == LEAF & DAPageFault; From 356993df7cb1b19755711315deb56dbc009b3f9f Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 21 Feb 2022 20:30:39 +0000 Subject: [PATCH 018/199] new trace generation method --- linux/testvector-generation/genRecording.sh | 34 +++++++++++++++++++++ linux/testvector-generation/genTrace.gdb | 25 --------------- linux/testvector-generation/genTrace.sh | 28 ++++++++--------- 3 files changed, 46 insertions(+), 41 deletions(-) create mode 100755 linux/testvector-generation/genRecording.sh delete mode 100755 linux/testvector-generation/genTrace.gdb diff --git a/linux/testvector-generation/genRecording.sh b/linux/testvector-generation/genRecording.sh new file mode 100755 index 000000000..318de2880 --- /dev/null +++ b/linux/testvector-generation/genRecording.sh @@ -0,0 +1,34 @@ +#!/bin/bash +imageDir=$RISCV/buildroot/output/images +tvDir=$RISCV/linux-testvectors +recordFile="$tvDir/all.qemu" + +read -p "Warning: running this script will overwrite $recordFile +Would you like to proceed? (y/n) " -n 1 -r +echo +if [[ $REPLY =~ ^[Yy]$ ]] +then + # Create Output Directory + echo "Elevating permissions to create $recordFile" + sudo mkdir -p $tvDir + sudo chown cad $tvDir + sudo touch $recordFile + sudo chmod a+rw $recordFile + + # Compile Devicetree from Source + dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb + + # QEMU Simulation + echo "Launching QEMU!" + qemu-system-riscv64 \ + -M virt -dtb ../devicetree/wally-virt.dtb \ + -nographic \ + -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ + -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile + + # Cleanup + echo "Elevating permissions to restrict write access to $recordFile" + sudo chown cad $recordFile + sudo chmod o-w $recordFile +fi + diff --git a/linux/testvector-generation/genTrace.gdb b/linux/testvector-generation/genTrace.gdb deleted file mode 100755 index e69e28ec5..000000000 --- a/linux/testvector-generation/genTrace.gdb +++ /dev/null @@ -1,25 +0,0 @@ -define genTrace - # Arguments - set $tcpPort=$arg0 - set $vmlinux=$arg1 - - # GDB config - set pagination off - set logging overwrite on - set logging redirect on - set confirm off - - # Connect to QEMU session - eval "target extended-remote :%d",$tcpPort - - # Symbol Files - eval "file %s",$vmlinux - - # Run until Linux login prompt - b do_idle - ignore 1 2 - c - - kill - q -end diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh index 44ce1b822..ea14aad1a 100755 --- a/linux/testvector-generation/genTrace.sh +++ b/linux/testvector-generation/genTrace.sh @@ -1,13 +1,12 @@ #!/bin/bash tcpPort=1234 imageDir=$RISCV/buildroot/output/images -outDir=$RISCV/linux-testvectors -recordFile="$outDir/all.qemu" -traceFile="$outDir/all.txt" -interruptsFile="$outDir/interrupts.txt" +tvDir=$RISCV/linux-testvectors +recordFile="$tvDir/all.qemu" +traceFile="$tvDir/all.txt" +interruptsFile="$tvDir/interrupts.txt" read -p "Warning: running this script will overwrite the contents of: - * $recordFile * $traceFile * $interruptsFile Would you like to proceed? (y/n) " -n 1 -r @@ -15,12 +14,11 @@ echo if [[ $REPLY =~ ^[Yy]$ ]] then # Create Output Directory - sudo mkdir -p $outDir - sudo chown cad $outDir - sudo touch $recordFile + echo "Elevating permissions to create $traceFile, $interruptsFile" + sudo mkdir -p $tvDir + sudo chown cad $tvDir sudo touch $traceFile sudo touch $interruptsFile - sudo chmod a+rw $recordFile sudo chmod a+rw $traceFile sudo chmod a+rw $interruptsFile @@ -28,21 +26,19 @@ then dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb # QEMU Simulation + echo "Launching QEMU in replay mode!" (qemu-system-riscv64 \ -M virt -dtb ../devicetree/wally-virt.dtb \ - -nographic -serial /dev/null \ + -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ - -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \ + -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ -d nochain,cpu,in_asm,int \ - -gdb tcp::$tcpPort -S \ - 2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) \ - & riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort \"$imageDir/vmlinux\"" + 2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) # Cleanup - sudo chown cad $recordFile + echo "Elevating permissions to restrict write access to $traceFile, $interruptsFile" sudo chown cad $traceFile sudo chown cad $interruptsFile - sudo chmod o-w $recordFile sudo chmod o-w $traceFile sudo chmod o-w $interruptsFile fi From 414e73edd9059eb47ad6e7e3d2c0fe867210831f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Feb 2022 16:44:30 -0600 Subject: [PATCH 019/199] Cleaned up names in lsuvirtmem. --- pipelined/src/lsu/lsuvirtmen.sv | 8 +++++--- pipelined/src/mmu/hptw.sv | 6 +++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index c7aa798a7..25edad544 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -75,13 +75,15 @@ module lsuvirtmem( logic [2:0] HPTWSize; logic SelReplayCPURequest; logic [11:0] PreLSUAdrE; - logic ITLBMissOrDAFaultF; - logic DTLBMissOrDAFaultM; + logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF; + logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM; logic HPTWWrite; assign AnyCPUReqM = (|MemRWM) | (|AtomicM); assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM); + assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM; + assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM; interlockfsm interlockfsm ( .clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF, .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, @@ -89,7 +91,7 @@ module lsuvirtmem( hptw hptw( // *** remove logic from (), mention this in style guide CH3 .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, - .ITLBMissF(ITLBMissOrDAFaultF & ~TrapM), .DTLBMissM(DTLBMissOrDAFaultM & ~TrapM), // *** Fix me. *** I'm not sure ITLBMiss should be suppressed on TrapM. + .ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), .DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWWrite, .HPTWSize); diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index b34193588..968b10c8e 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -41,7 +41,7 @@ module hptw input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic [1:0] STATUS_MPP, input logic [1:0] PrivilegeModeW, - (* mark_debug = "true" *) input logic ITLBMissF, DTLBMissM, // TLB Miss + (* mark_debug = "true" *) input logic ITLBMissOrDAFaultNoTrapF, DTLBMissOrDAFaultNoTrapM, // TLB Miss input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU input logic DCacheStallM, // stall from LSU output logic [`XLEN-1:0] PTE, // page table entry to TLBs @@ -82,14 +82,14 @@ module hptw // Extract bits from CSRs and inputs assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; - assign TLBMiss = (DTLBMissM | ITLBMissF); + assign TLBMiss = (DTLBMissOrDAFaultNoTrapM | ITLBMissOrDAFaultNoTrapF); // Determine which address to translate assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF; assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops - flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) + flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRead & ~DCacheStallM; flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache From ace743ae91538d5b658038517df1c488aa5544bd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Feb 2022 16:54:38 -0600 Subject: [PATCH 020/199] Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. --- pipelined/src/lsu/lsuvirtmen.sv | 7 +++---- pipelined/src/mmu/hptw.sv | 13 ++++++------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 25edad544..d4043a1d9 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -71,13 +71,12 @@ module lsuvirtmem( logic AnyCPUReqM; logic [`PA_BITS-1:0] HPTWAdr; - logic HPTWRead; + logic [1:0] HPTWRW; logic [2:0] HPTWSize; logic SelReplayCPURequest; logic [11:0] PreLSUAdrE; logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF; logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM; - logic HPTWWrite; assign AnyCPUReqM = (|MemRWM) | (|AtomicM); assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); @@ -93,10 +92,10 @@ module lsuvirtmem( .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), - .DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWWrite, .HPTWSize); + .DCacheStallM, .HPTWAdr, .HPTWRW, .HPTWSize); // multiplex the outputs to LSU - mux2 #(2) rwmux(MemRWM, {HPTWRead, HPTWWrite}, SelHPTW, PreLSURWM); + mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M); mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 968b10c8e..f3e156b33 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -48,8 +48,7 @@ module hptw output logic [1:0] PageType, // page type to TLBs (* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry output logic [`PA_BITS-1:0] HPTWAdr, - output logic HPTWRead, // HPTW requesting to read memory - output logic HPTWWrite, + output logic [1:0] HPTWRW, // HPTW requesting to read memory output logic [2:0] HPTWSize // 32 or 64 bit access. ); @@ -90,7 +89,7 @@ module hptw // State flops flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) - assign PRegEn = HPTWRead & ~DCacheStallM; + assign PRegEn = HPTWRW[1] & ~DCacheStallM; flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache @@ -120,7 +119,7 @@ module hptw assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE; flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); assign SaveHPTWAdr = WalkerState == L0_ADR; - assign SelHPTWWriteAdr = UpdatePTE | HPTWWrite; + assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0]; mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); @@ -157,19 +156,19 @@ module hptw // However any other fault should not cause the update. assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault; - assign HPTWWrite = (WalkerState == UPDATE_PTE); + assign HPTWRW[0] = (WalkerState == UPDATE_PTE); assign UpdatePTE = WalkerState == LEAF & DAPageFault; end else begin // block: hptwwrites assign NextPTE = HPTWReadPTE; assign HPTWAdr = HPTWReadAdr; assign DAPageFault = '0; assign UpdatePTE = '0; - assign HPTWWrite = '0; + assign HPTWRW[0] = '0; end // Enable and select signals based on states assign StartWalk = (WalkerState == IDLE) & TLBMiss; - assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD); + assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD); assign DTLBWriteM = (WalkerState == LEAF & ~DAPageFault) & DTLBWalk; assign ITLBWriteF = (WalkerState == LEAF & ~DAPageFault) & ~DTLBWalk; From 8a280f211f4f445252db49bcc8507dc6138e83b3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Feb 2022 17:20:34 -0600 Subject: [PATCH 021/199] Annotated IFU for mux changes. --- pipelined/src/ifu/ifu.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 0fd3188cb..96bbdcbbc 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -249,6 +249,8 @@ module ifu ( assign PrivilegedChangePCM = RetM | TrapM; + // *** look at moves pcmux2 and pcmux3 to generates as they are needed only on supporting caches and + // privilege instructions respectively. mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F)); mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); From 1ab2e7590b3fd48d7086b56e85ed7b62f856341d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Feb 2022 17:20:58 -0600 Subject: [PATCH 022/199] Added some clearity to lsuvirtmem.sv. --- pipelined/src/lsu/lsuvirtmen.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index d4043a1d9..1e32bd9f4 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -100,11 +100,11 @@ module lsuvirtmem( mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE); - mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache. mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM); if(`HPTW_WRITES_SUPPORTED) mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM); else assign LSUWriteDataM = WriteDataM; + mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache. // always block interrupts when using the hardware page table walker. assign CPUBusy = StallW & ~SelHPTW; From c26526c9f337710588bf52d53c62a4d1b07cc609 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 22 Feb 2022 03:34:08 +0000 Subject: [PATCH 023/199] change RX side of UART to aslo be LSB-first --- pipelined/src/uncore/uartPC16550D.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index d1f72fdea..f679bba7c 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -278,12 +278,12 @@ module uartPC16550D( assign rxstopbit = rxshiftreg[0]; always_comb case(LCR[1:0]) // check how many bits used. Grab all bits including possible parity - 2'b00: rxdata9 = {3'b0, rxshiftreg[6:1]}; // 5-bit character - 2'b01: rxdata9 = {2'b0, rxshiftreg[7:1]}; // 6-bit - 2'b10: rxdata9 = {1'b0, rxshiftreg[8:1]}; // 7-bit - 2'b11: rxdata9 = rxshiftreg[9:1]; + 2'b00: rxdata9 = {3'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6]}; // 5-bit character + 2'b01: rxdata9 = {2'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7]}; // 6-bit + 2'b10: rxdata9 = {1'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8]}; // 7-bit + 2'b11: rxdata9 = { rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8], rxshiftreg[9]}; // 8-bit endcase - assign rxdata = LCR[3] ? rxdata9[8:1] : rxdata9[7:0]; // discard parity bit + assign rxdata = LCR[3] ? rxdata9[8:0] : rxdata9[8:1]; // discard parity bit // ERROR CONDITIONS assign rxparity = ^rxdata; From 202bd2f8f8375236f4fcf8daac30a6c1a1a14a3e Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 22 Feb 2022 03:46:08 +0000 Subject: [PATCH 024/199] change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests --- pipelined/config/buildroot/wally-config.vh | 2 +- pipelined/config/fpga/wally-config.vh | 2 +- pipelined/config/rv32e/wally-config.vh | 4 +- pipelined/config/rv32gc/wally-config.vh | 4 +- pipelined/config/rv32ic/wally-config.vh | 4 +- pipelined/config/rv64BP/wally-config.vh | 4 +- pipelined/config/rv64gc/wally-config.vh | 4 +- pipelined/config/rv64ic/wally-config.vh | 4 +- pipelined/regression/wave.do | 530 +++++------ pipelined/testbench/testbench.sv | 3 +- pipelined/testbench/tests.vh | 14 +- .../rv64i_m/privilege/Makefrag | 4 +- .../references/WALLY-PERIPH.reference_output | 432 +++++++++ .../rv64i_m/privilege/src/WALLY-PERIPH.S | 820 ++++++++++++++++++ ...eriph-test-signature-address-calculator.py | 23 + 15 files changed, 1571 insertions(+), 283 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S create mode 100755 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index eaedcd726..de6c910dc 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -117,7 +117,7 @@ // Interrupt configuration `define PLIC_NUM_SRC 53 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/buildroot/twoBitPredictor.txt" `define BTB_PRELOAD "../config/buildroot/BTBPredictor.txt" diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 2e8063e23..a1dc805b3 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -123,7 +123,7 @@ // Interrupt configuration `define PLIC_NUM_SRC 53 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt" `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt" diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index aadc41cbc..c532ce167 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -117,11 +117,11 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 4 +`define PLIC_NUM_SRC 10 // comment out the following if >=32 sources `define PLIC_NUM_SRC_LT_32 `define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index da45b57ba..47f9d100d 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -115,11 +115,11 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 4 +`define PLIC_NUM_SRC 10 // comment out the following if >=32 sources `define PLIC_NUM_SRC_LT_32 `define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index bddc02337..7ccb04758 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -115,11 +115,11 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 4 +`define PLIC_NUM_SRC 10 // comment out the following if >=32 sources `define PLIC_NUM_SRC_LT_32 `define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index dea046868..0d2439f56 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -117,11 +117,11 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 4 +`define PLIC_NUM_SRC 10 // comment out the following if >=32 sources `define PLIC_NUM_SRC_LT_32 `define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/rv64BP/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv64BP/BTBPredictor.txt" diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index a7dc78386..1f61ab5ba 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -118,11 +118,11 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 4 +`define PLIC_NUM_SRC 10 // comment out the following if >=32 sources `define PLIC_NUM_SRC_LT_32 `define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 927924721..73c11dbda 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -118,11 +118,11 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 4 +`define PLIC_NUM_SRC 10 // comment out the following if >=32 sources `define PLIC_NUM_SRC_LT_32 `define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 +`define PLIC_UART_ID 10 `define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 8159f58c7..aa078369d 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -5,39 +5,39 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/StoreStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -51,15 +51,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName @@ -175,186 +175,186 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED -add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr -add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM +add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState +add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall +add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr +add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM +add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE +add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF +add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM +add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF +add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR @@ -368,6 +368,19 @@ add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingArray +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingMaxP +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingPGrouped +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingRequestsAtMaxP +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR @@ -396,35 +409,44 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESETn -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESPUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADYUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/Din -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/LCR -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART +add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR +add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitssent +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txsr +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SIN +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SOUT +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DTRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT1b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT2b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DSRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DCDb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/CTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/TXRDYb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RXRDYb add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM @@ -474,8 +496,8 @@ add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/Nex add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWWrite add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {283655 ns} 1} {{Cursor 5} {86805 ns} 0} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 5} {0 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 configure wave -justifyvalue left @@ -490,4 +512,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {86757 ns} {87017 ns} +WaveRestoreZoom {0 ns} {224 ns} diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 3117c1112..226b2f287 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -100,7 +100,7 @@ logic [3:0] dummy; "testsBP64": tests = testsBP64; "wally64i": tests = wally64i; // *** redo "wally64priv": tests = wally64priv;// *** redo - "imperas64periph": tests = imperas64periph; + "wally64periph": tests = wally64periph; "coremark": tests = coremark; endcase end else begin // RV32 @@ -123,7 +123,6 @@ logic [3:0] dummy; "wally32i": tests = wally32i; // *** redo "wally32e": tests = wally32e; "wally32priv": tests = wally32priv; // *** redo - "imperas32periph": tests = imperas32periph; endcase end if (tests.size() == 0) begin diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 0a2aa706d..39f93b3d3 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -890,17 +890,6 @@ string imperas32f[] = '{ "rv32p/WALLY-CSR-PERMISSIONS-S", "3000" }; - string imperas64periph[] = '{ - `MYIMPERASTEST, - "rv64i-periph/WALLY-PERIPH", "2000" - }; - - string imperas32periph[] = '{ - `MYIMPERASTEST, - "rv32i-periph/WALLY-PLIC", "2080" - }; - - string arch64priv[] = '{ `RISCVARCHTEST, "rv64i_m/privilege/ebreak", "2090", @@ -1493,7 +1482,8 @@ string imperas32f[] = '{ }; string wally64periph[] = '{ - `WALLYTEST + `WALLYTEST, + "rv64i_m/privilege/WALLY-PERIPH", "3110" }; string wally32e[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index e8c000283..00430ef85 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -35,7 +35,9 @@ rv64i_sc_tests = \ WALLY-CSR-permission-s-01 \ WALLY-CSR-permission-u-01 -target_tests_nosim = WALLY-PMA \ +target_tests_nosim = \ + WALLY-PMA \ + WALLY-PERIPH rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output new file mode 100644 index 000000000..a67889e2a --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output @@ -0,0 +1,432 @@ +01BEEF00 +0000000B +80000000 +0000000A +00000004 +00000061 +00000061 +00000068 +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01BEEF01 +0000000B +80000000 +00000003 +00080000 +00080000 +00080000 +00000000 +00000000 +00000000 +00080000 +00080000 +FFFFFFFF +FFF7FFFF +00000000 +00000000 +01BEEF02 +0000000B +80000000 +00000003 +00000001 +00000001 +00000001 +00000000 +00080000 +00000000 +00080001 +00000001 +FFFFFFFF +FFFFFFFE +00000000 +00000000 +01BEEF03 +0000000B +80000000 +0000000A +00000004 +00000061 +00000061 +00000065 +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +02BEEF04 +0000000B +80000000 +00000003 +0000F0F0 +3030F0F0 +0000F0F0 +00000000 +00000001 +00000000 +0000F0F1 +0000F0F0 +FFFFFFFF +FFFF0F0F +00000000 +00000000 +02BEEF05 +0000000B +80000000 +00000003 +30300000 +3030F0F0 +30300000 +00000000 +0000F0F0 +00000000 +3030F0F0 +30300000 +FFFFFFFF +CFCFFFFF +00000000 +00000000 +02BEEF06 +0000000B +80000000 +00000003 +30000000 +3030F0F0 +00000000 +00000000 +00300000 +00000000 +30300000 +30000000 +CFFFFFFF +CFFFFFFF +00000000 +00000000 +02BEEF07 +0000000B +80000000 +00000003 +0F000000 +0F0F0F0F +0F000000 +00000000 +30000000 +00000000 +3F000000 +0F000000 +FFFFFFFF +F0FFFFFF +00000000 +00000000 +02BEEF08 +0000000B +80000000 +00000003 +00FFFF00 +00FFFF00 +00FFFF00 +00000000 +00000000 +00000000 +00FFFF00 +00FFFF00 +FFFFFFFF +FF0000FF +00000000 +00000000 +02BEEF09 +0000000B +80000000 +00000003 +33FFFF33 +33FFFF33 +33000033 +00000000 +00000000 +00000000 +33FFFF33 +33FFFF33 +FF0000FF +CC0000CC +00000000 +00000000 +02BEEF0A +0000000B +80000000 +00000003 +33000033 +33000033 +00000000 +00000000 +00FFFF00 +00000000 +33FFFF33 +33000033 +CCFFFFCC +CCFFFFCC +00000000 +00000000 +02BEEF0B +0000000B +80000000 +00000003 +00CCCC00 +00CCCC00 +00CCCC00 +00000000 +33000033 +00000000 +33CCCC33 +00CCCC00 +FFFFFFFF +FF3333FF +00000000 +00000000 +02BEEF0C +0000000B +80000000 +00000003 +00CCCC00 +00CCCC00 +00000000 +00000000 +00000000 +00000000 +00CCCC00 +00CCCC00 +FF3333FF +FF3333FF +00000000 +00000000 +02BEEF0D +0000000B +80000000 +00000003 +CC00CCCC +CCCCCCCC +CC00CCCC +00000000 +00CCCC00 +00000000 +CC00CCCC +CC00CCCC +FFFFFFFF +33FF3333 +00000000 +00000000 +02BEEF0E +0000000B +80000000 +00000003 +CCCCCCCC +CCCCCCCC +00CC0000 +00000000 +00000000 +00000000 +CCCCCCCC +CCCCCCCC +33FF3333 +33333333 +00000000 +00000000 +02BEEF0F +0000000B +80000000 +00000003 +000011FF +FF1111FF +33333333 +00000000 +FFFFEE00 +00000000 +FFFFFFFF +000011FF +FFFFEE00 +FFFFEE00 +00000000 +00000000 +02BEEF10 +0000000B +80000000 +00000003 +000000FF +FFFFFFFF +000000FF +00000000 +00000000 +00000000 +000000FF +000000FF +FFFFFFFF +FFFFFF00 +00000000 +00000000 +02BEEF11 +0000000B +80000000 +00000003 +000000CC +CCCCCCCC +00000000 +00000000 +00000033 +00000000 +000000FF +000000CC +FFFFFF33 +FFFFFF33 +00000000 +00000000 +03BEEF12 +0000000B +80000000 +0000000A +00000002 +00000061 +00000061 +0000006C +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF13 +0000000B +80000000 +0000000A +00000002 +00000021 +00000021 +0000006C +00000020 +00000001 +00000002 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF14 +0000000B +80000000 +0000000A +00000004 +00000061 +00000061 +0000006F +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF15 +0000000B +80000000 +0000000A +00000004 +00000061 +00000061 +00000020 +00000060 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF16 +0000000B +80000000 +0000000A +00000004 +00000061 +00000061 +00000074 +00000060 +00000001 +00000020 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF17 +0000000B +80000000 +0000000A +00000002 +00000020 +00000020 +00000074 +00000020 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF18 +0000000B +80000000 +0000000A +00000002 +00000020 +00000020 +00000074 +00000020 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF19 +0000000B +80000000 +0000000A +00000004 +00000061 +00000061 +00000065 +00000060 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF1A +0000000B +80000000 +0000000A +00000006 +00000063 +00000061 +00000047 +00000060 +00000001 +000000FF +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S new file mode 100644 index 000000000..de9e671ba --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S @@ -0,0 +1,820 @@ +/////////////////////////////////////////// +// WALLY-PERIPH.S +// 64 bit version +// +// Ben Bracker (bbracker@hmc.edu) +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + j main_code + +################### +################### +trap_handler: ##### +################### +################### + # save registers + addi sp, sp, 0x20 + sw t0, 0x00(sp) + sw t1, 0x08(sp) + sw t2, 0x10(sp) + sw t3, 0x18(sp) + + # =================================== + # ===== Signature Output Format ===== + # =================================== + # + # Base address = +0x40* + # Use sigout-translator.py for help with this! + # + # : + # 0x00: test ID = 0xBEEF + # 0x04: mcause (low) = 0x0000000B + # 0x08: mcause (high) = 0x80000000 + # ----- If GPIO ----- + # 0x0C: claim ID = 3 + # 0x10: input_val + # 0x14: output_val + # 0x18: incoming rise_ip + # 0x1C: serviced rise_ip = 0 + # 0x20: incoming fall_ip + # 0x24: serviced fall_ip = 0 + # 0x28: incoming high_ip + # 0x2C: serviced high_ip = 0 + # 0x30: incoming low_ip + # 0x34: serviced low_ip = 0 + # ----- If UART ----- + # 0x0C: claim ID = 0xA + # 0x10: IIR + # 0x14: LSR + # 0x18: LSR (after reading LSR) + # 0x1C: RBR + # 0x20: LSR (after reading RBR too) + # 0x24: IIR (after reading everything else) + # 0x28: SCR + + # 0x00: test ID = 0xBEEF + la t0, wally_signature + sub t0, s0, t0 # sigout offset + srli t0, t0, 6 # intr_num + add t0, t0, a1 + sw t0, 0x00(s0) + + # 0x04: mcause (low) = 0x0000000B + # 0x08: mcause (high) = 0x80000000 + # Expect interrupt from src 11 (machine external interrupt) + csrrc t1, mcause, x0 + sw t1, 0x04(s0) + srli t1,t1,32 + sw t1, 0x08(s0) + + # 0x: claim ID + # 3: GPIO + # A: UART + li t0, 0x0C200004 + lw t1, 0(t0) + sw t1, 0x0C(s0) + li t2, 0xA + beq t1, t2, uart_handler + li t2, 3 + bne t1, t2, trap_handler_end + + gpio_handler: + # 0x10: input_val + li t0, 0x10060000 + lw t1, 0x00(t0) + sw t1, 0x10(s0) + # 0x14: output_val + lw t1, 0x0C(t0) + sw t1, 0x14(s0) + # 0x18: incoming rise_ip + lw t1, 0x1C(t0) + sw t1, 0x18(s0) + # 0x1C: serviced rise_ip = 0 + sw t1, 0x1C(t0) + lw t1, 0x1C(t0) + sw t1, 0x1C(s0) + # 0x20: incoming fall_ip + lw t1, 0x24(t0) + sw t1, 0x20(s0) + # 0x24: serviced fall_ip = 0 + sw t1, 0x24(t0) + lw t1, 0x24(t0) + sw t1, 0x24(s0) + # 0x28: incoming high_ip + lw t1, 0x2C(t0) + sw t1, 0x28(s0) + # 0x2C: serviced high_ip = 0 + sw t1, 0x2C(t0) + lw t1, 0x2C(t0) + sw t1, 0x2C(s0) + # 0x30: incoming low_ip + lw t1, 0x34(t0) + sw t1, 0x30(s0) + # 0x34: serviced low_ip = 0 + sw t1, 0x34(t0) + lw t1, 0x34(t0) + sw t1, 0x34(s0) + # disable high_ie and low_ie so interrupt + # is not taken again immediately + li t1, 0 + sw t1, 0x28(t0) + sw t1, 0x30(t0) + # signal to main code that gpio was serviced + ori a0, a0, 0b00001000 + # signal to plic that gpio was serviced + li t0, 0x0C200004 + li t1, 3 + sw t1, 0(t0) + j trap_handler_end + + uart_handler: + # 0x10: IIR + li t0, 0x10000000 + lbu t1, 2(t0) + sw t1, 0x10(s0) + # 0x14: LSR + lbu t1, 5(t0) + sw t1, 0x14(s0) + # 0x18: LSR (after reading LSR) + lbu t1, 5(t0) + sw t1, 0x18(s0) + # 0x1C: RBR + lbu t1, 0(t0) + sw t1, 0x1C(s0) + # 0x20: LSR (after reading RBR) + lbu t1, 5(t0) + sw t1, 0x20(s0) + # 0x24: IIR (after reading everything else) + lbu t1, 2(t0) + sw t1, 0x24(s0) + # 0x28: SCR + lbu t1, 7(t0) + sw t1, 0x28(s0) + # signal to main code that uart was serviced + ori a0, a0, 0b00010000 + # signal to plic that uart was serviced + li t0, 0x0C200004 + li t1, 0xA + sw t1, 0(t0) + + trap_handler_end: + # increment signature pointer + addi s0,s0,0x40 + # restore vars + ld t0, 0x00(sp) + ld t1, 0x08(sp) + ld t2, 0x10(sp) + ld t3, 0x18(sp) + addi sp, sp, SEXT_IMM(-0x20) + mret + +################ +################ +main_code: ##### +################ +################ + + ########################## + ##### Initialization ##### + ########################## + # ========== Global Vars ========== + la s0, wally_signature # signature output base adr + la sp, stack # stack pointer + li a0, 0 # interrupt complete flag + # ========== Configure Privileged Unit ========== + # load address of trap handler + la t0, trap_handler + csrrw x0, mtvec, t0 + # delegate all external interrupts to machine mode + li t0, 0xD00 + csrrc x0, mideleg, t0 + # set MIE + li t0, 0x8 + csrrs x0, mstatus, t0 + + ################################## + ##### Test 1 - Signs of Life ##### + ################################## + li a1, 0x01beef00 # group ID + # clear MEIE (good to turn off while configuring peripherals) + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 3 (GPIO) priority = 6 + li t0, 0xC000000 + li t1, 6 + sw t1, 0x0C(t0) + # source 0xA (UART) priority = 7 + li t1, 7 + sw t1, 0x28(t0) + # enable sources 3,0xA + li t0, 0x0C002000 + li t1, 0b10000001000 + sw t1, 0(t0) + # ========== Configure UART ========== + # MCR: Loop = 1 + li t0, 0x10000000 + li t1, 0b10000 + sb t1, 4(t0) + # LCR: Use 8 data bits plus odd parity bit + li t1, 0b00001011 + sb t1, 3(t0) + # IER: Enable Received Data Available Interrupt + li t1, 0x01 + sb t1, 1(t0) + # ========== Configure GPIO ========== + # raise all input_en + li t0, 0x10060000 + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # raise all output_en + sw t1, 0x08(t0) + # raise all input_en + sw t1, 0x18(t0) + # ========== Execute Test ========== + # set MEIE + li t0, 0x800 + csrrs x0, mie, t0 +Intr01BEEF01: + # UART TX 'h' + li t0, 0x10000000 + li t1, 'h' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr01BEEF02: + # GPIO raise pin 19 + li t0, 0x10060000 + li t1, 0x00080000 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # Now let's go bonkers and trigger both! +Intr01BEEF03: + # TX 'e' + li t0, 0x10000000 + li t1, 'e' + sb t1, 0(t0) +Intr01BEEF04: + # GPIO lower pin 19 raise pin 0 + li t0, 0x10060000 + li t1, 0x00000001 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00011000 + 1: bne t1,a0,1b + li a0, 0 + + ################################## + ##### Test 2 - GPIO Testing ##### + ################################## + li a1, 0x02beef00 # group ID + # clear MEIE + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 3 (GPIO) priority = 1 + li t0, 0xC000000 + li t1, 1 + sw t1, 0x0C(t0) + # enable source 3 + li t0, 0x0C002000 + li t1, 0b1000 + sw t1, 0(t0) + # ========== Input Enables ========== + # Note that this inherits + # a bit of state from the previous test. + # Namely output_val = 0x00000001 + # + # enable some inputs + li t0, 0x10060000 + li t1, 0x0000FFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # enable all rising edge interrupts + sw t1, 0x18(t0) + # set MEIE + li t1, 0x800 + csrrs x0, mie, t1 + # raise some input-disabled pins + # interrupt should not happen + li t1, 0xF0F00001 + sw t1, 0x0C(t0) +Intr02BEEF04: + # change some input-enabled pins + # interrupt should happen + li t1, 0x3030F0F0 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 +Intr02BEEF05: + # enable some different inputs + # this itself will cause some rise interrupts + li t1, 0xFFFF0000 + sw t1, 0x04(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Output Enables ========== + # enable all fall interrupts + li t1, 0xFFFFFFFF + sw t1, 0x20(t0) +Intr02BEEF06: + # disable some outputs + # should affect input value but not output val register itself + # this itself will cause some fall interrupts + li t1, 0xFF0000FF + sw t1, 0x08(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # change pins whose inputs and/or outputs are disabled + # should not cause any rise or fall interrupts + li t1, 0x300F0F0F + sw t1, 0x0C(t0) +Intr02BEEF07: + # change pins whose inputs and outputs are enabled + li t1, 0x0F0F0F0F + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Clear GPIO State ========== + # (I've gotten a little annoyed with tests depending + # upon the results of previous tests). + # disable all interrupts + sw x0, 0x18(t0) + sw x0, 0x20(t0) + sw x0, 0x28(t0) + sw x0, 0x30(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # set initial output state + sw x0, 0x0C(t0) + # clear all pending interrupts + li t1, 0xFFFFFFFF + sw t1, 0x1C(t0) + sw t1, 0x24(t0) + sw t1, 0x2C(t0) + sw t1, 0x34(t0) + # ========== Rise Interrupt Enables ========== + # enable some rising edge interrupts + li t1, 0x0000FFFF + sw t1, 0x18(t0) +Intr02BEEF08: + # raise some pins + li t1, 0x00FFFF00 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 +Intr02BEEF09: + # raise pins whose rise IEs are disabled + # should not cause an interrupt + li t1, 0x33FFFF00 + sw t1, 0x0C(t0) + # raise pins whose rise IEs are enabled + li t1, 0x33FFFF33 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # =========== Fall Interrupts =========== + # (admittedly these are already used elsewhere) + # disable all rising edge interrupts + li t1, 0 + sw t1, 0x18(t0) + # enable some falling edge interrupts + li t1, 0x0000FFFF + sw t1, 0x20(t0) +Intr02BEEF0A: + # lower some pins + li t1, 0x33000033 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # lower pins whose fall IEs are disabled + # and raise a bunch of other pins + # should not cause an interrupt + li t1, 0x00CCCC33 + sw t1, 0x0C(t0) +Intr02BEEF0B: + # lower pins whose fall IEs are enabled + li t1, 0x00CCCC00 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # =========== High Interrupts =========== + # disable all falling edge interrupts + li t1, 0 + sw t1, 0x20(t0) + # enable some high_ie's for low pins + # should not cause an interrupt + li t1, 0xFF0000FF + sw t1, 0x28(t0) +Intr02BEEF0C: + # enable some high_ie's for high pins + li t1, 0x0000FFFF + sw t1, 0x28(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # lower all pins + li t1, 0 + sw t1, 0x0C(t0) + # lower any existing high_ip's + li t1, 0xFFFFFFFF + sw t1, 0x2C(t0) + # re-enable some high_ie's + li t1, 0xFFFF0000 + sw t1, 0x28(t0) + # raise some pins whose high_ie's are disabled + li t1, 0x0000CCCC + sw t1, 0x0C(t0) + # disable some inputs + li t1, 0xFF00FFFF + sw t1, 0x04(t0) + # raise some pins whose inputs are disabled + li t1, 0x00CCCCCC + sw t1, 0x0C(t0) +Intr02BEEF0D: + # raise some pins whose high_ie's and inputs are enabled + li t1, 0xCCCCCCCC + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # =========== Low Interrupts =========== + # disable all high interrupts + li t1, 0 + sw t1, 0x28(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable some low_ie's for high pins + # should not cause an interrupt + li t1, 0xCC0000CC + sw t1, 0x30(t0) +Intr02BEEF0E: + # enable some low_ie's for low pins + li t1, 0xCCCCFFFF + sw t1, 0x30(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # raise all pins + li t1, 0xFFFFFFFF + sw t1, 0x0C(t0) + # lower any existing low_ip's + # actually takes a little time for vals + # to propagate through synchronizer + # so this extra load is a nop effectively + li t1, 0xFFFFFFFF + sw t1, 0x34(t0) + # re-enable some low_ie's + li t1, 0xFF0000FF + sw t1, 0x30(t0) + # lower some pins whose low_ie's are disabled + li t1, 0xFF1111FF + sw t1, 0x0C(t0) +Intr02BEEF0F: + # disable some inputs of pins whose low_ie's are enabled + li t1, 0x0000FFFF + sw t1, 0x04(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Clear GPIO State ========== + # disable all interrupts + sw x0, 0x18(t0) + sw x0, 0x20(t0) + sw x0, 0x28(t0) + sw x0, 0x30(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # set initial output state + sw x0, 0x0C(t0) + # clear all pending interrupts + li t1, 0xFFFFFFFF + sw t1, 0x1C(t0) + sw t1, 0x24(t0) + sw t1, 0x2C(t0) + sw t1, 0x34(t0) + # ========== Output XOR Test ========== + # enable some inputs + li t1, 0x0000FFFF + sw t1, 0x04(t0) + # enable some outputs + li t1, 0xFF0000FF + sw t1, 0x08(t0) + # enable all rising and falling edge interrupts + li t1, 0xFFFFFFFF + sw t1, 0x18(t0) + sw t1, 0x20(t0) +Intr02BEEF10: + # XOR all outputs + li t1, 0xFFFFFFFF + sw t1, 0x40(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 +Intr02BEEF11: + # XOR some outputs + li t1, 0x33333333 + sw t1, 0x40(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Clear GPIO State ========== + # disable all interrupts + sw x0, 0x18(t0) + sw x0, 0x20(t0) + sw x0, 0x28(t0) + sw x0, 0x30(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # set initial output state + sw x0, 0x0C(t0) + # clear all pending interrupts + li t1, 0xFFFFFFFF + sw t1, 0x1C(t0) + sw t1, 0x24(t0) + sw t1, 0x2C(t0) + sw t1, 0x34(t0) + + ################################## + ##### Test 3 - UART Testing ##### + ################################## + li a1, 0x03beef00 # group ID + # clear MEIE + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 0xA (UART) priority = 1 + li t0, 0xC000000 + li t1, 1 + sw t1, 0x28(t0) + # enable source 0xA + li t0, 0x0C002000 + li t1, 0b10000000000 + sw t1, 0(t0) + # ========== Transmitter Holding Register Empty Interrupt (THRE) ========== + # MCR: Loop = 1 + li t0, 0x10000000 + li t1, 0b00010000 + sb t1, 4(t0) + # LCR: Use 8 data bits plus odd parity bit + li t1, 0b00001011 + sb t1, 3(t0) + # IER: Disable all interrupts for now + li t1, 0x0 + sb t1, 1(t0) + # set MEIE + li t1, 0x800 + csrrs x0, mie, t1 + # THR: TX 'l' + li t1, 'l' + sb t1, 0(t0) + # wait directly on UART for completion + li t1, 0b01100001 + 1: lb t2, 5(t0) + bne t1, t2, 1b +Intr03BEEF12: + # IER: enable THR empty intr (ETBEI) + li t1, 0b00000010 + sb t1, 1(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # IER: disable THR empty intr (ETBEI) + sb x0, 1(t0) + # THR: TX 'l' + li t1, 'l' + sb t1, 0(t0) + # THR: TX 'o' + li t1, 'o' + sb t1, 0(t0) +Intr03BEEF13: + # IER: enable THR empty intr (ETBEI) + li t1, 0b00000010 + sb t1, 1(t0) + # This will take a few cycles before UART finishes TX'ing + # If we see SCR modifications in output, it means UART probably + # did wait until empty THR before triggering the interrupt. + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ========== + # Clear SCR + sb x0, 7(t0) +Intr03BEEF14: + # IER: enable RBR ready intr ERBFI + li t1, 0x1 + sb t1, 1(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr03BEEF15: + # THR: TX ' ' + li t1, 0x20 + sb t1, 0(t0) + # This will take a few cycles before UART finishes RX'ing + # If we see SCR modifications in output, it means UART probably + # did wait until received data available before triggering the interrupt. + li t1, 3 + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr03BEEF16: + # THR: TX 't' + li t1, 't' + sb t1, 0(t0) + # Same shenanigans as before, only now we also confirm + # that you can read the RBR before new data is available + # without messing up the receive interrupt. + lb t1, 0(t0) + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # MCR: Loop = 0 + li t1, 0b00000000 + sb t1, 4(t0) + # Clear SCR + sb x0, 7(t0) + # THR: TX 'h' + # should TX but not not trigger interrupt + li t1, 'h' + sb t1, 0(t0) + # wait directly on UART for completion + li t1, 0b01100000 + 1: lb t2, 5(t0) + bne t1, t2, 1b + # Can use THRE test from before to verify we are transmitting + # THR: TX 'e' + li t1, 'e' + sb t1, 0(t0) + # THR: TX 'r' + li t1, 'r' + sb t1, 0(t0) +Intr03BEEF17: + # IER: enable THR empty intr (ETBEI) and RBR ready intr (ERBFI) + li t1, 0b00000011 + sb t1, 1(t0) + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # manually wait until transmitter finishes before enabling loop mode + li t1, 0b01100000 + 1: lb t2, 5(t0) + bne t1, t2, 1b + # MCR: Loop = 1 + li t1, 0b00010000 + sb t1, 4(t0) +Intr03BEEF18: +Intr03BEEF19: + # THR: TX 'e' + li t1, 'e' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # wait to finish again + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Receiver Line Status Intr (ELSI) & Overrun Error (OE) ========== + # IER: Enable Receiver Line Status Intr (ELSI) + li t1, 0b00000100 + sb t1, 1(t0) + li t1, 0xFF + sb t1, 7(t0) + # We can't cause all kinds of interesting errors, but at least we can + # cause an overrun error by transmitting twice without reading. +Intr03BEEF1A: + # THR: TX '\n' + li t1, 0xD + sb t1, 0(t0) + # THR: TX 'G' + li t1, 'G' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # --------------------------------------------------------------------------------------------- + +//terminate_test: +// li a0, 2 // Trap handler behavior (go to machine mode) +// ecall // writes mcause to the output. +// csrw mtvec, x4 // restore original trap handler to halt program + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +# stack memory (size 16 words) +.align 3 +stack: +.fill 16, 8, 0xdeadbeef +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 0x200, 8, 0x00000000 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py new file mode 100755 index 000000000..5eb7b45b4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +if __name__ == "__main__": + import sys + if (('-h' in sys.argv) or ('--help' in sys.argv)): + helptxt = "This script helps to develop WALLY-PERIPH.S\n" \ + "Give it a physical address such as 80002084,\n" \ + "and it describes where that address is the signature output." + print(helptxt) + else: + adr = str(input("Address: ")) + try: + adr = int(adr,16) + except: + exit("Oi that was not a valid address.") + base_adr = int("80002000",16) + sig_adr = adr-base_adr + line_num = int(sig_adr / 4) + 1 + offset = sig_adr & 0x3F + test_num = int((sig_adr-offset)/int("40",16)) + print("IntrNum 0x{:02X}".format(test_num)) + print("Offset 0x{:02X}".format(offset)) + print("LineNum "+str(line_num)) + From 2322e66f9f34e6f1ca2448c544e9e194a0fcd26a Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 22 Feb 2022 05:04:18 +0000 Subject: [PATCH 025/199] fix lint bugs in PLIC and UART --- pipelined/src/uncore/plic.sv | 6 +++--- pipelined/src/uncore/uartPC16550D.sv | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv index f7924c568..2d5459989 100644 --- a/pipelined/src/uncore/plic.sv +++ b/pipelined/src/uncore/plic.sv @@ -113,7 +113,7 @@ module plic ( 24'h002004: intEn[N:32] <= #1 Din[31:0]; `endif 24'h200000: intThreshold[2:0] <= #1 Din[2:0]; - 24'h200004: intInProgress <= #1 intInProgress & ~(4'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h200004: intInProgress <= #1 intInProgress & ~(`PLIC_NUM_SRC'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase // reading if (memread) @@ -132,7 +132,7 @@ module plic ( 24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]}; 24'h200004: begin Dout <= #1 {26'b0,intClaim}; - intInProgress <= #1 intInProgress | (4'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed + intInProgress <= #1 intInProgress | (`PLIC_NUM_SRC'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed end default: Dout <= #1 32'h0; // invalid access endcase @@ -155,7 +155,7 @@ module plic ( // pending updates // *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered) assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress - ~({4{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read + ~({N{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); // pending array - indexed by priority_lvl x source_ID diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index f679bba7c..36ce77ee2 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -283,7 +283,7 @@ module uartPC16550D( 2'b10: rxdata9 = {1'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8]}; // 7-bit 2'b11: rxdata9 = { rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8], rxshiftreg[9]}; // 8-bit endcase - assign rxdata = LCR[3] ? rxdata9[8:0] : rxdata9[8:1]; // discard parity bit + assign rxdata = LCR[3] ? rxdata9[7:0] : rxdata9[8:1]; // discard parity bit // ERROR CONDITIONS assign rxparity = ^rxdata; From 971dd494f6edd28f078cd88779739ed441f5d41a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Feb 2022 11:31:28 -0600 Subject: [PATCH 026/199] Clarified interlockfsm. --- pipelined/src/lsu/interlockfsm.sv | 87 +++++++++++++++++-------------- pipelined/src/lsu/lsuvirtmen.sv | 3 +- 2 files changed, 50 insertions(+), 40 deletions(-) diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 29b060caf..43bf3d284 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -31,33 +31,44 @@ `include "wally-config.vh" -module interlockfsm - (input logic clk, - input logic reset, - input logic AnyCPUReqM, - input logic ITLBMissOrDAFaultF, - input logic ITLBWriteF, - input logic DTLBMissOrDAFaultM, - input logic DTLBWriteM, - input logic TrapM, - input logic DCacheStallM, +module interlockfsm( + input logic clk, + input logic reset, + input logic [1:0] MemRWM, + input logic [1:0] AtomicM, + input logic ITLBMissOrDAFaultF, + input logic ITLBWriteF, + input logic DTLBMissOrDAFaultM, + input logic DTLBWriteM, + input logic TrapM, + input logic DCacheStallM, - output logic InterlockStall, - output logic SelReplayCPURequest, - output logic SelHPTW, - output logic IgnoreRequestTLB, - output logic IgnoreRequestTrapM); + output logic InterlockStall, + output logic SelReplayCPURequest, + output logic SelHPTW, + output logic IgnoreRequestTLB, + output logic IgnoreRequestTrapM); + logic ToITLBMiss; + logic ToITLBMissNoReplay; + logic ToDTLBMiss; + logic ToBoth; + logic AnyCPUReqM; - typedef enum logic[2:0] {STATE_T0_READY, - STATE_T0_REPLAY, - STATE_T3_DTLB_MISS, - STATE_T4_ITLB_MISS, - STATE_T5_ITLB_MISS, - STATE_T7_DITLB_MISS} statetype; + typedef enum logic[2:0] {STATE_T0_READY, + STATE_T0_REPLAY, + STATE_T3_DTLB_MISS, + STATE_T4_ITLB_MISS, + STATE_T5_ITLB_MISS, + STATE_T7_DITLB_MISS} statetype; (* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState; + assign AnyCPUReqM = (|MemRWM) | (|AtomicM); + assign ToITLBMiss = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM; + assign ToITLBMissNoReplay = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM; + assign ToDTLBMiss = ~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM; + assign ToBoth = ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM; always_ff @(posedge clk) if (reset) InterlockCurrState <= #1 STATE_T0_READY; @@ -65,23 +76,23 @@ module interlockfsm always_comb begin case(InterlockCurrState) - STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY; - else if(~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; - else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; - else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; - else if(ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS; - else InterlockNextState = STATE_T0_READY; - STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T0_READY; - STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T3_DTLB_MISS; - STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; - else InterlockNextState = STATE_T4_ITLB_MISS; - STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; - else InterlockNextState = STATE_T5_ITLB_MISS; - STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; - else InterlockNextState = STATE_T7_DITLB_MISS; - default: InterlockNextState = STATE_T0_READY; + STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY; + else if(ToDTLBMiss) InterlockNextState = STATE_T3_DTLB_MISS; + else if(ToITLBMissNoReplay) InterlockNextState = STATE_T4_ITLB_MISS; + else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS; + else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS; + else InterlockNextState = STATE_T0_READY; + STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T0_READY; + STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T3_DTLB_MISS; + STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; + else InterlockNextState = STATE_T4_ITLB_MISS; + STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; + else InterlockNextState = STATE_T5_ITLB_MISS; + STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; + else InterlockNextState = STATE_T7_DITLB_MISS; + default: InterlockNextState = STATE_T0_READY; endcase end // always_comb diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 1e32bd9f4..0db6ebb16 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -78,13 +78,12 @@ module lsuvirtmem( logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF; logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM; - assign AnyCPUReqM = (|MemRWM) | (|AtomicM); assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM); assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM; assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM; interlockfsm interlockfsm ( - .clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF, + .clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF, .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, .InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); hptw hptw( // *** remove logic from (), mention this in style guide CH3 From 59f04f251803e58bcba505162a2e9e913138f170 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Feb 2022 17:28:26 -0600 Subject: [PATCH 027/199] Minor busdp cleanup. --- pipelined/src/ifu/ifu.sv | 12 ++++----- pipelined/src/lsu/busdp.sv | 6 ++--- pipelined/src/lsu/busfsm.sv | 50 ++++++++++++++++++------------------- pipelined/src/lsu/lsu.sv | 11 ++++---- 4 files changed, 40 insertions(+), 39 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 96bbdcbbc..58eceb7c0 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -83,8 +83,8 @@ module ifu ( output logic ICacheAccess, output logic ICacheMiss ); - -(* mark_debug = "true" *) logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; + localparam CACHE_ENABLED = `IMEM == `MEM_CACHE; + (* mark_debug = "true" *) logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; logic BranchMisalignedFaultE; logic PrivilegedChangePCM; logic IllegalCompInstrD; @@ -182,8 +182,8 @@ module ifu ( .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); end else begin : bus - localparam integer WORDSPERLINE = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/`XLEN : 1; - localparam integer LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN; + localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS/`XLEN : 1; + localparam integer LINELEN = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS : `XLEN; localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] ReadDataLine; logic [LINELEN-1:0] ICacheBusWriteData; @@ -193,7 +193,7 @@ module ifu ( logic [31:0] temp; logic SelUncachedAdr; - busdp #(WORDSPERLINE, LINELEN, LOGWPL) + busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), .LSUBusRead(IFUBusRead), .LSUBusSize(), @@ -210,7 +210,7 @@ module ifu ( .s(SelUncachedAdr), .y(AllInstrRawF[31:0])); - if(`IMEM == `MEM_CACHE) begin : icache + if(CACHE_ENABLED) begin : icache logic [1:0] IFURWF; assign IFURWF = CacheableF ? 2'b10 : 2'b00; diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index d3bfed681..0c172037f 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, LSU=0) +module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) ( input logic clk, reset, // bus interface @@ -66,7 +66,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, LSU=0) output logic BusCommittedM); - localparam integer WordCountThreshold = (`DMEM == `MEM_CACHE) ? WORDSPERLINE - 1 : 0; + localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; genvar index; @@ -80,7 +80,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, LSU=0) mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); - busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix. + busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 837326d51..3b3a38a8f 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -32,7 +32,7 @@ module busfsm #(parameter integer WordCountThreshold, - parameter integer LOGWPL, parameter logic CacheEnabled ) + parameter integer LOGWPL, parameter logic CACHE_ENABLED ) (input logic clk, input logic reset, @@ -88,7 +88,7 @@ module busfsm #(parameter integer WordCountThreshold, assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); assign CntEn = PreCntEn & LSUBusAck; - assign UnCachedAccess = ~CacheEnabled | ~CacheableM; + assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; always_ff @(posedge clk) if (reset) BusCurrState <= #1 STATE_BUS_READY; @@ -96,27 +96,27 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(BusCurrState) - STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(LSURWM[0] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(LSURWM[1] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_READ; + STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; + else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; - else BusNextState = STATE_BUS_READY; - STATE_BUS_UNCACHED_WRITE: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; - else BusNextState = STATE_BUS_UNCACHED_WRITE; - STATE_BUS_UNCACHED_READ: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; - else BusNextState = STATE_BUS_UNCACHED_READ; - STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; - STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; - STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; - STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) BusNextState = STATE_BUS_READY; - else BusNextState = STATE_BUS_FETCH; - STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) BusNextState = STATE_BUS_READY; - else BusNextState = STATE_BUS_WRITE; - default: BusNextState = STATE_BUS_READY; + else BusNextState = STATE_BUS_READY; + STATE_BUS_UNCACHED_WRITE: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; + else BusNextState = STATE_BUS_UNCACHED_WRITE; + STATE_BUS_UNCACHED_READ: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; + else BusNextState = STATE_BUS_UNCACHED_READ; + STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; + else BusNextState = STATE_BUS_READY; + STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; + else BusNextState = STATE_BUS_READY; + STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; + else BusNextState = STATE_BUS_READY; + STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) BusNextState = STATE_BUS_READY; + else BusNextState = STATE_BUS_FETCH; + STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) BusNextState = STATE_BUS_READY; + else BusNextState = STATE_BUS_WRITE; + default: BusNextState = STATE_BUS_READY; endcase end @@ -128,14 +128,14 @@ module busfsm #(parameter integer WordCountThreshold, (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; - assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (LSURWM[0] & ~IgnoreRequest)) | + assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE); - assign LSUBusWriteCrit = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (LSURWM[0])) | + assign LSUBusWriteCrit = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (|LSURWM[1] & IgnoreRequest)) | + assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); @@ -147,5 +147,5 @@ module busfsm #(parameter integer WordCountThreshold, BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) | - ~CacheEnabled; // if no dcache always select uncachedadr. + ~CACHE_ENABLED; // if no dcache always select uncachedadr. endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 48ca50a7d..d980f0216 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -82,6 +82,7 @@ module lsu ( input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. ); + localparam CACHE_ENABLED = `DMEM == `MEM_CACHE; logic [`XLEN+1:0] IEUAdrExtM; logic [`PA_BITS-1:0] LSUPAdrM; logic DTLBMissM; @@ -192,9 +193,9 @@ module lsu ( .DCacheMiss, .DCacheAccess); assign SelUncachedAdr = '0; // value does not matter. end else begin : bus - localparam integer WORDSPERLINE = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS/`XLEN : 1; - localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN; - localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; + localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1; + localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN; + localparam integer LOGWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] ReadDataLineM; logic [LINELEN-1:0] DCacheBusWriteData; logic [`PA_BITS-1:0] DCacheBusAdr; @@ -206,7 +207,7 @@ module lsu ( logic SelBus; logic [LOGWPL-1:0] WordCount; - busdp #(WORDSPERLINE, LINELEN, LOGWPL, 1) busdp( + busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( .clk, .reset, .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .WordCount, .LSUBusWriteCrit, @@ -224,7 +225,7 @@ module lsu ( .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. - if(`DMEM == `MEM_CACHE) begin : dcache + if(CACHE_ENABLED) begin : dcache logic [1:0] RW, Atomic; assign RW = CacheableM ? LSURWM : 2'b00; // AND gate assign Atomic = CacheableM ? LSUAtomicM : 2'b00; // AND gate From 834b308ed67f953f6eb54e1e37962424efa60d55 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Feb 2022 22:19:25 -0600 Subject: [PATCH 028/199] Fixed "bug" with wally-pipelined.do --- pipelined/regression/wally-pipelined.do | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index db50042e9..f558d56f4 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -37,7 +37,8 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084 - #-- Run the Simulation + #-- Run the Simulation + run -all add log -recursive /* do linux-wave.do run -all From 15f6871a8dacfca2d26e9a898ece0e9d8deff896 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Feb 2022 22:45:00 -0600 Subject: [PATCH 029/199] Added generates to pcnextf muxes for privileged and caches. --- pipelined/src/ifu/ifu.sv | 26 +++++++++++++++++++------- pipelined/src/lsu/busdp.sv | 10 +++++----- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 58eceb7c0..663639f8d 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -76,7 +76,6 @@ module ifu ( input logic [1:0] STATUS_MPP, input logic ITLBWriteF, ITLBFlushF, output logic ITLBMissF, InstrDAPageFaultF, - // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], output logic InstrAccessFaultF, @@ -120,7 +119,7 @@ module ifu ( assign PCFExt = {2'b00, PCFSpill}; ///////////////////////////////////////////////////////////////////////////////////////////// - // Spill Support *** add other banners + // Spill Support ///////////////////////////////////////////////////////////////////////////////////////////// if(`C_SUPPORTED) begin : SpillSupport @@ -247,18 +246,28 @@ module ifu ( flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD); + //////////////////////////////////////////////////////////////////////////////////////////////// + // PCNextF logic + //////////////////////////////////////////////////////////////////////////////////////////////// + assign PrivilegedChangePCM = RetM | TrapM; - // *** look at moves pcmux2 and pcmux3 to generates as they are needed only on supporting caches and - // privilege instructions respectively. mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); - mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F)); - mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); + if(CACHE_ENABLED) + mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), + .y(PCNext2F)); + else assign PCNext2F = PCNext1F; + if(`ZICSR_SUPPORTED) + mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), + .y(UnalignedPCNextF)); + else assign UnalignedPCNextF = PCNext2F; assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); - // branch and jump predictor + //////////////////////////////////////////////////////////////////////////////////////////////// + // Branch and Jump Predictor + //////////////////////////////////////////////////////////////////////////////////////////////// if (`BPRED_ENABLED) begin : bpred logic BPPredWrongM; logic SelBPPredF; @@ -295,6 +304,9 @@ module ifu ( else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 + //////////////////////////////////////////////////////////////////////////////////////////////// + // Decode stage pipeline register and compressed instruction decoding. + //////////////////////////////////////////////////////////////////////////////////////////////// // Decode stage pipeline register and logic flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 0c172037f..66e41675d 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -67,17 +67,17 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; - logic [`PA_BITS-1:0] LocalLSUBusAdr; genvar index; - for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer - flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)), - .d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); + logic [WORDSPERLINE-1:0] CaptureWord; + assign CaptureWord[index] = LSUBusAck & LSUBusRead & (index == WordCount); + flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), + .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); end mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; - mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), + mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) From 19ec874641623f28108aa8088f0033dbffcceafe Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Feb 2022 10:16:12 -0600 Subject: [PATCH 030/199] Fixed bug with spill support and Instruction DA Page Faults. --- pipelined/src/ifu/ifu.sv | 6 ++-- pipelined/src/ifu/spillsupport.sv | 50 +++++++++++++++---------------- 2 files changed, 27 insertions(+), 29 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 663639f8d..62518b263 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -125,8 +125,8 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport spillsupport spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF, - .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, - .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); + .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, + .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport assign PCNextFSpill = PCNextF; assign PCFSpill = PCF; @@ -160,7 +160,7 @@ module ifu ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin - assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF} = '0; + assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrDAPageFaultF} = '0; assign PCPF = PCFExt[`PA_BITS-1:0]; assign CacheableF = '1; end diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index a55155513..c84d7e82a 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -42,6 +42,7 @@ module spillsupport ( input logic [31:0] InstrRawF, input logic IFUCacheBusStallF, input logic ITLBMissF, + input logic InstrDAPageFaultF, output logic [`XLEN-1:0] PCNextFSpill, output logic [`XLEN-1:0] PCFSpill, output logic SelNextSpillF, @@ -50,44 +51,41 @@ module spillsupport ( localparam integer SPILLTHRESHOLD = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/32 : 1; - logic [`XLEN-1:0] PCPlus2F; - logic TakeSpillF; - logic SpillF; - logic SelSpillF, SpillSaveF; - logic [15:0] SpillDataLine0; + logic [`XLEN-1:0] PCPlus2F; + logic TakeSpillF; + logic SpillF; + logic SelSpillF, SpillSaveF; + logic [15:0] SpillDataLine0; + typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; + (* mark_debug = "true" *) statetype CurrState, NextState; - // *** PLACE ALL THIS IN A MODULE - // this exists only if there are compressed instructions. - // reuse PC+2/4 circuitry to avoid needing a second CPA to add 2 - mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); - mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF), .y(PCNextFSpill)); + mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), + .s(PCF[1]), .y(PCPlus2F)); + mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF), + .y(PCNextFSpill)); mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; - - typedef enum logic [1:0] {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype; - (* mark_debug = "true" *) statetype CurrState, NextState; - + assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | InstrDAPageFaultF); + always_ff @(posedge clk) - if (reset) CurrState <= #1 STATE_SPILL_READY; + if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; - assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~ITLBMissF; - always_comb begin case (CurrState) - STATE_SPILL_READY: if (TakeSpillF) NextState = STATE_SPILL_SPILL; - else NextState = STATE_SPILL_READY; - STATE_SPILL_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL_SPILL; - else NextState = STATE_SPILL_READY; - default: NextState = STATE_SPILL_READY; + STATE_READY: if (TakeSpillF) NextState = STATE_SPILL; + else NextState = STATE_READY; + STATE_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL; + else NextState = STATE_READY; + default: NextState = STATE_READY; endcase end - assign SelSpillF = (CurrState == STATE_SPILL_SPILL); - assign SelNextSpillF = (CurrState == STATE_SPILL_READY & TakeSpillF) | - (CurrState == STATE_SPILL_SPILL & IFUCacheBusStallF); - assign SpillSaveF = (CurrState == STATE_SPILL_READY) & TakeSpillF; + assign SelSpillF = (CurrState == STATE_SPILL); + assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | + (CurrState == STATE_SPILL & IFUCacheBusStallF); + assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF; flopenr #(16) SpillInstrReg(.clk(clk), .en(SpillSaveF), From 6f53f7943f7846e03fde53fe04961efae8773525 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Feb 2022 10:27:14 -0600 Subject: [PATCH 031/199] More spillsupport more structual. --- pipelined/src/ifu/spillsupport.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index c84d7e82a..3d3c15752 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -93,7 +93,8 @@ module spillsupport ( .d((`IMEM == `MEM_CACHE) ? InstrRawF[15:0] : InstrRawF[31:16]), .q(SpillDataLine0)); - assign PostSpillInstrRawF = SpillF ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF; + mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF), + .y(PostSpillInstrRawF)); assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11; endmodule From 730fdb029aad7ed1081464c02cc72857fd2ed5be Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Feb 2022 10:54:34 -0600 Subject: [PATCH 032/199] Fixed bug with DAPageFault being wrong when HPTW writes not supported. --- pipelined/src/ifu/spillsupport.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 3d3c15752..db9ed8e28 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -66,7 +66,7 @@ module spillsupport ( mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; - assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | InstrDAPageFaultF); + assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF)); always_ff @(posedge clk) if (reset) CurrState <= #1 STATE_READY; From 5d7d40a4c7b43804949c5c016df6c269a6eb4f95 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 24 Feb 2022 00:05:23 +0000 Subject: [PATCH 033/199] Linux disassembly makefile --- linux/buildroot-scripts/Makefile | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile index b0e3bdf9b..7e0c0cfc5 100644 --- a/linux/buildroot-scripts/Makefile +++ b/linux/buildroot-scripts/Makefile @@ -1,3 +1,6 @@ +IMAGES := ${RISCV}/buildroot/output/images +DIS := ${IMAGES}/disassembly + all: make disassemble make generate @@ -7,15 +10,18 @@ generate: dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb disassemble: - mkdir ${RISCV}/buildroot/output/images/disassembly - # fw_jump - riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/fw_jump.elf >> ${RISCV}/buildroot/output/images/disassembly/fw_jump.objdump - # vmlinux - riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/vmlinux >> ${RISCV}/buildroot/output/images/disassembly/vmlinux.objdump + mkdir -p ${DIS} + make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump # filesystem mkdir ${RISCV}/buildroot/output/images/disassembly/rootfs -cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -idv < ../../rootfs.cpio + riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/disassembly/rootfs/bin/busybox >> ${RISCV}/buildroot/output/images/disassembly/busybox.objdump + +${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf + riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/fw_jump.elf >> ${RISCV}/buildroot/output/images/disassembly/fw_jump.objdump +${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux + riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/vmlinux >> ${RISCV}/buildroot/output/images/disassembly/vmlinux.objdump clean: - rm ${RISCV}/buildroot/output/images/wally-virt.dtb - rm -rf ${RISCV}/buildroot/output/images/disassembly + rm -f ${IMAGES}/wally-virt.dtb + rm -rf ${DIS} From 09a1519dce0fdd858d231a64751e73e2c22d2d1f Mon Sep 17 00:00:00 2001 From: kaveh Pezeshki Date: Thu, 24 Feb 2022 00:08:10 +0000 Subject: [PATCH 034/199] removed verbose cpio and excluded /dev/console --- linux/buildroot-scripts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile index 7e0c0cfc5..5139f74c2 100644 --- a/linux/buildroot-scripts/Makefile +++ b/linux/buildroot-scripts/Makefile @@ -14,7 +14,7 @@ disassemble: make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump # filesystem mkdir ${RISCV}/buildroot/output/images/disassembly/rootfs - -cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -idv < ../../rootfs.cpio + -cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/disassembly/rootfs/bin/busybox >> ${RISCV}/buildroot/output/images/disassembly/busybox.objdump ${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf From 4e20df64e23826265801f20502c9a4aa30c54b69 Mon Sep 17 00:00:00 2001 From: kaveh Pezeshki Date: Thu, 24 Feb 2022 04:49:04 +0000 Subject: [PATCH 035/199] Updated busybox disassembly --- linux/buildroot-scripts/Makefile | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile index 5139f74c2..53673c9c2 100644 --- a/linux/buildroot-scripts/Makefile +++ b/linux/buildroot-scripts/Makefile @@ -11,16 +11,26 @@ generate: disassemble: mkdir -p ${DIS} - make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump + # disassemblies + make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump ${DIS}/busybox.objdump # filesystem - mkdir ${RISCV}/buildroot/output/images/disassembly/rootfs - -cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio - riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/disassembly/rootfs/bin/busybox >> ${RISCV}/buildroot/output/images/disassembly/busybox.objdump + make ${DIS}/rootfs/bin/busybox + # mkdir -p ${DIS}/rootfs + # -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio ${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf - riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/fw_jump.elf >> ${RISCV}/buildroot/output/images/disassembly/fw_jump.objdump + riscv64-unknown-elf-objdump -D ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump + ${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux - riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/vmlinux >> ${RISCV}/buildroot/output/images/disassembly/vmlinux.objdump + riscv64-unknown-elf-objdump -D ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump + +${DIS}/busybox.objdump: ${DIS}/rootfs/bin/busybox + riscv64-unknown-elf-objdump -D ${DIS}/rootfs/bin/busybox >> ${DIS}/busybox.objdump + +${DIS}/rootfs/bin/busybox: + mkdir -p ${DIS}/rootfs + -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio + clean: rm -f ${IMAGES}/wally-virt.dtb From 8eb7ab0dca83178e455a1ebb226b12a3a7445599 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 25 Feb 2022 20:05:10 +0000 Subject: [PATCH 037/199] parser rename --- linux/testvector-generation/genRecording.sh | 1 - linux/testvector-generation/genTrace.sh | 3 +-- .../{parseQemuToGDB.py => parseQEMUtoGDB.py} | 2 +- 3 files changed, 2 insertions(+), 4 deletions(-) rename linux/testvector-generation/{parseQemuToGDB.py => parseQEMUtoGDB.py} (100%) diff --git a/linux/testvector-generation/genRecording.sh b/linux/testvector-generation/genRecording.sh index 318de2880..d7319413a 100755 --- a/linux/testvector-generation/genRecording.sh +++ b/linux/testvector-generation/genRecording.sh @@ -31,4 +31,3 @@ then sudo chown cad $recordFile sudo chmod o-w $recordFile fi - diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh index ea14aad1a..6c3548be5 100755 --- a/linux/testvector-generation/genTrace.sh +++ b/linux/testvector-generation/genTrace.sh @@ -33,7 +33,7 @@ then -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ -d nochain,cpu,in_asm,int \ - 2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) + 2>&1 >/dev/null | ./parseQEMUtoGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) # Cleanup echo "Elevating permissions to restrict write access to $traceFile, $interruptsFile" @@ -42,4 +42,3 @@ then sudo chmod o-w $traceFile sudo chmod o-w $interruptsFile fi - diff --git a/linux/testvector-generation/parseQemuToGDB.py b/linux/testvector-generation/parseQEMUtoGDB.py similarity index 100% rename from linux/testvector-generation/parseQemuToGDB.py rename to linux/testvector-generation/parseQEMUtoGDB.py index fa2646abe..707d48539 100755 --- a/linux/testvector-generation/parseQemuToGDB.py +++ b/linux/testvector-generation/parseQEMUtoGDB.py @@ -1,7 +1,6 @@ #! /usr/bin/python3 import fileinput, sys -sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n") parseState = "idle" beginPageFault = 0 inPageFault = 0 @@ -13,6 +12,7 @@ pageFaultRegs = {} instrs = {} instrCount = 0 returnAdr = 0 +sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n") def printPC(l): global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, instrCount From 8518fd44a50e26f786105832eaddc7cbf2e1a125 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 25 Feb 2022 23:51:40 +0000 Subject: [PATCH 038/199] revived checkpointing and hacked it up to generate a trace starting at the checkpoint --- .gitignore | 4 + linux/testvector-generation/Makefile | 17 ++++ .../createGenCheckpointScript.py | 71 +++++++++++++ linux/testvector-generation/fixBinMem.c | 33 +++++++ linux/testvector-generation/genCheckpoint.sh | 89 +++++++++++++++++ linux/testvector-generation/parseState.py | 99 +++++++++++++++++++ linux/testvector-generation/silencePipe.c | 19 ++++ 7 files changed, 332 insertions(+) create mode 100644 linux/testvector-generation/Makefile create mode 100755 linux/testvector-generation/createGenCheckpointScript.py create mode 100644 linux/testvector-generation/fixBinMem.c create mode 100755 linux/testvector-generation/genCheckpoint.sh create mode 100755 linux/testvector-generation/parseState.py create mode 100644 linux/testvector-generation/silencePipe.c diff --git a/.gitignore b/.gitignore index 368992380..9b3e6dc62 100644 --- a/.gitignore +++ b/.gitignore @@ -54,6 +54,10 @@ examples/C/sum/sum examples/C/fir/fir linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh +linux/testvector-generation/genCheckpoint.gdb +linux/testvector-generation/silencePipe +linux/testvector-generation/silencePipe.control +linux/testvector-generation/fixBinMem *.dtb synthDC/WORK synthDC/alib-52 diff --git a/linux/testvector-generation/Makefile b/linux/testvector-generation/Makefile new file mode 100644 index 000000000..8f3441e5a --- /dev/null +++ b/linux/testvector-generation/Makefile @@ -0,0 +1,17 @@ +SHELL = /bin/sh + +CFLAG = -Wall -g +CC = clang + +all: fixBinMem silencePipe + +fixBinMem: fixBinMem.c + ${CC} ${CFLAGS} fixBinMem.c -o fixBinMem + chmod +x fixBinMem + +silencePipe: silencePipe.c + ${CC} ${CFLAGS} silencePipe.c -o silencePipe + chmod +x silencePipe +clean: + -rm -f fixBinMem + -rm -f silencePipe diff --git a/linux/testvector-generation/createGenCheckpointScript.py b/linux/testvector-generation/createGenCheckpointScript.py new file mode 100755 index 000000000..fee2b603a --- /dev/null +++ b/linux/testvector-generation/createGenCheckpointScript.py @@ -0,0 +1,71 @@ +#! /usr/bin/python3 +import sys + +if len(sys.argv) != 8: + sys.exit("""Error createGenCheckpointScript.py expects 7 args: + + + + + + + """) + +tcpPort=sys.argv[1] +vmlinux=sys.argv[2] +instrCount=sys.argv[3] +statePath=sys.argv[4] +ramPath=sys.argv[5] +checkPC=sys.argv[6] +checkPCoccurences=sys.argv[7] + +GDBscript = f""" +# GDB config +set pagination off +set logging overwrite on +set logging redirect on +set confirm off + +# Connect to QEMU session +target extended-remote :{tcpPort} + +# QEMU Config +maintenance packet Qqemu.PhyMemMode:1 + +# Symbol file +file {vmlinux} + +# Silence Trace Generation +shell echo 1 > ./silencePipe.control + +# Step over reset vector into actual code +stepi 100 +# Proceed to checkpoint +print "GDB proceeding to checkpoint at {instrCount} instrs, pc {checkPC}\\n" +b *0x{checkPC} +ignore 1 {checkPCoccurences} +c +print "Reached checkpoint at {instrCount} instrs\\n" + +# Log all registers to a file +printf "GDB storing state to {statePath}\\n" +set logging file {statePath} +set logging on +info all-registers +set logging off + +# Log main memory to a file +print "GDB storing RAM to {ramPath}\\n" +#dump binary memory {ramPath} 0x80000000 0xffffffff +#dump binary memory {ramPath} 0x80000000 0x80ffffff + +# Generate Trace Until End +shell echo 0 > ./silencePipe.control +# Do this by setting an impossible breakpoint +b *0x1000 +del 1 +c +""" +GDBscriptFile = open("genCheckpoint.gdb",'w') +GDBscriptFile.write(GDBscript) +GDBscriptFile.close() diff --git a/linux/testvector-generation/fixBinMem.c b/linux/testvector-generation/fixBinMem.c new file mode 100644 index 000000000..fe071008b --- /dev/null +++ b/linux/testvector-generation/fixBinMem.c @@ -0,0 +1,33 @@ +#include +#include +#include +int main(int argc, char *argv[]) { + if (argc < 3){ + fprintf(stderr, "Expected 2 arguments: \n"); + exit(1); + } + char* rawGDBfilePath = argv[1]; + FILE* rawGDBfile; + if ((rawGDBfile = fopen(rawGDBfilePath,"rb"))==NULL) { + fprintf(stderr, "File not found: %s\n",rawGDBfilePath); + exit(1); + } + char* outFilePath = argv[2]; + FILE* outFile = fopen(outFilePath,"w"); + uint64_t qemuWord; + uint64_t verilogWord; + int bytesReturned=0; + do { + bytesReturned=fread(&qemuWord, 8, 1, rawGDBfile); + verilogWord = (((qemuWord>>0 )&0xff)<<56 | + ((qemuWord>>8 )&0xff)<<48 | + ((qemuWord>>16)&0xff)<<40 | + ((qemuWord>>24)&0xff)<<32 | + ((qemuWord>>32)&0xff)<<24 | + ((qemuWord>>40)&0xff)<<16 | + ((qemuWord>>48)&0xff)<<8 | + ((qemuWord>>56)&0xff)<<0); + fwrite(&verilogWord, 8, 1, outFile); + } while(bytesReturned!=0); + return 0; +} diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh new file mode 100755 index 000000000..d468e9fda --- /dev/null +++ b/linux/testvector-generation/genCheckpoint.sh @@ -0,0 +1,89 @@ +#!/bin/bash +tcpPort=1237 +imageDir=$RISCV/buildroot/output/images +tvDir=$RISCV/linux-testvectors +recordFile="$tvDir/all.qemu" +traceFile="$tvDir/all_up_to_498.txt" + +# Parse Commandline Arg +if [ "$#" -ne 1 ]; then + echo "genCheckpoint requires 1 argument: " >&2 + exit 1 +fi +instrs=$1 +if ! [ "$instrs" -eq "$instrs" ] 2> /dev/null +then + echo "Error expected integer number of instructions, got $instrs" >&2 + exit 1 +fi + +checkPtDir="$tvDir/checkpoint$instrs" +outTraceFile="$checkPtDir/all.txt" +interruptsFile="$checkPtDir/interrupts.txt" +rawStateFile="$checkPtDir/stateGDB.txt" +rawRamFile="$checkPtDir/ramGDB.bin" +ramFile="$checkPtDir/ram.bin" + +read -p "This scripts is going to create a checkpoint at $instrs instrs. +Is that what you wanted? (y/n) " -n 1 -r +echo +if [[ $REPLY =~ ^[Yy]$ ]] +then + echo "Creating checkpoint at $instrs instructions!" + make silencePipe + + # Create Output Directory + echo "Elevating permissions to create $checkPtDir and stuff inside it" + sudo mkdir -p $checkPtDir + sudo chown -R cad:users $checkPtDir + sudo chmod -R a+rw $checkPtDir + sudo touch $outTraceFile + sudo chmod a+rw $outTraceFile + sudo touch $interruptsFile + sudo chmod a+rw $interruptsFile + sudo touch $rawStateFile + sudo chmod a+rw $rawStateFile + sudo touch $rawRamFile + sudo chmod a+rw $rawRamFile + sudo touch $ramFile + sudo chmod a+rw $ramFile + + # Identify instruction in trace + instr=$(sed "${instrs}q;d" "$traceFile") + echo "Found ${instrs}th instr: ${instr}" + pc=$(echo $instr | cut -d " " -f1) + asm=$(echo $instr | cut -d " " -f2) + occurences=$(($(head -$instrs "$traceFile" | grep -c "${pc} ${asm}")-1)) + echo "It occurs ${occurences} times before the ${instrs}th instr." + + # Create GDB script because GDB is terrible at handling arguments / variables + ./createGenCheckpointScript.py $tcpPort $imageDir/vmlinux $instrs $rawStateFile $rawRamFile $pc $occurences + + # GDB+QEMU + echo "Starting QEMU in replay mode with attached GDB script at $(date +%H:%M:%S)" + (qemu-system-riscv64 \ + -M virt -dtb $imageDir/wally-virt.dtb \ + -nographic \ + -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ + -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ + -d nochain,cpu,in_asm,int \ + -gdb tcp::$tcpPort -S \ + 2>&1 >/dev/null | ./silencePipe | ./parseQEMUtoGDB/parseQEMUtoGDB_run.py | ./parseGDBtoTrace/parseGDBtoTrace_run.py $interruptsFile | ./remove_dup.awk > $outTraceFile) \ + & riscv64-unknown-elf-gdb --quiet -ex "source genCheckpoint.gdb" + echo "Completed GDB script at $(date +%H:%M:%S)" + + # Post-Process GDB outputs + ./parseState.py "$checkPtDir" + echo "Changing Endianness at $(date +%H:%M:%S)" + make fixBinMem + ./fixBinMem "$rawRamFile" "$ramFile" + #echo "Creating truncated trace at $(date +%H:%M:%S)" + #tail -n+$instrs "$tvDir/$traceFile" > "$checkPtDir/$traceFile" + echo "Checkpoint completed at $(date +%H:%M:%S)" + + # Cleanup + echo "Elevating permissions to restrict write access to $checkPtDir" + sudo chown -R cad:users $checkPtDir + sudo chmod -R go-w $checkPtDir +fi + diff --git a/linux/testvector-generation/parseState.py b/linux/testvector-generation/parseState.py new file mode 100755 index 000000000..5275597c4 --- /dev/null +++ b/linux/testvector-generation/parseState.py @@ -0,0 +1,99 @@ +#! /usr/bin/python3 +import sys, os + +################ +# Helper Funcs # +################ + +def tokenize(string): + tokens = [] + token = '' + whitespace = 0 + prevWhitespace = 0 + for char in string: + prevWhitespace = whitespace + whitespace = char in ' \t\n' + if (whitespace): + if ((not prevWhitespace) and (token != '')): + tokens.append(token) + token = '' + else: + token = token + char + return tokens + +############# +# Main Code # +############# +print("Begin parsing state.") + +# Parse Args +if len(sys.argv) != 2: + sys.exit('Error parseState.py expects 1 arg:\n parseState.py ') +outDir = sys.argv[1]+'/' +stateGDBpath = outDir+'stateGDB.txt' +if not os.path.exists(stateGDBpath): + sys.exit('Error input file '+stateGDBpath+'not found') + +singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv'] +# priv (current privilege mode) isn't technically a CSR but we can log it with the same machinery +thirtyTwoBitCSRs = ['mcounteren','scounteren'] +listCSRs = ['hpmcounter','pmpaddr'] +pmpcfg = ['pmpcfg'] + +# Initialize List CSR files to empty +# (because later we'll open them in append mode) +for csr in listCSRs+pmpcfg: + outFileName = 'checkpoint-'+csr.upper() + outFile = open(outDir+outFileName, 'w') + outFile.close() + +# Initial State for Main Loop +currState = 'regFile' +regFileIndex = 0 +outFileName = 'checkpoint-RF' +outFile = open(outDir+outFileName, 'w') + +# Main Loop +with open(stateGDBpath, 'r') as stateGDB: + for line in stateGDB: + line = tokenize(line) + name = line[0] + val = line[1][2:] + if (currState == 'regFile'): + if (regFileIndex == 0 and name != 'zero'): + print('Whoops! Expected regFile registers to come first, starting with zero') + exit(1) + if (name != 'zero'): + # Wally doesn't need to know zero=0 + outFile.write(val+'\n') + regFileIndex += 1 + if (regFileIndex == 32): + outFile.close() + currState = 'CSRs' + elif (currState == 'CSRs'): + if name in singleCSRs: + outFileName = 'checkpoint-'+name.upper() + outFile = open(outDir+outFileName, 'w') + outFile.write(val+'\n') + outFile.close() + elif name in thirtyTwoBitCSRs: + outFileName = 'checkpoint-'+name.upper() + outFile = open(outDir+outFileName, 'w') + val = int(val,16) & 0xffffffff + outFile.write(hex(val)[2:]+'\n') + outFile.close() + elif name.strip('0123456789') in listCSRs: + outFileName = 'checkpoint-'+name.upper().strip('0123456789') + outFile = open(outDir+outFileName, 'a') + outFile.write(val+'\n') + outFile.close() + elif name.strip('0123456789') in pmpcfg: + outFileName = 'checkpoint-'+name.upper().strip('0123456789') + outFile = open(outDir+outFileName, 'a') + fourPmp = int(val,16) + for i in range(0,4): + byte = (fourPmp >> 8*i) & 0xff + outFile.write(hex(byte)[2:]+'\n') + outFile.close() + +print("Finished parsing state!") diff --git a/linux/testvector-generation/silencePipe.c b/linux/testvector-generation/silencePipe.c new file mode 100644 index 000000000..2cd531b89 --- /dev/null +++ b/linux/testvector-generation/silencePipe.c @@ -0,0 +1,19 @@ +#include +#include + +int main(void) +{ + char *line = NULL; + size_t len = 0; + while (1) { + FILE* controlFile = fopen("silencePipe.control", "r"); + char silenceChar = getc(controlFile); + fclose(controlFile); + ssize_t lineSize = getline(&line, &len, stdin); + if (silenceChar!='1') { + printf("%s",line); + } + } + free(line); + return 0; +} From ac03a95aeb3c5fc9a85ae10c0c808b1d27932968 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 25 Feb 2022 22:14:52 +0000 Subject: [PATCH 039/199] added support for trap handlers in in multiple pivilege modes --- .../privilege/src/WALLY-CSR-permission-s-01.S | 2 +- .../privilege/src/WALLY-CSR-permission-u-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-MMU-SV39.S | 3 +- .../rv64i_m/privilege/src/WALLY-MMU-SV48.S | 3 +- .../rv64i_m/privilege/src/WALLY-PMA.S | 3 +- .../rv64i_m/privilege/src/WALLY-PMP.S | 3 +- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 131 ++++++++++-------- .../rv64i_m/privilege/src/WALLY-minfo-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-misa-01.S | 3 +- .../rv64i_m/privilege/src/WALLY-scratch-01.S | 2 +- .../privilege/src/WALLY-sscratch-s-01.S | 2 +- 11 files changed, 85 insertions(+), 71 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S index 4336a510a..9b24b6efe 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S @@ -25,7 +25,7 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S index 21fdc1d7d..904e15dbd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -25,7 +25,7 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S index 38f277606..2cabaf68a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S @@ -25,7 +25,8 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m + j test_loop_setup // begin test loop/table tests instead of executing inline code. INIT_TEST_TABLE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S index f1625155d..68ea5c2b4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S @@ -25,7 +25,8 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m + j test_loop_setup // begin test loop/table tests instead of executing inline code. INIT_TEST_TABLE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S index 0e544fe36..7780e187f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S @@ -38,7 +38,8 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m + j test_loop_setup // begin test loop/table tests instead of executing inline code. INIT_TEST_TABLE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S index 157f0fe7f..ca4617c55 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S @@ -25,7 +25,8 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m + j test_loop_setup // begin test loop/table tests instead of executing inline code. INIT_TEST_TABLE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index e8ad5de04..21280a719 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -34,13 +34,14 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN + + // --------------------------------------------------------------------------------------------- // Initialization Overview: // // Initialize x6 as a virtual pointer to the test results // Initialize x16 as a physical pointer to the test results // Set up stack pointer (sp = x2) - // Set up the exception Handler, keeping the original handler in x4. // // --------------------------------------------------------------------------------------------- @@ -52,17 +53,25 @@ RVTEST_CODE_BEGIN // address for stack la sp, top_of_stack +.endm + +.macro TRAP_HANDLER MODE // default to vectored tests + // Set up the exception Handler, keeping the original handler in x4. + // trap handler setup - la x1, machine_trap_handler - csrrw x4, mtvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test. + + la x1, trap_handler_\MODE\() +.if (\MODE\() == m) + csrrw x4, \MODE\()tvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test. +.else + csrw \MODE\()tvec, x1 // we only neet save the machine trap handler and this if statement ensures it isn't overwritten +.endif + li a0, 0 li a1, 0 li a2, 0 // reset trap handler inputs to zero - // go to beginning of S file where we can decide between using the test data loop - // or using the macro inline code insertion - j s_file_begin - + j trap_handler_end_\MODE\() // --------------------------------------------------------------------------------------------- // General traps Handler // @@ -98,14 +107,14 @@ RVTEST_CODE_BEGIN // -------------------------------------------------------------------------------------------- -machine_trap_handler: +trap_handler_\MODE\(): // The processor is always in machine mode when a trap takes us here // save registers on stack before using sd x1, -8(sp) sd x5, -16(sp) // Record trap - csrr x1, mcause // record the mcause + csrr x1, \MODE\()cause // record the mcause sd x1, 0(x16) addi x6, x6, 8 addi x16, x16, 8 // update pointers for logging results @@ -114,22 +123,22 @@ machine_trap_handler: // All interrupts should return after being logged li x5, 0x8000000000000000 // if msb is set, it is an interrupt and x5, x5, x1 - bnez x5, trapreturn // return from interrupt + bnez x5, trapreturn_\MODE\() // return from interrupt // Other trap handling is specified in the vector Table slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table - la x5, trap_handler_vector_table + la x5, trap_handler_vector_table_\MODE\() add x5, x5, x1 // compute address of vector in Table ld x5, 0(x5) // fectch address of handler from vector Table jr x5 // and jump to the handler -segfault: +segfault_\MODE\(): ld x5, -16(sp) // restore registers from stack before faulting ld x1, -8(sp) j terminate_test // halt program. -trapreturn: +trapreturn_\MODE\(): // look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1 - csrr x1, mepc // get the mepc + csrr x1, \MODE\()epc // get the mepc addi x1, x1, 4 // *** should be 2 for compressed instructions, see note. @@ -153,13 +162,13 @@ trapreturn: // csrr x1, mepc // get the mepc again // addi x1, x1, 4 // add 4 to find the next instruction -trapreturn_specified: +trapreturn_specified_\MODE\(): // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc) // so that when we return to a new virtual address, they're all in the right spot as well. - beqz a1, trapreturn_finished // either update values, of go to default return address. + beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address. - la x5, trap_return_pagetype_table + la x5, trap_return_pagetype_table_\MODE\() slli a2, a2, 3 add x5, x5, a2 ld a2, 0(x5) // a2 = number of offset bits in current page type @@ -191,54 +200,53 @@ trapreturn_specified: li a1, 0 li a2, 0 // reset trapreturn inputs to the trap handler -trapreturn_finished: - csrw mepc, x1 // update the mepc with address of next instruction +trapreturn_finished_\MODE\(): + csrw \MODE\()epc, x1 // update the epc with address of next instruction ld x5, -16(sp) // restore registers from stack before returning ld x1, -8(sp) - mret // return from trap + \MODE\()ret // return from trap -ecallhandler: +ecallhandler_\MODE\(): // Check input parameter a0. encoding above. - // *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs. li x5, 2 // case 2: change to machine mode - beq a0, x5, ecallhandler_changetomachinemode + beq a0, x5, ecallhandler_changetomachinemode_\MODE\() li x5, 3 // case 3: change to supervisor mode - beq a0, x5, ecallhandler_changetosupervisormode + beq a0, x5, ecallhandler_changetosupervisormode_\MODE\() li x5, 4 // case 4: change to user mode - beq a0, x5, ecallhandler_changetousermode + beq a0, x5, ecallhandler_changetousermode_\MODE\() // unsupported ecalls should segfault - j segfault + j segfault_\MODE\() -ecallhandler_changetomachinemode: - // Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret +ecallhandler_changetomachinemode_\MODE\(): + // Force status.MPP (bits 12:11) to 11 to enter machine mode after mret li x1, 0b1100000000000 - csrs mstatus, x1 - j trapreturn + csrs \MODE\()status, x1 + j trapreturn_\MODE\() -ecallhandler_changetosupervisormode: - // Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret +ecallhandler_changetosupervisormode_\MODE\(): + // Force status.MPP (bits 12:11) to 01 to enter supervisor mode after mret li x1, 0b1100000000000 - csrc mstatus, x1 + csrc \MODE\()status, x1 li x1, 0b0100000000000 - csrs mstatus, x1 - j trapreturn + csrs \MODE\()status, x1 + j trapreturn_\MODE\() -ecallhandler_changetousermode: +ecallhandler_changetousermode_\MODE\(): // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret li x1, 0b1100000000000 csrc mstatus, x1 - j trapreturn + j trapreturn_\MODE\() -instrfault: +instrfault_\MODE\(): ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page) - j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page) + j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page) -illegalinstr: - j trapreturn // return to the code after recording the mcause +illegalinstr_\MODE\(): + j trapreturn_\MODE\() // return to the code after recording the mcause -accessfault: +accessfault_\MODE\(): // *** What do I have to do here? - j trapreturn + j trapreturn_\MODE\() // Table of trap behavior // lists what to do on each exception (not interrupts) @@ -246,31 +254,32 @@ accessfault: // Expected exceptions should increment the EPC to the next instruction and return .align 3 // aligns this data table to an 8 byte boundary -trap_handler_vector_table: - .8byte segfault // 0: instruction address misaligned - .8byte instrfault // 1: instruction access fault - .8byte illegalinstr // 2: illegal instruction - .8byte segfault // 3: breakpoint - .8byte segfault // 4: load address misaligned - .8byte accessfault // 5: load access fault - .8byte segfault // 6: store address misaligned - .8byte accessfault // 7: store access fault - .8byte ecallhandler // 8: ecall from U-mode - .8byte ecallhandler // 9: ecall from S-mode - .8byte segfault // 10: reserved - .8byte ecallhandler // 11: ecall from M-mode - .8byte instrfault // 12: instruction page fault - .8byte trapreturn // 13: load page fault - .8byte segfault // 14: reserved - .8byte trapreturn // 15: store page fault +trap_handler_vector_table_\MODE\(): + .8byte segfault_\MODE\() // 0: instruction address misaligned + .8byte instrfault_\MODE\() // 1: instruction access fault + .8byte illegalinstr_\MODE\() // 2: illegal instruction + .8byte segfault_\MODE\() // 3: breakpoint + .8byte segfault_\MODE\() // 4: load address misaligned + .8byte accessfault_\MODE\() // 5: load access fault + .8byte segfault_\MODE\() // 6: store address misaligned + .8byte accessfault_\MODE\() // 7: store access fault + .8byte ecallhandler_\MODE\() // 8: ecall from U-mode + .8byte ecallhandler_\MODE\() // 9: ecall from S-mode + .8byte segfault_\MODE\() // 10: reserved + .8byte ecallhandler_\MODE\() // 11: ecall from M-mode + .8byte instrfault_\MODE\() // 12: instruction page fault + .8byte trapreturn_\MODE\() // 13: load page fault + .8byte segfault_\MODE\() // 14: reserved + .8byte trapreturn_\MODE\() // 15: store page fault .align 3 -trap_return_pagetype_table: +trap_return_pagetype_table_\MODE\(): .8byte 0xC // 0: kilopage has 12 offset bits .8byte 0x15 // 1: megapage has 21 offset bits .8byte 0x1E // 2: gigapage has 30 offset bits .8byte 0x27 // 3: terapage has 39 offset bits +trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test .endm // Test Summary table! diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index 850d0c2a4..bdfe4b316 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -25,7 +25,7 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m // Test 5.2.3.1: testing Read-only access to Machine info CSRs CSR_R_ACCESS mvendorid diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S index 7ea1e7827..6e6a984ac 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S @@ -25,7 +25,8 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m + // Test 5.3.2.2: Machine ISA register test // Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S index a5b2d4e0d..5674a5267 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-scratch-01.S @@ -25,7 +25,7 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m // Test 5.3.2.3: Scratch registers test WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S index 091e50cb1..38278a793 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sscratch-s-01.S @@ -25,7 +25,7 @@ INIT_TESTS -s_file_begin: +TRAP_HANDLER m // Test 5.3.2.3: Scratch registers test WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode From 2da39c7052fb1475d61f3735cb39df483d1bb9d2 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 25 Feb 2022 22:37:11 +0000 Subject: [PATCH 040/199] allowed for vectored and unvectored interrupts in trap handlers --- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 53 ++++++++++++++++--- 1 file changed, 46 insertions(+), 7 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 21280a719..bce7a70b6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -55,12 +55,15 @@ RVTEST_CODE_BEGIN .endm -.macro TRAP_HANDLER MODE // default to vectored tests +.macro TRAP_HANDLER MODE, VECTORED=1 // default to vectored tests // Set up the exception Handler, keeping the original handler in x4. // trap handler setup - la x1, trap_handler_\MODE\() +.if (\VECTORED == 1) + ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts +.endif + .if (\MODE\() == m) csrrw x4, \MODE\()tvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test. .else @@ -71,7 +74,8 @@ RVTEST_CODE_BEGIN li a1, 0 li a2, 0 // reset trap handler inputs to zero - j trap_handler_end_\MODE\() + j trap_handler_end_\MODE\() // skip the trap handler when it is being defined. + // --------------------------------------------------------------------------------------------- // General traps Handler // @@ -106,9 +110,25 @@ RVTEST_CODE_BEGIN // // -------------------------------------------------------------------------------------------- - +.align 2 trap_handler_\MODE\(): - // The processor is always in machine mode when a trap takes us here + j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler + // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented + // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code + .4byte s_soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. + .4byte segfault_\MODE\() // 2: reserved + .4byte m_soft_interrupt_\MODE\() // 3: breakpoint + .4byte segfault_\MODE\() // 4: reserved + .4byte s_time_interrupt_\MODE\() // 5: load access fault + .4byte segfault_\MODE\() // 6: reserved + .4byte m_time_interrupt_\MODE\() // 7: store access fault + .4byte segfault_\MODE\() // 8: reserved + .4byte s_ext_interrupt_\MODE\() // 9: ecall from S-mode + .4byte segfault_\MODE\() // 10: reserved + .4byte m_ext_interrupt_\MODE\() // 11: ecall from M-mode + // 12 through >=16 are reserved or designated for platform use + +trap_unvectored_\MODE\(): // save registers on stack before using sd x1, -8(sp) sd x5, -16(sp) @@ -126,7 +146,7 @@ trap_handler_\MODE\(): bnez x5, trapreturn_\MODE\() // return from interrupt // Other trap handling is specified in the vector Table slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table - la x5, trap_handler_vector_table_\MODE\() + la x5, exception_vector_table_\MODE\() add x5, x5, x1 // compute address of vector in Table ld x5, 0(x5) // fectch address of handler from vector Table jr x5 // and jump to the handler @@ -248,13 +268,32 @@ accessfault_\MODE\(): // *** What do I have to do here? j trapreturn_\MODE\() +s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet + j trapreturn_\MODE\() + +m_soft_interrupt_\MODE\(): + j trapreturn_\MODE\() + +s_time_interrupt_\MODE\(): + j trapreturn_\MODE\() + +m_time_interrupt_\MODE\(): + j trapreturn_\MODE\() + +s_ext_interrupt_\MODE\(): + j trapreturn_\MODE\() + +m_ext_interrupt_\MODE\(): + j trapreturn_\MODE\() + + // Table of trap behavior // lists what to do on each exception (not interrupts) // unexpected exceptions should cause segfaults for easy detection // Expected exceptions should increment the EPC to the next instruction and return .align 3 // aligns this data table to an 8 byte boundary -trap_handler_vector_table_\MODE\(): +exception_vector_table_\MODE\(): .8byte segfault_\MODE\() // 0: instruction address misaligned .8byte instrfault_\MODE\() // 1: instruction access fault .8byte illegalinstr_\MODE\() // 2: illegal instruction From 860eca356e413e1fa9ad92a7439d413ed248f178 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 26 Feb 2022 13:02:57 -0600 Subject: [PATCH 041/199] Delete unused FP vector scripts --- .../build/Linux-x86_64-GCC/softfloat.a | Bin 514606 -> 0 bytes tests/fp/create_vectors16.csh | 22 ---------- tests/fp/create_vectors32.csh | 20 --------- tests/fp/create_vectors32_64.csh | 16 ------- tests/fp/create_vectors32cmp.csh | 9 ---- tests/fp/create_vectors64.csh | 20 --------- tests/fp/create_vectors64_32.csh | 18 -------- tests/fp/create_vectors64cmp.csh | 9 ---- tests/fp/create_vectorsi.csh | 41 ------------------ 9 files changed, 155 deletions(-) delete mode 100644 tests/fp/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a delete mode 100755 tests/fp/create_vectors16.csh delete mode 100755 tests/fp/create_vectors32.csh delete mode 100755 tests/fp/create_vectors32_64.csh delete mode 100755 tests/fp/create_vectors32cmp.csh delete mode 100755 tests/fp/create_vectors64.csh delete mode 100755 tests/fp/create_vectors64_32.csh delete mode 100755 tests/fp/create_vectors64cmp.csh delete mode 100755 tests/fp/create_vectorsi.csh diff --git a/tests/fp/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a b/tests/fp/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a deleted file mode 100644 index b4466d620c87eb2f27cca4ea509da998f57c5a2b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 514606 zcmeEv4}4rjwf}6ACQXaEQBaB?-5`G&#WtI!p;e^2B`J4tQ+c!n0cGnRB3^qSc*co5eP+_&`R_Bp1Cu3XJ>b^ zfA}LQ+)uJ|@0ovR&dfdM%$YfJE6$(0eBOc!MosW1UxC_*=LIGQCfC&Z{Z%|l{q_56 zt7~iA9M_Fv%y%whXa10}%7+*m|2Sh44>2}nJYyGpmaz+e%9wqGu^HDgHnWGZ&y+EC z?WK&(+r-$yD;ZmQHe=0zf92zh-Fg{gU;i#+cOmY_fYJZ`TN!)cgYN$?PiL&Fi?QuX z7<=@~jP2gQ*pp{4wy&14KclW*)cx`y#`;nBYloPxa0c_0ewF#k9%a4{T*`c>-otzq zJC89&eau$__$QV#-!!BHj=mYwneVbL=DYf7=4+~EzGY?1_l1X;Z%r}tIY{@l z+nDbg2=Dy>^Zgj<{u}WRewq0m{wecq`!4f!BmBd~%(wq8=6i7`^ZoTj=6kJ&6_m_i z1@HL?D>%8B6@2KMtl;c>SV7e^RxoXA^8ZDjX9W#+v4WWov4Sg}V+Gfq!3yR*$_f@7 zVFgQ&CkpuIA7=$?3RuA{wX9&>epc{xlzrDBR`9Lytl)cq-*+u5_^&Qj@IOtgVB=0! zuxSY^c;rW{U?fEu)>p? zSm6hcu)>NLS>d?-tZ>3HRygUqtnmDMSmCs3tngFQS>Zn+y!--II0x`XJTFH2oAA84 zixsvb->suq;q55z?vJp-dsec-??1^3e^kZ_@Bbhx-0)LY_{*QO!p*g;a0k+NqrN?W z{{i{_^bjlTMf@S)F@Su7%URKg53r)LkF%naYFW_-t69+*x3Qve2&v^q8Te$(X4N>qATxVMRN;S(G5#j(W39NqUAqjMK@o}idN5HMeX}p(XB}LFL?eY z!tbE``vCvhC|0xq<@{nNE9!cj6>a}KE84Y*747L_MSs}Jik_Rsih7@BMSnwh>=rhn z-{~h_er~5g&Vqji^4xMog(@Bc}e4ji^U_WCj~?X%`#u znG4v6>&{>!njU2%7UMbkQ#RrY-(@4#ApNZuvk|wW+`9q)&L%eEC)cwP8vyS_{%tGS zh~FM$BYroXjd=3&Y{WBPVj~WGmW_A;`Cqw`jd-<~jX3rrR$MfL6_0u!E4ChI#qa+n zD?asFR$NiQiqHNbD?ayPR$N`oiqGp|#TOu~`#38OzsQO|{asc(`!ZI1)hJec9nv*T zW5u6)nib!O{5MT!#a}$cid)NAv9q5QuOH8f?>fSYzjYTY{{GKd@sE-Je^Bm27qH^k z8LW8wJ*@aK?m#tmLdSSjk84 zVkLo{tYk_VD+yl8O6mds)Wxjik{4OYWk`Q@Ei0LOh?U&%Q&zJ0v#eyr*{oz0(tl|Q zD{1=(D{&rWC0|3jJ2$bCe>=!ZzJv1qV>v7NuhUt{&yjB9N>;LI6f4<$4=dSG%}O49 zj+OlGt1Ff^MVl5aog1Cgcw?Y?GD|!!YSf;i$7+8U+aM7caKkFH-8T|RfnG$!0+8Hi6U1h~uiiPcHPD=`{!NijnfsiUOi%!Ez# zq}m1rpLt80mw?K1=Pz7x!9vz}g5p61$qP4P@&t15par&aUH>jvI1!`x9 zXDz*O>Egvpm&}+uL&0U9gw0wyol+@LX!NqVH_VMTB8MK=G_g9H5-F9bL@lnVwkDer zDV3>29@n@kI(>3g!<>aHW-h#8$=pR47RfDk6J${r1~5u8R_8@GVf+kHA4O+T+jO4H z)HFSEIY#~bSxaY!lip1an)F@@XxgOVq?AjRE?+#e`FaZGE<%@sf(k;soJ;1;`y3xC zN(809ln_c6i8rnRqY*=wKZmpQb?=PC@E56lmwI*B>@FSNw6f0+)-&n%8gcfLZehlyg)4lF0f01Cm};) z+K388ni0`rC54jnND?JO5(>nEZrdWp1FW+&3^#m`FhcO5CF~0aw7tCZU|1%jYa!xCHzr0Yn`-keZMJ zOOp5{m7!pzQ7p~-> z<&BHoq!9o7rtwA|ENXNE37oS+NuRjc)9ssPdr6N;EM+X?ag=b?-T)#ccwr zQ96-Lp{kcZ6_!M4Hywy1tK^h+p_0<-6DTdSVALr0ZiGr{q~nxE$SIAGQ`!wVrE$wC zjgV6s;R;S^+z_P^5Tz*qEjdu7G>?|V<%yIBozm`LcgM86Cz`tVoYLYp0o5p-$fi)$ z%byBERAQXF={TjuEe&t?R#IAh0zqXKqIBZkjZi6#I8JGVoYDw6rQMKI8n>L%2sxz@ zx|GHZQ5peJngURo164}%Xh~e2NO{mG?KZ|6*6JfDn|LIWD^E#r$%Id&;#}IJX#$?a zQWP*yO_Q2BA(05BTLPT-*}XWm+2I;vTdYcObvK zQ(~1)kg<(|^zvD<7xA37HyX6=5YJv)`E#N}+{fhDbY0>Vqf=RymmZ$lD?ELoTii#l zU);xJbX@N4wz)y&@Dh~hoCf|@NO+=q8u%+A;fW4H`a};k(CZ=7czx7BuZe^<-k8!$ zh)?b&${=4Eh;FYts2T19nkOGPGZGQ5gq4ZFbWJl>VUbQ;QXl6yuLmqf1Zld!i5JKp%E6OzEvgqIf1&2#3MdNSOZqS4SHqLQ*I zwzG-VGLr(Vtw{?sm7&zE6auIz16j-58d7a>26&*>5Fs0oQj%;0Uf$Z8X*YA*YUBKg z)w7m*_#z7Tvz8|CNwUs;YK2>;0tDjRHIjUa=Tn}IVf&s^ogG*ifQIY^TW;Wnt$Lgc{J3sK=SJ<}RD z8>JQ^2f1E|3ik?e>6orXZcN%nsZkJ-WQ0>eVA?t;x%HrVx*Cb*Y3uVMy!T~A6c%Ml z%S9O`^o@L^q(V4Pkp>Vo5k#GrjVB_lLW88F!D}hi8&CLAogQ2fpbA`7SX6NO)Gn4B zCn`4~9c5Nka!FX~=%+cQuyiEjD&czVE<6QS0ZyM<#T5xPTmebJ6|gk8qV%-5O1NIT z3s1pSfYYZ|aitWl@f(&CPD4Oaa0M(CSGO36F6C7r?n|aZh%CZ%l$zKOr8g{59vQRJ z7uO`-9+5V=c><`nP=KXEuiz(j9|dG01=r^2Jxrt(Ae9&#l$r?bNy(O$VqTGHnlH;X zMx`Yh&xJQks~_);4oSh0Xw6?xmw@UdP0gF0+zCBXO{)@|ikAZ{sZEIptwl0IA2=S| zklw|g@Zc$v2Mq`5ZQ#Jvp+I2KMOybMF=>!U+jU+ReYATKg6f>{CRNo|PxOzw zv~j-Qo*Q-HAFHXUq+(9uWnquh=PzZxRpq`@Pbe9=9taTpG!bWsaHxQAE@Cearb|

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z!g^ELF45h1+3Gv_fktTBIvWS#H@=Mn;rQipAm206&4*_CZMeEmMVKgDJ*b{vE(h|w z$|%=kZTTM?Tiv!+!RnFwI4)S&C_1#q{I^AVtr4u&vlMNR)D$_IDa38#KS|EtA7ez; zqgO~OpA1~bY@}1S&78MCg?t#>j6!D1+_qNQWrX5h^k3S?Feao@t~F82m@&-S!0XyN zR$Mlb3j`z0lx`}^S@`K&LLIQa_?)RTn@t{6-=xlqlE`nH<8AyvBUHC_r8b-FH@?j# zbNq5`@5nlnQd}M zo3zOYv4!jG=wFz9zVFZ`7wd_SOq*oG$s1IJc^pxN?9*6m>jyH;Y_eiBe2fJOaWcO; zBAkdZ_hsVbj>34&4#i&}#1`7*q9V1<1smGrVmnJG8`>V#u)nro@+4J#%DIn z3*0x4$1hQe6C&B}82gaB5c;6L^i&Hg-Mn~Zs(X8J7jekVdbqfww{b)nr;yuVP08@nve`WLMA!dBa2r<@XJ7DWy2xg; z&+*yk4mSIW21y``|B>4U8`b6h`R02yvN9nOAKGla3~4`z%_bY_WwYxbAI4^Pw6(6y zwzp|$S_zovkf%djZR*fwqq$$KZX?J(ab2C|wlOcv{~}7!X4<%rf2MXI#(M=-{ePLe z>heO8#GYAxHXB{(-$q{<2v?8s{DL$tF>Dk3bZm6Sw9!hSY&0K*+=ubag*Mu|kKIJK J5l$By{eSLk`= f16_add_rne.tv -./testfloat_gen -rminMag f16_add > f16_add_rz.tv -./testfloat_gen -rmin f16_add > f16_add_ru.tv -./testfloat_gen -rmax f16_add > f16_add_rd.tv - -./testfloat_gen -rnear_even f16_sub > f16_sub_rne.tv -./testfloat_gen -rminMag f16_sub > f16_sub_rz.tv -./testfloat_gen -rmin f16_sub > f16_sub_ru.tv -./testfloat_gen -rmax f16_sub > f16_sub_rd.tv - -./testfloat_gen -rnear_even f16_div > f16_div_rne.tv -./testfloat_gen -rminMag f16_div > f16_div_rz.tv -./testfloat_gen -rmin f16_div > f16_div_ru.tv -./testfloat_gen -rmax f16_div > f16_div_rd.tv - -./testfloat_gen -rnear_even f16_sqrt > f16_sqrt_rne.tv -./testfloat_gen -rminMag f16_sqrt > f16_sqrt_rz.tv -./testfloat_gen -rmin f16_sqrt > f16_sqrt_ru.tv -./testfloat_gen -rmax f16_sqrt > f16_sqrt_rd.tv - - diff --git a/tests/fp/create_vectors32.csh b/tests/fp/create_vectors32.csh deleted file mode 100755 index 958c3fad3..000000000 --- a/tests/fp/create_vectors32.csh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh -./testfloat_gen -rnear_even f32_add > f32_add_rne.tv -./testfloat_gen -rminMag f32_add > f32_add_rz.tv -./testfloat_gen -rmax f32_add > f32_add_ru.tv -./testfloat_gen -rmin f32_add > f32_add_rd.tv - -./testfloat_gen -rnear_even f32_sub > f32_sub_rne.tv -./testfloat_gen -rminMag f32_sub > f32_sub_rz.tv -./testfloat_gen -rmax f32_sub > f32_sub_ru.tv -./testfloat_gen -rmin f32_sub > f32_sub_rd.tv - -./testfloat_gen -rnear_even f32_div > f32_div_rne.tv -./testfloat_gen -rminMag f32_div > f32_div_rz.tv -./testfloat_gen -rmax f32_div > f32_div_ru.tv -./testfloat_gen -rmin f32_div > f32_div_rd.tv - -./testfloat_gen -rnear_even f32_sqrt > f32_sqrt_rne.tv -./testfloat_gen -rminMag f32_sqrt > f32_sqrt_rz.tv -./testfloat_gen -rmax f32_sqrt > f32_sqrt_ru.tv -./testfloat_gen -rmin f32_sqrt > f32_sqrt_rd.tv diff --git a/tests/fp/create_vectors32_64.csh b/tests/fp/create_vectors32_64.csh deleted file mode 100755 index 63ba70d13..000000000 --- a/tests/fp/create_vectors32_64.csh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh -./testfloat_gen -rnear_even f32_to_f64 > f32_f64_rne.tv -./testfloat_gen -rminMag f32_to_f64 > f32_f64_rz.tv -./testfloat_gen -rmax f32_to_f64 > f32_f64_ru.tv -./testfloat_gen -rmin f32_to_f64 > f32_f64_rd.tv - -./testfloat_gen -rnear_even f32_to_i64 > f32_i64_rne.tv -./testfloat_gen -rminMag f32_to_i64 > f32_i64_rz.tv -./testfloat_gen -rmax f32_to_i64 > f32_i64_ru.tv -./testfloat_gen -rmin f32_to_i64 > f32_i64_rd.tv - -./testfloat_gen -rnear_even f32_to_ui64 > f32_ui64_rne.tv -./testfloat_gen -rminMag f32_to_ui64 > f32_ui64_rz.tv -./testfloat_gen -rmax f32_to_ui64 > f32_ui64_ru.tv -./testfloat_gen -rmin f32_to_ui64 > f32_ui64_rd.tv - diff --git a/tests/fp/create_vectors32cmp.csh b/tests/fp/create_vectors32cmp.csh deleted file mode 100755 index d7356d3f7..000000000 --- a/tests/fp/create_vectors32cmp.csh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh -./testfloat_gen f32_eq > f32_cmp_eq.tv -./testfloat_gen f32_le > f32_cmp_le.tv -./testfloat_gen f32_lt > f32_cmp_lt.tv - -./testfloat_gen f32_eq_signaling > f32_cmp_eq_signaling.tv -./testfloat_gen f32_le_quiet > f32_cmp_le_quiet.tv -./testfloat_gen f32_lt_quiet > f32_cmp_lt_quiet.tv - diff --git a/tests/fp/create_vectors64.csh b/tests/fp/create_vectors64.csh deleted file mode 100755 index fb4f3cef6..000000000 --- a/tests/fp/create_vectors64.csh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh -./testfloat_gen -rnear_even f64_add > f64_add_rne.tv -./testfloat_gen -rminMag f64_add > f64_add_rz.tv -./testfloat_gen -rmax f64_add > f64_add_ru.tv -./testfloat_gen -rmin f64_add > f64_add_rd.tv - -./testfloat_gen -rnear_even f64_sub > f64_sub_rne.tv -./testfloat_gen -rminMag f64_sub > f64_sub_rz.tv -./testfloat_gen -rmax f64_sub > f64_sub_ru.tv -./testfloat_gen -rmin f64_sub > f64_sub_rd.tv - -./testfloat_gen -rnear_even f64_div > f64_div_rne.tv -./testfloat_gen -rminMag f64_div > f64_div_rz.tv -./testfloat_gen -rmax f64_div > f64_div_ru.tv -./testfloat_gen -rmin f64_div > f64_div_rd.tv - -./testfloat_gen -rnear_even f64_sqrt > f64_sqrt_rne.tv -./testfloat_gen -rminMag f64_sqrt > f64_sqrt_rz.tv -./testfloat_gen -rmax f64_sqrt > f64_sqrt_ru.tv -./testfloat_gen -rmin f64_sqrt > f64_sqrt_rd.tv diff --git a/tests/fp/create_vectors64_32.csh b/tests/fp/create_vectors64_32.csh deleted file mode 100755 index 45f054054..000000000 --- a/tests/fp/create_vectors64_32.csh +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/sh -./testfloat_gen -rnear_even f64_to_f32 > f64_f32_rne.tv -./testfloat_gen -rminMag f64_to_f32 > f64_f32_rz.tv -./testfloat_gen -rmax f64_to_f32 > f64_f32_ru.tv -./testfloat_gen -rmin f64_to_f32 > f64_f32_rd.tv - -./testfloat_gen -rnear_even f64_to_i32 > f64_i32_rne.tv -./testfloat_gen -rminMag f64_to_i32 > f64_i32_rz.tv -./testfloat_gen -rmax f64_to_i32 > f64_i32_ru.tv -./testfloat_gen -rmin f64_to_i32 > f64_i32_rd.tv - -./testfloat_gen -rnear_even f64_to_ui32 > f64_ui32_rne.tv -./testfloat_gen -rminMag f64_to_ui32 > f64_ui32_rz.tv -./testfloat_gen -rmax f64_to_ui32 > f64_ui32_ru.tv -./testfloat_gen -rmin f64_to_ui32 > f64_ui32_rd.tv - - - diff --git a/tests/fp/create_vectors64cmp.csh b/tests/fp/create_vectors64cmp.csh deleted file mode 100755 index b2f5dd5b0..000000000 --- a/tests/fp/create_vectors64cmp.csh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh -./testfloat_gen f64_eq > f64_cmp_eq.tv -./testfloat_gen f64_le > f64_cmp_le.tv -./testfloat_gen f64_lt > f64_cmp_lt.tv - -./testfloat_gen f64_eq_signaling > f64_cmp_eq_signaling.tv -./testfloat_gen f64_le_quiet > f64_cmp_le_quiet.tv -./testfloat_gen f64_lt_quiet > f64_cmp_lt_quiet.tv - diff --git a/tests/fp/create_vectorsi.csh b/tests/fp/create_vectorsi.csh deleted file mode 100755 index f6c249839..000000000 --- a/tests/fp/create_vectorsi.csh +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/sh -./testfloat_gen -rnear_even -i32_to_f64 > i32_f64_rne.tv -./testfloat_gen -rminMag -i32_to_f64 > i32_f64_rz.tv -./testfloat_gen -rmax -i32_to_f64 > i32_f64_ru.tv -./testfloat_gen -rmin -i32_to_f64 > i32_f64_rd.tv - -./testfloat_gen -rnear_even -i64_to_f64 > i64_f64_rne.tv -./testfloat_gen -rminMag -i64_to_f64 > i64_f64_rz.tv -./testfloat_gen -rmax -i64_to_f64 > i64_f64_ru.tv -./testfloat_gen -rmin -i64_to_f64 > i64_f64_rd.tv - -./testfloat_gen -rnear_even -i32_to_f32 > i32_f32_rne.tv -./testfloat_gen -rminMag -i32_to_f32 > i32_f32_rz.tv -./testfloat_gen -rmax -i32_to_f32 > i32_f32_ru.tv -./testfloat_gen -rmin -i32_to_f32 > i32_f32_rd.tv - -./testfloat_gen -rnear_even -i64_to_f32 > i64_f32_rne.tv -./testfloat_gen -rminMag -i64_to_f32 > i64_f32_rz.tv -./testfloat_gen -rmax -i64_to_f32 > i64_f32_ru.tv -./testfloat_gen -rmin -i64_to_f32 > i64_f32_rd.tv - -./testfloat_gen -rnear_even -ui32_to_f64 > ui32_f64_rne.tv -./testfloat_gen -rminMag -ui32_to_f64 > ui32_f64_rz.tv -./testfloat_gen -rmax -ui32_to_f64 > ui32_f64_ru.tv -./testfloat_gen -rmin -ui32_to_f64 > ui32_f64_rd.tv - -./testfloat_gen -rnear_even -ui64_to_f64 > ui64_f64_rne.tv -./testfloat_gen -rminMag -ui64_to_f64 > ui64_f64_rz.tv -./testfloat_gen -rmax -ui64_to_f64 > ui64_f64_ru.tv -./testfloat_gen -rmin -ui64_to_f64 > ui64_f64_rd.tv - -./testfloat_gen -rnear_even -ui32_to_f32 > ui32_f32_rne.tv -./testfloat_gen -rminMag -ui32_to_f32 > ui32_f32_rz.tv -./testfloat_gen -rmax -ui32_to_f32 > ui32_f32_ru.tv -./testfloat_gen -rmin -ui32_to_f32 > ui32_f32_rd.tv - -./testfloat_gen -rnear_even -ui64_to_f32 > ui64_f32_rne.tv -./testfloat_gen -rminMag -ui64_to_f32 > ui64_f32_rz.tv -./testfloat_gen -rmax -ui64_to_f32 > ui64_f32_ru.tv -./testfloat_gen -rmin -ui64_to_f32 > ui64_f32_rd.tv - From ff674b695c47ca2031d9aa1f11ac0bc08105682a Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 26 Feb 2022 19:17:32 +0000 Subject: [PATCH 042/199] Moved Softfloat / TestFloat --- {tests/fp => addins}/SoftFloat-3e/COPYING.txt | 0 {tests/fp => addins}/SoftFloat-3e/README.html | 0 {tests/fp => addins}/SoftFloat-3e/README.txt | 0 .../SoftFloat-3e/build/Linux-386-GCC/Makefile | 0 .../build/Linux-386-GCC/platform.h | 0 .../build/Linux-386-SSE2-GCC/Makefile | 0 .../build/Linux-386-SSE2-GCC/platform.h | 0 .../build/Linux-ARM-VFPv2-GCC/Makefile | 0 .../build/Linux-ARM-VFPv2-GCC/platform.h | 0 .../build/Linux-x86_64-GCC/Makefile | 0 .../build/Linux-x86_64-GCC/platform.h | 0 .../build/Linux-x86_64-GCC/softfloat.a | Bin 0 -> 514606 bytes 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102 insertions(+) create mode 100755 tests/fp/sample/compile.sh create mode 100644 tests/fp/sample/div.c create mode 100644 tests/fp/sample/fma.c diff --git a/tests/fp/sample/compile.sh b/tests/fp/sample/compile.sh new file mode 100755 index 000000000..24d71efa2 --- /dev/null +++ b/tests/fp/sample/compile.sh @@ -0,0 +1,3 @@ +#!/bin/sh +gcc -c -I. -I../../source/include -O2 -o $1.o $1.c +gcc -I -I. -I../../source/include -o $1 $1.o softfloat.a diff --git a/tests/fp/sample/div.c b/tests/fp/sample/div.c new file mode 100644 index 000000000..c76efab20 --- /dev/null +++ b/tests/fp/sample/div.c @@ -0,0 +1,52 @@ +#include +#include +#include "softfloat.h" +#include "softfloat_types.h" + +int float_rounding_mode = 0; + +union dp { + unsigned short x[4]; + double y; +} X; + + +int main() +{ + uint8_t rounding_mode; + uint8_t exceptions; + + uint64_t n, d, result; + float64_t d_n, d_d, d_result; + + n = 0x3feffffffefffff6; + d = 0xffeffffffffffffe; + //n = 0x00000000400001ff; + //d = 0x3ffffdfffffffbfe; + + d_n.v = n; + d_d.v = d; + + softfloat_roundingMode = rounding_mode; + softfloat_exceptionFlags = 0; + softfloat_detectTininess = softfloat_tininess_beforeRounding; + + d_result = f64_div(d_n, d_d); + + //result = d_result.v; + //exceptions = softfloat_exceptionFlags & 0x1f; + + X.x[3] = (d_result.v & 0xffff000000000000) >> 48; + X.x[2] = (d_result.v & 0x0000ffff00000000) >> 32; + X.x[1] = (d_result.v & 0x00000000ffff0000) >> 16; + X.x[0] = (d_result.v & 0x000000000000ffff); + + printf("Number = %.4x\n", X.x[3]); + printf("Number = %.4x\n", X.x[2]); + printf("Number = %.4x\n", X.x[1]); + printf("Number = %.4x\n", X.x[0]); + printf("Number = %1.25lg\n", X.y); + + + return 0; +} diff --git a/tests/fp/sample/fma.c b/tests/fp/sample/fma.c new file mode 100644 index 000000000..4b7bda1fd --- /dev/null +++ b/tests/fp/sample/fma.c @@ -0,0 +1,47 @@ +#include +#include +#include "softfloat.h" +#include "softfloat_types.h" + +int float_rounding_mode = 0; + +union sp { + unsigned short x[2]; + float y; +} X; + + +int main() +{ + uint8_t rounding_mode; + uint8_t exceptions; + + uint32_t multiplier, multiplicand, addend, result; + float32_t f_multiplier, f_multiplicand, f_addend, f_result; + + multiplier = 0xbf800000; + multiplicand = 0xbf800000; + addend = 0xffaaaaaa; + + f_multiplier.v = multiplier; + f_multiplicand.v = multiplicand; + f_addend.v = addend; + + softfloat_roundingMode = rounding_mode; + softfloat_exceptionFlags = 0; + softfloat_detectTininess = softfloat_tininess_beforeRounding; + + f_result = f32_mulAdd(f_multiplier, f_multiplicand, f_addend); + + result = f_result.v; + exceptions = softfloat_exceptionFlags & 0x1f; + + printf("%x\n", f_result.v); + + // Print out SP number + X.x[1] = (f_result.v & 0xffff0000) >> 16; + X.x[0] = (f_result.v & 0x0000ffff); + printf("Number = %f\n", X.y); + + return 0; +} From a9f9cfa5b65db48bfdf80a440e337626b7871b65 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 26 Feb 2022 19:51:19 +0000 Subject: [PATCH 044/199] Added start of fma --- pipelined/src/fma/Makefile | 10 +++ pipelined/src/fma/div.c | 52 +++++++++++++ pipelined/src/fma/fma.c | 47 +++++++++++ pipelined/src/fma/fma16.sv | 121 +++++++++++++++++++++++++++++ pipelined/src/fma/fma16_testgen.py | 31 ++++++++ pipelined/src/fma/softfloat.a | Bin 0 -> 514606 bytes 6 files changed, 261 insertions(+) create mode 100644 pipelined/src/fma/Makefile create mode 100644 pipelined/src/fma/div.c create mode 100644 pipelined/src/fma/fma.c create mode 100644 pipelined/src/fma/fma16.sv create mode 100755 pipelined/src/fma/fma16_testgen.py create mode 100644 pipelined/src/fma/softfloat.a diff --git a/pipelined/src/fma/Makefile b/pipelined/src/fma/Makefile new file mode 100644 index 000000000..75bd56e5a --- /dev/null +++ b/pipelined/src/fma/Makefile @@ -0,0 +1,10 @@ +TARGET ?= fma + +$(TARGET): $(TARGET).c Makefile + gcc -c -I../../../addins/SoftFloat-3e/source/include -O2 -o $(TARGET).o $(TARGET).c + gcc -L../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC \ + -o $(TARGET) $(TARGET).o softfloat.a \ + +clean: + rm $(TARGET).o + rm $(TARGET) diff --git a/pipelined/src/fma/div.c b/pipelined/src/fma/div.c new file mode 100644 index 000000000..c76efab20 --- /dev/null +++ b/pipelined/src/fma/div.c @@ -0,0 +1,52 @@ +#include +#include +#include "softfloat.h" +#include "softfloat_types.h" + +int float_rounding_mode = 0; + +union dp { + unsigned short x[4]; + double y; +} X; + + +int main() +{ + uint8_t rounding_mode; + uint8_t exceptions; + + uint64_t n, d, result; + float64_t d_n, d_d, d_result; + + n = 0x3feffffffefffff6; + d = 0xffeffffffffffffe; + //n = 0x00000000400001ff; + //d = 0x3ffffdfffffffbfe; + + d_n.v = n; + d_d.v = d; + + softfloat_roundingMode = rounding_mode; + softfloat_exceptionFlags = 0; + softfloat_detectTininess = softfloat_tininess_beforeRounding; + + d_result = f64_div(d_n, d_d); + + //result = d_result.v; + //exceptions = softfloat_exceptionFlags & 0x1f; + + X.x[3] = (d_result.v & 0xffff000000000000) >> 48; + X.x[2] = (d_result.v & 0x0000ffff00000000) >> 32; + X.x[1] = (d_result.v & 0x00000000ffff0000) >> 16; + X.x[0] = (d_result.v & 0x000000000000ffff); + + printf("Number = %.4x\n", X.x[3]); + printf("Number = %.4x\n", X.x[2]); + printf("Number = %.4x\n", X.x[1]); + printf("Number = %.4x\n", X.x[0]); + printf("Number = %1.25lg\n", X.y); + + + return 0; +} diff --git a/pipelined/src/fma/fma.c b/pipelined/src/fma/fma.c new file mode 100644 index 000000000..4b7bda1fd --- /dev/null +++ b/pipelined/src/fma/fma.c @@ -0,0 +1,47 @@ +#include +#include +#include "softfloat.h" +#include "softfloat_types.h" + +int float_rounding_mode = 0; + +union sp { + unsigned short x[2]; + float y; +} X; + + +int main() +{ + uint8_t rounding_mode; + uint8_t exceptions; + + uint32_t multiplier, multiplicand, addend, result; + float32_t f_multiplier, f_multiplicand, f_addend, f_result; + + multiplier = 0xbf800000; + multiplicand = 0xbf800000; + addend = 0xffaaaaaa; + + f_multiplier.v = multiplier; + f_multiplicand.v = multiplicand; + f_addend.v = addend; + + softfloat_roundingMode = rounding_mode; + softfloat_exceptionFlags = 0; + softfloat_detectTininess = softfloat_tininess_beforeRounding; + + f_result = f32_mulAdd(f_multiplier, f_multiplicand, f_addend); + + result = f_result.v; + exceptions = softfloat_exceptionFlags & 0x1f; + + printf("%x\n", f_result.v); + + // Print out SP number + X.x[1] = (f_result.v & 0xffff0000) >> 16; + X.x[0] = (f_result.v & 0x0000ffff); + printf("Number = %f\n", X.y); + + return 0; +} diff --git a/pipelined/src/fma/fma16.sv b/pipelined/src/fma/fma16.sv new file mode 100644 index 000000000..c537baf6d --- /dev/null +++ b/pipelined/src/fma/fma16.sv @@ -0,0 +1,121 @@ +// fma16.sv +// David_Harris@hmc.edu 26 February 2022 +// 16-bit floating-point multiply-accumulate + +// Operation: general purpose multiply, add, fma, with optional negation +// If mul=1, p = x * y. Else p = x. +// If add=1, result = p + z. Else result = p. +// If negp or negz = 1, negate p or z to handle negations and subtractions +// fadd: mul = 0, add = 1, negp = negz = 0 +// fsub: mul = 0, add = 1, negp = 0, negz = 1 +// fmul: mul = 1, add = 0, negp = 0, negz = 0 +// fma: mul = 1, add = 1, negp = 0, negz = 0 + +module fma16( + input logic [15:0] x, y, z, + input logic add, mul, negp, negz, + input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn + output logic [15:0] result); + + logic [10:0] xm, ym, zm; + logic [4:0] xe, ye, ze; + logic xs, ys, zs; + logic zs1; // sign before optional negation + logic ps; // sign of product + + unpack unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs + signadj signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations + mult mult(mul, xm, ym, xe, ye, pm, pe); // p = x * y + add add(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p + postproc post(roundmode, rm, re, rs, result); // normalize, round, pack +endmodule + +module mult( + input logic mul, + input logic [10:0] xm, ym, + input logic [4:0] xe, ye, + input logic xs, ys, + output logic [21:0] pm, + output logic [5:0] pe); + + // only multiply if mul = 1 + assign pm = mul ? xm * ym : xm; // multiply mantiassas + assign pe = mul ? xe + ye : xe; +endmodule + +module add( + input logic add, + input logic [21:0] pm, + input logic [10:0] zm, + input logic [5:0] pe, + input logic [4:0] ze, + input logic ps, zs, + output logic [22:0] rm, + output logic [6:0] re, + output logic rs); + + logic [22:0] arm; + logic [6:0] are; + logic ars; + + alignshift as(pe, ze, zm, zmaligned); + condneg cnp(pm, ps, pmn); + condneg cnz(zm, zs, zmn); + + // add or pass product through + assign rm = add ? arm : pm; + assign re = add ? are : pe; + assign rs = add ? ars : ps; +); + +module postproc( + input logic [1:0] roundmode, + input logic [22:0] rm, + input logic [6:0] re, + input logic rs, + output logic [15:0] result); + + // add special case handling for zeros, NaN, Infinity +endmodule + +module signadj( + input logic negx, negz, + input logic xs, ys, zs1, + output logic ps, zs); + + assign ps = xs ^ ys ^ negx; // sign of product + assign zs = zs1 ^ negz; // +endmodule + +module unpack( + input logic [15:0] x, y, z, + output logic [10:0] xm, ym, zm, + output logic [4:0] xe, ye, ze, + output logic xs, ys, zs); + + unpacknum upx(x, xm, xe, xs); + unpacknum upy(y, ym, ye, ys); + unpacknum upz(z, zm, ze, zs); +endmodule + +module unpacknum( + input logic [15:0] num, + output logic [10:0] m, + output logic [4:0] e, + output logic s); + + logic [9:0] f; // fraction without leading 1 + logic [4:0] eb; // biased exponent + + assign {f, eb, s} = num; // pull bit fields out of floating-point number + assign m = {1'b1, f}; // prepend leading 1 to fraction + assign e = eb - 15; // remove bias from exponent +endmodule + + +// Tests: +// Every permutation for x, y, z of +// mantissa = {1.0, 1.0000000001, 1.1, 1.1111111110, 1.1111111111} +// biased exponent = {1, 2, 14, 15, 16, 21, 29, 30} +// sign = {0, 1} +// special case: [normal, 0, INF, NaN] \ No newline at end of file diff --git a/pipelined/src/fma/fma16_testgen.py b/pipelined/src/fma/fma16_testgen.py new file mode 100755 index 000000000..c3cc8d72f --- /dev/null +++ b/pipelined/src/fma/fma16_testgen.py @@ -0,0 +1,31 @@ +#!/usr/bin/python3 + +# fma16_testgen.py +# David_Harris@hmc.edu 26 February 2022 +# Generate test cases for 16-bit FMA + +def makeVal(val): + +def makeCase(x, y, z, mul, add, msg): + xval = makeVal(x); + yval = makeVal(y); + zval = makeVal(z); + mode = mul*2+add; # convert to hexadecimal code + expected = makeExpected(x, y, z, mul, add); + print(xval,"_", yval, "_", zval, "_", mode, "_", expected, " //", msg); + +def makeMulCase(x, y, msg): + makeCase(x, y, "0", 1, 0, msg) + +################################ +## Main program +################################ + +# Directed cases +makeMulCase("1", "1", "1 x 1"); + + +# Corner cases + +# Random cases + diff --git a/pipelined/src/fma/softfloat.a b/pipelined/src/fma/softfloat.a new file mode 100644 index 0000000000000000000000000000000000000000..b4466d620c87eb2f27cca4ea509da998f57c5a2b GIT binary patch literal 514606 zcmeEv4}4rjwf}6ACQXaEQBaB?-5`G&#WtI!p;e^2B`J4tQ+c!n0cGnRB3^qSc*co5eP+_&`R_Bp1Cu3XJ>b^ zfA}LQ+)uJ|@0ovR&dfdM%$YfJE6$(0eBOc!MosW1UxC_*=LIGQCfC&Z{Z%|l{q_56 zt7~iA9M_Fv%y%whXa10}%7+*m|2Sh44>2}nJYyGpmaz+e%9wqGu^HDgHnWGZ&y+EC z?WK&(+r-$yD;ZmQHe=0zf92zh-Fg{gU;i#+cOmY_fYJZ`TN!)cgYN$?PiL&Fi?QuX z7<=@~jP2gQ*pp{4wy&14KclW*)cx`y#`;nBYloPxa0c_0ewF#k9%a4{T*`c>-otzq zJC89&eau$__$QV#-!!BHj=mYwneVbL=DYf7=4+~EzGY?1_l1X;Z%r}tIY{@l z+nDbg2=Dy>^Zgj<{u}WRewq0m{wecq`!4f!BmBd~%(wq8=6i7`^ZoTj=6kJ&6_m_i z1@HL?D>%8B6@2KMtl;c>SV7e^RxoXA^8ZDjX9W#+v4WWov4Sg}V+Gfq!3yR*$_f@7 zVFgQ&CkpuIA7=$?3RuA{wX9&>epc{xlzrDBR`9Lytl)cq-*+u5_^&Qj@IOtgVB=0! zuxSY^c;rW{U?fEu)>p? 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--- a/pipelined/src/fma/Makefile +++ b/pipelined/src/fma/Makefile @@ -1,10 +1,10 @@ TARGET ?= fma +# for some reason, softfloat.a needs to be symlinked to the local directory. -L isn't working $(TARGET): $(TARGET).c Makefile - gcc -c -I../../../addins/SoftFloat-3e/source/include -O2 -o $(TARGET).o $(TARGET).c - gcc -L../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC \ - -o $(TARGET) $(TARGET).o softfloat.a \ + gcc -O2 -o $(TARGET) $(TARGET).c softfloat.a \ + -I../../../addins/SoftFloat-3e/source/include \ + -L../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC clean: - rm $(TARGET).o rm $(TARGET) From 85b5d92f3f229b571eb2b72657bd243890fce78b Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 26 Feb 2022 14:10:27 -0600 Subject: [PATCH 047/199] Update Makefile for SoftFloat-3e --- tests/fp/sample/Makefile | 19 +++++++++++++++++++ tests/fp/sample/compile.sh | 3 --- tests/fp/sample/div | Bin 0 -> 17456 bytes tests/fp/sample/fma | Bin 0 -> 17544 bytes 4 files changed, 19 insertions(+), 3 deletions(-) create mode 100644 tests/fp/sample/Makefile delete mode 100755 tests/fp/sample/compile.sh create mode 100755 tests/fp/sample/div create mode 100755 tests/fp/sample/fma diff --git a/tests/fp/sample/Makefile b/tests/fp/sample/Makefile new file mode 100644 index 000000000..7ca0b2926 --- /dev/null +++ b/tests/fp/sample/Makefile @@ -0,0 +1,19 @@ +# Makefile + +CC = gcc +CFLAGS = -O3 +LIBS = -lm +LFLAGS = -L. +IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ +LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a +SRCS = $(wildcard *.c) + +PROGS = $(patsubst %.c,%,$(SRCS)) + +all: $(PROGS) + +%: %.c + $(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) + +clean: + rm -f $(PROGS) diff --git a/tests/fp/sample/compile.sh b/tests/fp/sample/compile.sh deleted file mode 100755 index 24d71efa2..000000000 --- a/tests/fp/sample/compile.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh -gcc -c -I. -I../../source/include -O2 -o $1.o $1.c -gcc -I -I. -I../../source/include -o $1 $1.o softfloat.a diff --git a/tests/fp/sample/div b/tests/fp/sample/div new file mode 100755 index 0000000000000000000000000000000000000000..f1fefd76b9396cedddab26453b98089c8c5daa9b GIT binary patch literal 17456 zcmeHPe{fXCec#g$5XioFP!r3TniGK(+2N3|kVPC-cS1k*;u8=MF^ywCPP&u0v7}S) z-Z_G?gUCr9KZ6oF4JmCi9hzyUX*!ABPHSU#8t#w*1-r2@jqMDR7AVvw2(iG%2xIa3 z{qEcE>D}q%&ZPaPncErNclY!Cx!>J=@9o`N?QZfl7ual!N+J7whONp4CgPTizAwrO z5I3u3cf#jVb|0Gq?IMAhe78w}YnFElGHHp#3xT3u8CG)8B__;>QiMoRZ?@vZfS?d% z4zrDV#aNZ?Y`Q`QMwIwze@;|};uN20nv(q^YSqI~4zDuh57%YVuS&gsNl6czs5dJ0 zMx`Fn2@D7dQOYOg1pjJfKC`J4cvzg`ld){QZBj3rHcEM-=mX1^i(23}@wZ9pt#k@A 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zc1=_oLsp4w<@O+olnDn~M5P8di%Od6;0_vrSQ*$MC-)9Nv~kJQVa{?>g7av~*U<)L zrZ`4eRAPncz^cKk*dI^n&XKMOSeA{%`xd6W|CQASFXxHggdg4OuzWSvQ%X$jMrq;? z??)L~g-p8qHYv|^F*8ca*HebwS@OJJVrpkbNweke0*+U3LAIaw^-Q^a-q&Z_?}I$; z=~1o6WtQiC8q=pxm!3#RdZOzv?a5i5_j63Gl9}yiKBkYL zp7!`$=6xU2Dk-0Bzl6mAGUQX1=lvnmm}KPkv-|%eDPJr3_&Eks_7lldK3o1Dfss#G zKW<*kBx&}}D0}>$$&$BAxfGS^m}IFJ|B@x|lnhLne=7Osv*dZ7%k+Pfe<4f$eks7T zpC9;01G4oU$dc#hWK8+_nG`q1n)5^t<46AI@fUU!DA|p_*uiC{Z2$iT)#>u3c9WlJ z_7ayZe=19UP|7pilrqfJ%kg8Dgm@nrnj>=AN$uOLk@xEPrzfF*9T^$?S`QIW3M(d16h^aF7wVtCX2 Date: Sat, 26 Feb 2022 14:17:41 -0600 Subject: [PATCH 048/199] Update FP vector scripts for testing 754 --- tests/fp/create_vectors16.sh | 2 +- tests/fp/create_vectors32.sh | 2 +- tests/fp/create_vectors32_64.sh | 2 +- tests/fp/create_vectors32cmp.sh | 2 +- tests/fp/create_vectors64.sh | 2 +- tests/fp/create_vectors64_32.sh | 2 +- tests/fp/create_vectors64cmp.sh | 2 +- tests/fp/create_vectorsi.sh | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/fp/create_vectors16.sh b/tests/fp/create_vectors16.sh index 5b4d3dc3b..85bfacaaa 100755 --- a/tests/fp/create_vectors16.sh +++ b/tests/fp/create_vectors16.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen -rnear_even f16_add > $OUTPUT/f16_add_rne.tv diff --git a/tests/fp/create_vectors32.sh b/tests/fp/create_vectors32.sh index a862de769..003d8ee31 100755 --- a/tests/fp/create_vectors32.sh +++ b/tests/fp/create_vectors32.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen -rnear_even f32_add > $OUTPUT/f32_add_rne.tv diff --git a/tests/fp/create_vectors32_64.sh b/tests/fp/create_vectors32_64.sh index 57cc763cb..be14f71d2 100755 --- a/tests/fp/create_vectors32_64.sh +++ b/tests/fp/create_vectors32_64.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen -rnear_even f32_to_f64 > $OUTPUT/f32_f64_rne.tv diff --git a/tests/fp/create_vectors32cmp.sh b/tests/fp/create_vectors32cmp.sh index 49fd041e6..eb4acec71 100755 --- a/tests/fp/create_vectors32cmp.sh +++ b/tests/fp/create_vectors32cmp.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen f32_eq > $OUTPUT/f32_cmp_eq.tv diff --git a/tests/fp/create_vectors64.sh b/tests/fp/create_vectors64.sh index d34666190..b21d2c260 100755 --- a/tests/fp/create_vectors64.sh +++ b/tests/fp/create_vectors64.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen -rnear_even f64_add > $OUTPUT/f64_add_rne.tv diff --git a/tests/fp/create_vectors64_32.sh b/tests/fp/create_vectors64_32.sh index a1c45f215..db6117c91 100755 --- a/tests/fp/create_vectors64_32.sh +++ b/tests/fp/create_vectors64_32.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen -rnear_even f64_to_f32 > $OUTPUT/f64_f32_rne.tv diff --git a/tests/fp/create_vectors64cmp.sh b/tests/fp/create_vectors64cmp.sh index ca286caa8..7f5f8c0ba 100755 --- a/tests/fp/create_vectors64cmp.sh +++ b/tests/fp/create_vectors64cmp.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen f64_eq > $OUTPUT/f64_cmp_eq.tv diff --git a/tests/fp/create_vectorsi.sh b/tests/fp/create_vectorsi.sh index 82654fa1c..5d753e500 100755 --- a/tests/fp/create_vectorsi.sh +++ b/tests/fp/create_vectorsi.sh @@ -1,6 +1,6 @@ #!/bin/sh -BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" $BUILD/testfloat_gen -rnear_even -i32_to_f64 > $OUTPUT/i32_f64_rne.tv From 40bc3800731ee9ca4465a945d58f0289d76cd979 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 04:36:01 +0000 Subject: [PATCH 049/199] fma passing multiply vectors --- pipelined/src/fma/Makefile | 23 +++++++--- pipelined/src/fma/fma.c | 47 -------------------- pipelined/src/fma/fma16.sv | 70 +++++++++++++++++++++--------- pipelined/src/fma/fma16_testgen.py | 31 ------------- pipelined/src/fma/softfloat.a | 1 - 5 files changed, 65 insertions(+), 107 deletions(-) delete mode 100644 pipelined/src/fma/fma.c delete mode 100755 pipelined/src/fma/fma16_testgen.py delete mode 120000 pipelined/src/fma/softfloat.a diff --git a/pipelined/src/fma/Makefile b/pipelined/src/fma/Makefile index 270954f72..7ca0b2926 100644 --- a/pipelined/src/fma/Makefile +++ b/pipelined/src/fma/Makefile @@ -1,10 +1,19 @@ -TARGET ?= fma +# Makefile -# for some reason, softfloat.a needs to be symlinked to the local directory. -L isn't working -$(TARGET): $(TARGET).c Makefile - gcc -O2 -o $(TARGET) $(TARGET).c softfloat.a \ - -I../../../addins/SoftFloat-3e/source/include \ - -L../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC +CC = gcc +CFLAGS = -O3 +LIBS = -lm +LFLAGS = -L. +IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ +LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a +SRCS = $(wildcard *.c) + +PROGS = $(patsubst %.c,%,$(SRCS)) + +all: $(PROGS) + +%: %.c + $(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) clean: - rm $(TARGET) + rm -f $(PROGS) diff --git a/pipelined/src/fma/fma.c b/pipelined/src/fma/fma.c deleted file mode 100644 index 4b7bda1fd..000000000 --- a/pipelined/src/fma/fma.c +++ /dev/null @@ -1,47 +0,0 @@ -#include -#include -#include "softfloat.h" -#include "softfloat_types.h" - -int float_rounding_mode = 0; - -union sp { - unsigned short x[2]; - float y; -} X; - - -int main() -{ - uint8_t rounding_mode; - uint8_t exceptions; - - uint32_t multiplier, multiplicand, addend, result; - float32_t f_multiplier, f_multiplicand, f_addend, f_result; - - multiplier = 0xbf800000; - multiplicand = 0xbf800000; - addend = 0xffaaaaaa; - - f_multiplier.v = multiplier; - f_multiplicand.v = multiplicand; - f_addend.v = addend; - - softfloat_roundingMode = rounding_mode; - softfloat_exceptionFlags = 0; - softfloat_detectTininess = softfloat_tininess_beforeRounding; - - f_result = f32_mulAdd(f_multiplier, f_multiplicand, f_addend); - - result = f_result.v; - exceptions = softfloat_exceptionFlags & 0x1f; - - printf("%x\n", f_result.v); - - // Print out SP number - X.x[1] = (f_result.v & 0xffff0000) >> 16; - X.x[0] = (f_result.v & 0x0000ffff); - printf("Number = %f\n", X.y); - - return 0; -} diff --git a/pipelined/src/fma/fma16.sv b/pipelined/src/fma/fma16.sv index c537baf6d..9732d6c93 100644 --- a/pipelined/src/fma/fma16.sv +++ b/pipelined/src/fma/fma16.sv @@ -13,20 +13,25 @@ module fma16( input logic [15:0] x, y, z, - input logic add, mul, negp, negz, + input logic mul, add, negp, negz, input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn output logic [15:0] result); logic [10:0] xm, ym, zm; - logic [4:0] xe, ye, ze; - logic xs, ys, zs; - logic zs1; // sign before optional negation - logic ps; // sign of product + logic [4:0] xe, ye, ze; + logic xs, ys, zs; + logic zs1; // sign before optional negation + logic [21:0] pm; + logic [5:0] pe; + logic ps; // sign of product + logic [22:0] rm; + logic [6:0] re; + logic rs; unpack unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs signadj signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations - mult mult(mul, xm, ym, xe, ye, pm, pe); // p = x * y - add add(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p + mult m(mul, xm, ym, xe, ye, pm, pe); // p = x * y + add a(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p postproc post(roundmode, rm, re, rs, result); // normalize, round, pack endmodule @@ -34,13 +39,12 @@ module mult( input logic mul, input logic [10:0] xm, ym, input logic [4:0] xe, ye, - input logic xs, ys, output logic [21:0] pm, output logic [5:0] pe); // only multiply if mul = 1 - assign pm = mul ? xm * ym : xm; // multiply mantiassas - assign pe = mul ? xe + ye : xe; + assign pm = mul ? xm * ym : {1'b0, xm, 10'b0}; // multiply mantiassas + assign pe = mul ? xe + ye : {1'b0, xe}; endmodule module add( @@ -58,15 +62,18 @@ module add( logic [6:0] are; logic ars; + /* alignshift as(pe, ze, zm, zmaligned); condneg cnp(pm, ps, pmn); condneg cnz(zm, zs, zmn); + assign + */ // add or pass product through - assign rm = add ? arm : pm; - assign re = add ? are : pe; + assign rm = add ? arm : {1'b0, pm}; + assign re = add ? are : {1'b0, pe}; assign rs = add ? ars : ps; -); +endmodule module postproc( input logic [1:0] roundmode, @@ -75,6 +82,33 @@ module postproc( input logic rs, output logic [15:0] result); + logic [9:0] uf, uff; + logic [6:0] ue; + logic [6:0] ueb, uebiased; + + always_comb + if (rm[21]) begin // normalization right shift by 1 and bump up exponent; + ue = re + 7'b1; + uf = rm[20:11]; + end else begin // no normalization shift needed + ue = re; + uf = rm[19:10]; + end + + // overflow + always_comb begin + ueb = ue-7'd15; + if (ue >= 7'd46) begin // overflow + uebiased = 5'd30; + uff = 10'h3ff; + end else begin + uebiased = ue-7'd15; + uff = uf; + end + end + + assign result = {rs, uebiased[4:0], uff}; + // add special case handling for zeros, NaN, Infinity endmodule @@ -107,15 +141,9 @@ module unpacknum( logic [9:0] f; // fraction without leading 1 logic [4:0] eb; // biased exponent - assign {f, eb, s} = num; // pull bit fields out of floating-point number + assign {s, eb, f} = num; // pull bit fields out of floating-point number assign m = {1'b1, f}; // prepend leading 1 to fraction - assign e = eb - 15; // remove bias from exponent + assign e = eb; // leave bias in exponent *** endmodule -// Tests: -// Every permutation for x, y, z of -// mantissa = {1.0, 1.0000000001, 1.1, 1.1111111110, 1.1111111111} -// biased exponent = {1, 2, 14, 15, 16, 21, 29, 30} -// sign = {0, 1} -// special case: [normal, 0, INF, NaN] \ No newline at end of file diff --git a/pipelined/src/fma/fma16_testgen.py b/pipelined/src/fma/fma16_testgen.py deleted file mode 100755 index c3cc8d72f..000000000 --- a/pipelined/src/fma/fma16_testgen.py +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/python3 - -# fma16_testgen.py -# David_Harris@hmc.edu 26 February 2022 -# Generate test cases for 16-bit FMA - -def makeVal(val): - -def makeCase(x, y, z, mul, add, msg): - xval = makeVal(x); - yval = makeVal(y); - zval = makeVal(z); - mode = mul*2+add; # convert to hexadecimal code - expected = makeExpected(x, y, z, mul, add); - print(xval,"_", yval, "_", zval, "_", mode, "_", expected, " //", msg); - -def makeMulCase(x, y, msg): - makeCase(x, y, "0", 1, 0, msg) - -################################ -## Main program -################################ - -# Directed cases -makeMulCase("1", "1", "1 x 1"); - - -# Corner cases - -# Random cases - diff --git a/pipelined/src/fma/softfloat.a b/pipelined/src/fma/softfloat.a deleted file mode 120000 index 508aa0da8..000000000 --- a/pipelined/src/fma/softfloat.a +++ /dev/null @@ -1 +0,0 @@ -../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a \ No newline at end of file From 283a25e1a763cf72d8174b6be7ca49efcb377165 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 04:36:43 +0000 Subject: [PATCH 050/199] fma simulation infrastructure --- pipelined/src/fma/fma.do | 23 +++++ pipelined/src/fma/fma16_testgen.c | 142 ++++++++++++++++++++++++++++++ pipelined/src/fma/lint-fma | 8 ++ pipelined/src/fma/sim-fma | 2 + pipelined/src/fma/testbench.sv | 50 +++++++++++ 5 files changed, 225 insertions(+) create mode 100644 pipelined/src/fma/fma.do create mode 100644 pipelined/src/fma/fma16_testgen.c create mode 100755 pipelined/src/fma/lint-fma create mode 100755 pipelined/src/fma/sim-fma create mode 100644 pipelined/src/fma/testbench.sv diff --git a/pipelined/src/fma/fma.do b/pipelined/src/fma/fma.do new file mode 100644 index 000000000..40956e514 --- /dev/null +++ b/pipelined/src/fma/fma.do @@ -0,0 +1,23 @@ +# fma.do +# +# run with vsim -do "do fma.do" +# add -c before -do for batch simulation + +onbreak {resume} + +# create library +vlib worklib + +vlog -lint -work worklib fma16.sv testbench.sv +vopt +acc worklib.testbench -work worklib -o testbenchopt +vsim -lib worklib testbenchopt + +add wave sim:/testbench/clk +add wave sim:/testbench/reset +add wave sim:/testbench/x +add wave sim:/testbench/y +add wave sim:/testbench/z +add wave sim:/testbench/result +add wave sim:/testbench/rexpected + +run -all \ No newline at end of file diff --git a/pipelined/src/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c new file mode 100644 index 000000000..69bade22f --- /dev/null +++ b/pipelined/src/fma/fma16_testgen.c @@ -0,0 +1,142 @@ +#include +#include +#include "softfloat.h" +#include "softfloat_types.h" + +typedef union sp { + float32_t v; + float f; +} sp; + +// lists of tests, terminated with 0x8000 +uint16_t easyExponents[] = {15, 0x8000}; +uint16_t medExponents[] = {1, 14, 15, 16, 20, 30, 0x8000}; +uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1 +uint16_t medFracts[] = {0, 0x200, 0x001, 0x3FF, 0x8000}; +uint16_t zeros[] = {0x0000, 0x8000}; +uint16_t infs[] = {0x7C00, 0xFC00}; +uint16_t nans[] = {0x7D00, 0x7D01}; + +void softfloatInit(void) { + softfloat_roundingMode = softfloat_round_minMag; + softfloat_exceptionFlags = 0; + softfloat_detectTininess = softfloat_tininess_beforeRounding; +} + +float convFloat(float16_t f16) { + float32_t f32; + float res; + sp r; + + f32 = f16_to_f32(f16); + r.v = f32; + res = r.f; + return res; +} + +void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int zeroAllowed, int infAllowed, int nanAllowed) { + float16_t result; + int op; + char calc[80]; + float32_t x32, y32, z32, r32; + float xf, yf, zf, rf; + float16_t smallest; + + if (!mul) y.v = 0x3C00; // force y to 1 to avoid multiply + if (!add) z.v = 0x0000; // force z to 0 to avoid add + if (negp) x.v ^= 0x8000; // flip sign of x to negate p + if (negz) z.v ^= 0x8000; // flip sign of z to negate z + op = mul<<3 | add<<2 | negp<<1 | negz; + result = f16_mulAdd(x, y, z); + + // convert to floats for printing + xf = convFloat(x); + yf = convFloat(y); + zf = convFloat(z); + rf = convFloat(result); + if (mul) + if (add) sprintf(calc, "%f * %f + %f = %f", xf, yf, zf, rf); + else sprintf(calc, "%f * %f = %f", xf, yf, rf); + else sprintf(calc, "%f + %f = %f", xf, zf, rf); + + // omit denorms, which aren't required for this project + smallest.v = 0x0400; + float16_t resultmag = result; + resultmag.v &= 0x7FFF; // take absolute value + if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: "); + if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: "); + if (resultmag.v == 0x7C00 && !infAllowed) fprintf(fptr, "// Skip inf: "); + if (resultmag.v > 0x7C00 && !nanAllowed) fprintf(fptr, "// Skip NaN: "); + fprintf(fptr, "%04x_%04x_%04x_%02x_%04x // %s\n", x.v, y.v, z.v, op, result.v, calc); +} + +void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases, + FILE *fptr, int *numCases) { + int i, j; + + fprintf(fptr, desc); fprintf(fptr, "\n"); + *numCases=0; + for (i=0; e[i] != 0x8000; i++) + for (j=0; f[j] != 0x8000; j++) { + cases[*numCases].v = f[j] | e[i]<<10; + *numCases = *numCases + 1; + } +} + +void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) { + int i, j, k, numCases; + float16_t x, y, z; + float16_t cases[100000]; + FILE *fptr; + char fn[80]; + + sprintf(fn, "work/%s.tv", testName); + fptr = fopen(fn, "w"); + prepTests(e, f, testName, desc, cases, fptr, &numCases); + z.v = 0x0000; + for (i=0; i < numCases; i++) { + x.v = cases[i].v; + for (j=0; j Date: Sun, 27 Feb 2022 14:20:15 +0000 Subject: [PATCH 051/199] Moved fma directory --- {pipelined/src/fma => fma}/Makefile | 0 fma/div | Bin 0 -> 22376 bytes {pipelined/src/fma => fma}/div.c | 0 {pipelined/src/fma => fma}/fma.do | 0 {pipelined/src/fma => fma}/fma16.sv | 2 +- fma/fma16_testgen | Bin 0 -> 27592 bytes {pipelined/src/fma => fma}/fma16_testgen.c | 2 +- fma/fma32 | Bin 0 -> 22472 bytes fma/fma32.c | 47 +++++++++++++++++++++ {pipelined/src/fma => fma}/lint-fma | 0 {pipelined/src/fma => fma}/sim-fma | 0 {pipelined/src/fma => fma}/testbench.sv | 0 12 files changed, 49 insertions(+), 2 deletions(-) rename {pipelined/src/fma => fma}/Makefile (100%) create mode 100755 fma/div rename {pipelined/src/fma => fma}/div.c (100%) rename {pipelined/src/fma => fma}/fma.do (100%) rename {pipelined/src/fma => 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inf: "); + if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed) fprintf(fptr, "// Skip inf: "); if (resultmag.v > 0x7C00 && !nanAllowed) fprintf(fptr, "// Skip NaN: "); fprintf(fptr, "%04x_%04x_%04x_%02x_%04x // %s\n", x.v, y.v, z.v, op, result.v, calc); } diff --git a/fma/fma32 b/fma/fma32 new file mode 100755 index 0000000000000000000000000000000000000000..44be8588f834e8451238a2fe1f47ea056f972c23 GIT binary patch literal 22472 zcmeHP4RBM}mA;Y<*g*75AqxpDRyKyk6of^9nl=Q9Soo%en1wsjJ2^XMt%yA zWQtkaXbH*`~88L(&OIn4dy_Vw`02*X@v$WMy0u(lprl!P@WK zcdsQqNm*uRw@IeH_S3odyXTyD?zunjzI)$$yF9)%R*QwnU}ZNjN|j7-ame^(Os(Zf zfmO0%=3;Z$*VsfLg*aS1ho}*gbVR6@v`Fw3fRbFL)c`83E*_Ees|L&@l@=16Ao2|2 z5-EeuFENsmGG^xh$&sxv+6Z$RGU&W9J4C*aBbek$gj|V`leC`{BSuK+rsTa(r>WlWaRc)$NWl33;#oV<#~)nuMQQH=gUO;Olbp; zQClJZ%8*FIsa|BbkcP{)MtLJ?czS=FWpCi3lkh9+n}83LIUlQCe=Jh>OxQWw&eWcm zW=;01T}O-hIKTW!E{h;LIakB4QtCpC(k+xdcqW-l)*WW7^YC*|J@r&lA3Z*y4Vmot zgrGs{h$PBUuERUfZ}dL>xHFb`7GnC>s*%^MycausFLDl2(LYdbo8SbR*bfG0?Djr7 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+ + uint32_t multiplier, multiplicand, addend, result; + float32_t f_multiplier, f_multiplicand, f_addend, f_result; + + multiplier = 0xbf800000; + multiplicand = 0xbf800000; + addend = 0xffaaaaaa; + + f_multiplier.v = multiplier; + f_multiplicand.v = multiplicand; + f_addend.v = addend; + + softfloat_roundingMode = rounding_mode; + softfloat_exceptionFlags = 0; + softfloat_detectTininess = softfloat_tininess_beforeRounding; + + f_result = f32_mulAdd(f_multiplier, f_multiplicand, f_addend); + + result = f_result.v; + exceptions = softfloat_exceptionFlags & 0x1f; + + printf("%x\n", f_result.v); + + // Print out SP number + X.x[1] = (f_result.v & 0xffff0000) >> 16; + X.x[0] = (f_result.v & 0x0000ffff); + printf("Number = %f\n", X.y); + + return 0; +} diff --git a/pipelined/src/fma/lint-fma b/fma/lint-fma similarity index 100% rename from pipelined/src/fma/lint-fma rename to fma/lint-fma diff --git a/pipelined/src/fma/sim-fma b/fma/sim-fma similarity index 100% rename from pipelined/src/fma/sim-fma rename to fma/sim-fma diff --git a/pipelined/src/fma/testbench.sv b/fma/testbench.sv similarity index 100% rename from pipelined/src/fma/testbench.sv rename to fma/testbench.sv From 5b15e552c631b10ea32a9e762af87ffcd26f9f21 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 15:12:10 +0000 Subject: [PATCH 052/199] Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue --- fma/fma16.sv | 4 ++-- fma/testbench.sv | 2 +- pipelined/regression/Makefile | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/fma/fma16.sv b/fma/fma16.sv index 5fe63b1d3..995483457 100644 --- a/fma/fma16.sv +++ b/fma/fma16.sv @@ -99,8 +99,8 @@ module postproc( always_comb begin ueb = ue-7'd15; if (ue >= 7'd46) begin // overflow - uebiased = 7'd30; - uff = 10'h3ff; +/* uebiased = 7'd30; + uff = 10'h3ff; */ end else begin uebiased = ue-7'd15; uff = uf; diff --git a/fma/testbench.sv b/fma/testbench.sv index c5e89cf30..f37561ba8 100644 --- a/fma/testbench.sv +++ b/fma/testbench.sv @@ -20,7 +20,7 @@ module testbench; // at start of test, load vectors and pulse reset initial begin - $readmemh("work/fmul_1.tv", testvectors); + $readmemh("work/fmul_2.tv", testvectors); vectornum = 0; errors = 0; reset = 1; #22; reset = 0; end diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile index 72eadd5ba..0176b7eca 100644 --- a/pipelined/regression/Makefile +++ b/pipelined/regression/Makefile @@ -10,9 +10,9 @@ make clean: make all: # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test - # Also delete bin/exe2memfile at that point - make -C ../../tests/imperas-riscv-tests --jobs - make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs + # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired + #make -C ../../tests/imperas-riscv-tests --jobs + #make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs # Build riscv-arch-test 64 and 32-bit versions make -C ../../addins/riscv-arch-test --jobs From 62d62f9a9ec06fc94a33c857a833b01f84fdff8e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 15:41:41 +0000 Subject: [PATCH 053/199] Moved FMA back into source tree to facilitate synthesis --- {fma => pipelined/src/fma}/Makefile | 0 {fma => pipelined/src/fma}/div | Bin {fma => pipelined/src/fma}/div.c | 0 {fma => pipelined/src/fma}/fma.do | 2 +- {fma => pipelined/src/fma}/fma16.sv | 28 ++++++++++----------- {fma => pipelined/src/fma}/fma16_testgen | Bin {fma => pipelined/src/fma}/fma16_testgen.c | 0 {fma => pipelined/src/fma}/fma32 | Bin {fma => pipelined/src/fma}/fma32.c | 0 {fma => pipelined/src/fma}/lint-fma | 0 {fma => pipelined/src/fma}/sim-fma | 0 {fma => pipelined/src/fma}/testbench.sv | 2 +- 12 files changed, 16 insertions(+), 16 deletions(-) rename {fma => pipelined/src/fma}/Makefile (100%) rename {fma => pipelined/src/fma}/div (100%) rename {fma => pipelined/src/fma}/div.c (100%) rename {fma => pipelined/src/fma}/fma.do (85%) rename {fma => pipelined/src/fma}/fma16.sv (84%) rename {fma => pipelined/src/fma}/fma16_testgen (100%) rename {fma => pipelined/src/fma}/fma16_testgen.c (100%) rename {fma => pipelined/src/fma}/fma32 (100%) rename {fma => pipelined/src/fma}/fma32.c (100%) rename {fma => pipelined/src/fma}/lint-fma (100%) rename {fma => pipelined/src/fma}/sim-fma (100%) rename {fma => pipelined/src/fma}/testbench.sv (98%) diff --git a/fma/Makefile b/pipelined/src/fma/Makefile similarity index 100% rename from fma/Makefile rename to pipelined/src/fma/Makefile diff --git a/fma/div b/pipelined/src/fma/div similarity index 100% rename from fma/div rename to pipelined/src/fma/div diff --git a/fma/div.c b/pipelined/src/fma/div.c similarity index 100% rename from fma/div.c rename to pipelined/src/fma/div.c diff --git a/fma/fma.do b/pipelined/src/fma/fma.do similarity index 85% rename from fma/fma.do rename to pipelined/src/fma/fma.do index 40956e514..6f53eacce 100644 --- a/fma/fma.do +++ b/pipelined/src/fma/fma.do @@ -9,7 +9,7 @@ onbreak {resume} vlib worklib vlog -lint -work worklib fma16.sv testbench.sv -vopt +acc worklib.testbench -work worklib -o testbenchopt +vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt vsim -lib worklib testbenchopt add wave sim:/testbench/clk diff --git a/fma/fma16.sv b/pipelined/src/fma/fma16.sv similarity index 84% rename from fma/fma16.sv rename to pipelined/src/fma/fma16.sv index 995483457..d2f34430a 100644 --- a/fma/fma16.sv +++ b/pipelined/src/fma/fma16.sv @@ -28,14 +28,14 @@ module fma16( logic [6:0] re; logic rs; - unpack unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs - signadj signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations - mult m(mul, xm, ym, xe, ye, pm, pe); // p = x * y - add a(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p - postproc post(roundmode, rm, re, rs, result); // normalize, round, pack + unpack16 unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs + signadj16 signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations + mult16 m(mul, xm, ym, xe, ye, pm, pe); // p = x * y + add16 a(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p + postproc16 post(roundmode, rm, re, rs, result); // normalize, round, pack endmodule -module mult( +module mult16( input logic mul, input logic [10:0] xm, ym, input logic [4:0] xe, ye, @@ -47,7 +47,7 @@ module mult( assign pe = mul ? xe + ye : {1'b0, xe}; endmodule -module add( +module add16( input logic add, input logic [21:0] pm, input logic [10:0] zm, @@ -75,7 +75,7 @@ module add( assign rs = add ? ars : ps; endmodule -module postproc( +module postproc16( input logic [1:0] roundmode, input logic [22:0] rm, input logic [6:0] re, @@ -112,7 +112,7 @@ module postproc( // add special case handling for zeros, NaN, Infinity endmodule -module signadj( +module signadj16( input logic negx, negz, input logic xs, ys, zs1, output logic ps, zs); @@ -121,18 +121,18 @@ module signadj( assign zs = zs1 ^ negz; // endmodule -module unpack( +module unpack16( input logic [15:0] x, y, z, output logic [10:0] xm, ym, zm, output logic [4:0] xe, ye, ze, output logic xs, ys, zs); - unpacknum upx(x, xm, xe, xs); - unpacknum upy(y, ym, ye, ys); - unpacknum upz(z, zm, ze, zs); + unpacknum16 upx(x, xm, xe, xs); + unpacknum16 upy(y, ym, ye, ys); + unpacknum16 upz(z, zm, ze, zs); endmodule -module unpacknum( +module unpacknum16( input logic [15:0] num, output logic [10:0] m, output logic [4:0] e, diff --git a/fma/fma16_testgen b/pipelined/src/fma/fma16_testgen similarity index 100% rename from fma/fma16_testgen rename to pipelined/src/fma/fma16_testgen diff --git a/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c similarity index 100% rename from fma/fma16_testgen.c rename to pipelined/src/fma/fma16_testgen.c diff --git a/fma/fma32 b/pipelined/src/fma/fma32 similarity index 100% rename from fma/fma32 rename to pipelined/src/fma/fma32 diff --git a/fma/fma32.c b/pipelined/src/fma/fma32.c similarity index 100% rename from fma/fma32.c rename to pipelined/src/fma/fma32.c diff --git a/fma/lint-fma b/pipelined/src/fma/lint-fma similarity index 100% rename from fma/lint-fma rename to pipelined/src/fma/lint-fma diff --git a/fma/sim-fma b/pipelined/src/fma/sim-fma similarity index 100% rename from fma/sim-fma rename to pipelined/src/fma/sim-fma diff --git a/fma/testbench.sv b/pipelined/src/fma/testbench.sv similarity index 98% rename from fma/testbench.sv rename to pipelined/src/fma/testbench.sv index f37561ba8..2767c4899 100644 --- a/fma/testbench.sv +++ b/pipelined/src/fma/testbench.sv @@ -1,5 +1,5 @@ /* verilator lint_off STMTDLY */ -module testbench; +module testbench_fma16; logic clk, reset; logic [15:0] x, y, z, rexpected, result; logic [7:0] ctrl; From 3675a813c65178ae2d8a804622dff11d41709f68 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 17:23:33 +0000 Subject: [PATCH 054/199] Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior --- pipelined/src/fma/Makefile | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/pipelined/src/fma/Makefile b/pipelined/src/fma/Makefile index 7ca0b2926..4d0efe20e 100644 --- a/pipelined/src/fma/Makefile +++ b/pipelined/src/fma/Makefile @@ -4,8 +4,12 @@ CC = gcc CFLAGS = -O3 LIBS = -lm LFLAGS = -L. -IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ -LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a +# Link against the riscv-isa-sim version of SoftFloat rather than +# the regular version to get RISC-V NaN behavior +IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat +LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a +#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ +#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a SRCS = $(wildcard *.c) PROGS = $(patsubst %.c,%,$(SRCS)) From dbd73e8cfdec7ca48ea617bc1ba84a189bfc9485 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 17:35:09 +0000 Subject: [PATCH 055/199] Moved regression work directories to regression/wkdir to reduce clutter --- pipelined/regression/wally-pipelined-batch.do | 18 +++++++++--------- pipelined/regression/wkdir/README | 0 2 files changed, 9 insertions(+), 9 deletions(-) create mode 100644 pipelined/regression/wkdir/README diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 6520660b6..f12b3f78c 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -20,10 +20,10 @@ onbreak {resume} # create library -if [file exists work_${1}_${2}] { - vdel -lib work_${1}_${2} -all +if [file exists wkdir/work_${1}_${2}] { + vdel -lib wkdir/work_${1}_${2} -all } -vlib work_${1}_${2} +vlib wkdir/work_${1}_${2} # compile source files # suppress spurious warnngs about @@ -33,21 +33,21 @@ vlib work_${1}_${2} # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32ic rv32ic if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt work_${1}_${2}.testbench -work work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084 + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt + vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084 run -all run -all exec ./slack-notifier/slack-notifier.py quit } else { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals - vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt + vsim -lib wkdir/work_${1}_${2} testbenchopt # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf #vsim -coverage -lib work_$2 workopt_$2 diff --git a/pipelined/regression/wkdir/README b/pipelined/regression/wkdir/README new file mode 100644 index 000000000..e69de29bb From f4be78ecc3563eaad175b4798eb64bf174a40233 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 18:17:21 +0000 Subject: [PATCH 056/199] Created softfloat_demo showcasing how to do math with SoftFloat --- .gitignore | 2 + examples/fp/softfloat_demo/Makefile | 23 +++++++++ examples/fp/softfloat_demo/softfloat_demo.c | 53 ++++++++++++++++++++ pipelined/src/fma/div | Bin 22376 -> 0 bytes pipelined/src/fma/div.c | 52 ------------------- pipelined/src/fma/fma16_testgen | Bin 27592 -> 0 bytes pipelined/src/fma/fma32 | Bin 22472 -> 0 bytes pipelined/src/fma/fma32.c | 47 ----------------- 8 files changed, 78 insertions(+), 99 deletions(-) create mode 100644 examples/fp/softfloat_demo/Makefile create mode 100644 examples/fp/softfloat_demo/softfloat_demo.c delete mode 100755 pipelined/src/fma/div delete mode 100644 pipelined/src/fma/div.c delete mode 100755 pipelined/src/fma/fma16_testgen delete mode 100755 pipelined/src/fma/fma32 delete mode 100644 pipelined/src/fma/fma32.c diff --git a/.gitignore b/.gitignore index 9b3e6dc62..6ea4b650e 100644 --- a/.gitignore +++ b/.gitignore @@ -52,6 +52,8 @@ examples/asm/sumtest/sumtest examples/asm/example/example examples/C/sum/sum examples/C/fir/fir +examples/fp/softfloat_demo/softfloat_demo +pipelined/src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh linux/testvector-generation/genCheckpoint.gdb diff --git a/examples/fp/softfloat_demo/Makefile b/examples/fp/softfloat_demo/Makefile new file mode 100644 index 000000000..4d0efe20e --- /dev/null +++ b/examples/fp/softfloat_demo/Makefile @@ -0,0 +1,23 @@ +# Makefile + +CC = gcc +CFLAGS = -O3 +LIBS = -lm +LFLAGS = -L. +# Link against the riscv-isa-sim version of SoftFloat rather than +# the regular version to get RISC-V NaN behavior +IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat +LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a +#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ +#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a +SRCS = $(wildcard *.c) + +PROGS = $(patsubst %.c,%,$(SRCS)) + +all: $(PROGS) + +%: %.c + $(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) + +clean: + rm -f $(PROGS) diff --git a/examples/fp/softfloat_demo/softfloat_demo.c b/examples/fp/softfloat_demo/softfloat_demo.c new file mode 100644 index 000000000..0f34ac255 --- /dev/null +++ b/examples/fp/softfloat_demo/softfloat_demo.c @@ -0,0 +1,53 @@ +// softfloat_demo.c +// David_Harris@hmc.edu 27 February 2022 +// +// Demonstrate using SoftFloat do compute a floating-point, then print results + +#include +#include +#include "softfloat.h" +#include "softfloat_types.h" +typedef union sp { + uint32_t v; + float f; +} sp; + +void printF32(char *msg, float32_t f) { + sp conv; + conv.v = f.v; // use union to convert between hexadecimal and floating-point views + printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); +} + +void printFlags(void) { + int NX = softfloat_exceptionFlags % 2; + int UF = (softfloat_exceptionFlags >> 1) % 2; + int OF = (softfloat_exceptionFlags >> 2) % 2; + int DZ = (softfloat_exceptionFlags >> 3) % 2; + int NV = (softfloat_exceptionFlags >> 4) % 2; + printf ("exceptions: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", + NX, UF, OF, DZ, NV); +} + +void softfloatInit(void) { + // rounding modes: RNE: softfloat_round_near_even + // RZ: softfloat_round_minMag + // RP: softfloat_round_max + // RM: softfloat_round_min + softfloat_roundingMode = softfloat_round_near_even; + softfloat_exceptionFlags = 0; // clear exceptions + softfloat_detectTininess = softfloat_tininess_beforeRounding; // RISC-V behavior for tininess +} + +int main() +{ + float32_t x, y, z, r; + + x.v = 0x3fc00000; + y.v = 0x3fc00000; + z.v = 0x00000001; + + softfloatInit(); + r = f32_mulAdd(x, y, z); + printF32("X", x); printF32("Y", y); printF32("Z", z); + printF32("result = X*Y+Z", r); printFlags(); +} diff --git a/pipelined/src/fma/div b/pipelined/src/fma/div deleted file mode 100755 index faeb00d9780c130fc13bf8389a7432620000dd33..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 22376 zcmeHP4{%$>nP16&V#kRjAR*>YlSeP)lF%r2u!D0njgbT9bgjXi3BAnC+zg#El-@Ac++CZd*Ou7iA8_=}KwCI+y-6T&3LzKMLJ|^U z-S_R=PkQg^iDqu@3QV>3d*AMFzwdjy-~M^4-F^E|i@()wvoUgZ_9cd)?g|fwv^!&& z4Lm5YCRWWnY(D!Os|2JRE)S1Es`-ds5UPn*3BEF*DA#1yfF`?#dx+ks!Hg)S5NU;o z(}+ieH2R!F3le2a;sDBFS|QPzo8N7qi$pp+f|48tQO+ggTtbfMq(~T1${*$puP&jl z%kF^?hCN7FGr#94@}k@LmKsFAe-;k{^>7c-pawIdB==>IC!zS^(Vs>F< z4?#tC+44xZXJy0kNN`ys98GRtw!LZPvXu?)M9jT{=Nt7SZ(GM^{v<4KQiW-r0~cZ# zpLNOWp7{GW_c{Agm%rn^^qtplSN;}d=>qQ+yE@>MEVyd`yV?Rr%nJ7dE?My3T?A)f zk6z6FN;VV^N7X*2Cy#Dl74Al+_`2GaU??8y4=2=6ysLd( zBo+;I1$rVOknA6fMTMlIv05_n^x1QE#h{JBGegT&;Kan+uklv9VQ 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fsZH~KOP@G^DBZ+}-#l5#KaVd4aMzgxOhNWPPs -#include -#include "softfloat.h" -#include "softfloat_types.h" - -int float_rounding_mode = 0; - -union dp { - unsigned short x[4]; - double y; -} X; - - -int main() -{ - uint8_t rounding_mode; - uint8_t exceptions; - - uint64_t n, d, result; - float64_t d_n, d_d, d_result; - - n = 0x3feffffffefffff6; - d = 0xffeffffffffffffe; - //n = 0x00000000400001ff; - //d = 0x3ffffdfffffffbfe; - - d_n.v = n; - d_d.v = d; - - softfloat_roundingMode = rounding_mode; - softfloat_exceptionFlags = 0; - softfloat_detectTininess = softfloat_tininess_beforeRounding; - - d_result = f64_div(d_n, d_d); - - //result = d_result.v; - //exceptions = softfloat_exceptionFlags & 0x1f; - - X.x[3] = (d_result.v & 0xffff000000000000) >> 48; - X.x[2] = (d_result.v & 0x0000ffff00000000) >> 32; - X.x[1] = (d_result.v & 0x00000000ffff0000) >> 16; - X.x[0] = (d_result.v & 0x000000000000ffff); - - printf("Number = %.4x\n", X.x[3]); - printf("Number = %.4x\n", X.x[2]); - printf("Number = %.4x\n", X.x[1]); - printf("Number = %.4x\n", X.x[0]); - printf("Number = %1.25lg\n", X.y); - - - return 0; -} diff --git a/pipelined/src/fma/fma16_testgen b/pipelined/src/fma/fma16_testgen deleted file mode 100755 index 625c721897366e56d5283567e853a5d456632a6c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 27592 zcmeHw3v^T0neLHngUv(73?w)t!Rn0Ym^28B05xft=zwG&Wn`e(5JEy^VN2k|wtV#n zBrDU{l}$K9+1TtwbA&GUr zf1karho#=ES?f;H8E=sOy}$kc|Ni&CA7`I^j42 z+Q5<=tB{H$yEIq2UYZ0XA0Io*A*#m&z06e$TFCkGKuNB`r~?&7JBtWPicn8aFRpys)WZK~rN(Wcz~c6-yT^U2F{ntczH^Nk8#cty;%QqV^W5 z$mUu25JveYe|7QfO(*uuTv=iJ_K%-mf9_zxi@zsX@j>)UhZ=C2vv5>T8kwt&woO z}_n3s@$#>D?N*>i>yl|kE^!Y)8GsGwls#q zzF=+j%BDbzuhzS{$tQU{TbctcT+*YnW@RKhjr^a85oTcjFrFxZ5Si0hMEO;EQW{!V z$70l%sr^NWr{JQ`Q{KfCJhlH{PQj-LC7>ncbu2X*-=aSfU{1lQUy4wcf~U?qVGvLI$27Jq< zcEl*XmGXv%5(x7)Qkq;fJiyXxDNR)yjJEZ z;u$yR*D-$J3Nn3*x1)|spzPm}SC?;g(C15R5Eye0kQAKQ7C_VV4Tc1Df9b8$_r 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- - -int main() -{ - uint8_t rounding_mode; - uint8_t exceptions; - - uint32_t multiplier, multiplicand, addend, result; - float32_t f_multiplier, f_multiplicand, f_addend, f_result; - - multiplier = 0xbf800000; - multiplicand = 0xbf800000; - addend = 0xffaaaaaa; - - f_multiplier.v = multiplier; - f_multiplicand.v = multiplicand; - f_addend.v = addend; - - softfloat_roundingMode = rounding_mode; - softfloat_exceptionFlags = 0; - softfloat_detectTininess = softfloat_tininess_beforeRounding; - - f_result = f32_mulAdd(f_multiplier, f_multiplicand, f_addend); - - result = f_result.v; - exceptions = softfloat_exceptionFlags & 0x1f; - - printf("%x\n", f_result.v); - - // Print out SP number - X.x[1] = (f_result.v & 0xffff0000) >> 16; - X.x[0] = (f_result.v & 0x0000ffff); - printf("Number = %f\n", X.y); - - return 0; -} From 50f56077993b5b00392fbaf477f3b6c85d46c1fb Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 27 Feb 2022 20:35:01 +0000 Subject: [PATCH 057/199] New softfloat_calc program --- .gitignore | 1 + examples/fp/softfloat_calc/softfloat_calc.c | 211 ++++++++++++++++++++ 2 files changed, 212 insertions(+) create mode 100644 examples/fp/softfloat_calc/softfloat_calc.c diff --git a/.gitignore b/.gitignore index 6ea4b650e..71d4771a1 100644 --- a/.gitignore +++ b/.gitignore @@ -53,6 +53,7 @@ examples/asm/example/example examples/C/sum/sum examples/C/fir/fir examples/fp/softfloat_demo/softfloat_demo +examples/fp/softfloat_calc/softfloat_calc pipelined/src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh diff --git a/examples/fp/softfloat_calc/softfloat_calc.c b/examples/fp/softfloat_calc/softfloat_calc.c new file mode 100644 index 000000000..a3396cf24 --- /dev/null +++ b/examples/fp/softfloat_calc/softfloat_calc.c @@ -0,0 +1,211 @@ +// softfloat_calc.c +// David_Harris@hmc.edu 27 February 2022 +// +// Use SoftFloat as a calculator + +#include +#include +#include +#include +#include "softfloat.h" +#include "softfloat_types.h" + +typedef union hp { + uint16_t v; + float16_t h; +} hp; + +typedef union sp { + uint32_t v; + float32_t ft; + float f; +} sp; + +typedef union dp { + uint64_t v; + double d; +} dp; + + +int opSize = 0; + +void printF16(char *msg, float16_t f) { + hp convh; + sp convf; + float32_t temp; + convh.v = f.v; // use union to convert between hexadecimal and floating-point views + temp = f16_to_f32(convh.h); + convf.ft = temp; + printf ("%s: 0x%04x = %g\n", msg, convh.v, convf.f); // no easy way to print half prec. +} + +void printF32(char *msg, float32_t f) { + sp conv; + conv.v = f.v; // use union to convert between hexadecimal and floating-point views + printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); +} + +void printF64(char *msg, float64_t f) { + dp conv; + conv.v = f.v; // use union to convert between hexadecimal and floating-point views + printf ("%s: 0x%016lx = %lg\n", msg, conv.v, conv.d); +} + +void printFlags(void) { + int NX = softfloat_exceptionFlags % 2; + int UF = (softfloat_exceptionFlags >> 1) % 2; + int OF = (softfloat_exceptionFlags >> 2) % 2; + int DZ = (softfloat_exceptionFlags >> 3) % 2; + int NV = (softfloat_exceptionFlags >> 4) % 2; + printf ("exceptions: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", + NX, UF, OF, DZ, NV); +} + +void softfloatInit(void) { + // rounding modes: RNE: softfloat_round_near_even + // RZ: softfloat_round_minMag + // RP: softfloat_round_max + // RM: softfloat_round_min + softfloat_roundingMode = softfloat_round_near_even; + softfloat_exceptionFlags = 0; // clear exceptions + softfloat_detectTininess = softfloat_tininess_beforeRounding; // RISC-V behavior for tininess +} + +uint64_t parseNum(char *num) { + uint64_t result; + int size; // size of operands in bytes (2= half, 4=single, 8 = double) + if (strlen(num) < 8) size = 2; + else if (strlen(num) < 16) size = 4; + else if (strlen(num) < 19) size = 8; + else { + printf("Error: only half, single, and double precision supported"); + exit(1); + } + if (opSize != 0) { + if (size != opSize) { + printf("Error: inconsistent operand sizes %d and %d\n", size, opSize); + exit(1); + } + } else { + opSize = size; + //printf ("Operand size is %d\n", opSize); + } + result = (uint64_t)strtoul(num, NULL, 16); + //printf("Parsed %s as 0x%lx\n", num, result); + return result; +} + +char parseOp(char *op) { + if (strlen(op) > 1) { + printf ("Bad op %s must be 1 character\n", op); + exit(1); + } else { + return op[0]; + } +} + +char parseRound(char *rnd) { + if (strcmp(rnd, "RNE") == 0) return softfloat_round_near_even; + else if (strcmp(rnd, "RZ") == 0) return softfloat_round_minMag; + else if (strcmp(rnd, "RP") == 0) return softfloat_round_max; + else if (strcmp(rnd, "RM") == 0) return softfloat_round_min; + else { + printf("Rounding mode of %s is not known\n", rnd); + exit(1); + } +} + +int main(int argc, char *argv[]) +{ + uint64_t xn, yn, zn; + char op1, op2; + char cmd[80]; + + softfloatInit(); + + if (argc < 4 || argc > 7) { + printf("Usage: %s x op y [RNE/RZ/RM/RP] or x x y + z [RNE/RZ/RM/RP]\n Example: 0x3f800000 + 0x3fC00000\n Use x for multiplication\n", argv[0]); + exit(1); + } else { + softfloat_roundingMode = softfloat_round_near_even; + xn = parseNum(argv[1]); + yn = parseNum(argv[3]); + op1 = parseOp(argv[2]); + if (argc == 5) softfloat_roundingMode = parseRound(argv[4]); + if (argc >= 6) { + zn = parseNum(argv[5]); + op2 = parseOp(argv[4]); + if (argc == 7) softfloat_roundingMode = parseRound(argv[6]); + if (op1 != 'x' || op2 != '+') { + printf("Error: only x * y + z supported for 3-input operations, not %c %c\n", op1, op2); + } + else { + if (opSize == 2) { + float16_t x, y, z, r; + x.v = xn; y.v = yn; z.v = zn; + r = f16_mulAdd(x, y, z); + printF16("X", x); printF16("Y", y); printF16("Z", z); + printF16("result = X*Y+Z", r); printFlags(); + } else if (opSize == 4) { + float32_t x, y, z, r; + x.v = xn; y.v = yn; z.v = zn; + r = f32_mulAdd(x, y, z); + printF32("X", x); printF32("Y", y); printF32("Z", z); + printF32("result = X*Y+Z", r); printFlags(); + } else { // opSize = 8 + float64_t x, y, z, r; + x.v = xn; y.v = yn; z.v = zn; + r = f64_mulAdd(x, y, z); + printF64("X", x); printF64("Y", y); printF64("Z", z); + printF64("result = X*Y+Z", r); printFlags(); + } + } + } else { + if (opSize == 2) { + float16_t x, y, r; + x.v = xn; y.v = yn; + switch (op1) { + case 'x': r = f16_mul(x, y); break; + case '+': r = f16_add(x, y); break; + case '-': r = f16_sub(x, y); break; + case '/': r = f16_div(x, y); break; + case '%': r = f16_rem(x, y); break; + default: printf("Unknown op %c\n", op1); exit(1); + } + printF16("X", x); printF16("Y", y); + sprintf(cmd, "0x%04x %c 0x%04x", x.v, op1, y.v); + printF16(cmd, r); printFlags(); + } else if (opSize == 4) { + float32_t x, y, r; + x.v = xn; y.v = yn; + switch (op1) { + case 'x': r = f32_mul(x, y); break; + case '+': r = f32_add(x, y); break; + case '-': r = f32_sub(x, y); break; + case '/': r = f32_div(x, y); break; + case '%': r = f32_rem(x, y); break; + default: printf("Unknown op %c\n", op1); exit(1); + } + printF32("X", x); printF32("Y", y); + sprintf(cmd, "0x%08x %c 0x%08x", x.v, op1, y.v); + printF32(cmd, r); printFlags(); + + } else { // opSize = 8 + float64_t x, y, r; + x.v = xn; y.v = yn; + switch (op1) { + case 'x': r = f64_mul(x, y); break; + case '+': r = f64_add(x, y); break; + case '-': r = f64_sub(x, y); break; + case '/': r = f64_div(x, y); break; + case '%': r = f64_rem(x, y); break; + default: printf("Unknown op %c\n", op1); exit(1); + } + printF64("X", x); printF64("Y", y); + sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v); + printF64(cmd, r); printFlags(); + + } + } + } +} From 369e799ce32097c9e3cef480a9a4b5589fbc7e29 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sun, 27 Feb 2022 23:28:25 +0000 Subject: [PATCH 058/199] added minor sections to MMU tests that had been missing, global bits still need to be checked --- .../WALLY-MMU-SV32.reference_output | 16 ++--- .../rv32i_m/privilege/src/WALLY-MMU-SV32.S | 38 ++++++++++- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 42 ++++++++++-- .../WALLY-MMU-SV39.reference_output | 54 ++++++++-------- .../WALLY-MMU-SV48.reference_output | 30 ++++----- .../rv64i_m/privilege/src/WALLY-MMU-SV39.S | 37 ++++++++++- .../rv64i_m/privilege/src/WALLY-MMU-SV48.S | 39 ++++++++++- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 64 +++++++++++++++---- 8 files changed, 246 insertions(+), 74 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output index d75b730de..3c828a4e2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MMU-SV32.reference_output @@ -41,14 +41,14 @@ beef0110 00000bad 0000000f beef0bb0 -00000009 -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +beef0077 # Test 12.3.1.4.1: successful read back of saved value with new memory mapping +00000009 # Test 12.3.1.5.1: ecall from going to m mode from s mode +00000000 # previous value of mprv before being set +beef0099 # Read success from translated address when mprv=1, mpp=S and priv mode = m +0000000b # Test 12.3.1.5.2: ecall from going to S mode from m mode +00000009 # ecall from going straight back to m mode to access mstatus +00000000 # previous zeroed out value of mprv +0000000b # ecall from terminating tests in m mode deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S index 69ba260b3..e573ed10c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S @@ -40,9 +40,9 @@ test_cases: # Here is where the actual tests are held, or rather, what the actual tests do. # each entry consists of 3 values that will be read in as follows: # -# '.8byte [x28 Value], [x29 Value], [x30 value]' +# '.4byte [x28 Value], [x29 Value], [x30 value]' # or -# '.8byte [address], [value], [test type]' +# '.4byte [address], [value], [test type]' # # The encoding for x30 test type values can be found in the test handler in the framework file # @@ -70,6 +70,9 @@ test_cases: # Level 0 page table B .4byte 0x80015FFC, 0x202004C7, write32_test # Vaddr 0xBFF000 Paddr 0x80801000: aligned kilopage with X=0, U=0 +# second page table to check context switches with satp +.4byte 0x8000F000, 0x200000CF, write32_test # Vaddr 0x0 Paddr 0x80000000: aligned megapage +.4byte 0x8000F800, 0x200000CF, write32_test # Vaddr 0x80000000 Paddr 0x80000000: aligned megapage (program and data memory) # test 12.3.1.1.2 write values to Paddrs in each page # each of these values is used for 12.3.1.1.3 and some other tests, specified in the comments. @@ -96,7 +99,7 @@ test_cases: .4byte 0x8000FFA4, 0x00008067, read32_test # test 12.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs -.4byte 0x0, 0x0, goto_sv32 # satp.MODE = sv32, Nothing written to output +.4byte 0x8000D, 0x0, goto_sv32 # satp.MODE = sv32, Nothing written to output .4byte 0x4AAAA8, 0xBEEF0055, read32_test # megapage at Vaddr 0x400000, Paddr 0x80000000 .4byte 0xBFF7E0, 0xBEEF0099, read32_test # kilopage at Vaddr 0xBFF000, Paddr 0x80201000 @@ -159,6 +162,35 @@ test_cases: .4byte 0x4658, 0xBEEF0AA0, write32_test # store page fault when D=0 .4byte 0x4AA0, 0xBEEF0BB0, read32_test # read success when D=0 +# =========== test 12.3.1.4 SATP Register =========== + +# test 12.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) +// *** .4byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write32_test # write identical value to global PTE to make sure it's still in the TLB +.4byte 0x8000F, 0x11, goto_sv32 # go to SV39 on a second, very minimal page table +.4byte 0xE3130, 0xBEEF0077, read32_test # Read success of old written value from a new page table mapping + +# test 12.3.1.4.2 Test Global mapping +// ***.4byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read32_test # read success of global PTE undefined in current mapping. + + +# =========== test 12.3.1.5 STATUS Registers =========== + +# test 12.3.1.5.1 mstatus.mprv translation +# *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this. +.4byte 0x8000D, 0x0, goto_sv32 // go back to old, extensive page table +.4byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus +.4byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S +.4byte 0xBFF7E0, 0xBEEF0099, read32_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1 + +# test 12.3.1.5.2 mstatus.mprv clearing +# mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret +.4byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to +.4byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus. +.4byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero. + +# test 12.3.1.5.3 sstatus.mxr read +# this bitfield already tested in 12.3.1.3.3 + # terminate tests .4byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index b96ee15a1..aa72d5b19 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -398,17 +398,17 @@ trap_return_pagetype_table: // Turn translation off li x7, 0 // satp.MODE value for bare metal (0) slli x7, x7, 31 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location - add x7, x7, x28 - csrw satp, x7 sfence.vma x0, x0 // *** flushes global pte's as well .endm -.macro GOTO_SV32 +.macro GOTO_SV32 ASID BASE_PPN // Turn on sv39 virtual memory li x7, 1 // satp.MODE value for Sv32 (1) slli x7, x7, 31 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + li x29, \ASID + slli x29, x29, 22 + or x7, x7, x29 // put ASID into the correct field of SATP + li x28, \BASE_PPN // Base Pagetable physical page number, satp.PPN field. add x7, x7, x28 csrw satp, x7 sfence.vma x0, x0 // *** flushes global pte's as well @@ -611,7 +611,14 @@ goto_baremetal: j test_loop // go to next test case goto_sv32: - GOTO_SV32 + // Turn sv48 translation on + // Base PPN in x28, ASID in x29 + li x7, 1 // satp.MODE value for sv32 (1) + slli x7, x7, 31 + slli x29, x29, 22 + or x7, x7, x29 // put ASID into the correct field of SATP + or x7, x7, x28 // Base Pagetable physical page number, satp.PPN field. + csrw satp, x7 j test_loop // go to next test case write_mxr_sum: @@ -625,6 +632,29 @@ write_mxr_sum: csrs sstatus, x29 j test_loop +read_write_mprv: + // reads old mstatus.mprv value to output, then + // Writes mstatus.mprv with the 1 bit value in x29. assumes we're in m mode + li x30, 0x20000 // mask bits for mprv + csrr x7, mstatus + and x7, x7, x30 + srli x7, x7, 17 + sw x7, 0(x6) // store old mprv to output + addi x6, x6, 4 + addi x16, x16, 4 + + not x7, x29 + slli x7, x7, 17 + slli x29, x29, 17 + csrc mstatus, x7 + csrs mstatus, x29 // clear or set mprv bit + li x7, 0x1800 + csrc mstatus, x7 + li x7, 0x800 + csrs mstatus, x7 // set mpp to supervisor mode to see if mprv=1 really executes in the mpp mode + j test_loop + + write_pmpcfg_0: // writes the value in x29 to the pmpcfg register specified in x28. // then writes the final value of pmpcfgX to the output. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output index b0f6ca4c7..23b88c0df 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output @@ -1,30 +1,30 @@ 0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode 00000000 -beef0000 # 7 read test successes +beef0000 # Read test success from confirming writes of known values 0000dead -beef0055 # read 2 +beef0055 # Read test success from confirming writes of known values 0880dead -beef0033 # read 3 +beef0033 # Read test success from confirming writes of known values 0990dead -beef0077 # read 4 +beef0077 # Read test success from confirming writes of known values 0110dead -beef0099 # read 5 +beef0099 # Read test success from confirming writes of known values 0220dead -beef0440 # read 6 +beef0440 # Read test success from confirming writes of known values 0330dead -beef0bb0 # read 7 +beef0bb0 # Read test success from confirming writes of known values 0440dead -beef0000 # Test 12.3.1.1.4: 3 read test successes +beef0000 # Test 12.3.1.1.4: Read test success from checking translation works 0000dead -beef0055 # read 2 +beef0055 # Read test success from checking translation works 0880dead -beef0099 # read 3 +beef0099 # Read test success from checking translation works 0220dead -0000000d # Test 12.3.1.2.1: 2 read tests with page fault +0000000d # Test 12.3.1.2.1: Read test with page fault from upper vaddr bits not the same 00000000 00000bad 00000000 -0000000d # read 2 +0000000d # Read test with page fault from upper vaddr bits not the same 00000000 00000bad 00000000 @@ -96,7 +96,21 @@ beef0110 # Test 12.3.1.3.4: read test success 00000000 beef0bb0 # read test success 0440dead -00000009 # ecall from test termination from S mode +beef0000 # Test 12.3.1.4.1: read test success from new page table mapping +0000dead +00000009 # Test 12.3.1.5.1: ecall from going to m mode from s mode +00000000 +00000000 # previous mprv value before writing 1 to it. +00000000 +beef0099 # Read test success when mprv=1 So translation should occur +0220dead # even though we're in M mode with translation off +0000000b # Test 12.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv) +00000000 +00000009 # ecall from going to m mode from s mode (so we can access mstatus) +00000000 +00000000 # previous mprv value zeroed out from mret after going to s mode. +00000000 +0000000b # ecall from test termination from M mode 00000000 deadbeef # rest of the output space deadbeef @@ -1008,17 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output index 1d4ff8e33..ee8ae119e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output @@ -104,7 +104,21 @@ beef0110 # Test 12.3.1.3.4: read test success 00000000 beef0bb0 # read test success 0440dead -00000009 # ecall from test termination in S mode. +beef0000 # Test 12.3.1.4.1: read test success on new page table mapping +0000dead +00000009 # Test 12.3.1.5.1: ecall from going to m mode from s mode +00000000 +00000000 # previous value of mprv before write +00000000 +beef0099 # Read test success when mprv=1 So translation should occur +0220dead # even though we're in M mode with translation off +0000000b # Test 12.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv) +00000000 +00000009 # ecall from going to m mode from s mode (so we can access mstatus) +00000000 +00000000 # previous mprv value zeroed out from mret after going to s mode. +00000000 +0000000b # ecall from test termination in S mode. 00000000 deadbeef # rest of the output space deadbeef @@ -1008,17 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S index 2cabaf68a..ace2ef7bd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S @@ -83,10 +83,14 @@ test_cases: # Level 0 page table B .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage +# second page table to check context switches with satp +.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage +.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) + # test 12.3.1.1.2 write values to Paddrs in each page # each of these values is used for 12.3.1.1.3 and some other tests, specified in the comments. # when a test is supposed to fault, nothing is written into where it'll be reading/executing since it shuold fault before getting there. -.8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test# 12.3.1.1.4 +.8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test# 12.3.1.1.4 and 12.3.1.4.1 .8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test# 12.3.1.1.4 .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test# 12.3.1.3.2 .8byte 0x80203130, 0x0110DEADBEEF0077, write64_test# 12.3.1.3.2 @@ -108,7 +112,7 @@ test_cases: .8byte 0x80203AA0, 0x0440DEADBEEF0BB0, read64_test # test 12.3.1.1.4 check translation works in sv39, read the same values from previous tests, this time with Vaddrs -.8byte 0x0, 0x0, goto_sv39 # satp.MODE = sv39, current VPN: gigapage at 0x80000000. Nothing written to output +.8byte 0x8000D, 0x0, goto_sv39 # satp.MODE = sv39, with base page table PPN = 0x8000D and ASID = 0. current VPN: gigapage at 0x80000000. .8byte 0x80200AB0, 0x0000DEADBEEF0000, read64_test # gigapage at Vaddr 0x80000000, Paddr 0x80000000 .8byte 0x400FFAB8, 0x0880DEADBEEF0055, read64_test # megapage at Vaddr 0x40400000, Paddr 0x80000000 .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test # kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 @@ -175,6 +179,35 @@ test_cases: .8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test# store page fault when D=0 .8byte 0x4AA0, 0x0440DEADBEEF0BB0, read64_test# read success when D=0 +# =========== test 12.3.1.4 SATP Register =========== + +# test 12.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) +// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB +.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table +.8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping + +# test 12.3.1.4.2 Test Global mapping +// ***.8byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read64_test # read success of global PTE undefined in current mapping. + + +# =========== test 12.3.1.5 STATUS Registers =========== + +# test 12.3.1.5.1 mstatus.mprv translation +# *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this. +.8byte 0x8000D, 0x0, goto_sv39 // go back to old, extensive page table +.8byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus +.8byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S +.8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1 + +# test 12.3.1.5.2 mstatus.mprv clearing +# mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret +.8byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to +.8byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus. +.8byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero. + +# test 12.3.1.5.3 sstatus.mxr read +# this bitfield already tested in 12.3.1.3.3 + # terminate tests .8byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S index 68ea5c2b4..dc4d514c4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S @@ -91,6 +91,14 @@ test_cases: # Level 0 page table B .8byte 0x000000008001AFF8, 0x00000000200804CF, write64_test # Vaddr 0xFFFFFFFFF000, Paddr 0x80201000: aligned kilopage +# second page table to check context switches with satp +# Level 3 page table A +.8byte 0x8000F000, 0x2000BC01, write64_test # points to level 2 page table A +# Level 2 page table A +.8byte 0x8002F000, 0x200000CF, write64_test # Vaddr 0x0, Paddr 0x80000000: aligned gigapage +.8byte 0x8002F010, 0x200000CF, write64_test # Vaddr 0x80000000, Paddr 0x80000000: aligned gigapage (data and instr memory) + + # test 12.3.1.1.2 write values to Paddrs in each page # each of these values is used for 12.3.1.1.3 and some other tests, specified in the comments. # when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there. @@ -119,7 +127,7 @@ test_cases: .8byte 0x80203AA0, 0x0440DEADBEEF0BB0, read64_test # test 12.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs -.8byte 0x0, 0x0, goto_sv48 # satp.MODE = sv48, current VPN: megapage at 0x80000000. Nothing written to output +.8byte 0x8000D, 0x0, goto_sv48 # satp.MODE = sv48, with base page table PPN = 0x8000D and ASID = 0. current VPN: megapage at 0x80000000. Nothing written to output .8byte 0x10082777778, 0x0EE0DEADBEEF0CC0, read64_test # terapage at Vaddr 0x010000000000, Paddr 0x0 .8byte 0x8005BC0AB0, 0x0000DEADBEEF0000, read64_test # gigapage at Vaddr 0x008000000000, Paddr 0x80000000 .8byte 0x800F0AB8, 0x0880DEADBEEF0055, read64_test # megapage at Vaddr 0x80000000, Paddr 0x80000000 @@ -187,6 +195,35 @@ test_cases: .8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # write fault when D=0 .8byte 0x80204AA0, 0x0440DEADBEEF0BB0, read64_test# read success when D=0 +# =========== test 12.3.1.4 SATP Register =========== + +# test 12.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) +// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB +.8byte 0x8000F, 0x11, goto_sv48 # go to SV39 on a second, very minimal page table +.8byte 0x5BC0AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping + +# test 12.3.1.4.2 Test Global mapping +// ***.8byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read64_test # read success of global PTE undefined in current mapping. + + +# =========== test 12.3.1.5 STATUS Registers =========== + +# test 12.3.1.5.1 mstatus.mprv translation +# *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this. +.8byte 0x8000D, 0x0, goto_sv48 // go back to old, extensive page table +.8byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus +.8byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S +.8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1 + +# test 12.3.1.5.2 mstatus.mprv clearing +# mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret +.8byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to +.8byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus. +.8byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero. + +# test 12.3.1.5.3 sstatus.mxr read +# this bitfield already tested in 12.3.1.3.3 + # terminate tests .8byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index bce7a70b6..e569ce570 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -469,30 +469,31 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // Turn translation off li x7, 0 // satp.MODE value for bare metal (0) slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location - add x7, x7, x28 csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well .endm -.macro GOTO_SV39 +.macro GOTO_SV39 ASID BASE_PPN // Turn on sv39 virtual memory li x7, 8 // satp.MODE value for Sv39 (8) slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + li x29, \ASID + slli x29, x29, 44 + or x7, x7, x29 // put ASID into the correct field of SATP + li x28, \BASE_PPN // Base Pagetable physical page number, satp.PPN field. add x7, x7, x28 csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well .endm -.macro GOTO_SV48 +.macro GOTO_SV48 ASID BASE_PPN // Turn on sv48 virtual memory li x7, 9 // satp.MODE value for Sv39 (8) slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + li x29, \ASID + slli x29, x29, 44 + or x7, x7, x29 // put ASID into the correct field of SATP + li x28, \BASE_PPN // Base Pagetable physical page number, satp.PPN field. add x7, x7, x28 csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well .endm .macro WRITE_READ_CSR CSR VAL @@ -709,15 +710,31 @@ goto_baremetal: j test_loop // go to next test case goto_sv39: - GOTO_SV39 + // Turn sv39 translation on + // Base PPN in x28, ASID in x29 + li x7, 8 // satp.MODE value for sv39 (8) + slli x7, x7, 60 + slli x29, x29, 44 + or x7, x7, x29 // put ASID into the correct field of SATP + or x7, x7, x28 // Base Pagetable physical page number, satp.PPN field. + csrw satp, x7 + li x29, 0xFFFFFFFFFFFFF888 + sfence.vma x0, x29 // just an attempt *** j test_loop // go to next test case goto_sv48: - GOTO_SV48 + // Turn sv48 translation on + // Base PPN in x28, ASID in x29 + li x7, 9 // satp.MODE value for sv48 (9) + slli x7, x7, 60 + slli x29, x29, 44 + or x7, x7, x29 // put ASID into the correct field of SATP + or x7, x7, x28 // Base Pagetable physical page number, satp.PPN field. + csrw satp, x7 j test_loop // go to next test case write_mxr_sum: - // writes sstatus.[mxr, sum] with the (assumed to be) 2 bit value in x29. also assumes we're in S. M mode + // writes sstatus.[mxr, sum] with the (assumed to be) 2 bit value in x29. also assumes we're in S or M mode li x30, 0xC0000 // mask bits for MXR, SUM not x7, x29 slli x7, x7, 18 @@ -727,6 +744,29 @@ write_mxr_sum: csrs sstatus, x29 j test_loop +read_write_mprv: + // reads old mstatus.mprv value to output, then + // Writes mstatus.mprv with the 1 bit value in x29. assumes we're in m mode + li x30, 0x20000 // mask bits for mprv + csrr x7, mstatus + and x7, x7, x30 + srli x7, x7, 17 + sd x7, 0(x6) // store old mprv to output + addi x6, x6, 8 + addi x16, x16, 8 + + not x7, x29 + slli x7, x7, 17 + slli x29, x29, 17 + csrc mstatus, x7 + csrs mstatus, x29 // clear or set mprv bit + li x7, 0x1800 + csrc mstatus, x7 + li x7, 0x800 + csrs mstatus, x7 // set mpp to supervisor mode to see if mprv=1 really executes in the mpp mode + j test_loop + + write_pmpcfg_0: // writes the value in x29 to the pmpcfg register specified in x28. // then writes the final value of pmpcfgX to the output. From 6f701a16b3012b8987e7913d9c692a365a7b5e5e Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sun, 27 Feb 2022 23:29:46 +0000 Subject: [PATCH 059/199] added snippet to ignore comments in .diff files as well --- tests/wally-riscv-arch-test/riscv-test-env/verify.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh index 6a809b730..3e06a2cc9 100755 --- a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh +++ b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh @@ -36,7 +36,8 @@ do else echo -e "\e[31m ... FAIL \e[39m" FAIL=$((${FAIL} + 1)) - sdiff <(grep -o '^[^#]*' ${ref}) ${sig} > ${dif} + # KMG: changed sdiff similar to above + sdiff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^#]*' ${ref}) ${sig} > ${dif} fi done From 0cc09ed91849d74b702189423988ab7af19180f0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Feb 2022 04:15:20 +0000 Subject: [PATCH 060/199] Enhanced printing intermediate results in fpcalc.c --- .gitignore | 2 +- .../softfloat_calc.c => fpcalc/fpcalc.c} | 77 ++++++++++++++++++- 2 files changed, 75 insertions(+), 4 deletions(-) rename examples/fp/{softfloat_calc/softfloat_calc.c => fpcalc/fpcalc.c} (69%) diff --git a/.gitignore b/.gitignore index 71d4771a1..1f2f31d3d 100644 --- a/.gitignore +++ b/.gitignore @@ -53,7 +53,7 @@ examples/asm/example/example examples/C/sum/sum examples/C/fir/fir examples/fp/softfloat_demo/softfloat_demo -examples/fp/softfloat_calc/softfloat_calc +examples/fp/fpcalc/fpcalc pipelined/src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh diff --git a/examples/fp/softfloat_calc/softfloat_calc.c b/examples/fp/fpcalc/fpcalc.c similarity index 69% rename from examples/fp/softfloat_calc/softfloat_calc.c rename to examples/fp/fpcalc/fpcalc.c index a3396cf24..6b9dc5354 100644 --- a/examples/fp/softfloat_calc/softfloat_calc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -29,26 +29,97 @@ typedef union dp { int opSize = 0; +void long2binstr(long val, char *str, int bits) { + int i; + long masked; + + if (val == 0) { // just return zero + str[0] = '0'; + str[1] = 0; + } else { + for (i=0; i> 10) & ((1<<5) -1); + sign = f.v >> 15 ? '-' : '+'; + //printf("%c %d %d ", sign, exp, fract); + if (exp == 0 && fract == 0) sprintf(sci, "%czero", sign); + else if (exp == 0 && fract != 0) sprintf(sci, "Denorm: %c0.%s x 2^-14", sign, fractstr); + else if (exp == 31 && fract == 0) sprintf(sci, "%cinf", sign); + else if (exp == 31 && fract != 0) sprintf(sci, "NaN Payload: %c%s", sign, fractstr); + else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-15); + + printf ("%s: 0x%04x = %g = %s: Biased Exp %d Fract 0x%lx\n", + msg, convh.v, convf.f, sci, exp, fract); // no easy way to print half prec. } void printF32(char *msg, float32_t f) { sp conv; + long exp, fract; + char sign; + char sci[80], fractstr[80]; + conv.v = f.v; // use union to convert between hexadecimal and floating-point views - printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); + + fract = f.v & ((1<<23) - 1); long2binstr(fract, fractstr, 23); + exp = (f.v >> 23) & ((1<<8) -1); + sign = f.v >> 31 ? '-' : '+'; + //printf("%c %d %d ", sign, exp, fract); + if (exp == 0 && fract == 0) sprintf(sci, "%czero", sign); + else if (exp == 0 && fract != 0) sprintf(sci, "Denorm: %c0.%s x 2^-126", sign, fractstr); + else if (exp == 255 && fract == 0) sprintf(sci, "%cinf", sign); + else if (exp == 255 && fract != 0) sprintf(sci, "NaN Payload: %c%s", sign, fractstr); + else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-127); + + //printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); + printf ("%s: 0x%08x = %g = %s: Biased Exp %d Fract 0x%lx\n", + msg, conv.v, conv.f, sci, exp, fract); } void printF64(char *msg, float64_t f) { dp conv; + long exp, fract; + long mask; + char sign; + char sci[80], fractstr[80]; + conv.v = f.v; // use union to convert between hexadecimal and floating-point views - printf ("%s: 0x%016lx = %lg\n", msg, conv.v, conv.d); + + mask = 1; mask = (mask << 52) - 1; + fract = f.v & mask; long2binstr(fract, fractstr, 52); + exp = (f.v >> 52) & ((1<<11) -1); + sign = f.v >> 63 ? '-' : '+'; + //printf("%c %d %d ", sign, exp, fract); + if (exp == 0 && fract == 0) sprintf(sci, "%czero", sign); + else if (exp == 0 && fract != 0) sprintf(sci, "Denorm: %c0.%s x 2^-1022", sign, fractstr); + else if (exp == 2047 && fract == 0) sprintf(sci, "%cinf", sign); + else if (exp == 2047 && fract != 0) sprintf(sci, "NaN Payload: %c%s", sign, fractstr); + else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-1023); + + //printf ("%s: 0x%016lx = %lg\n", msg, conv.v, conv.d); + printf ("%s: 0x%016x = %g = %s: Biased Exp %d Fract 0x%lx\n", + msg, conv.v, conv.d, sci, exp, fract); } void printFlags(void) { From 9b4d6427f4158b2e60571d0d0f323b1a002d4139 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Feb 2022 04:28:07 +0000 Subject: [PATCH 061/199] Corrected printing doubles --- examples/fp/fpcalc/fpcalc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index 6b9dc5354..116cf8680 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -118,7 +118,7 @@ void printF64(char *msg, float64_t f) { else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-1023); //printf ("%s: 0x%016lx = %lg\n", msg, conv.v, conv.d); - printf ("%s: 0x%016x = %g = %s: Biased Exp %d Fract 0x%lx\n", + printf ("%s: 0x%016lx = %lg = %s: Biased Exp %d Fract 0x%lx\n", msg, conv.v, conv.d, sci, exp, fract); } From 3a43450ac98020ac075db27218d43dd0270f0f13 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Feb 2022 05:54:34 +0000 Subject: [PATCH 062/199] hptw cleanup for synthesis --- pipelined/src/mmu/hptw.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index f3e156b33..39ec91d5a 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -124,11 +124,11 @@ module hptw assign {Dirty, Accessed} = PTE[7:6]; - assign WriteAccess = (MemRWM[0] | |AtomicM); - assign SetDirty = ~Dirty & & DTLBWalk & WriteAccess; + assign WriteAccess = MemRWM[0] | (|AtomicM); + assign SetDirty = ~Dirty & DTLBWalk & WriteAccess; assign ReadAccess = MemRWM[1]; - assign EffectivePrivilegeMode = (DTLBWalk == 0) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 + assign EffectivePrivilegeMode = DTLBWalk ? (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW) : PrivilegeModeW; // DTLB uses MPP mode when MPRV is 1 assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | ((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk)); From 5b30fb7328adee86eb16a58483cf4650b5ee7392 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Sun, 27 Feb 2022 09:50:10 +0000 Subject: [PATCH 063/199] added make allsynth --- synthDC/Makefile | 70 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index aa148802d..ddbf5c0ff 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -24,9 +24,10 @@ export SAIFPOWER ?= 0 CONFIGDIR ?= ~/riscv-wally/pipelined/config #CONFIGS ?= $(shell find $(CONFIGDIR) -name "rv*") CONFIGS ?= ("rv32e", "rv32ic") - +CONFIGFILES ?= $(shell find $(CONFIGDIR) -name *_*) +CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) print: - echo "files in $(CONFIGDIR) are $(CONFIGS)." + echo $(CONFIGFILESTRIM) default: @echo "Basic synthesis procedure for Wally:" @@ -38,22 +39,57 @@ test: rv% rv%.log: rv% echo $< -flavors: - rm -rf $(CONFIGDIR)/rv32em - cp -r $(CONFIGDIR)/rv32e $(CONFIGDIR)/rv32em - sed -i 's/h00000010/h00001010/' $(CONFIGDIR)/rv32em/wally-config.vh - # rv32e, 32ic, 32gc 64ic, 64gc - # 64gc - FPU - # PMP16 - # PMP0 - # No virtual memory - # Muldiv - -allsynth: - make flavors - make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky90 FREQ=500 MAXCORES=1 - make synth DESIGN=wallypipelinedcore CONFIG=rv32em TECH=sky90 FREQ=500 MAXCORES=1 +DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic +CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig +CONFIGFILES ?= $(shell find $(CONFIGDIR) -type d -regex "*_*") +del: + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;) + +configs: + # @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) + # @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) + # turn off FPU + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;) + @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_FPUoff;) + @$(foreach dir, $(DIRS), sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$(dir)_FPUoff/wally-config.vh;) + @$(foreach dir, $(DIRS), sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$(dir)_FPUoff/wally-config.vh;) + + # PMP 16 + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;) + @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_PMP16;) + @$(foreach dir, $(DIRS), sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$(dir)_PMP16/wally-config.vh;) + + # PMP 0 + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;) + @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_PMP0;) + @$(foreach dir, $(DIRS), sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$(dir)_PMP0/wally-config.vh;) + + # No Virtual Memory + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;) + @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_noVirtMem;) + @$(foreach dir, $(DIRS), sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$(dir)_noVirtMem/wally-config.vh;) + + #no muldiv + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;) + @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_noMulDiv;) + @$(foreach dir, $(DIRS), sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$(dir)_noMulDiv/wally-config.vh;) + + +# allsynth: +# make configs +# $(foreach dir, $(CONFIGFILESTRIM), \ +# make synth DESIGN=wallypipelinedcore CONFIG=$(dir) TECH=sky90 FREQ=500 --jobs;) + +allsynth: $(CONFIGFILESTRIM) + +$(CONFIGFILESTRIM): + make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 --jobs synth: @echo "DC Synthesis" From db38b69f830ff4439824e9e6774145164a1eb298 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Mon, 28 Feb 2022 17:14:56 +0000 Subject: [PATCH 064/199] Makefile for running multiple synthesis --- synthDC/Makefile | 67 +++++++++++++++++++++------------------ synthDC/extractSummary.py | 25 +++++++++++++++ 2 files changed, 61 insertions(+), 31 deletions(-) create mode 100644 synthDC/extractSummary.py diff --git a/synthDC/Makefile b/synthDC/Makefile index ddbf5c0ff..f0096c731 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -22,9 +22,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(has export SAIFPOWER ?= 0 CONFIGDIR ?= ~/riscv-wally/pipelined/config -#CONFIGS ?= $(shell find $(CONFIGDIR) -name "rv*") -CONFIGS ?= ("rv32e", "rv32ic") -CONFIGFILES ?= $(shell find $(CONFIGDIR) -name *_*) +CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) print: echo $(CONFIGFILESTRIM) @@ -40,9 +38,11 @@ rv%.log: rv% echo $< -DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic +DIRS = rv32e rv32gc rv64ic rv64gc rv32ic +DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig -CONFIGFILES ?= $(shell find $(CONFIGDIR) -type d -regex "*_*") + + del: @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;) @@ -51,45 +51,50 @@ del: @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;) @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;) -configs: - # @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) - # @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) - # turn off FPU - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_FPUoff;) - @$(foreach dir, $(DIRS), sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$(dir)_FPUoff/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$(dir)_FPUoff/wally-config.vh;) +configs: $(DIRS) +$(DIRS): + #turn off FPU + rm -rf $(CONFIGDIR)/$@_FPUoff + cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_FPUoff + sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh + sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh # PMP 16 - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_PMP16;) - @$(foreach dir, $(DIRS), sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$(dir)_PMP16/wally-config.vh;) + rm -rf $(CONFIGDIR)/$@_PMP16 + cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_PMP16 + sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP16/wally-config.vh + sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP16/wally-config.vh + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh # PMP 0 - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_PMP0;) - @$(foreach dir, $(DIRS), sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$(dir)_PMP0/wally-config.vh;) + rm -rf $(CONFIGDIR)/$@_PMP0 + cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_PMP0 + sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP0/wally-config.vh + sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP0/wally-config.vh + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh # No Virtual Memory - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_noVirtMem;) - @$(foreach dir, $(DIRS), sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$(dir)_noVirtMem/wally-config.vh;) + rm -rf $(CONFIGDIR)/$@_noVirtMem + cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_noVirtMem + sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh #no muldiv - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_noMulDiv;) - @$(foreach dir, $(DIRS), sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$(dir)_noMulDiv/wally-config.vh;) + rm -rf $(CONFIGDIR)/$@_noMulDiv + cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_noMulDiv + sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh -# allsynth: -# make configs -# $(foreach dir, $(CONFIGFILESTRIM), \ -# make synth DESIGN=wallypipelinedcore CONFIG=$(dir) TECH=sky90 FREQ=500 --jobs;) - allsynth: $(CONFIGFILESTRIM) $(CONFIGFILESTRIM): - make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 --jobs + make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1 --jobs synth: @echo "DC Synthesis" diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py new file mode 100644 index 000000000..2a7806604 --- /dev/null +++ b/synthDC/extractSummary.py @@ -0,0 +1,25 @@ +import glob +import re +import csv + +field_names = [ 'Name', 'Critical Path Length', 'Cell Area'] +data = [] +for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypipelinedcore_qor.rep"): + f = open(name, 'r') + trimName = re.search("runs\/(.*?)\/reports", name).group(1) + # trimName = re.search("wallypipelinedcore_(.*?)_sky9",name).group(1) + for line in f: + if "Critical Path Length" in line: + pathLen = re.search("Length: *(.*?)\\n", line).group(1) + if "Cell Area" in line: + area = re.search("Area: *(.*?)\\n", line).group(1) + data += [{'Name' : trimName, 'Critical Path Length': pathLen, 'Cell Area' : area}] + +with open('Summary.csv', 'w') as csvfile: + writer = csv.DictWriter(csvfile, fieldnames=field_names) + writer.writeheader() + writer.writerows(data) + + + + \ No newline at end of file From 06c2744ac1532b96ba470590459538b55ce1c3e0 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Mon, 28 Feb 2022 17:32:08 +0000 Subject: [PATCH 065/199] Copied previous cofig file instead of orig --- synthDC/Makefile | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index f0096c731..aafadb648 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -39,8 +39,8 @@ rv%.log: rv% DIRS = rv32e rv32gc rv64ic rv64gc rv32ic -DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic -CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig +# DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic +# CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig del: @@ -61,33 +61,33 @@ $(DIRS): # PMP 16 rm -rf $(CONFIGDIR)/$@_PMP16 - cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_PMP16 - sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP16/wally-config.vh - sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP16/wally-config.vh + cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 + # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP16/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP16/wally-config.vh sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh # PMP 0 rm -rf $(CONFIGDIR)/$@_PMP0 - cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_PMP0 - sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP0/wally-config.vh - sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP0/wally-config.vh + cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 + # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP0/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP0/wally-config.vh sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh # No Virtual Memory rm -rf $(CONFIGDIR)/$@_noVirtMem - cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_noVirtMem - sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh - sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + # cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_noVirtMem + # sed -i 's/1 *<< *3/0 <_PMP0< 3/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + # sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh #no muldiv rm -rf $(CONFIGDIR)/$@_noMulDiv - cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_noMulDiv - sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv + # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + # sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + # sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh From 6a1f1e249638b1728a27bb2867bfdeee757110f1 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Mon, 28 Feb 2022 17:33:15 +0000 Subject: [PATCH 066/199] changed filename --- synthDC/extractSummary.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 2a7806604..e9fa69772 100644 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -6,8 +6,8 @@ field_names = [ 'Name', 'Critical Path Length', 'Cell Area'] data = [] for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypipelinedcore_qor.rep"): f = open(name, 'r') - trimName = re.search("runs\/(.*?)\/reports", name).group(1) - # trimName = re.search("wallypipelinedcore_(.*?)_sky9",name).group(1) + # trimName = re.search("runs\/(.*?)\/reports", name).group(1) + trimName = re.search("wallypipelinedcore_(.*?)_sky9",name).group(1) for line in f: if "Critical Path Length" in line: pathLen = re.search("Length: *(.*?)\\n", line).group(1) From 2de31a15da27ae012bba4d5626131098308e39d7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Feb 2022 19:13:14 +0000 Subject: [PATCH 067/199] Modified address decoder for native access to CLINT --- pipelined/src/mmu/adrdecs.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 5cb96ba5e..f34da8a3d 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -37,6 +37,7 @@ module adrdecs ( input logic [1:0] Size, output logic [8:0] SelRegions ); + logic [3:0] clintaccesssize; // Determine which region of physical memory (if any) is being accessed // *** eventually uncomment Access signals @@ -44,7 +45,8 @@ module adrdecs ( adrdec boottimdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, /*1'b1*/AccessRX, Size, 4'b1111, SelRegions[6]); adrdec timdec(PhysicalAddress, `RAM_BASE, `RAM_RANGE, `RAM_SUPPORTED, /*1'b1*/AccessRWX, Size, 4'b1111, SelRegions[5]); - adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, 4'b1111, SelRegions[4]); + assign clintaccesssize = (`XLEN==64) ? 4'b1000 : 4'b0100; + adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, clintaccesssize, SelRegions[4]); adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]); adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[2]); adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[1]); From f14acac1bf6ecb73e91a9e36cdcde6ca004e223f Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 28 Feb 2022 19:22:44 +0000 Subject: [PATCH 068/199] Changed PMA tests to only allow native length accesses to CLINT --- .../references/WALLY-PMA.reference_output | 12 +++---- .../rv32i_m/privilege/src/WALLY-PMA.S | 10 +++--- .../references/WALLY-PMA.reference_output | 34 +++++++++---------- .../rv64i_m/privilege/src/WALLY-PMA.S | 14 ++++---- 4 files changed, 35 insertions(+), 35 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output index f62663131..38042cfc7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output @@ -1,6 +1,10 @@ beef00b5 -000000b6 -ffffffb7 +00000007 # write access fault with 16 bit write to CLINT +00000005 # read access fault with 16 bit write to CLINT +00000bad +00000007 # write access fault with 8 bit write to CLINT +00000005 # read access fault with 8 bit write to CLINT +00000bad 00000001 00000bad 00000002 @@ -1018,7 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S index 475a6dd83..f9dbe8d57 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S @@ -66,7 +66,7 @@ test_cases: # | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic | # | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO | -# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO | +# | CLINT | 0x2000000 | 32-bit | YES | YES | NO | NO | NO | NO | # | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO | # | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO | # | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO | @@ -82,10 +82,10 @@ test_cases: # Use timecmp register as readable and writable section of the CLINT .4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success .4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test# 16-bit write: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test# 16-bit read: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test# 08-bit write: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test# 08-bit read: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test# 16-bit write: failure *** Due to non-native access length in CLINT +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test# 16-bit read: failure +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test# 08-bit write: failure +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test# 08-bit read: failure .4byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output index c8a68e8e2..036b97aea 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output @@ -1,11 +1,23 @@ beef00b4 # Test 12.3.2.1: read 64 bits success in CLINT 0000dead # all of these read successes are also confirming successful writes -beef00b5 # read 32 bits success in CLINT (sign extended) -ffffffff -000000b6 # read 16 bits success in CLINT +00000007 # write 32 bits with access fault in CLINT +00000000 +00000005 # read 32 bits with access fault in CLINT +00000000 +00000bad +00000000 +00000007 # write 16 bits with access fault in CLINT +00000000 +00000005 # read 16 bits with access fault in CLINT +00000000 +00000bad +00000000 +00000007 # write 8 bits with access fault in CLINT +00000000 +00000005 # read 8 bits with access fault in CLINT +00000000 +00000bad 00000000 -ffffffb7 # read 8 bits success in CLINT (sign extended) -ffffffff 00000001 # execute test with access fault in CLINT 00000000 00000bad @@ -1010,15 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S index 7780e187f..3dd6a91c7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S @@ -69,7 +69,7 @@ test_cases: # | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic | # | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO | -# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO | +# | CLINT | 0x2000000 | 64-bit | YES | YES | NO | NO | NO | NO | # | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO | # | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO | # | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO | @@ -85,12 +85,12 @@ test_cases: # Use timecmp register as readable and writable section of the CLINT .8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, write64_test # 64-bit write: success .8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, read64_test # 64-bit read: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, write32_test # 32-bit write: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, read32_test # 32-bit read: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, write16_test # 16-bit write: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, read16_test # 16-bit read: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, write08_test # 08-bit write: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, read08_test # 08-bit read: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, write32_test # 32-bit write: failure *** due to non-native length access +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, read32_test # 32-bit read: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, write16_test # 16-bit write: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, read16_test # 16-bit read: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, write08_test # 08-bit write: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, read08_test # 08-bit read: failure .8byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault From eba4eda245cb8fc498b61efb087e7e7182c9ea67 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 28 Feb 2022 14:10:22 -0600 Subject: [PATCH 069/199] Minor tweak of output of fpcalc - can be reversed with commented out code --- examples/fp/fpcalc/Makefile | 23 +++++++++++++++++++++ examples/fp/fpcalc/fpcalc.c | 22 ++++++++++++++++---- examples/fp/softfloat_demo/softfloat_demo.c | 11 ++++++++-- 3 files changed, 50 insertions(+), 6 deletions(-) create mode 100644 examples/fp/fpcalc/Makefile diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile new file mode 100644 index 000000000..4d0efe20e --- /dev/null +++ b/examples/fp/fpcalc/Makefile @@ -0,0 +1,23 @@ +# Makefile + +CC = gcc +CFLAGS = -O3 +LIBS = -lm +LFLAGS = -L. +# Link against the riscv-isa-sim version of SoftFloat rather than +# the regular version to get RISC-V NaN behavior +IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat +LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a +#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ +#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a +SRCS = $(wildcard *.c) + +PROGS = $(patsubst %.c,%,$(SRCS)) + +all: $(PROGS) + +%: %.c + $(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) + +clean: + rm -f $(PROGS) diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index 116cf8680..b8e180bf7 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -93,8 +93,13 @@ void printF32(char *msg, float32_t f) { else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-127); //printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); - printf ("%s: 0x%08x = %g = %s: Biased Exp %d Fract 0x%lx\n", - msg, conv.v, conv.f, sci, exp, fract); + printf("%s: ", msg); + printf("0x%04x", (conv.v >> 16)); + printf("_"); + printf("%04x", (conv.v & 0xFF)); + printf(" = %g = %s: Biased Exp %d Fract 0x%lx\n", conv.f, sci, exp, fract); + //printf ("%s: 0x%08x = %g = %s: Biased Exp %d Fract 0x%lx\n", + // msg, conv.v, conv.f, sci, exp, fract); } void printF64(char *msg, float64_t f) { @@ -118,8 +123,17 @@ void printF64(char *msg, float64_t f) { else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-1023); //printf ("%s: 0x%016lx = %lg\n", msg, conv.v, conv.d); - printf ("%s: 0x%016lx = %lg = %s: Biased Exp %d Fract 0x%lx\n", - msg, conv.v, conv.d, sci, exp, fract); + printf("%s: ", msg); + printf("0x%04x", (conv.v >> 48)); + printf("_"); + printf("%04x", (conv.v >> 32) & 0xFFFF); + printf("_"); + printf("%04x", (conv.v >> 16)); + printf("_"); + printf("%04x", (conv.v & 0xFFFF)); + printf(" = %lg = %s: Biased Exp %d Fract 0x%lx\n", conv.d, sci, exp, fract); + //printf ("%s: 0x%016lx = %lg = %s: Biased Exp %d Fract 0x%lx\n", + // msg, conv.v, conv.d, sci, exp, fract); } void printFlags(void) { diff --git a/examples/fp/softfloat_demo/softfloat_demo.c b/examples/fp/softfloat_demo/softfloat_demo.c index 0f34ac255..111847a4f 100644 --- a/examples/fp/softfloat_demo/softfloat_demo.c +++ b/examples/fp/softfloat_demo/softfloat_demo.c @@ -12,10 +12,17 @@ typedef union sp { float f; } sp; -void printF32(char *msg, float32_t f) { +void printF32 (char *msg, float32_t f) { sp conv; + int i, j; conv.v = f.v; // use union to convert between hexadecimal and floating-point views - printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); + // Print out nicely + printf("%s: ", msg); + printf("0x%04x", (conv.v >> 16)); + printf("_"); + printf("%04x", (conv.v & 0xFFFF)); + printf(" = %g\n", conv.f); + //printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); } void printFlags(void) { From 2ea93c4ac3aeb319fbdb38b8eb73acef59c8ab31 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Feb 2022 20:33:41 +0000 Subject: [PATCH 070/199] adrdecs comments --- pipelined/src/mmu/adrdecs.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index f34da8a3d..5464f4ac6 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -50,7 +50,7 @@ module adrdecs ( adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]); adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[2]); adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[1]); - adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, 4'b1100, SelRegions[0]); + adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, 4'b1100, SelRegions[0]); // *** PMA chapter says xlen only like CLINT assign SelRegions[8] = ~|(SelRegions[7:0]); From 5faf52ae8752bbe4d13fcfc6c8f18560c0c08d95 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Feb 2022 20:34:33 +0000 Subject: [PATCH 071/199] fpcalc Makefile --- examples/fp/fpcalc/Makefile | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 examples/fp/fpcalc/Makefile diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile new file mode 100644 index 000000000..4d0efe20e --- /dev/null +++ b/examples/fp/fpcalc/Makefile @@ -0,0 +1,23 @@ +# Makefile + +CC = gcc +CFLAGS = -O3 +LIBS = -lm +LFLAGS = -L. +# Link against the riscv-isa-sim version of SoftFloat rather than +# the regular version to get RISC-V NaN behavior +IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat +LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a +#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ +#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a +SRCS = $(wildcard *.c) + +PROGS = $(patsubst %.c,%,$(SRCS)) + +all: $(PROGS) + +%: %.c + $(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) + +clean: + rm -f $(PROGS) From 329fea932950771202d81642bcab04dc2d9a26e1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Feb 2022 20:50:51 +0000 Subject: [PATCH 072/199] Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath --- pipelined/src/fpu/fpu.sv | 4 ++-- pipelined/src/fpu/unpacking.sv | 2 +- pipelined/src/ieu/datapath.sv | 18 +++++++++--------- pipelined/srt/testbench.sv | 2 +- pipelined/testbench/testbench-f64.sv | 2 +- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 834314262..0dd6ea1b2 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -173,10 +173,10 @@ module fpu ( mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); - // unpacking unit + // unpack unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpacking unpacking (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, + unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv index 78a4d7446..f503e47be 100644 --- a/pipelined/src/fpu/unpacking.sv +++ b/pipelined/src/fpu/unpacking.sv @@ -1,6 +1,6 @@ `include "wally-config.vh" -module unpacking ( +module unpack ( input logic [63:0] X, Y, Z, input logic FmtE, input logic [2:0] FOpCtrlE, diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index aa43a5b19..52c0dc208 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -86,17 +86,17 @@ module datapath ( logic [`XLEN-1:0] WriteDataE; // Memory stage signals logic [`XLEN-1:0] IEUResultM; - logic [`XLEN-1:0] ResultM; + logic [`XLEN-1:0] IFResultM; // Writeback stage signals logic [`XLEN-1:0] SCResultW; - logic [`XLEN-1:0] WriteDataW; logic [`XLEN-1:0] ResultW; + logic [`XLEN-1:0] IFResultW; // Decode stage assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; - regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, WriteDataW, R1D, R2D); + regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD); // Execute stage pipeline register and logic @@ -107,8 +107,8 @@ module datapath ( flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); - mux3 #(`XLEN) faemux(R1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE); - mux3 #(`XLEN) fbemux(R2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE); + mux3 #(`XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE); + mux3 #(`XLEN) fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE); comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE); @@ -123,17 +123,17 @@ module datapath ( flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); // Writeback stage pipeline register and logic - flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW); + flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW); flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW); flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW); - mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW); + mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); // floating point interactions: fcvt, fp stores if (`F_SUPPORTED) begin:fpmux - mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM); + mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); end else begin:fpmux - assign ResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE; + assign IFResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE; end // handle Store Conditional result if atomic extension supported diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index c9cf72bdd..8b3fec51d 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -83,7 +83,7 @@ module testbench; // Unpacker // Note: BiasE will probably get taken out eventually - unpacking unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), + unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), diff --git a/pipelined/testbench/testbench-f64.sv b/pipelined/testbench/testbench-f64.sv index e3cdc84d9..a0c7e6a31 100755 --- a/pipelined/testbench/testbench-f64.sv +++ b/pipelined/testbench/testbench-f64.sv @@ -51,7 +51,7 @@ module testbench (); integer desc3; // instantiate device under test - unpacking unpacking(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE, + unpack unpack(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); From 3f5ae216b5112f7f7b56ebb13ab977546bcec403 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 28 Feb 2022 22:55:23 +0000 Subject: [PATCH 073/199] change pipe silencer to redirect to stderr so that we can see if QEMU is at least still alive --- linux/testvector-generation/silencePipe.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux/testvector-generation/silencePipe.c b/linux/testvector-generation/silencePipe.c index 2cd531b89..3ffeb14b4 100644 --- a/linux/testvector-generation/silencePipe.c +++ b/linux/testvector-generation/silencePipe.c @@ -12,6 +12,8 @@ int main(void) ssize_t lineSize = getline(&line, &len, stdin); if (silenceChar!='1') { printf("%s",line); + } else { + fprintf(stderr,"%s",line); } } free(line); From 7af81d93ec16a1b39958a6fd4afd34c6ef334ae0 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 28 Feb 2022 23:00:00 +0000 Subject: [PATCH 074/199] greatly improve trace-generating checkpoint process with QEMU hack --- .gitignore | 1 + ...n-on-logging-mid-execution-using-GDB.patch | 53 +++++++++++++++++++ .../createGenCheckpointScript.py | 9 ++-- linux/testvector-generation/genCheckpoint.sh | 8 ++- 4 files changed, 60 insertions(+), 11 deletions(-) create mode 100644 linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch diff --git a/.gitignore b/.gitignore index 1f2f31d3d..9acf2e18c 100644 --- a/.gitignore +++ b/.gitignore @@ -61,6 +61,7 @@ linux/testvector-generation/genCheckpoint.gdb linux/testvector-generation/silencePipe linux/testvector-generation/silencePipe.control linux/testvector-generation/fixBinMem +linux/testvector-generation/qemu-serial *.dtb synthDC/WORK synthDC/alib-52 diff --git a/linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch b/linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch new file mode 100644 index 000000000..1b0e1d4aa --- /dev/null +++ b/linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch @@ -0,0 +1,53 @@ +From f9882bd274bde82d8c38a9c31692b6ee33d8cd9a Mon Sep 17 00:00:00 2001 +From: root +Date: Mon, 28 Feb 2022 22:48:29 +0000 +Subject: [PATCH] bens hack to turn on logging mid-execution using GDB + +--- + gdbstub.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/gdbstub.c b/gdbstub.c +index 141d7bc4ec..98ecce1b67 100644 +--- a/gdbstub.c ++++ b/gdbstub.c +@@ -2317,6 +2317,23 @@ static void handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx) + } + put_packet("OK"); + } ++ ++static void handle_set_qemu_logging(GArray *params, void *user_ctx) ++{ ++ if (!params->len) { ++ put_packet("E22"); ++ return; ++ } ++ ++ int log_mask; ++ if (!get_param(params, 0)->val_ul) { ++ log_mask = 0; ++ } else { ++ log_mask = CPU_LOG_TB_IN_ASM | CPU_LOG_INT | CPU_LOG_TB_CPU | CPU_LOG_TB_NOCHAIN; ++ } ++ qemu_set_log(log_mask); ++ put_packet("OK"); ++} + #endif + + static const GdbCmdParseEntry gdb_gen_query_set_common_table[] = { +@@ -2430,6 +2447,12 @@ static const GdbCmdParseEntry gdb_gen_set_table[] = { + .cmd_startswith = 1, + .schema = "l0" + }, ++ { ++ .handler = handle_set_qemu_logging, ++ .cmd = "qemu.Logging:", ++ .cmd_startswith = 1, ++ .schema = "l0" ++ }, + #endif + }; + +-- +2.27.0 + diff --git a/linux/testvector-generation/createGenCheckpointScript.py b/linux/testvector-generation/createGenCheckpointScript.py index fee2b603a..2b5f1fd11 100755 --- a/linux/testvector-generation/createGenCheckpointScript.py +++ b/linux/testvector-generation/createGenCheckpointScript.py @@ -35,9 +35,6 @@ maintenance packet Qqemu.PhyMemMode:1 # Symbol file file {vmlinux} -# Silence Trace Generation -shell echo 1 > ./silencePipe.control - # Step over reset vector into actual code stepi 100 # Proceed to checkpoint @@ -56,11 +53,11 @@ set logging off # Log main memory to a file print "GDB storing RAM to {ramPath}\\n" -#dump binary memory {ramPath} 0x80000000 0xffffffff -#dump binary memory {ramPath} 0x80000000 0x80ffffff +dump binary memory {ramPath} 0x80000000 0xffffffff +dump binary memory {ramPath} 0x80000000 0x80ffffff # Generate Trace Until End -shell echo 0 > ./silencePipe.control +maintenance packet Qqemu.Logging:1 # Do this by setting an impossible breakpoint b *0x1000 del 1 diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index d468e9fda..2478bbcc6 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -1,9 +1,9 @@ #!/bin/bash -tcpPort=1237 +tcpPort=1238 imageDir=$RISCV/buildroot/output/images tvDir=$RISCV/linux-testvectors recordFile="$tvDir/all.qemu" -traceFile="$tvDir/all_up_to_498.txt" +traceFile="$tvDir/all.txt" # Parse Commandline Arg if [ "$#" -ne 1 ]; then @@ -30,7 +30,6 @@ echo if [[ $REPLY =~ ^[Yy]$ ]] then echo "Creating checkpoint at $instrs instructions!" - make silencePipe # Create Output Directory echo "Elevating permissions to create $checkPtDir and stuff inside it" @@ -66,9 +65,8 @@ then -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ - -d nochain,cpu,in_asm,int \ -gdb tcp::$tcpPort -S \ - 2>&1 >/dev/null | ./silencePipe | ./parseQEMUtoGDB/parseQEMUtoGDB_run.py | ./parseGDBtoTrace/parseGDBtoTrace_run.py $interruptsFile | ./remove_dup.awk > $outTraceFile) \ + 2>&1 1>./qemu-serial | ./parseQEMUtoGDB/parseQEMUtoGDB_run.py | ./parseGDBtoTrace/parseGDBtoTrace_run.py $interruptsFile | ./remove_dup.awk > $outTraceFile) \ & riscv64-unknown-elf-gdb --quiet -ex "source genCheckpoint.gdb" echo "Completed GDB script at $(date +%H:%M:%S)" From d8ddda760b21f6e4b50e3d153bc40c1d13b9779b Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 00:37:46 +0000 Subject: [PATCH 075/199] deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test --- pipelined/regression/regression-wally | 2 +- pipelined/testbench/testbench.sv | 3 - pipelined/testbench/tests.vh | 37 +- .../rv64i_m/privilege/Makefrag | 26 +- .../WALLY-CSR-PERMISSIONS-M.reference_output | 1008 ++++ .../WALLY-CSR-PERMISSIONS-S.reference_output | 336 ++ .../references/WALLY-MARCHID.reference_output | 392 ++ .../references/WALLY-MCAUSE.reference_output | 208 + .../references/WALLY-MEDELEG.reference_output | 120 + .../references/WALLY-MHARTID.reference_output | 392 ++ .../references/WALLY-MIMPID.reference_output | 392 ++ .../references/WALLY-MSTATUS.reference_output | 16 + .../references/WALLY-MTVEC.reference_output | 96 + .../WALLY-MVENDORID.reference_output | 392 ++ .../references/WALLY-SCAUSE.reference_output | 128 + .../references/WALLY-STVEC.reference_output | 64 + .../references/WALLY-UCAUSE.reference_output | 80 + .../privilege/src/WALLY-CSR-PERMISSIONS-M.S | 5265 +++++++++++++++++ .../privilege/src/WALLY-CSR-PERMISSIONS-S.S | 2627 ++++++++ .../rv64i_m/privilege/src/WALLY-MARCHID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MCAUSE.S | 2324 ++++++++ .../rv64i_m/privilege/src/WALLY-MEDELEG.S | 3675 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MHARTID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MIMPID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-MSTATUS.S | 433 ++ .../rv64i_m/privilege/src/WALLY-MTVEC.S | 1455 +++++ .../rv64i_m/privilege/src/WALLY-MVENDORID.S | 3778 ++++++++++++ .../rv64i_m/privilege/src/WALLY-SCAUSE.S | 1396 +++++ .../rv64i_m/privilege/src/WALLY-STVEC.S | 1022 ++++ .../rv64i_m/privilege/src/WALLY-UCAUSE.S | 459 ++ 30 files changed, 37431 insertions(+), 29 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-S.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MARCHID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MCAUSE.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MEDELEG.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MHARTID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIMPID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MSTATUS.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MTVEC.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MVENDORID.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-SCAUSE.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-STVEC.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-UCAUSE.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-M.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index a35684b32..17782b9de 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -62,7 +62,7 @@ tc = TestCase( grepstr="400100000 instructions") configs.append(tc) -tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] +tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] for test in tests64gc: tc = TestCase( name=test, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 226b2f287..7c582280f 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -33,8 +33,6 @@ `include "tests.vh" module testbench; - parameter TESTSPERIPH = 0; // set to 0 for regression - parameter TESTSPRIV = 0; // set to 0 for regression parameter DEBUG=0; parameter TEST="none"; @@ -89,7 +87,6 @@ logic [3:0] dummy; "arch64m": if (`M_SUPPORTED) tests = arch64m; "arch64d": if (`D_SUPPORTED) tests = arch64d; "imperas64i": tests = imperas64i; - "imperas64p": tests = imperas64p; // "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index c90484f3e..e8f8fd12d 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -846,28 +846,6 @@ string imperas32f[] = '{ "rv64BP/dhrystone", "1000000" }; - string imperas64p[] = '{ - `MYIMPERASTEST, - "rv64p/WALLY-MSTATUS", "2000", - "rv64p/WALLY-MCAUSE", "3000", - "rv64p/WALLY-SCAUSE", "2000", - "rv64p/WALLY-MEPC", "5000", - "rv64p/WALLY-SEPC", "4000", - "rv64p/WALLY-MTVAL", "6000", - "rv64p/WALLY-STVAL", "4000", - "rv64p/WALLY-MTVEC", "2000", - "rv64p/WALLY-STVEC", "2000", - "rv64p/WALLY-MARCHID", "4000", - "rv64p/WALLY-MIMPID", "4000", - "rv64p/WALLY-MHARTID", "4000", - "rv64p/WALLY-MVENDORID", "4000", - "rv64p/WALLY-MIE", "3000", - "rv64p/WALLY-MEDELEG", "4000", - "rv64p/WALLY-IP", "2000", - "rv64p/WALLY-CSR-PERMISSIONS-M", "5000", - "rv64p/WALLY-CSR-PERMISSIONS-S", "3000" - }; - string imperas32p[] = '{ `MYIMPERASTEST, "rv32p/WALLY-MSTATUS", "2000", @@ -1481,7 +1459,20 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0", "rv64i_m/privilege/WALLY-misa-01", "40A0", "rv64i_m/privilege/WALLY-scratch-01", "40A0", - "rv64i_m/privilege/WALLY-sscratch-s-01", "40A0" + "rv64i_m/privilege/WALLY-sscratch-s-01", "40A0", + "rv64i_m/privilege/WALLY-MSTATUS", "2090", + "rv64i_m/privilege/WALLY-MCAUSE", "3090", + "rv64i_m/privilege/WALLY-SCAUSE", "2090", + "rv64i_m/privilege/WALLY-UCAUSE", "2090", + "rv64i_m/privilege/WALLY-MTVEC", "2090", + "rv64i_m/privilege/WALLY-STVEC", "2090", + "rv64i_m/privilege/WALLY-MEDELEG", "4090", + "rv64i_m/privilege/WALLY-MARCHID", "4090", + "rv64i_m/privilege/WALLY-MHARTID", "4090", + "rv64i_m/privilege/WALLY-MIMPID", "4090", + "rv64i_m/privilege/WALLY-MVENDORID", "4090", + "rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "5090", + "rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "3090" }; string wally64periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 395374e85..bdfaaa657 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -36,11 +36,33 @@ rv64i_sc_tests = \ WALLY-CSR-permission-u-01 \ WALLY-misa-01 \ WALLY-scratch-01 \ - WALLY-sscratch-s-01 + WALLY-sscratch-s-01 \ +# Don't simulate these because they rely on SoC features that Wally does not offer. target_tests_nosim = \ WALLY-PMA \ - WALLY-PERIPH + WALLY-PERIPH \ + WALLY-MSTATUS \ + WALLY-MCAUSE \ + WALLY-SCAUSE \ + WALLY-UCAUSE \ + WALLY-MTVEC \ + WALLY-STVEC \ + WALLY-MEDELEG \ + WALLY-MARCHID \ + WALLY-MHARTID \ + WALLY-MIMPID \ + WALLY-MVENDORID \ + WALLY-CSR-PERMISSIONS-M \ + WALLY-CSR-PERMISSIONS-S + # Have all 0's in references! + #WALLY-MEPC \ + #WALLY-SEPC \ + #WALLY-MTVAL \ + #WALLY-STVAL \ + # Otherwise Broken for Unknown Reasons + #WALLY-MIE \ + #WALLY-IP \ rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output new file mode 100644 index 000000000..ce736a358 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-M.reference_output @@ -0,0 +1,1008 @@ +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 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index 000000000..771190ecb --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-PERMISSIONS-S.reference_output @@ -0,0 +1,336 @@ +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 +00000002 +00000000 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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MHARTID.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MHARTID.reference_output new file mode 100644 index 000000000..15b0e0631 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MHARTID.reference_output @@ -0,0 +1,392 @@ +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 +00000000 +00000000 +00000002 +00000000 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+00000002 +00000000 +00000003 +00000000 +00000004 +00000000 +00000006 +00000000 +00000008 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-M.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-M.S new file mode 100644 index 000000000..b3e66eba9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-M.S @@ -0,0 +1,5265 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-CSR-PERMISSIONS-M.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:21.723799// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mstatus_0 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_s_mstatus_0 + + _m_trap_from_s_mstatus_0: + bnez x30, _j_end_s_mstatus_0 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mstatus_0: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo0: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo1: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo2: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo3: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo4: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo5: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo6: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mstatus_0: + + li x30, 0 + la x1, _m_trap_from_u_mstatus_7 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_u_mstatus_7 + + _m_trap_from_u_mstatus_7: + bnez x30, _j_end_u_mstatus_7 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mstatus_7: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo7: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo8: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo9: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo10: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo11: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo12: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo13: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mstatus_7: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mstatus_14 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_s_mstatus_14 + + _m_trap_from_s_mstatus_14: + bnez x30, _j_end_s_mstatus_14 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mstatus_14: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo14: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo15: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo16: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo17: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo18: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo19: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo20: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mstatus_14: + + li x30, 0 + la x1, _m_trap_from_u_mstatus_21 + csrw mtvec, x1 + + csrr x23, mstatus + + j _j_test_u_mstatus_21 + + _m_trap_from_u_mstatus_21: + bnez x30, _j_end_u_mstatus_21 + + csrr x25, mcause + csrr x24, mstatus + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mstatus_21: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo21: + li x25, 0xDEADBEA7 + + csrrw x1, mstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo22: + li x25, 0xDEADBEA7 + + csrrw x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo23: + li x25, 0xDEADBEA7 + + csrrwi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo24: + li x25, 0xDEADBEA7 + + csrrs x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo25: + li x25, 0xDEADBEA7 + + csrrc x0, mstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo26: + li x25, 0xDEADBEA7 + + csrrsi x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo27: + li x25, 0xDEADBEA7 + + csrrci x0, mstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mstatus_21: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_medeleg_28 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_s_medeleg_28 + + _m_trap_from_s_medeleg_28: + bnez x30, _j_end_s_medeleg_28 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_medeleg_28: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo28: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo30: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo32: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo34: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo36: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo38: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo40: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_medeleg_28: + + li x30, 0 + la x1, _m_trap_from_u_medeleg_42 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_u_medeleg_42 + + _m_trap_from_u_medeleg_42: + bnez x30, _j_end_u_medeleg_42 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_medeleg_42: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo42: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo44: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo46: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo48: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo50: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo52: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo54: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_medeleg_42: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_medeleg_56 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_s_medeleg_56 + + _m_trap_from_s_medeleg_56: + bnez x30, _j_end_s_medeleg_56 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_medeleg_56: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo56: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo58: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo60: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo62: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo64: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo66: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo68: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_medeleg_56: + + li x30, 0 + la x1, _m_trap_from_u_medeleg_70 + csrw mtvec, x1 + + csrr x23, medeleg + + j _j_test_u_medeleg_70 + + _m_trap_from_u_medeleg_70: + bnez x30, _j_end_u_medeleg_70 + + csrr x25, mcause + csrr x24, medeleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_medeleg_70: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo70: + li x25, 0xDEADBEA7 + + csrrw x1, medeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo72: + li x25, 0xDEADBEA7 + + csrrw x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo74: + li x25, 0xDEADBEA7 + + csrrwi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo76: + li x25, 0xDEADBEA7 + + csrrs x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo78: + li x25, 0xDEADBEA7 + + csrrc x0, medeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo80: + li x25, 0xDEADBEA7 + + csrrsi x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo82: + li x25, 0xDEADBEA7 + + csrrci x0, medeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_medeleg_70: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mideleg_84 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_s_mideleg_84 + + _m_trap_from_s_mideleg_84: + bnez x30, _j_end_s_mideleg_84 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mideleg_84: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo84: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo86: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo88: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo90: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo92: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo94: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo96: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mideleg_84: + + li x30, 0 + la x1, _m_trap_from_u_mideleg_98 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_u_mideleg_98 + + _m_trap_from_u_mideleg_98: + bnez x30, _j_end_u_mideleg_98 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mideleg_98: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo98: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo100: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo102: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo104: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo106: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo108: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo110: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mideleg_98: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mideleg_112 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_s_mideleg_112 + + _m_trap_from_s_mideleg_112: + bnez x30, _j_end_s_mideleg_112 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mideleg_112: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo112: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo114: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo116: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo118: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo120: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo122: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo124: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mideleg_112: + + li x30, 0 + la x1, _m_trap_from_u_mideleg_126 + csrw mtvec, x1 + + csrr x23, mideleg + + j _j_test_u_mideleg_126 + + _m_trap_from_u_mideleg_126: + bnez x30, _j_end_u_mideleg_126 + + csrr x25, mcause + csrr x24, mideleg + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mideleg_126: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo126: + li x25, 0xDEADBEA7 + + csrrw x1, mideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo128: + li x25, 0xDEADBEA7 + + csrrw x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo130: + li x25, 0xDEADBEA7 + + csrrwi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo132: + li x25, 0xDEADBEA7 + + csrrs x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo134: + li x25, 0xDEADBEA7 + + csrrc x0, mideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo136: + li x25, 0xDEADBEA7 + + csrrsi x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo138: + li x25, 0xDEADBEA7 + + csrrci x0, mideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mideleg_126: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mie_140 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_s_mie_140 + + _m_trap_from_s_mie_140: + bnez x30, _j_end_s_mie_140 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mie_140: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo140: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo142: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo144: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo146: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo148: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo150: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo152: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mie_140: + + li x30, 0 + la x1, _m_trap_from_u_mie_154 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_u_mie_154 + + _m_trap_from_u_mie_154: + bnez x30, _j_end_u_mie_154 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mie_154: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo154: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo156: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo158: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo160: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo162: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo164: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo166: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mie_154: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mie_168 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_s_mie_168 + + _m_trap_from_s_mie_168: + bnez x30, _j_end_s_mie_168 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mie_168: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo168: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo170: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo172: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo174: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo176: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo178: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo180: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mie_168: + + li x30, 0 + la x1, _m_trap_from_u_mie_182 + csrw mtvec, x1 + + csrr x23, mie + + j _j_test_u_mie_182 + + _m_trap_from_u_mie_182: + bnez x30, _j_end_u_mie_182 + + csrr x25, mcause + csrr x24, mie + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mie_182: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo182: + li x25, 0xDEADBEA7 + + csrrw x1, mie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo184: + li x25, 0xDEADBEA7 + + csrrw x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo186: + li x25, 0xDEADBEA7 + + csrrwi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo188: + li x25, 0xDEADBEA7 + + csrrs x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo190: + li x25, 0xDEADBEA7 + + csrrc x0, mie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo192: + li x25, 0xDEADBEA7 + + csrrsi x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo194: + li x25, 0xDEADBEA7 + + csrrci x0, mie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mie_182: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtvec_196 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_s_mtvec_196 + + _m_trap_from_s_mtvec_196: + bnez x30, _j_end_s_mtvec_196 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtvec_196: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo196: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo198: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo200: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo202: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo204: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo206: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo208: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtvec_196: + + li x30, 0 + la x1, _m_trap_from_u_mtvec_210 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_u_mtvec_210 + + _m_trap_from_u_mtvec_210: + bnez x30, _j_end_u_mtvec_210 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtvec_210: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo210: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo212: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo214: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo216: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo218: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo220: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo222: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtvec_210: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtvec_224 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_s_mtvec_224 + + _m_trap_from_s_mtvec_224: + bnez x30, _j_end_s_mtvec_224 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtvec_224: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo224: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo226: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo228: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo230: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo232: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo234: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo236: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtvec_224: + + li x30, 0 + la x1, _m_trap_from_u_mtvec_238 + csrw mtvec, x1 + + csrr x23, mtvec + + j _j_test_u_mtvec_238 + + _m_trap_from_u_mtvec_238: + bnez x30, _j_end_u_mtvec_238 + + csrr x25, mcause + csrr x24, mtvec + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtvec_238: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo238: + li x25, 0xDEADBEA7 + + csrrw x1, mtvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo240: + li x25, 0xDEADBEA7 + + csrrw x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo242: + li x25, 0xDEADBEA7 + + csrrwi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo244: + li x25, 0xDEADBEA7 + + csrrs x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo246: + li x25, 0xDEADBEA7 + + csrrc x0, mtvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo248: + li x25, 0xDEADBEA7 + + csrrsi x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo250: + li x25, 0xDEADBEA7 + + csrrci x0, mtvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtvec_238: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcounteren_252 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_s_mcounteren_252 + + _m_trap_from_s_mcounteren_252: + bnez x30, _j_end_s_mcounteren_252 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcounteren_252: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo252: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo254: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo256: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo258: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo260: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo262: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo264: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcounteren_252: + + li x30, 0 + la x1, _m_trap_from_u_mcounteren_266 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_u_mcounteren_266 + + _m_trap_from_u_mcounteren_266: + bnez x30, _j_end_u_mcounteren_266 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcounteren_266: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo266: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo268: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo270: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo272: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo274: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo276: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo278: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcounteren_266: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcounteren_280 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_s_mcounteren_280 + + _m_trap_from_s_mcounteren_280: + bnez x30, _j_end_s_mcounteren_280 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcounteren_280: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo280: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo282: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo284: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo286: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo288: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo290: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo292: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcounteren_280: + + li x30, 0 + la x1, _m_trap_from_u_mcounteren_294 + csrw mtvec, x1 + + csrr x23, mcounteren + + j _j_test_u_mcounteren_294 + + _m_trap_from_u_mcounteren_294: + bnez x30, _j_end_u_mcounteren_294 + + csrr x25, mcause + csrr x24, mcounteren + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcounteren_294: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo294: + li x25, 0xDEADBEA7 + + csrrw x1, mcounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo296: + li x25, 0xDEADBEA7 + + csrrw x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo298: + li x25, 0xDEADBEA7 + + csrrwi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo300: + li x25, 0xDEADBEA7 + + csrrs x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo302: + li x25, 0xDEADBEA7 + + csrrc x0, mcounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo304: + li x25, 0xDEADBEA7 + + csrrsi x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo306: + li x25, 0xDEADBEA7 + + csrrci x0, mcounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcounteren_294: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mscratch_308 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_s_mscratch_308 + + _m_trap_from_s_mscratch_308: + bnez x30, _j_end_s_mscratch_308 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mscratch_308: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo308: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo310: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo312: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo314: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo316: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo318: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo320: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mscratch_308: + + li x30, 0 + la x1, _m_trap_from_u_mscratch_322 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_u_mscratch_322 + + _m_trap_from_u_mscratch_322: + bnez x30, _j_end_u_mscratch_322 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mscratch_322: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo322: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo324: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo326: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo328: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo330: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo332: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo334: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mscratch_322: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mscratch_336 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_s_mscratch_336 + + _m_trap_from_s_mscratch_336: + bnez x30, _j_end_s_mscratch_336 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mscratch_336: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo336: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo338: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo340: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo342: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo344: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo346: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo348: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mscratch_336: + + li x30, 0 + la x1, _m_trap_from_u_mscratch_350 + csrw mtvec, x1 + + csrr x23, mscratch + + j _j_test_u_mscratch_350 + + _m_trap_from_u_mscratch_350: + bnez x30, _j_end_u_mscratch_350 + + csrr x25, mcause + csrr x24, mscratch + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mscratch_350: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo350: + li x25, 0xDEADBEA7 + + csrrw x1, mscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo352: + li x25, 0xDEADBEA7 + + csrrw x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo354: + li x25, 0xDEADBEA7 + + csrrwi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo356: + li x25, 0xDEADBEA7 + + csrrs x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo358: + li x25, 0xDEADBEA7 + + csrrc x0, mscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo360: + li x25, 0xDEADBEA7 + + csrrsi x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo362: + li x25, 0xDEADBEA7 + + csrrci x0, mscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mscratch_350: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mepc_364 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_s_mepc_364 + + _m_trap_from_s_mepc_364: + bnez x30, _j_end_s_mepc_364 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mepc_364: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo364: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo365: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo366: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo367: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo368: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo369: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo370: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mepc_364: + + li x30, 0 + la x1, _m_trap_from_u_mepc_371 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_u_mepc_371 + + _m_trap_from_u_mepc_371: + bnez x30, _j_end_u_mepc_371 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mepc_371: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo371: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo372: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo373: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo374: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo375: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo376: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo377: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mepc_371: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mepc_378 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_s_mepc_378 + + _m_trap_from_s_mepc_378: + bnez x30, _j_end_s_mepc_378 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mepc_378: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo378: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo379: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo380: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo381: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo382: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo383: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo384: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mepc_378: + + li x30, 0 + la x1, _m_trap_from_u_mepc_385 + csrw mtvec, x1 + + csrr x23, mepc + + j _j_test_u_mepc_385 + + _m_trap_from_u_mepc_385: + bnez x30, _j_end_u_mepc_385 + + csrr x25, mcause + csrr x24, mepc + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mepc_385: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo385: + li x25, 0xDEADBEA7 + + csrrw x1, mepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo386: + li x25, 0xDEADBEA7 + + csrrw x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo387: + li x25, 0xDEADBEA7 + + csrrwi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo388: + li x25, 0xDEADBEA7 + + csrrs x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo389: + li x25, 0xDEADBEA7 + + csrrc x0, mepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo390: + li x25, 0xDEADBEA7 + + csrrsi x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo391: + li x25, 0xDEADBEA7 + + csrrci x0, mepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mepc_385: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcause_392 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_s_mcause_392 + + _m_trap_from_s_mcause_392: + bnez x30, _j_end_s_mcause_392 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcause_392: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo392: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo393: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo394: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo395: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo396: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo397: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo398: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcause_392: + + li x30, 0 + la x1, _m_trap_from_u_mcause_399 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_u_mcause_399 + + _m_trap_from_u_mcause_399: + bnez x30, _j_end_u_mcause_399 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcause_399: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo399: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo400: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo401: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo402: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo403: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo404: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo405: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcause_399: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mcause_406 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_s_mcause_406 + + _m_trap_from_s_mcause_406: + bnez x30, _j_end_s_mcause_406 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mcause_406: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo406: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo407: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo408: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo409: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo410: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo411: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo412: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mcause_406: + + li x30, 0 + la x1, _m_trap_from_u_mcause_413 + csrw mtvec, x1 + + csrr x23, mcause + + j _j_test_u_mcause_413 + + _m_trap_from_u_mcause_413: + bnez x30, _j_end_u_mcause_413 + + csrr x25, mcause + csrr x24, mcause + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mcause_413: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo413: + li x25, 0xDEADBEA7 + + csrrw x1, mcause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo414: + li x25, 0xDEADBEA7 + + csrrw x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo415: + li x25, 0xDEADBEA7 + + csrrwi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo416: + li x25, 0xDEADBEA7 + + csrrs x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo417: + li x25, 0xDEADBEA7 + + csrrc x0, mcause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo418: + li x25, 0xDEADBEA7 + + csrrsi x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo419: + li x25, 0xDEADBEA7 + + csrrci x0, mcause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mcause_413: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtval_420 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_s_mtval_420 + + _m_trap_from_s_mtval_420: + bnez x30, _j_end_s_mtval_420 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtval_420: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo420: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo421: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo422: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo423: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo424: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo425: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo426: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtval_420: + + li x30, 0 + la x1, _m_trap_from_u_mtval_427 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_u_mtval_427 + + _m_trap_from_u_mtval_427: + bnez x30, _j_end_u_mtval_427 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtval_427: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo427: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo428: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo429: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo430: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo431: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo432: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo433: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtval_427: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mtval_434 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_s_mtval_434 + + _m_trap_from_s_mtval_434: + bnez x30, _j_end_s_mtval_434 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mtval_434: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo434: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo435: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo436: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo437: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo438: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo439: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo440: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mtval_434: + + li x30, 0 + la x1, _m_trap_from_u_mtval_441 + csrw mtvec, x1 + + csrr x23, mtval + + j _j_test_u_mtval_441 + + _m_trap_from_u_mtval_441: + bnez x30, _j_end_u_mtval_441 + + csrr x25, mcause + csrr x24, mtval + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mtval_441: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo441: + li x25, 0xDEADBEA7 + + csrrw x1, mtval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo442: + li x25, 0xDEADBEA7 + + csrrw x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo443: + li x25, 0xDEADBEA7 + + csrrwi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo444: + li x25, 0xDEADBEA7 + + csrrs x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo445: + li x25, 0xDEADBEA7 + + csrrc x0, mtval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo446: + li x25, 0xDEADBEA7 + + csrrsi x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo447: + li x25, 0xDEADBEA7 + + csrrci x0, mtval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mtval_441: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mip_448 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_s_mip_448 + + _m_trap_from_s_mip_448: + bnez x30, _j_end_s_mip_448 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mip_448: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo448: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo450: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo452: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo454: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo456: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo458: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo460: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mip_448: + + li x30, 0 + la x1, _m_trap_from_u_mip_462 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_u_mip_462 + + _m_trap_from_u_mip_462: + bnez x30, _j_end_u_mip_462 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mip_462: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo462: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo464: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo466: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo468: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo470: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo472: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo474: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mip_462: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_s_mip_476 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_s_mip_476 + + _m_trap_from_s_mip_476: + bnez x30, _j_end_s_mip_476 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_s_mip_476: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + _jdo476: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo478: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo480: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo482: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo484: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo486: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo488: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_s_mip_476: + + li x30, 0 + la x1, _m_trap_from_u_mip_490 + csrw mtvec, x1 + + csrr x23, mip + + j _j_test_u_mip_490 + + _m_trap_from_u_mip_490: + bnez x30, _j_end_u_mip_490 + + csrr x25, mcause + csrr x24, mip + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_mip_490: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo490: + li x25, 0xDEADBEA7 + + csrrw x1, mip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo492: + li x25, 0xDEADBEA7 + + csrrw x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo494: + li x25, 0xDEADBEA7 + + csrrwi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo496: + li x25, 0xDEADBEA7 + + csrrs x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo498: + li x25, 0xDEADBEA7 + + csrrc x0, mip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo500: + li x25, 0xDEADBEA7 + + csrrsi x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo502: + li x25, 0xDEADBEA7 + + csrrci x0, mip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + sub x25, x24, x23 + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_mip_490: + + csrw mtvec, x19 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 504, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S new file mode 100644 index 000000000..c176e6191 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-PERMISSIONS-S.S @@ -0,0 +1,2627 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-CSR-PERMISSIONS-S.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:21.731076// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sstatus_0 + csrw mtvec, x1 + + csrr x23, sstatus + + j _j_test_u_sstatus_0 + + _m_trap_from_u_sstatus_0: + bnez x30, _j_end_u_sstatus_0 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sstatus_0: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo0: + li x25, 0xDEADBEA7 + + csrrw x1, sstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo1: + li x25, 0xDEADBEA7 + + csrrw x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo2: + li x25, 0xDEADBEA7 + + csrrwi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo3: + li x25, 0xDEADBEA7 + + csrrs x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo4: + li x25, 0xDEADBEA7 + + csrrc x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo5: + li x25, 0xDEADBEA7 + + csrrsi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo6: + li x25, 0xDEADBEA7 + + csrrci x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sstatus_0: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sstatus_7 + csrw mtvec, x1 + + csrr x23, sstatus + + j _j_test_u_sstatus_7 + + _m_trap_from_u_sstatus_7: + bnez x30, _j_end_u_sstatus_7 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sstatus_7: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo7: + li x25, 0xDEADBEA7 + + csrrw x1, sstatus, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo8: + li x25, 0xDEADBEA7 + + csrrw x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo9: + li x25, 0xDEADBEA7 + + csrrwi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo10: + li x25, 0xDEADBEA7 + + csrrs x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo11: + li x25, 0xDEADBEA7 + + csrrc x0, sstatus, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo12: + li x25, 0xDEADBEA7 + + csrrsi x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo13: + li x25, 0xDEADBEA7 + + csrrci x0, sstatus, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sstatus_7: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sedeleg_14 + csrw mtvec, x1 + + csrr x23, sedeleg + + j _j_test_u_sedeleg_14 + + _m_trap_from_u_sedeleg_14: + bnez x30, _j_end_u_sedeleg_14 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sedeleg_14: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo14: + li x25, 0xDEADBEA7 + + csrrw x1, sedeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo15: + li x25, 0xDEADBEA7 + + csrrw x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo16: + li x25, 0xDEADBEA7 + + csrrwi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo17: + li x25, 0xDEADBEA7 + + csrrs x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo18: + li x25, 0xDEADBEA7 + + csrrc x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo19: + li x25, 0xDEADBEA7 + + csrrsi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo20: + li x25, 0xDEADBEA7 + + csrrci x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sedeleg_14: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sedeleg_21 + csrw mtvec, x1 + + csrr x23, sedeleg + + j _j_test_u_sedeleg_21 + + _m_trap_from_u_sedeleg_21: + bnez x30, _j_end_u_sedeleg_21 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sedeleg_21: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo21: + li x25, 0xDEADBEA7 + + csrrw x1, sedeleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo22: + li x25, 0xDEADBEA7 + + csrrw x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo23: + li x25, 0xDEADBEA7 + + csrrwi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo24: + li x25, 0xDEADBEA7 + + csrrs x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo25: + li x25, 0xDEADBEA7 + + csrrc x0, sedeleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo26: + li x25, 0xDEADBEA7 + + csrrsi x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo27: + li x25, 0xDEADBEA7 + + csrrci x0, sedeleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sedeleg_21: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sideleg_28 + csrw mtvec, x1 + + csrr x23, sideleg + + j _j_test_u_sideleg_28 + + _m_trap_from_u_sideleg_28: + bnez x30, _j_end_u_sideleg_28 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sideleg_28: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo28: + li x25, 0xDEADBEA7 + + csrrw x1, sideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo29: + li x25, 0xDEADBEA7 + + csrrw x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo30: + li x25, 0xDEADBEA7 + + csrrwi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo31: + li x25, 0xDEADBEA7 + + csrrs x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo32: + li x25, 0xDEADBEA7 + + csrrc x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo33: + li x25, 0xDEADBEA7 + + csrrsi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo34: + li x25, 0xDEADBEA7 + + csrrci x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sideleg_28: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sideleg_35 + csrw mtvec, x1 + + csrr x23, sideleg + + j _j_test_u_sideleg_35 + + _m_trap_from_u_sideleg_35: + bnez x30, _j_end_u_sideleg_35 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sideleg_35: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo35: + li x25, 0xDEADBEA7 + + csrrw x1, sideleg, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo36: + li x25, 0xDEADBEA7 + + csrrw x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo37: + li x25, 0xDEADBEA7 + + csrrwi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo38: + li x25, 0xDEADBEA7 + + csrrs x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo39: + li x25, 0xDEADBEA7 + + csrrc x0, sideleg, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo40: + li x25, 0xDEADBEA7 + + csrrsi x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo41: + li x25, 0xDEADBEA7 + + csrrci x0, sideleg, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sideleg_35: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sie_42 + csrw mtvec, x1 + + csrr x23, sie + + j _j_test_u_sie_42 + + _m_trap_from_u_sie_42: + bnez x30, _j_end_u_sie_42 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sie_42: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo42: + li x25, 0xDEADBEA7 + + csrrw x1, sie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo43: + li x25, 0xDEADBEA7 + + csrrw x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo44: + li x25, 0xDEADBEA7 + + csrrwi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo45: + li x25, 0xDEADBEA7 + + csrrs x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo46: + li x25, 0xDEADBEA7 + + csrrc x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo47: + li x25, 0xDEADBEA7 + + csrrsi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo48: + li x25, 0xDEADBEA7 + + csrrci x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sie_42: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sie_49 + csrw mtvec, x1 + + csrr x23, sie + + j _j_test_u_sie_49 + + _m_trap_from_u_sie_49: + bnez x30, _j_end_u_sie_49 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sie_49: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo49: + li x25, 0xDEADBEA7 + + csrrw x1, sie, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo50: + li x25, 0xDEADBEA7 + + csrrw x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo51: + li x25, 0xDEADBEA7 + + csrrwi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo52: + li x25, 0xDEADBEA7 + + csrrs x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo53: + li x25, 0xDEADBEA7 + + csrrc x0, sie, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo54: + li x25, 0xDEADBEA7 + + csrrsi x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo55: + li x25, 0xDEADBEA7 + + csrrci x0, sie, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sie_49: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stvec_56 + csrw mtvec, x1 + + csrr x23, stvec + + j _j_test_u_stvec_56 + + _m_trap_from_u_stvec_56: + bnez x30, _j_end_u_stvec_56 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stvec_56: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo56: + li x25, 0xDEADBEA7 + + csrrw x1, stvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo57: + li x25, 0xDEADBEA7 + + csrrw x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo58: + li x25, 0xDEADBEA7 + + csrrwi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo59: + li x25, 0xDEADBEA7 + + csrrs x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo60: + li x25, 0xDEADBEA7 + + csrrc x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo61: + li x25, 0xDEADBEA7 + + csrrsi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo62: + li x25, 0xDEADBEA7 + + csrrci x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stvec_56: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stvec_63 + csrw mtvec, x1 + + csrr x23, stvec + + j _j_test_u_stvec_63 + + _m_trap_from_u_stvec_63: + bnez x30, _j_end_u_stvec_63 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stvec_63: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo63: + li x25, 0xDEADBEA7 + + csrrw x1, stvec, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo64: + li x25, 0xDEADBEA7 + + csrrw x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo65: + li x25, 0xDEADBEA7 + + csrrwi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo66: + li x25, 0xDEADBEA7 + + csrrs x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo67: + li x25, 0xDEADBEA7 + + csrrc x0, stvec, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo68: + li x25, 0xDEADBEA7 + + csrrsi x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo69: + li x25, 0xDEADBEA7 + + csrrci x0, stvec, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stvec_63: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scounteren_70 + csrw mtvec, x1 + + csrr x23, scounteren + + j _j_test_u_scounteren_70 + + _m_trap_from_u_scounteren_70: + bnez x30, _j_end_u_scounteren_70 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scounteren_70: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo70: + li x25, 0xDEADBEA7 + + csrrw x1, scounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo71: + li x25, 0xDEADBEA7 + + csrrw x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo72: + li x25, 0xDEADBEA7 + + csrrwi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo73: + li x25, 0xDEADBEA7 + + csrrs x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo74: + li x25, 0xDEADBEA7 + + csrrc x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo75: + li x25, 0xDEADBEA7 + + csrrsi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo76: + li x25, 0xDEADBEA7 + + csrrci x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scounteren_70: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scounteren_77 + csrw mtvec, x1 + + csrr x23, scounteren + + j _j_test_u_scounteren_77 + + _m_trap_from_u_scounteren_77: + bnez x30, _j_end_u_scounteren_77 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scounteren_77: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo77: + li x25, 0xDEADBEA7 + + csrrw x1, scounteren, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo78: + li x25, 0xDEADBEA7 + + csrrw x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo79: + li x25, 0xDEADBEA7 + + csrrwi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo80: + li x25, 0xDEADBEA7 + + csrrs x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo81: + li x25, 0xDEADBEA7 + + csrrc x0, scounteren, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo82: + li x25, 0xDEADBEA7 + + csrrsi x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo83: + li x25, 0xDEADBEA7 + + csrrci x0, scounteren, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scounteren_77: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sscratch_84 + csrw mtvec, x1 + + csrr x23, sscratch + + j _j_test_u_sscratch_84 + + _m_trap_from_u_sscratch_84: + bnez x30, _j_end_u_sscratch_84 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sscratch_84: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo84: + li x25, 0xDEADBEA7 + + csrrw x1, sscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo85: + li x25, 0xDEADBEA7 + + csrrw x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo86: + li x25, 0xDEADBEA7 + + csrrwi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo87: + li x25, 0xDEADBEA7 + + csrrs x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo88: + li x25, 0xDEADBEA7 + + csrrc x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo89: + li x25, 0xDEADBEA7 + + csrrsi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo90: + li x25, 0xDEADBEA7 + + csrrci x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sscratch_84: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sscratch_91 + csrw mtvec, x1 + + csrr x23, sscratch + + j _j_test_u_sscratch_91 + + _m_trap_from_u_sscratch_91: + bnez x30, _j_end_u_sscratch_91 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sscratch_91: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo91: + li x25, 0xDEADBEA7 + + csrrw x1, sscratch, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo92: + li x25, 0xDEADBEA7 + + csrrw x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo93: + li x25, 0xDEADBEA7 + + csrrwi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo94: + li x25, 0xDEADBEA7 + + csrrs x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo95: + li x25, 0xDEADBEA7 + + csrrc x0, sscratch, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo96: + li x25, 0xDEADBEA7 + + csrrsi x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo97: + li x25, 0xDEADBEA7 + + csrrci x0, sscratch, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sscratch_91: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sepc_98 + csrw mtvec, x1 + + csrr x23, sepc + + j _j_test_u_sepc_98 + + _m_trap_from_u_sepc_98: + bnez x30, _j_end_u_sepc_98 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sepc_98: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo98: + li x25, 0xDEADBEA7 + + csrrw x1, sepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo99: + li x25, 0xDEADBEA7 + + csrrw x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo100: + li x25, 0xDEADBEA7 + + csrrwi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo101: + li x25, 0xDEADBEA7 + + csrrs x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo102: + li x25, 0xDEADBEA7 + + csrrc x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo103: + li x25, 0xDEADBEA7 + + csrrsi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo104: + li x25, 0xDEADBEA7 + + csrrci x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sepc_98: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sepc_105 + csrw mtvec, x1 + + csrr x23, sepc + + j _j_test_u_sepc_105 + + _m_trap_from_u_sepc_105: + bnez x30, _j_end_u_sepc_105 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sepc_105: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo105: + li x25, 0xDEADBEA7 + + csrrw x1, sepc, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo106: + li x25, 0xDEADBEA7 + + csrrw x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo107: + li x25, 0xDEADBEA7 + + csrrwi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo108: + li x25, 0xDEADBEA7 + + csrrs x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo109: + li x25, 0xDEADBEA7 + + csrrc x0, sepc, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo110: + li x25, 0xDEADBEA7 + + csrrsi x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo111: + li x25, 0xDEADBEA7 + + csrrci x0, sepc, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sepc_105: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scause_112 + csrw mtvec, x1 + + csrr x23, scause + + j _j_test_u_scause_112 + + _m_trap_from_u_scause_112: + bnez x30, _j_end_u_scause_112 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scause_112: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo112: + li x25, 0xDEADBEA7 + + csrrw x1, scause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo113: + li x25, 0xDEADBEA7 + + csrrw x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo114: + li x25, 0xDEADBEA7 + + csrrwi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo115: + li x25, 0xDEADBEA7 + + csrrs x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo116: + li x25, 0xDEADBEA7 + + csrrc x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo117: + li x25, 0xDEADBEA7 + + csrrsi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo118: + li x25, 0xDEADBEA7 + + csrrci x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scause_112: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_scause_119 + csrw mtvec, x1 + + csrr x23, scause + + j _j_test_u_scause_119 + + _m_trap_from_u_scause_119: + bnez x30, _j_end_u_scause_119 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_scause_119: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo119: + li x25, 0xDEADBEA7 + + csrrw x1, scause, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo120: + li x25, 0xDEADBEA7 + + csrrw x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo121: + li x25, 0xDEADBEA7 + + csrrwi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo122: + li x25, 0xDEADBEA7 + + csrrs x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo123: + li x25, 0xDEADBEA7 + + csrrc x0, scause, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo124: + li x25, 0xDEADBEA7 + + csrrsi x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo125: + li x25, 0xDEADBEA7 + + csrrci x0, scause, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_scause_119: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stval_126 + csrw mtvec, x1 + + csrr x23, stval + + j _j_test_u_stval_126 + + _m_trap_from_u_stval_126: + bnez x30, _j_end_u_stval_126 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stval_126: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo126: + li x25, 0xDEADBEA7 + + csrrw x1, stval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo127: + li x25, 0xDEADBEA7 + + csrrw x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo128: + li x25, 0xDEADBEA7 + + csrrwi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo129: + li x25, 0xDEADBEA7 + + csrrs x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo130: + li x25, 0xDEADBEA7 + + csrrc x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo131: + li x25, 0xDEADBEA7 + + csrrsi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo132: + li x25, 0xDEADBEA7 + + csrrci x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stval_126: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_stval_133 + csrw mtvec, x1 + + csrr x23, stval + + j _j_test_u_stval_133 + + _m_trap_from_u_stval_133: + bnez x30, _j_end_u_stval_133 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_stval_133: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo133: + li x25, 0xDEADBEA7 + + csrrw x1, stval, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo134: + li x25, 0xDEADBEA7 + + csrrw x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo135: + li x25, 0xDEADBEA7 + + csrrwi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo136: + li x25, 0xDEADBEA7 + + csrrs x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo137: + li x25, 0xDEADBEA7 + + csrrc x0, stval, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo138: + li x25, 0xDEADBEA7 + + csrrsi x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo139: + li x25, 0xDEADBEA7 + + csrrci x0, stval, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_stval_133: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sip_140 + csrw mtvec, x1 + + csrr x23, sip + + j _j_test_u_sip_140 + + _m_trap_from_u_sip_140: + bnez x30, _j_end_u_sip_140 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sip_140: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo140: + li x25, 0xDEADBEA7 + + csrrw x1, sip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo141: + li x25, 0xDEADBEA7 + + csrrw x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo142: + li x25, 0xDEADBEA7 + + csrrwi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo143: + li x25, 0xDEADBEA7 + + csrrs x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo144: + li x25, 0xDEADBEA7 + + csrrc x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo145: + li x25, 0xDEADBEA7 + + csrrsi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo146: + li x25, 0xDEADBEA7 + + csrrci x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sip_140: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_sip_147 + csrw mtvec, x1 + + csrr x23, sip + + j _j_test_u_sip_147 + + _m_trap_from_u_sip_147: + bnez x30, _j_end_u_sip_147 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_sip_147: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo147: + li x25, 0xDEADBEA7 + + csrrw x1, sip, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo148: + li x25, 0xDEADBEA7 + + csrrw x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo149: + li x25, 0xDEADBEA7 + + csrrwi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo150: + li x25, 0xDEADBEA7 + + csrrs x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo151: + li x25, 0xDEADBEA7 + + csrrc x0, sip, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo152: + li x25, 0xDEADBEA7 + + csrrsi x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo153: + li x25, 0xDEADBEA7 + + csrrci x0, sip, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_sip_147: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_satp_154 + csrw mtvec, x1 + + csrr x23, satp + + j _j_test_u_satp_154 + + _m_trap_from_u_satp_154: + bnez x30, _j_end_u_satp_154 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_satp_154: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo154: + li x25, 0xDEADBEA7 + + csrrw x1, satp, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo155: + li x25, 0xDEADBEA7 + + csrrw x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo156: + li x25, 0xDEADBEA7 + + csrrwi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo157: + li x25, 0xDEADBEA7 + + csrrs x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo158: + li x25, 0xDEADBEA7 + + csrrc x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo159: + li x25, 0xDEADBEA7 + + csrrsi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo160: + li x25, 0xDEADBEA7 + + csrrci x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_satp_154: + + li x13, 1 + + li x30, 0 + la x1, _m_trap_from_u_satp_161 + csrw mtvec, x1 + + csrr x23, satp + + j _j_test_u_satp_161 + + _m_trap_from_u_satp_161: + bnez x30, _j_end_u_satp_161 + + csrr x25, mcause + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + + mret + + _j_test_u_satp_161: + + li x1, 0b110000000000 + csrrc x0, mstatus, x1 + li x1, 0b0100000000000 + csrrs x0, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x0, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + _jdo161: + li x25, 0xDEADBEA7 + + csrrw x1, satp, x0 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo162: + li x25, 0xDEADBEA7 + + csrrw x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo163: + li x25, 0xDEADBEA7 + + csrrwi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo164: + li x25, 0xDEADBEA7 + + csrrs x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo165: + li x25, 0xDEADBEA7 + + csrrc x0, satp, x13 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo166: + li x25, 0xDEADBEA7 + + csrrsi x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + _jdo167: + li x25, 0xDEADBEA7 + + csrrci x0, satp, 1 + + sd x25, 0(x7) + addi x7, x7, 8 + + li x30, 1 + ebreak + _j_end_u_satp_161: + + csrw mtvec, x19 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 168, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S new file mode 100644 index 000000000..0b4701d16 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MARCHID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MARCHID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.352985// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 0 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, marchid, x0 + csrrci x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 3 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, marchid, x0 + csrrci x0, marchid, 3 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 31 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, marchid, x0 + csrrci x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 0 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, marchid, x0 + csrrci x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 20 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 28 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, marchid, x0 + csrrci x0, marchid, 28 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 7 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, marchid, x0 + csrrci x0, marchid, 7 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 31 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 8 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, marchid, x0 + csrrci x0, marchid, 8 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 0 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 9 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, marchid, x0 + csrrci x0, marchid, 9 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 1 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 10 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, marchid, x0 + csrrci x0, marchid, 10 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 2 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 20 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, marchid, x0 + csrrci x0, marchid, 20 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 15 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, marchid, x0 + csrrci x0, marchid, 15 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 31 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 16 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, marchid, x0 + csrrci x0, marchid, 16 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 21 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 5 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(10606064097799060981) + csrrw x11, marchid, x0 + csrrci x0, marchid, 5 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 18 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4670668554830012946) + csrrw x11, marchid, x0 + csrrci x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 8 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1967122571526000840) + csrrw x11, marchid, x0 + csrrci x0, marchid, 30 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrw x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrwi x0, marchid, 22 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrs x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrc x0, marchid, x13 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrsi x0, marchid, 6 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(6416613002065245206) + csrrw x11, marchid, x0 + csrrci x0, marchid, 6 + csrrwi x12, marchid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S new file mode 100644 index 000000000..ec00a2de4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MCAUSE.S @@ -0,0 +1,2324 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MCAUSE.S +// dottolia@hmc.edu +// Created 2021-06-16 16:18:36.388509// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + slli a0,a0,0x1f + slli a0,a0,0x1e + slli a0,a0,0x1d + slli a0,a0,0x1c + slli a0,a0,0x1b + slli a0,a0,0x1a + slli a0,a0,0x19 + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak + csrw mtvec, x1 + la x1, _j_s_trap_ebreak + csrw stvec, x1 + la x1, _j_u_trap_ebreak + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak + + # Machine mode traps + _j_m_trap_ebreak: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak + mret + + # Supervisor mode traps + _j_s_trap_ebreak: + li x25, 0xBAD00001 + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak: + j _j_goto_machine_mode_ebreak + + _j_goto_machine_mode_ebreak: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak: + + csrr x18, medeleg + li x9, 0 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0 + csrw mideleg, x9 + + la x28, _jtest0 + j _jdo0 + + _jtest0: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo0: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 0(x6) + + la x28, _jtest1 + j _jdo1 + + _jtest1: + + csrr x25, mcause + + + jr x27 + + _jdo1: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 8(x6) + + la x28, _jtest2 + j _jdo2 + + _jtest2: + + csrr x25, mcause + + + jr x27 + + _jdo2: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 16(x6) + + la x28, _jtest3 + j _jdo3 + + _jtest3: + + csrr x25, mcause + + + jr x27 + + _jdo3: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 24(x6) + + la x28, _jtest4 + j _jdo4 + + _jtest4: + + csrr x25, mcause + + + jr x27 + + _jdo4: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 32(x6) + + la x28, _jtest5 + j _jdo5 + + _jtest5: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo5: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 40(x6) + + la x28, _jtest6 + j _jdo6 + + _jtest6: + + csrr x25, mcause + + + jr x27 + + _jdo6: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 48(x6) + + la x28, _jtest7 + j _jdo7 + + _jtest7: + + csrr x25, mcause + + + jr x27 + + _jdo7: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 56(x6) + + la x28, _jtest8 + j _jdo8 + + _jtest8: + + csrr x25, mcause + + + jr x27 + + _jdo8: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 64(x6) + + la x28, _jtest9 + j _jdo9 + + _jtest9: + + csrr x25, mcause + + + jr x27 + + _jdo9: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 72(x6) + + la x28, _jtest10 + j _jdo10 + + _jtest10: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo10: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 80(x6) + + la x28, _jtest11 + j _jdo11 + + _jtest11: + + csrr x25, mcause + + + jr x27 + + _jdo11: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 88(x6) + + la x28, _jtest12 + j _jdo12 + + _jtest12: + + csrr x25, mcause + + + jr x27 + + _jdo12: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 96(x6) + + la x28, _jtest13 + j _jdo13 + + _jtest13: + + csrr x25, mcause + + + jr x27 + + _jdo13: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 104(x6) + + la x28, _jtest14 + j _jdo14 + + _jtest14: + + csrr x25, mcause + + + jr x27 + + _jdo14: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 112(x6) + + la x28, _jtest15 + j _jdo15 + + _jtest15: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo15: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 120(x6) + + la x28, _jtest16 + j _jdo16 + + _jtest16: + + csrr x25, mcause + + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 128(x6) + + la x28, _jtest17 + j _jdo17 + + _jtest17: + + csrr x25, mcause + + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 136(x6) + + la x28, _jtest18 + j _jdo18 + + _jtest18: + + csrr x25, mcause + + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 144(x6) + + la x28, _jtest19 + j _jdo19 + + _jtest19: + + csrr x25, mcause + + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 152(x6) + + la x28, _jtest20 + j _jdo20 + + _jtest20: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 160(x6) + + la x28, _jtest21 + j _jdo21 + + _jtest21: + + csrr x25, mcause + + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 168(x6) + + la x28, _jtest22 + j _jdo22 + + _jtest22: + + csrr x25, mcause + + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 176(x6) + + la x28, _jtest23 + j _jdo23 + + _jtest23: + + csrr x25, mcause + + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 184(x6) + + la x28, _jtest24 + j _jdo24 + + _jtest24: + + csrr x25, mcause + + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 192(x6) + + la x28, _jtest25 + j _jdo25 + + _jtest25: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 200(x6) + + la x28, _jtest26 + j _jdo26 + + _jtest26: + + csrr x25, mcause + + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 208(x6) + + la x28, _jtest27 + j _jdo27 + + _jtest27: + + csrr x25, mcause + + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 216(x6) + + la x28, _jtest28 + j _jdo28 + + _jtest28: + + csrr x25, mcause + + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 224(x6) + + la x28, _jtest29 + j _jdo29 + + _jtest29: + + csrr x25, mcause + + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 232(x6) + + la x28, _jtest30 + j _jdo30 + + _jtest30: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 240(x6) + + la x28, _jtest31 + j _jdo31 + + _jtest31: + + csrr x25, mcause + + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 248(x6) + + la x28, _jtest32 + j _jdo32 + + _jtest32: + + csrr x25, mcause + + + jr x27 + + _jdo32: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 256(x6) + + la x28, _jtest33 + j _jdo33 + + _jtest33: + + csrr x25, mcause + + + jr x27 + + _jdo33: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 264(x6) + + la x28, _jtest34 + j _jdo34 + + _jtest34: + + csrr x25, mcause + + + jr x27 + + _jdo34: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 272(x6) + + la x28, _jtest35 + j _jdo35 + + _jtest35: + + csrr x25, mcause + + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + li x1, -1 + sd x1, 0(x18) + + jr x27 + + _jdo35: + li x25, 0xDEADBEA7 + li gp, 0 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + ld x11, 0(x18) + li x1, 0x3fffffffffffffff + sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 280(x6) + + la x28, _jtest36 + j _jdo36 + + _jtest36: + + csrr x25, mcause + + + jr x27 + + _jdo36: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 288(x6) + + la x28, _jtest37 + j _jdo37 + + _jtest37: + + csrr x25, mcause + + + jr x27 + + _jdo37: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 296(x6) + + la x28, _jtest38 + j _jdo38 + + _jtest38: + + csrr x25, mcause + + + jr x27 + + _jdo38: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 304(x6) + + la x28, _jtest39 + j _jdo39 + + _jtest39: + + csrr x25, mcause + + + jr x27 + + _jdo39: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 312(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + la x28, _jtest40 + j _jdo40 + + _jtest40: + + csrr x25, mcause + + + jr x27 + + _jdo40: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 320(x6) + + la x28, _jtest41 + j _jdo41 + + _jtest41: + + csrr x25, mcause + + + jr x27 + + _jdo41: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 328(x6) + + la x28, _jtest42 + j _jdo42 + + _jtest42: + + csrr x25, mcause + + + jr x27 + + _jdo42: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 336(x6) + + la x28, _jtest43 + j _jdo43 + + _jtest43: + + csrr x25, mcause + + + jr x27 + + _jdo43: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 344(x6) + + la x28, _jtest44 + j _jdo44 + + _jtest44: + + csrr x25, mcause + + + jr x27 + + _jdo44: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 352(x6) + + la x28, _jtest45 + j _jdo45 + + _jtest45: + + csrr x25, mcause + + + jr x27 + + _jdo45: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 360(x6) + + la x28, _jtest46 + j _jdo46 + + _jtest46: + + csrr x25, mcause + + + jr x27 + + _jdo46: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 368(x6) + + la x28, _jtest47 + j _jdo47 + + _jtest47: + + csrr x25, mcause + + + jr x27 + + _jdo47: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 376(x6) + + la x28, _jtest48 + j _jdo48 + + _jtest48: + + csrr x25, mcause + + + jr x27 + + _jdo48: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 384(x6) + + la x28, _jtest49 + j _jdo49 + + _jtest49: + + csrr x25, mcause + + + jr x27 + + _jdo49: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 392(x6) + + la x28, _jtest50 + j _jdo50 + + _jtest50: + + csrr x25, mcause + + + jr x27 + + _jdo50: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 400(x6) + + la x28, _jtest51 + j _jdo51 + + _jtest51: + + csrr x25, mcause + + + jr x27 + + _jdo51: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 408(x6) + + la x28, _jtest52 + j _jdo52 + + _jtest52: + + csrr x25, mcause + + + jr x27 + + _jdo52: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 416(x6) + + la x28, _jtest53 + j _jdo53 + + _jtest53: + + csrr x25, mcause + + + jr x27 + + _jdo53: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 424(x6) + + la x28, _jtest54 + j _jdo54 + + _jtest54: + + csrr x25, mcause + + + jr x27 + + _jdo54: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 432(x6) + + la x28, _jtest55 + j _jdo55 + + _jtest55: + + csrr x25, mcause + + + jr x27 + + _jdo55: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 440(x6) + + la x28, _jtest56 + j _jdo56 + + _jtest56: + + csrr x25, mcause + + + jr x27 + + _jdo56: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 448(x6) + + la x28, _jtest57 + j _jdo57 + + _jtest57: + + csrr x25, mcause + + + jr x27 + + _jdo57: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 456(x6) + + la x28, _jtest58 + j _jdo58 + + _jtest58: + + csrr x25, mcause + + + jr x27 + + _jdo58: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 464(x6) + + la x28, _jtest59 + j _jdo59 + + _jtest59: + + csrr x25, mcause + + + jr x27 + + _jdo59: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 472(x6) + + la x28, _jtest60 + j _jdo60 + + _jtest60: + + csrr x25, mcause + + + jr x27 + + _jdo60: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 480(x6) + + la x28, _jtest61 + j _jdo61 + + _jtest61: + + csrr x25, mcause + + + jr x27 + + _jdo61: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 488(x6) + + la x28, _jtest62 + j _jdo62 + + _jtest62: + + csrr x25, mcause + + + jr x27 + + _jdo62: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 496(x6) + + la x28, _jtest63 + j _jdo63 + + _jtest63: + + csrr x25, mcause + + + jr x27 + + _jdo63: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 504(x6) + + la x28, _jtest64 + j _jdo64 + + _jtest64: + + csrr x25, mcause + + + jr x27 + + _jdo64: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 512(x6) + + la x28, _jtest65 + j _jdo65 + + _jtest65: + + csrr x25, mcause + + + jr x27 + + _jdo65: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 520(x6) + + la x28, _jtest66 + j _jdo66 + + _jtest66: + + csrr x25, mcause + + + jr x27 + + _jdo66: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 528(x6) + + la x28, _jtest67 + j _jdo67 + + _jtest67: + + csrr x25, mcause + + + jr x27 + + _jdo67: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 536(x6) + + la x28, _jtest68 + j _jdo68 + + _jtest68: + + csrr x25, mcause + + + jr x27 + + _jdo68: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 544(x6) + + la x28, _jtest69 + j _jdo69 + + _jtest69: + + csrr x25, mcause + + + jr x27 + + _jdo69: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 552(x6) + + la x28, _jtest70 + j _jdo70 + + _jtest70: + + csrr x25, mcause + + + jr x27 + + _jdo70: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 560(x6) + + la x28, _jtest71 + j _jdo71 + + _jtest71: + + csrr x25, mcause + + + jr x27 + + _jdo71: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 568(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + la x28, _jtest72 + j _jdo72 + + _jtest72: + + csrr x25, mcause + + + jr x27 + + _jdo72: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 576(x6) + + la x28, _jtest73 + j _jdo73 + + _jtest73: + + csrr x25, mcause + + + jr x27 + + _jdo73: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 584(x6) + + la x28, _jtest74 + j _jdo74 + + _jtest74: + + csrr x25, mcause + + + jr x27 + + _jdo74: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 592(x6) + + la x28, _jtest75 + j _jdo75 + + _jtest75: + + csrr x25, mcause + + + jr x27 + + _jdo75: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 600(x6) + + la x28, _jtest76 + j _jdo76 + + _jtest76: + + csrr x25, mcause + + + jr x27 + + _jdo76: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 608(x6) + + la x28, _jtest77 + j _jdo77 + + _jtest77: + + csrr x25, mcause + + + jr x27 + + _jdo77: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 616(x6) + + la x28, _jtest78 + j _jdo78 + + _jtest78: + + csrr x25, mcause + + + jr x27 + + _jdo78: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 624(x6) + + la x28, _jtest79 + j _jdo79 + + _jtest79: + + csrr x25, mcause + + + jr x27 + + _jdo79: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 632(x6) + + la x28, _jtest80 + j _jdo80 + + _jtest80: + + csrr x25, mcause + + + jr x27 + + _jdo80: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 640(x6) + + la x28, _jtest81 + j _jdo81 + + _jtest81: + + csrr x25, mcause + + + jr x27 + + _jdo81: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 648(x6) + + la x28, _jtest82 + j _jdo82 + + _jtest82: + + csrr x25, mcause + + + jr x27 + + _jdo82: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 656(x6) + + la x28, _jtest83 + j _jdo83 + + _jtest83: + + csrr x25, mcause + + + jr x27 + + _jdo83: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 664(x6) + + la x28, _jtest84 + j _jdo84 + + _jtest84: + + csrr x25, mcause + + + jr x27 + + _jdo84: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 672(x6) + + la x28, _jtest85 + j _jdo85 + + _jtest85: + + csrr x25, mcause + + + jr x27 + + _jdo85: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 680(x6) + + la x28, _jtest86 + j _jdo86 + + _jtest86: + + csrr x25, mcause + + + jr x27 + + _jdo86: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 688(x6) + + la x28, _jtest87 + j _jdo87 + + _jtest87: + + csrr x25, mcause + + + jr x27 + + _jdo87: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 696(x6) + + la x28, _jtest88 + j _jdo88 + + _jtest88: + + csrr x25, mcause + + + jr x27 + + _jdo88: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 704(x6) + + la x28, _jtest89 + j _jdo89 + + _jtest89: + + csrr x25, mcause + + + jr x27 + + _jdo89: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 712(x6) + + la x28, _jtest90 + j _jdo90 + + _jtest90: + + csrr x25, mcause + + + jr x27 + + _jdo90: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 720(x6) + + la x28, _jtest91 + j _jdo91 + + _jtest91: + + csrr x25, mcause + + + jr x27 + + _jdo91: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 728(x6) + + la x28, _jtest92 + j _jdo92 + + _jtest92: + + csrr x25, mcause + + + jr x27 + + _jdo92: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 736(x6) + + la x28, _jtest93 + j _jdo93 + + _jtest93: + + csrr x25, mcause + + + jr x27 + + _jdo93: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 744(x6) + + la x28, _jtest94 + j _jdo94 + + _jtest94: + + csrr x25, mcause + + + jr x27 + + _jdo94: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 752(x6) + + la x28, _jtest95 + j _jdo95 + + _jtest95: + + csrr x25, mcause + + + jr x27 + + _jdo95: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 760(x6) + + la x28, _jtest96 + j _jdo96 + + _jtest96: + + csrr x25, mcause + + + jr x27 + + _jdo96: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 768(x6) + + la x28, _jtest97 + j _jdo97 + + _jtest97: + + csrr x25, mcause + + + jr x27 + + _jdo97: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 776(x6) + + la x28, _jtest98 + j _jdo98 + + _jtest98: + + csrr x25, mcause + + + jr x27 + + _jdo98: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 784(x6) + + la x28, _jtest99 + j _jdo99 + + _jtest99: + + csrr x25, mcause + + + jr x27 + + _jdo99: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 792(x6) + + la x28, _jtest100 + j _jdo100 + + _jtest100: + + csrr x25, mcause + + + jr x27 + + _jdo100: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 800(x6) + + la x28, _jtest101 + j _jdo101 + + _jtest101: + + csrr x25, mcause + + + jr x27 + + _jdo101: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 808(x6) + + la x28, _jtest102 + j _jdo102 + + _jtest102: + + csrr x25, mcause + + + jr x27 + + _jdo102: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 816(x6) + + la x28, _jtest103 + j _jdo103 + + _jtest103: + + csrr x25, mcause + + + jr x27 + + _jdo103: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 824(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 104, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S new file mode 100644 index 000000000..fb220ab66 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MEDELEG.S @@ -0,0 +1,3675 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MEDELEG.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:30.717084// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + csrr x18, medeleg + csrr x17, medeleg + + _start_0: + + la x1, _j_m_trap_0 + csrw mtvec, x1 + la x1, _j_s_trap_0 + csrw stvec, x1 + + j _j_test_0 + + _j_m_trap_0: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_0 + mret + + _j_s_trap_0: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_0 + sret + + _j_goto_machine_mode_0: + li x30, 1 + ebreak + + _j_test_0: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 0(x6) + + _j_finished_0: + li x30, 0 + + _start_1: + + la x1, _j_m_trap_1 + csrw mtvec, x1 + la x1, _j_s_trap_1 + csrw stvec, x1 + + j _j_test_1 + + _j_m_trap_1: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_1 + mret + + _j_s_trap_1: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_1 + sret + + _j_goto_machine_mode_1: + li x30, 1 + ebreak + + _j_test_1: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 8(x6) + + _j_finished_1: + li x30, 0 + + _start_2: + + la x1, _j_m_trap_2 + csrw mtvec, x1 + la x1, _j_s_trap_2 + csrw stvec, x1 + + j _j_test_2 + + _j_m_trap_2: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_2 + mret + + _j_s_trap_2: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_2 + sret + + _j_goto_machine_mode_2: + li x30, 1 + ebreak + + _j_test_2: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 16(x6) + + j _j_goto_machine_mode_2 + + _j_finished_2: + li x30, 0 + + _start_3: + + la x1, _j_m_trap_3 + csrw mtvec, x1 + la x1, _j_s_trap_3 + csrw stvec, x1 + + j _j_test_3 + + _j_m_trap_3: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_3 + mret + + _j_s_trap_3: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_3 + sret + + _j_goto_machine_mode_3: + li x30, 1 + ebreak + + _j_test_3: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 24(x6) + + j _j_goto_machine_mode_3 + + _j_finished_3: + li x30, 0 + + _start_4: + + la x1, _j_m_trap_4 + csrw mtvec, x1 + la x1, _j_s_trap_4 + csrw stvec, x1 + + j _j_test_4 + + _j_m_trap_4: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_4 + mret + + _j_s_trap_4: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_4 + sret + + _j_goto_machine_mode_4: + li x30, 1 + ebreak + + _j_test_4: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 32(x6) + + j _j_goto_machine_mode_4 + + _j_finished_4: + li x30, 0 + + _start_5: + + la x1, _j_m_trap_5 + csrw mtvec, x1 + la x1, _j_s_trap_5 + csrw stvec, x1 + + j _j_test_5 + + _j_m_trap_5: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_5 + mret + + _j_s_trap_5: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_5 + sret + + _j_goto_machine_mode_5: + li x30, 1 + ebreak + + _j_test_5: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 40(x6) + + j _j_goto_machine_mode_5 + + _j_finished_5: + li x30, 0 + + _start_6: + + la x1, _j_m_trap_6 + csrw mtvec, x1 + la x1, _j_s_trap_6 + csrw stvec, x1 + + j _j_test_6 + + _j_m_trap_6: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_6 + mret + + _j_s_trap_6: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_6 + sret + + _j_goto_machine_mode_6: + li x30, 1 + ecall + + _j_test_6: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + ebreak + + sd x25, 48(x6) + + _j_finished_6: + li x30, 0 + + _start_7: + + la x1, _j_m_trap_7 + csrw mtvec, x1 + la x1, _j_s_trap_7 + csrw stvec, x1 + + j _j_test_7 + + _j_m_trap_7: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_7 + mret + + _j_s_trap_7: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_7 + sret + + _j_goto_machine_mode_7: + li x30, 1 + ecall + + _j_test_7: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ebreak + + sd x25, 56(x6) + + _j_finished_7: + li x30, 0 + + _start_8: + + la x1, _j_m_trap_8 + csrw mtvec, x1 + la x1, _j_s_trap_8 + csrw stvec, x1 + + j _j_test_8 + + _j_m_trap_8: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_8 + mret + + _j_s_trap_8: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_8 + sret + + _j_goto_machine_mode_8: + li x30, 1 + ecall + + _j_test_8: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 64(x6) + + j _j_goto_machine_mode_8 + + _j_finished_8: + li x30, 0 + + _start_9: + + la x1, _j_m_trap_9 + csrw mtvec, x1 + la x1, _j_s_trap_9 + csrw stvec, x1 + + j _j_test_9 + + _j_m_trap_9: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_9 + mret + + _j_s_trap_9: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_9 + sret + + _j_goto_machine_mode_9: + li x30, 1 + ecall + + _j_test_9: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 72(x6) + + j _j_goto_machine_mode_9 + + _j_finished_9: + li x30, 0 + + _start_10: + + la x1, _j_m_trap_10 + csrw mtvec, x1 + la x1, _j_s_trap_10 + csrw stvec, x1 + + j _j_test_10 + + _j_m_trap_10: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_10 + mret + + _j_s_trap_10: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_10 + sret + + _j_goto_machine_mode_10: + li x30, 1 + ecall + + _j_test_10: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 80(x6) + + j _j_goto_machine_mode_10 + + _j_finished_10: + li x30, 0 + + _start_11: + + la x1, _j_m_trap_11 + csrw mtvec, x1 + la x1, _j_s_trap_11 + csrw stvec, x1 + + j _j_test_11 + + _j_m_trap_11: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_11 + mret + + _j_s_trap_11: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_11 + sret + + _j_goto_machine_mode_11: + li x30, 1 + ecall + + _j_test_11: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 88(x6) + + j _j_goto_machine_mode_11 + + _j_finished_11: + li x30, 0 + + _start_12: + + la x1, _j_m_trap_12 + csrw mtvec, x1 + la x1, _j_s_trap_12 + csrw stvec, x1 + + j _j_test_12 + + _j_m_trap_12: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_12 + mret + + _j_s_trap_12: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_12 + sret + + _j_goto_machine_mode_12: + li x30, 1 + ebreak + + _j_test_12: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 96(x6) + + _j_finished_12: + li x30, 0 + + _start_13: + + la x1, _j_m_trap_13 + csrw mtvec, x1 + la x1, _j_s_trap_13 + csrw stvec, x1 + + j _j_test_13 + + _j_m_trap_13: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_13 + mret + + _j_s_trap_13: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_13 + sret + + _j_goto_machine_mode_13: + li x30, 1 + ebreak + + _j_test_13: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 104(x6) + + _j_finished_13: + li x30, 0 + + _start_14: + + la x1, _j_m_trap_14 + csrw mtvec, x1 + la x1, _j_s_trap_14 + csrw stvec, x1 + + j _j_test_14 + + _j_m_trap_14: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_14 + mret + + _j_s_trap_14: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_14 + sret + + _j_goto_machine_mode_14: + li x30, 1 + ebreak + + _j_test_14: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 112(x6) + + j _j_goto_machine_mode_14 + + _j_finished_14: + li x30, 0 + + _start_15: + + la x1, _j_m_trap_15 + csrw mtvec, x1 + la x1, _j_s_trap_15 + csrw stvec, x1 + + j _j_test_15 + + _j_m_trap_15: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_15 + mret + + _j_s_trap_15: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_15 + sret + + _j_goto_machine_mode_15: + li x30, 1 + ebreak + + _j_test_15: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 120(x6) + + j _j_goto_machine_mode_15 + + _j_finished_15: + li x30, 0 + + _start_16: + + la x1, _j_m_trap_16 + csrw mtvec, x1 + la x1, _j_s_trap_16 + csrw stvec, x1 + + j _j_test_16 + + _j_m_trap_16: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_16 + mret + + _j_s_trap_16: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_16 + sret + + _j_goto_machine_mode_16: + li x30, 1 + ebreak + + _j_test_16: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 128(x6) + + j _j_goto_machine_mode_16 + + _j_finished_16: + li x30, 0 + + _start_17: + + la x1, _j_m_trap_17 + csrw mtvec, x1 + la x1, _j_s_trap_17 + csrw stvec, x1 + + j _j_test_17 + + _j_m_trap_17: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_17 + mret + + _j_s_trap_17: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_17 + sret + + _j_goto_machine_mode_17: + li x30, 1 + ebreak + + _j_test_17: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 136(x6) + + j _j_goto_machine_mode_17 + + _j_finished_17: + li x30, 0 + + _start_18: + + la x1, _j_m_trap_18 + csrw mtvec, x1 + la x1, _j_s_trap_18 + csrw stvec, x1 + + j _j_test_18 + + _j_m_trap_18: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_18 + mret + + _j_s_trap_18: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_18 + sret + + _j_goto_machine_mode_18: + li x30, 1 + ebreak + + _j_test_18: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 144(x6) + + _j_finished_18: + li x30, 0 + + _start_19: + + la x1, _j_m_trap_19 + csrw mtvec, x1 + la x1, _j_s_trap_19 + csrw stvec, x1 + + j _j_test_19 + + _j_m_trap_19: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_19 + mret + + _j_s_trap_19: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_19 + sret + + _j_goto_machine_mode_19: + li x30, 1 + ebreak + + _j_test_19: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 152(x6) + + _j_finished_19: + li x30, 0 + + _start_20: + + la x1, _j_m_trap_20 + csrw mtvec, x1 + la x1, _j_s_trap_20 + csrw stvec, x1 + + j _j_test_20 + + _j_m_trap_20: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_20 + mret + + _j_s_trap_20: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_20 + sret + + _j_goto_machine_mode_20: + li x30, 1 + ebreak + + _j_test_20: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 160(x6) + + j _j_goto_machine_mode_20 + + _j_finished_20: + li x30, 0 + + _start_21: + + la x1, _j_m_trap_21 + csrw mtvec, x1 + la x1, _j_s_trap_21 + csrw stvec, x1 + + j _j_test_21 + + _j_m_trap_21: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_21 + mret + + _j_s_trap_21: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_21 + sret + + _j_goto_machine_mode_21: + li x30, 1 + ebreak + + _j_test_21: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 168(x6) + + j _j_goto_machine_mode_21 + + _j_finished_21: + li x30, 0 + + _start_22: + + la x1, _j_m_trap_22 + csrw mtvec, x1 + la x1, _j_s_trap_22 + csrw stvec, x1 + + j _j_test_22 + + _j_m_trap_22: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_22 + mret + + _j_s_trap_22: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_22 + sret + + _j_goto_machine_mode_22: + li x30, 1 + ebreak + + _j_test_22: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 176(x6) + + j _j_goto_machine_mode_22 + + _j_finished_22: + li x30, 0 + + _start_23: + + la x1, _j_m_trap_23 + csrw mtvec, x1 + la x1, _j_s_trap_23 + csrw stvec, x1 + + j _j_test_23 + + _j_m_trap_23: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_23 + mret + + _j_s_trap_23: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_23 + sret + + _j_goto_machine_mode_23: + li x30, 1 + ebreak + + _j_test_23: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 184(x6) + + j _j_goto_machine_mode_23 + + _j_finished_23: + li x30, 0 + + _start_24: + + la x1, _j_m_trap_24 + csrw mtvec, x1 + la x1, _j_s_trap_24 + csrw stvec, x1 + + j _j_test_24 + + _j_m_trap_24: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_24 + mret + + _j_s_trap_24: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_24 + sret + + _j_goto_machine_mode_24: + li x30, 1 + ebreak + + _j_test_24: + + li x25, 0xDEADBEA7 + + + li x1, 2048 + csrw medeleg, x1 + + + ecall + + sd x25, 192(x6) + + _j_finished_24: + li x30, 0 + + _start_25: + + la x1, _j_m_trap_25 + csrw mtvec, x1 + la x1, _j_s_trap_25 + csrw stvec, x1 + + j _j_test_25 + + _j_m_trap_25: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_25 + mret + + _j_s_trap_25: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_25 + sret + + _j_goto_machine_mode_25: + li x30, 1 + ebreak + + _j_test_25: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ecall + + sd x25, 200(x6) + + _j_finished_25: + li x30, 0 + + _start_26: + + la x1, _j_m_trap_26 + csrw mtvec, x1 + la x1, _j_s_trap_26 + csrw stvec, x1 + + j _j_test_26 + + _j_m_trap_26: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_26 + mret + + _j_s_trap_26: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_26 + sret + + _j_goto_machine_mode_26: + li x30, 1 + ebreak + + _j_test_26: + + li x25, 0xDEADBEA7 + + + li x1, 512 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 208(x6) + + j _j_goto_machine_mode_26 + + _j_finished_26: + li x30, 0 + + _start_27: + + la x1, _j_m_trap_27 + csrw mtvec, x1 + la x1, _j_s_trap_27 + csrw stvec, x1 + + j _j_test_27 + + _j_m_trap_27: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_27 + mret + + _j_s_trap_27: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_27 + sret + + _j_goto_machine_mode_27: + li x30, 1 + ebreak + + _j_test_27: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 216(x6) + + j _j_goto_machine_mode_27 + + _j_finished_27: + li x30, 0 + + _start_28: + + la x1, _j_m_trap_28 + csrw mtvec, x1 + la x1, _j_s_trap_28 + csrw stvec, x1 + + j _j_test_28 + + _j_m_trap_28: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_28 + mret + + _j_s_trap_28: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_28 + sret + + _j_goto_machine_mode_28: + li x30, 1 + ebreak + + _j_test_28: + + li x25, 0xDEADBEA7 + + + li x1, 256 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 224(x6) + + j _j_goto_machine_mode_28 + + _j_finished_28: + li x30, 0 + + _start_29: + + la x1, _j_m_trap_29 + csrw mtvec, x1 + la x1, _j_s_trap_29 + csrw stvec, x1 + + j _j_test_29 + + _j_m_trap_29: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_29 + mret + + _j_s_trap_29: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_29 + sret + + _j_goto_machine_mode_29: + li x30, 1 + ebreak + + _j_test_29: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 232(x6) + + j _j_goto_machine_mode_29 + + _j_finished_29: + li x30, 0 + + _start_30: + + la x1, _j_m_trap_30 + csrw mtvec, x1 + la x1, _j_s_trap_30 + csrw stvec, x1 + + j _j_test_30 + + _j_m_trap_30: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_30 + mret + + _j_s_trap_30: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_30 + sret + + _j_goto_machine_mode_30: + li x30, 1 + ebreak + + _j_test_30: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 240(x6) + + _j_finished_30: + li x30, 0 + + _start_31: + + la x1, _j_m_trap_31 + csrw mtvec, x1 + la x1, _j_s_trap_31 + csrw stvec, x1 + + j _j_test_31 + + _j_m_trap_31: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_31 + mret + + _j_s_trap_31: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_31 + sret + + _j_goto_machine_mode_31: + li x30, 1 + ebreak + + _j_test_31: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + .fill 1, 4, 0 + + + sd x25, 248(x6) + + _j_finished_31: + li x30, 0 + + _start_32: + + la x1, _j_m_trap_32 + csrw mtvec, x1 + la x1, _j_s_trap_32 + csrw stvec, x1 + + j _j_test_32 + + _j_m_trap_32: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_32 + mret + + _j_s_trap_32: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_32 + sret + + _j_goto_machine_mode_32: + li x30, 1 + ebreak + + _j_test_32: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 256(x6) + + j _j_goto_machine_mode_32 + + _j_finished_32: + li x30, 0 + + _start_33: + + la x1, _j_m_trap_33 + csrw mtvec, x1 + la x1, _j_s_trap_33 + csrw stvec, x1 + + j _j_test_33 + + _j_m_trap_33: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_33 + mret + + _j_s_trap_33: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_33 + sret + + _j_goto_machine_mode_33: + li x30, 1 + ebreak + + _j_test_33: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + .fill 1, 4, 0 + + + sd x25, 264(x6) + + j _j_goto_machine_mode_33 + + _j_finished_33: + li x30, 0 + + _start_34: + + la x1, _j_m_trap_34 + csrw mtvec, x1 + la x1, _j_s_trap_34 + csrw stvec, x1 + + j _j_test_34 + + _j_m_trap_34: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_34 + mret + + _j_s_trap_34: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_34 + sret + + _j_goto_machine_mode_34: + li x30, 1 + ebreak + + _j_test_34: + + li x25, 0xDEADBEA7 + + + li x1, 4 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 272(x6) + + j _j_goto_machine_mode_34 + + _j_finished_34: + li x30, 0 + + _start_35: + + la x1, _j_m_trap_35 + csrw mtvec, x1 + la x1, _j_s_trap_35 + csrw stvec, x1 + + j _j_test_35 + + _j_m_trap_35: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_35 + mret + + _j_s_trap_35: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_35 + sret + + _j_goto_machine_mode_35: + li x30, 1 + ebreak + + _j_test_35: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + .fill 1, 4, 0 + + + sd x25, 280(x6) + + j _j_goto_machine_mode_35 + + _j_finished_35: + li x30, 0 + + _start_36: + + la x1, _j_m_trap_36 + csrw mtvec, x1 + la x1, _j_s_trap_36 + csrw stvec, x1 + + j _j_test_36 + + _j_m_trap_36: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_36 + mret + + _j_s_trap_36: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_36 + sret + + _j_goto_machine_mode_36: + li x30, 1 + ecall + + _j_test_36: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + ebreak + + sd x25, 288(x6) + + _j_finished_36: + li x30, 0 + + _start_37: + + la x1, _j_m_trap_37 + csrw mtvec, x1 + la x1, _j_s_trap_37 + csrw stvec, x1 + + j _j_test_37 + + _j_m_trap_37: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_37 + mret + + _j_s_trap_37: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_37 + sret + + _j_goto_machine_mode_37: + li x30, 1 + ecall + + _j_test_37: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ebreak + + sd x25, 296(x6) + + _j_finished_37: + li x30, 0 + + _start_38: + + la x1, _j_m_trap_38 + csrw mtvec, x1 + la x1, _j_s_trap_38 + csrw stvec, x1 + + j _j_test_38 + + _j_m_trap_38: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_38 + mret + + _j_s_trap_38: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_38 + sret + + _j_goto_machine_mode_38: + li x30, 1 + ecall + + _j_test_38: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 304(x6) + + j _j_goto_machine_mode_38 + + _j_finished_38: + li x30, 0 + + _start_39: + + la x1, _j_m_trap_39 + csrw mtvec, x1 + la x1, _j_s_trap_39 + csrw stvec, x1 + + j _j_test_39 + + _j_m_trap_39: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_39 + mret + + _j_s_trap_39: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_39 + sret + + _j_goto_machine_mode_39: + li x30, 1 + ecall + + _j_test_39: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ebreak + + sd x25, 312(x6) + + j _j_goto_machine_mode_39 + + _j_finished_39: + li x30, 0 + + _start_40: + + la x1, _j_m_trap_40 + csrw mtvec, x1 + la x1, _j_s_trap_40 + csrw stvec, x1 + + j _j_test_40 + + _j_m_trap_40: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_40 + mret + + _j_s_trap_40: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_40 + sret + + _j_goto_machine_mode_40: + li x30, 1 + ecall + + _j_test_40: + + li x25, 0xDEADBEA7 + + + li x1, 8 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 320(x6) + + j _j_goto_machine_mode_40 + + _j_finished_40: + li x30, 0 + + _start_41: + + la x1, _j_m_trap_41 + csrw mtvec, x1 + la x1, _j_s_trap_41 + csrw stvec, x1 + + j _j_test_41 + + _j_m_trap_41: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_41 + mret + + _j_s_trap_41: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_41 + sret + + _j_goto_machine_mode_41: + li x30, 1 + ecall + + _j_test_41: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ebreak + + sd x25, 328(x6) + + j _j_goto_machine_mode_41 + + _j_finished_41: + li x30, 0 + + _start_42: + + la x1, _j_m_trap_42 + csrw mtvec, x1 + la x1, _j_s_trap_42 + csrw stvec, x1 + + j _j_test_42 + + _j_m_trap_42: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_42 + mret + + _j_s_trap_42: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_42 + sret + + _j_goto_machine_mode_42: + li x30, 1 + ebreak + + _j_test_42: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 336(x6) + + _j_finished_42: + li x30, 0 + + _start_43: + + la x1, _j_m_trap_43 + csrw mtvec, x1 + la x1, _j_s_trap_43 + csrw stvec, x1 + + j _j_test_43 + + _j_m_trap_43: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_43 + mret + + _j_s_trap_43: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_43 + sret + + _j_goto_machine_mode_43: + li x30, 1 + ebreak + + _j_test_43: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + lw x0, 11(x0) + + + sd x25, 344(x6) + + _j_finished_43: + li x30, 0 + + _start_44: + + la x1, _j_m_trap_44 + csrw mtvec, x1 + la x1, _j_s_trap_44 + csrw stvec, x1 + + j _j_test_44 + + _j_m_trap_44: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_44 + mret + + _j_s_trap_44: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_44 + sret + + _j_goto_machine_mode_44: + li x30, 1 + ebreak + + _j_test_44: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 352(x6) + + j _j_goto_machine_mode_44 + + _j_finished_44: + li x30, 0 + + _start_45: + + la x1, _j_m_trap_45 + csrw mtvec, x1 + la x1, _j_s_trap_45 + csrw stvec, x1 + + j _j_test_45 + + _j_m_trap_45: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_45 + mret + + _j_s_trap_45: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_45 + sret + + _j_goto_machine_mode_45: + li x30, 1 + ebreak + + _j_test_45: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + lw x0, 11(x0) + + + sd x25, 360(x6) + + j _j_goto_machine_mode_45 + + _j_finished_45: + li x30, 0 + + _start_46: + + la x1, _j_m_trap_46 + csrw mtvec, x1 + la x1, _j_s_trap_46 + csrw stvec, x1 + + j _j_test_46 + + _j_m_trap_46: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_46 + mret + + _j_s_trap_46: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_46 + sret + + _j_goto_machine_mode_46: + li x30, 1 + ebreak + + _j_test_46: + + li x25, 0xDEADBEA7 + + + li x1, 16 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 368(x6) + + j _j_goto_machine_mode_46 + + _j_finished_46: + li x30, 0 + + _start_47: + + la x1, _j_m_trap_47 + csrw mtvec, x1 + la x1, _j_s_trap_47 + csrw stvec, x1 + + j _j_test_47 + + _j_m_trap_47: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_47 + mret + + _j_s_trap_47: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_47 + sret + + _j_goto_machine_mode_47: + li x30, 1 + ebreak + + _j_test_47: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + lw x0, 11(x0) + + + sd x25, 376(x6) + + j _j_goto_machine_mode_47 + + _j_finished_47: + li x30, 0 + + _start_48: + + la x1, _j_m_trap_48 + csrw mtvec, x1 + la x1, _j_s_trap_48 + csrw stvec, x1 + + j _j_test_48 + + _j_m_trap_48: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_48 + mret + + _j_s_trap_48: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_48 + sret + + _j_goto_machine_mode_48: + li x30, 1 + ebreak + + _j_test_48: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 384(x6) + + _j_finished_48: + li x30, 0 + + _start_49: + + la x1, _j_m_trap_49 + csrw mtvec, x1 + la x1, _j_s_trap_49 + csrw stvec, x1 + + j _j_test_49 + + _j_m_trap_49: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_49 + mret + + _j_s_trap_49: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_49 + sret + + _j_goto_machine_mode_49: + li x30, 1 + ebreak + + _j_test_49: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + sw x0, 11(x0) + + + sd x25, 392(x6) + + _j_finished_49: + li x30, 0 + + _start_50: + + la x1, _j_m_trap_50 + csrw mtvec, x1 + la x1, _j_s_trap_50 + csrw stvec, x1 + + j _j_test_50 + + _j_m_trap_50: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_50 + mret + + _j_s_trap_50: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_50 + sret + + _j_goto_machine_mode_50: + li x30, 1 + ebreak + + _j_test_50: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 400(x6) + + j _j_goto_machine_mode_50 + + _j_finished_50: + li x30, 0 + + _start_51: + + la x1, _j_m_trap_51 + csrw mtvec, x1 + la x1, _j_s_trap_51 + csrw stvec, x1 + + j _j_test_51 + + _j_m_trap_51: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_51 + mret + + _j_s_trap_51: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_51 + sret + + _j_goto_machine_mode_51: + li x30, 1 + ebreak + + _j_test_51: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + + sw x0, 11(x0) + + + sd x25, 408(x6) + + j _j_goto_machine_mode_51 + + _j_finished_51: + li x30, 0 + + _start_52: + + la x1, _j_m_trap_52 + csrw mtvec, x1 + la x1, _j_s_trap_52 + csrw stvec, x1 + + j _j_test_52 + + _j_m_trap_52: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_52 + mret + + _j_s_trap_52: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_52 + sret + + _j_goto_machine_mode_52: + li x30, 1 + ebreak + + _j_test_52: + + li x25, 0xDEADBEA7 + + + li x1, 64 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 416(x6) + + j _j_goto_machine_mode_52 + + _j_finished_52: + li x30, 0 + + _start_53: + + la x1, _j_m_trap_53 + csrw mtvec, x1 + la x1, _j_s_trap_53 + csrw stvec, x1 + + j _j_test_53 + + _j_m_trap_53: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_53 + mret + + _j_s_trap_53: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_53 + sret + + _j_goto_machine_mode_53: + li x30, 1 + ebreak + + _j_test_53: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + + sw x0, 11(x0) + + + sd x25, 424(x6) + + j _j_goto_machine_mode_53 + + _j_finished_53: + li x30, 0 + + _start_54: + + la x1, _j_m_trap_54 + csrw mtvec, x1 + la x1, _j_s_trap_54 + csrw stvec, x1 + + j _j_test_54 + + _j_m_trap_54: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_54 + mret + + _j_s_trap_54: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_54 + sret + + _j_goto_machine_mode_54: + li x30, 1 + ebreak + + _j_test_54: + + li x25, 0xDEADBEA7 + + + li x1, 2048 + csrw medeleg, x1 + + + ecall + + sd x25, 432(x6) + + _j_finished_54: + li x30, 0 + + _start_55: + + la x1, _j_m_trap_55 + csrw mtvec, x1 + la x1, _j_s_trap_55 + csrw stvec, x1 + + j _j_test_55 + + _j_m_trap_55: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_55 + mret + + _j_s_trap_55: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_55 + sret + + _j_goto_machine_mode_55: + li x30, 1 + ebreak + + _j_test_55: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + ecall + + sd x25, 440(x6) + + _j_finished_55: + li x30, 0 + + _start_56: + + la x1, _j_m_trap_56 + csrw mtvec, x1 + la x1, _j_s_trap_56 + csrw stvec, x1 + + j _j_test_56 + + _j_m_trap_56: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_56 + mret + + _j_s_trap_56: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_56 + sret + + _j_goto_machine_mode_56: + li x30, 1 + ebreak + + _j_test_56: + + li x25, 0xDEADBEA7 + + + li x1, 512 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 448(x6) + + j _j_goto_machine_mode_56 + + _j_finished_56: + li x30, 0 + + _start_57: + + la x1, _j_m_trap_57 + csrw mtvec, x1 + la x1, _j_s_trap_57 + csrw stvec, x1 + + j _j_test_57 + + _j_m_trap_57: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_57 + mret + + _j_s_trap_57: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_57 + sret + + _j_goto_machine_mode_57: + li x30, 1 + ebreak + + _j_test_57: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in s mode... + ecall + + sd x25, 456(x6) + + j _j_goto_machine_mode_57 + + _j_finished_57: + li x30, 0 + + _start_58: + + la x1, _j_m_trap_58 + csrw mtvec, x1 + la x1, _j_s_trap_58 + csrw stvec, x1 + + j _j_test_58 + + _j_m_trap_58: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_58 + mret + + _j_s_trap_58: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_58 + sret + + _j_goto_machine_mode_58: + li x30, 1 + ebreak + + _j_test_58: + + li x25, 0xDEADBEA7 + + + li x1, 256 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 464(x6) + + j _j_goto_machine_mode_58 + + _j_finished_58: + li x30, 0 + + _start_59: + + la x1, _j_m_trap_59 + csrw mtvec, x1 + la x1, _j_s_trap_59 + csrw stvec, x1 + + j _j_test_59 + + _j_m_trap_59: + + li x25, 3 + + csrr x1, mepc + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_finished_59 + mret + + _j_s_trap_59: + + li x25, 1 + + csrr x1, sepc + addi x1, x1, 4 + csrrw x0, sepc, x1 + bnez x30, _j_goto_machine_mode_59 + sret + + _j_goto_machine_mode_59: + li x30, 1 + ebreak + + _j_test_59: + + li x25, 0xDEADBEA7 + + + li x1, 0 + csrw medeleg, x1 + + + + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0000000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the ret instruction + csrrw x27, mepc, x1 + mret + + # From m, we're now in u mode... + ecall + + sd x25, 472(x6) + + j _j_goto_machine_mode_59 + + _j_finished_59: + li x30, 0 + + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x17 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 60, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S new file mode 100644 index 000000000..0db38c542 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MHARTID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MHARTID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.358935// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 0 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 3 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 3 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 31 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 0 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 20 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 28 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 28 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 30 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 7 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 7 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 31 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 0 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 9 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 9 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 1 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 10 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 10 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 20 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 20 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 30 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 15 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 15 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 31 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 16 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 16 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 19 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 27 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4361594610609017651) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 27 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 26 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9179397419557419674) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 2 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(11601989081396086434) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrw x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrwi x0, mhartid, 25 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrs x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrc x0, mhartid, x13 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrsi x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(8781402536572756665) + csrrw x11, mhartid, x0 + csrrci x0, mhartid, 8 + csrrwi x12, mhartid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S new file mode 100644 index 000000000..851c78db8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIMPID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MIMPID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.364454// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 0 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 3 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 3 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 31 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 0 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 20 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 28 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 28 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 30 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 7 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 7 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 31 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 8 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 8 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 0 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 9 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 9 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 1 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 10 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 10 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 2 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 20 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 20 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 30 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 15 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 15 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 31 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 16 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 16 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 23 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 22 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4592754222995915383) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 22 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 19 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 25 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4963089653811146067) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 25 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 26 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 6 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1500347522225688698) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 6 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrw x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrwi x0, mimpid, 21 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrs x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrc x0, mimpid, x13 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrsi x0, mimpid, 19 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1036740896647669429) + csrrw x11, mimpid, x0 + csrrci x0, mimpid, 19 + csrrwi x12, mimpid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S new file mode 100644 index 000000000..c9353e289 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MSTATUS.S @@ -0,0 +1,433 @@ +/////////////////////////////////////////// +// +// /imperas-riscv-tests/riscv-test-suite/rv64d/src/WALLY-MSTATUS-rv64d.S +// +// Generated by kmacsaigoren@hmc.edu +// Created on 2021-05-24 13:03:13.519323 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + + + +###################################################################### +# Notes: +# +# The following bitfeilds of mstatus are left untested in this file: +# (as of 25 May 2021) +# +# SXL, UXL (unsupported, hardware depends on XLEN) +# MBE, SBE, UBE (unsupported, endianness is constant) +# TSR, TW, TVM, MXR +# XS (extra extensions not supported) +# MPRV and SUM will be tested as part of the mmu +####################################################################### + + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + +########################### +# Test Code +########################### + +# I sectioned each test into smaller 'functions' with labels to help organize +# and make the code a little more readable + +xs_test: + # test hardwiring of xs to zero + csrr x8, mstatus + li x5, 3 # load mask bits into x5 + slli x5, x5, 15 + jal checkBits + # try to write 11 to xs bits to test hardwiring to zero + li x5, 3 + slli x5, x5, 15 + csrs mstatus, x5 + jal checkBits + + li x7, 1 + slli x7, x7, 5 # mask out F_SUPPORTED bit + csrr x5, misa + and x5, x5, x7 + bnez x5, float_supported + j float_unsupported + + +float_supported: + # *** KMG 6 July 2021: This test DOES NOT satisfactorily test the fs bit, for now it just chekcs that the initial value is zero + # and that it can be written but not much else. + # floating point supported, test, fs, sd bits + li x5, 3 + slli x5, x5, 13 # load fs mask bits into x5 + jal checkBits # should be zero since, even though float is supported, the unit hasn't been turned on *** is this true? + jal checkSD + # force fs to be 11, check SD == 1 + li x5, 3 + slli x5, x5, 13 # load fs mask bits into x5 + csrs mstatus, x5 + jal checkSD + j test_gpio + + +float_unsupported: + # write the same things to memory as if f was supported + + sw x0, 0(x6) # initial FS value is zero + li x5, 0xD5 + sw x5, 4(x6) # sd = 0 + li x5, 0x5D + sw x5, 8(x6) # sd = 1 + addi x6, x6, 12 + + +test_gpio: + # Test MIE bits with GPIO interrupt + # set trap handler for GPIO interrupt + la x5, GPIOTrapHandler + csrw mtvec, x5 + # load interrupt complete flag into x10 + li x10, 0 + # x7 holds 0x6410 if we go through an interrupt and 0x0146 if not. + li x7, 0x0146 + jal configPLIC + jal configGPIO + # set mie + li x5, 0x800 + csrs mie, x5 + # delegate interrupts to machine mode + li x5, 0xD00 + csrc mideleg, x5 + # set MIE bit + li x5, 8 + csrs mstatus, x5 + # Cause GPIO interrupt + li x5, 0x10060000 + li x28, 0x00080000 + sw x28, 0x0C(x5) + # wait for GPIO interrupt to finish. + 2: beq x0,x10,2b + + + +test_gpio_disabled: + # Test MIE bit with GPIO interrupt + # set trap handler for GPIO interrupt + la x5, GPIOTrapHandler + csrw mtvec, x5 + # load interrupt complete flag into x10 + li x10, 0 + # x7 holds 0x6410 if we go through an interrupt and 0x0146 if not. + li x7, 0x0146 + # clear MIE bit + li x5, 8 + csrc mstatus, x5 + # Cause GPIO interrupt (shouldn't happen) + li x5, 0x10060000 + li x28, 0x00080000 + sw x28, 0x0C(x5) + # Dont need to wait for handler to work since interrupt doesnt happen. + sw x7, 0(x6) + addi x6, x6, 4 + + +priv_stack_testM: + # test the privilege stack using ecall. + # set trap handler(s) + la x5, stackTrapHandlerM + csrw mtvec, x5 + # begin in machine mode. + csrr x28, mstatus + # cause m mode exception. + ecall + + + +priv_stack_testS: + # test the privilege stack using ecall, handling trap in S mode + li x5, 1 + slli x5, x5, 9 # mask out ecall_S_mode for medeleg + csrs medeleg, x5 # delegate traps to S Mode + # set trap handler(s) + la x5, stackTrapHandlerS + csrw stvec, x5 + jal go_supervisor_mode + csrr x28, sstatus + # cause s mode exception. + ecall + + j done + + +######################################### +# Functions/helpers +######################################### + + +checkBits: + # when we load the mask bits into x5, this function stores the masked mstatus to the output + csrr x8, mstatus + and x5, x5, x8 + sw x5, 0(x6) + addi x6, x6, 4 + li x5, 0 + ret + +checkBitsS: + # same as checkbits, but checks the sstatus csr + csrr x8, sstatus + and x5, x5, x8 + sw x5, 0(x6) + addi x6, x6, 4 + li x5, 0 + ret + + +checkSD: + # checks SD specially because its the first bit, so we don't have to mask. + csrr x8, mstatus + li x5, 0x5D # SD == 1 + bltz x8, sdDirty + li x5, 0xD5 # SD == 0 +sdDirty: + sw x5, 0(x6) + addi x6, x6, 4 + ret + + + + +go_supervisor_mode: + # taken from wally final report spr 2021 + li x28, 3 + slli x28, x28, 11 + csrc mstatus, x28 # clear bits 11 and 12 of mstatus + li x28, 1 + slli x28, x28, 11 + csrs mstatus, x28 # Set bits 11 and 12 of mstatus to 01, meaning + # the previous privilege mode is supervisor mode + auipc x28, 0 # Store the current program counter address in x28 + addi x28, x28, 16 # x28 is now right after the mret instruction + csrw mepc, x28 # Set mepc to the value in x28 + mret # On mret, we go back to the previous privilege mode in + # mstatus (S) and go to the next instruction. + ret # after going into supervisor mode, we need to return from this function + + +configPLIC: + + # priority threshold = 0 + li x5, 0xC200000 + li x28, 0 + sw x28, 0(x5) + # source 3 (GPIO) priority = 6 + li x5, 0xC000000 + li x28, 6 + sw x28, 0x0C(x5) + # source 4 (UART) priority = 7 + li x28, 7 + sw x28, 0x10(x5) + # enable sources 3,4 + li x5, 0x0C002000 + li x28, 0b11000 + sw x28, 0(x5) + ret + + + +configGPIO: + + # enable all inputs + li x5, 0x10060000 + li x28, 0xFFFFFFFF + sw x28, 0x04(x5) + # enable all outputs + sw x28, 0x08(x5) + # enable all rising edge interrupts + sw x28, 0x18(x5) + # set MEIE + li x5, 0x800 + csrs mie, x5 + ret + + +stackTrapHandlerM: + # trap handler for when we use ecall to test the privilege mode stack. + # x28 holds the previous mstatus value + csrr x29, mstatus + li x5, 3 + slli x5, x5, 11 # mask out MPP bits + jal checkBits # mpp should be 11 + + li x5, 1 + slli x5, x5, 8 # mask out spp bits + jal checkBits # spp should be zero. + + li x5, 1 + slli x5, x5, 3 # mask out MIE bit + jal checkBits # MIE should be set to zero + + li x5, 1 + slli x5, x5, 7 # mask out MPIE bit + and x5, x29, x5 + li x7, 1 + slli x7, x7, 3 # mask out previous MIE bit + and x7, x7, x28 + slli x7, x7, 4 # put the bits in the same place + xor x5, x7, x5 # check if theyre the same + sw x5, 0(x6) # should be all zeros. + addi x6, x6, 4 + + li x5, 1 + slli x5, x5, 5 # mask out SPIE bit + and x5, x29, x5 + li x7, 2 # mask out previous SIE bit + and x7, x7, x28 + slli x7, x7, 4 # put the bits in the same place + xor x5, x7, x5 # check if theyre the same + sw x5, 0(x6) # should be all zeros. + addi x6, x6, 4 + + csrr x29, mepc + addi x29, x29, 4 + csrw mepc, x29 + + mret + +stackTrapHandlerS: + # trap handler for when we use ecall to test the privilege mode stack. + # x28 holds the previous sstatus value + csrr x29, sstatus + + li x5, 1 + slli x5, x5, 8 # mask out spp bit + jal checkBitsS # spp should be 1. + + + li x5, 1 + slli x5, x5, 1 # mask out SIE bit + jal checkBitsS # SIE should be set to zero + + li x5, 1 + slli x5, x5, 5 # mask out SPIE bit + and x5, x29, x5 + li x7, 2 # mask out previous SIE bit + and x7, x7, x28 + slli x7, x7, 4 # put the bits in the same place + xor x5, x7, x5 # check if theyre the same + sw x5, 0(x6) # should be all zeros. + addi x6, x6, 4 + + # set return location to AFTER the ecall. + csrr x29, sepc + addi x29, x29, 4 + csrw sepc, x29 + + sret + + + + +GPIOTrapHandler: + + # several 'set low' reads to indicate we've handled the interrupt. + # 0x10: input_val + li x5, 0x10060000 + lw x7, 0x00(x5) + # 0x14: output_val + lw x7, 0x0C(x5) + # 0x18: incoming rise_ip + lw x7, 0x1C(x5) + # 0x1C: serviced rise_ip = 0 + sw x7, 0x1C(x5) + lw x7, 0x1C(x5) + # 0x20: incoming fall_ip + lw x7, 0x24(x5) + # 0x24: serviced fall_ip = 0 + sw x7, 0x24(x5) + lw x7, 0x24(x5) + # 0x28: incoming high_ip + lw x7, 0x2C(x5) + # 0x2C: serviced high_ip = 0 + sw x7, 0x2C(x5) + lw x7, 0x2C(x5) + # 0x30: incoming low_ip + lw x7, 0x34(x5) + + # 0x34: serviced low_ip = 0 + sw x7, 0x34(x5) + lw x7, 0x34(x5) + + + # check PLIC claim register + # (has the side effect of telling the PLIC that this interrupt is being handled) + li x5, 0x0C200004 + lw x7, 0(x5) + + # skip a lot of the GPIO handling because this test doesnt care about the actual input + # and receiving the value from GPIO, we just care about whther the interrupt happened. + li x7, 0x6410 # "gpio" + sw x7, 0(x6) + addi x6, x6, 4 + + # Signal to PLIC that the trap was handled. + li x5, 0x0C200004 + li x7, 3 + sw x7, 0(x5) + + # reset GPIO, show interrupt was handled + li x5, 0x10060000 + li x28, 0x00080000 + sw x28, 0x1C(x5) + + + li x10, 0x76 # random nonzero number to break the bne x0 loop + mret + +done: +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 16, 4, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S new file mode 100644 index 000000000..cef87b732 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MTVEC.S @@ -0,0 +1,1455 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MTVEC.S +// dottolia@hmc.edu +// Created 2021-06-15 11:28:06.476830// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + csrr x19, mtvec + + + li x1, 2 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 0(x6) + + + li x1, 3 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 8(x6) + + + li x1, 2 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 16(x6) + + + li x1, 3 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 24(x6) + + + li x1, 6 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 32(x6) + + + li x1, 7 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 40(x6) + + + li x1, 6 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 48(x6) + + + li x1, 7 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 56(x6) + + + li x1, 10 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 64(x6) + + + li x1, 11 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 72(x6) + + + li x1, 10 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 80(x6) + + + li x1, 11 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 88(x6) + + + li x1, 14 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 96(x6) + + + li x1, 15 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 104(x6) + + + li x1, 14 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 112(x6) + + + li x1, 15 + csrw mtvec, x1 + csrr x25, mtvec + + sd x25, 120(x6) + + csrw mtvec, x19 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_True + + # Machine mode traps + _j_m_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_True + + + _j_m_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_True + mret + + # Supervisor mode traps + _j_s_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_True + + + _j_s_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_True + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_True: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_True + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_True: + j _j_goto_machine_mode_ebreak_True + + _j_goto_machine_mode_ebreak_True: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_True in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_True: + + csrr x18, medeleg + li x9, 0 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0 + csrw mideleg, x9 + + + la x28, _jtest16 + j _jdo16 + + _jtest16: + nop + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 128(x6) + + + la x28, _jtest17 + j _jdo17 + + _jtest17: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 136(x6) + + + la x28, _jtest18 + j _jdo18 + + _jtest18: + nop + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 144(x6) + + + la x28, _jtest19 + j _jdo19 + + _jtest19: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 152(x6) + + + la x28, _jtest20 + j _jdo20 + + _jtest20: + nop + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 160(x6) + + + la x28, _jtest21 + j _jdo21 + + _jtest21: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 168(x6) + + + la x28, _jtest22 + j _jdo22 + + _jtest22: + nop + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 176(x6) + + + la x28, _jtest23 + j _jdo23 + + _jtest23: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 184(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest24 + j _jdo24 + + _jtest24: + nop + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 192(x6) + + + la x28, _jtest25 + j _jdo25 + + _jtest25: + nop + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 200(x6) + + + la x28, _jtest26 + j _jdo26 + + _jtest26: + nop + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 208(x6) + + + la x28, _jtest27 + j _jdo27 + + _jtest27: + nop + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 216(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest28 + j _jdo28 + + _jtest28: + nop + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 224(x6) + + + la x28, _jtest29 + j _jdo29 + + _jtest29: + nop + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 232(x6) + + + la x28, _jtest30 + j _jdo30 + + _jtest30: + nop + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 240(x6) + + + la x28, _jtest31 + j _jdo31 + + _jtest31: + nop + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 248(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_True: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_False + # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_False + + # Machine mode traps + _j_m_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_False + + + _j_m_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_False + mret + + # Supervisor mode traps + _j_s_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_False + + + _j_s_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_False + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_False: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_False + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_False: + j _j_goto_machine_mode_ebreak_False + + _j_goto_machine_mode_ebreak_False: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_False in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_False: + + csrr x18, medeleg + li x9, 0 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0 + csrw mideleg, x9 + + + la x28, _jtest32 + j _jdo32 + + _jtest32: + nop + + jr x27 + + _jdo32: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 256(x6) + + + la x28, _jtest33 + j _jdo33 + + _jtest33: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo33: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 264(x6) + + + la x28, _jtest34 + j _jdo34 + + _jtest34: + nop + + jr x27 + + _jdo34: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 272(x6) + + + la x28, _jtest35 + j _jdo35 + + _jtest35: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo35: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 280(x6) + + + la x28, _jtest36 + j _jdo36 + + _jtest36: + nop + + jr x27 + + _jdo36: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 288(x6) + + + la x28, _jtest37 + j _jdo37 + + _jtest37: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo37: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 296(x6) + + + la x28, _jtest38 + j _jdo38 + + _jtest38: + nop + + jr x27 + + _jdo38: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 304(x6) + + + la x28, _jtest39 + j _jdo39 + + _jtest39: + nop + + li x1, 0x80 + csrrc x0, mie, x1 + + li x1, 0x8 + csrrc x0, mstatus, x1 + + la x18, 0x2004000 + sd x0, 0(x18) + + jr x27 + + _jdo39: + li x25, 0xDEADBEA7 + + li x1, 0x8 + csrrs x0, mstatus, x1 + + la x18, 0x2004000 + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # sd x1, 0(x18) + + li x1, 0x80 + csrrs x0, mie, x1 + + sd x0, 0(x18) + + + sd x25, 312(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest40 + j _jdo40 + + _jtest40: + nop + + jr x27 + + _jdo40: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 320(x6) + + + la x28, _jtest41 + j _jdo41 + + _jtest41: + nop + + jr x27 + + _jdo41: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 328(x6) + + + la x28, _jtest42 + j _jdo42 + + _jtest42: + nop + + jr x27 + + _jdo42: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 336(x6) + + + la x28, _jtest43 + j _jdo43 + + _jtest43: + nop + + jr x27 + + _jdo43: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 344(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest44 + j _jdo44 + + _jtest44: + nop + + jr x27 + + _jdo44: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 352(x6) + + + la x28, _jtest45 + j _jdo45 + + _jtest45: + nop + + jr x27 + + _jdo45: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 360(x6) + + + la x28, _jtest46 + j _jdo46 + + _jtest46: + nop + + jr x27 + + _jdo46: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 368(x6) + + + la x28, _jtest47 + j _jdo47 + + _jtest47: + nop + + jr x27 + + _jdo47: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 376(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_False: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 48, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S new file mode 100644 index 000000000..88578124c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MVENDORID.S @@ -0,0 +1,3778 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-MVENDORID.S +// dottolia@hmc.edu +// Created 2021-06-15 11:27:52.370113// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + # Testcase 0 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest0 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest0: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend0: + + csrrw x0, mtvec, x31 + sd x25, 0(x6) +sd x15, 8(x6) + + # Testcase 2 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest2 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest2: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(0) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 0 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend2: + + csrrw x0, mtvec, x31 + sd x25, 16(x6) +sd x15, 24(x6) + + # Testcase 4 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest4 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest4: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend4: + + csrrw x0, mtvec, x31 + sd x25, 32(x6) +sd x15, 40(x6) + + # Testcase 6 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest6 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest6: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend6: + + csrrw x0, mtvec, x31 + sd x25, 48(x6) +sd x15, 56(x6) + + # Testcase 8 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest8 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest8: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend8: + + csrrw x0, mtvec, x31 + sd x25, 64(x6) +sd x15, 72(x6) + + # Testcase 10 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest10 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest10: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend10: + + csrrw x0, mtvec, x31 + sd x25, 80(x6) +sd x15, 88(x6) + + # Testcase 12 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest12 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest12: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend12: + + csrrw x0, mtvec, x31 + sd x25, 96(x6) +sd x15, 104(x6) + + # Testcase 14 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest14 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest14: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(1) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend14: + + csrrw x0, mtvec, x31 + sd x25, 112(x6) +sd x15, 120(x6) + + # Testcase 16 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest16 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest16: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend16: + + csrrw x0, mtvec, x31 + sd x25, 128(x6) +sd x15, 136(x6) + + # Testcase 18 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest18 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest18: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend18: + + csrrw x0, mtvec, x31 + sd x25, 144(x6) +sd x15, 152(x6) + + # Testcase 20 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest20 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest20: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend20: + + csrrw x0, mtvec, x31 + sd x25, 160(x6) +sd x15, 168(x6) + + # Testcase 22 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest22 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest22: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend22: + + csrrw x0, mtvec, x31 + sd x25, 176(x6) +sd x15, 184(x6) + + # Testcase 24 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest24 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest24: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 3 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend24: + + csrrw x0, mtvec, x31 + sd x25, 192(x6) +sd x15, 200(x6) + + # Testcase 26 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest26 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest26: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 3 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend26: + + csrrw x0, mtvec, x31 + sd x25, 208(x6) +sd x15, 216(x6) + + # Testcase 28 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest28 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest28: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend28: + + csrrw x0, mtvec, x31 + sd x25, 224(x6) +sd x15, 232(x6) + + # Testcase 30 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest30 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest30: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 31 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend30: + + csrrw x0, mtvec, x31 + sd x25, 240(x6) +sd x15, 248(x6) + + # Testcase 32 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest32 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest32: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend32: + + csrrw x0, mtvec, x31 + sd x25, 256(x6) +sd x15, 264(x6) + + # Testcase 34 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest34 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest34: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend34: + + csrrw x0, mtvec, x31 + sd x25, 272(x6) +sd x15, 280(x6) + + # Testcase 36 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest36 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest36: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend36: + + csrrw x0, mtvec, x31 + sd x25, 288(x6) +sd x15, 296(x6) + + # Testcase 38 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest38 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest38: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(31) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend38: + + csrrw x0, mtvec, x31 + sd x25, 304(x6) +sd x15, 312(x6) + + # Testcase 40 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest40 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest40: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend40: + + csrrw x0, mtvec, x31 + sd x25, 320(x6) +sd x15, 328(x6) + + # Testcase 42 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest42 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest42: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 0 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend42: + + csrrw x0, mtvec, x31 + sd x25, 336(x6) +sd x15, 344(x6) + + # Testcase 44 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest44 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest44: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend44: + + csrrw x0, mtvec, x31 + sd x25, 352(x6) +sd x15, 360(x6) + + # Testcase 46 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest46 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest46: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend46: + + csrrw x0, mtvec, x31 + sd x25, 368(x6) +sd x15, 376(x6) + + # Testcase 48 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest48 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest48: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend48: + + csrrw x0, mtvec, x31 + sd x25, 384(x6) +sd x15, 392(x6) + + # Testcase 50 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest50 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest50: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(32) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend50: + + csrrw x0, mtvec, x31 + sd x25, 400(x6) +sd x15, 408(x6) + + # Testcase 52 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest52 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest52: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend52: + + csrrw x0, mtvec, x31 + sd x25, 416(x6) +sd x15, 424(x6) + + # Testcase 54 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest54 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest54: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 20 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend54: + + csrrw x0, mtvec, x31 + sd x25, 432(x6) +sd x15, 440(x6) + + # Testcase 56 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest56 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest56: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend56: + + csrrw x0, mtvec, x31 + sd x25, 448(x6) +sd x15, 456(x6) + + # Testcase 58 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest58 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest58: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend58: + + csrrw x0, mtvec, x31 + sd x25, 464(x6) +sd x15, 472(x6) + + # Testcase 60 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest60 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest60: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 28 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend60: + + csrrw x0, mtvec, x31 + sd x25, 480(x6) +sd x15, 488(x6) + + # Testcase 62 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest62 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest62: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(7082823659048590612) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 28 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend62: + + csrrw x0, mtvec, x31 + sd x25, 496(x6) +sd x15, 504(x6) + + # Testcase 64 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest64 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest64: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend64: + + csrrw x0, mtvec, x31 + sd x25, 512(x6) +sd x15, 520(x6) + + # Testcase 66 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest66 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest66: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 30 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend66: + + csrrw x0, mtvec, x31 + sd x25, 528(x6) +sd x15, 536(x6) + + # Testcase 68 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest68 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest68: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend68: + + csrrw x0, mtvec, x31 + sd x25, 544(x6) +sd x15, 552(x6) + + # Testcase 70 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest70 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest70: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend70: + + csrrw x0, mtvec, x31 + sd x25, 560(x6) +sd x15, 568(x6) + + # Testcase 72 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest72 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest72: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 7 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend72: + + csrrw x0, mtvec, x31 + sd x25, 576(x6) +sd x15, 584(x6) + + # Testcase 74 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest74 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest74: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775806) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 7 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend74: + + csrrw x0, mtvec, x31 + sd x25, 592(x6) +sd x15, 600(x6) + + # Testcase 76 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest76 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest76: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend76: + + csrrw x0, mtvec, x31 + sd x25, 608(x6) +sd x15, 616(x6) + + # Testcase 78 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest78 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest78: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 31 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend78: + + csrrw x0, mtvec, x31 + sd x25, 624(x6) +sd x15, 632(x6) + + # Testcase 80 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest80 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest80: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend80: + + csrrw x0, mtvec, x31 + sd x25, 640(x6) +sd x15, 648(x6) + + # Testcase 82 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest82 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest82: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend82: + + csrrw x0, mtvec, x31 + sd x25, 656(x6) +sd x15, 664(x6) + + # Testcase 84 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest84 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest84: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 8 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend84: + + csrrw x0, mtvec, x31 + sd x25, 672(x6) +sd x15, 680(x6) + + # Testcase 86 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest86 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest86: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775807) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 8 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend86: + + csrrw x0, mtvec, x31 + sd x25, 688(x6) +sd x15, 696(x6) + + # Testcase 88 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest88 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest88: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend88: + + csrrw x0, mtvec, x31 + sd x25, 704(x6) +sd x15, 712(x6) + + # Testcase 90 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest90 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest90: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 0 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend90: + + csrrw x0, mtvec, x31 + sd x25, 720(x6) +sd x15, 728(x6) + + # Testcase 92 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest92 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest92: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend92: + + csrrw x0, mtvec, x31 + sd x25, 736(x6) +sd x15, 744(x6) + + # Testcase 94 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest94 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest94: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend94: + + csrrw x0, mtvec, x31 + sd x25, 752(x6) +sd x15, 760(x6) + + # Testcase 96 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest96 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest96: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 9 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend96: + + csrrw x0, mtvec, x31 + sd x25, 768(x6) +sd x15, 776(x6) + + # Testcase 98 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest98 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest98: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775808) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 9 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend98: + + csrrw x0, mtvec, x31 + sd x25, 784(x6) +sd x15, 792(x6) + + # Testcase 100 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest100 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest100: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend100: + + csrrw x0, mtvec, x31 + sd x25, 800(x6) +sd x15, 808(x6) + + # Testcase 102 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest102 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest102: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend102: + + csrrw x0, mtvec, x31 + sd x25, 816(x6) +sd x15, 824(x6) + + # Testcase 104 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest104 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest104: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend104: + + csrrw x0, mtvec, x31 + sd x25, 832(x6) +sd x15, 840(x6) + + # Testcase 106 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest106 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest106: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend106: + + csrrw x0, mtvec, x31 + sd x25, 848(x6) +sd x15, 856(x6) + + # Testcase 108 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest108 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest108: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 10 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend108: + + csrrw x0, mtvec, x31 + sd x25, 864(x6) +sd x15, 872(x6) + + # Testcase 110 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest110 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest110: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(9223372036854775809) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 10 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend110: + + csrrw x0, mtvec, x31 + sd x25, 880(x6) +sd x15, 888(x6) + + # Testcase 112 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest112 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest112: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend112: + + csrrw x0, mtvec, x31 + sd x25, 896(x6) +sd x15, 904(x6) + + # Testcase 114 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest114 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest114: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 2 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend114: + + csrrw x0, mtvec, x31 + sd x25, 912(x6) +sd x15, 920(x6) + + # Testcase 116 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest116 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest116: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend116: + + csrrw x0, mtvec, x31 + sd x25, 928(x6) +sd x15, 936(x6) + + # Testcase 118 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest118 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest118: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend118: + + csrrw x0, mtvec, x31 + sd x25, 944(x6) +sd x15, 952(x6) + + # Testcase 120 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest120 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest120: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 20 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend120: + + csrrw x0, mtvec, x31 + sd x25, 960(x6) +sd x15, 968(x6) + + # Testcase 122 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest122 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest122: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14079903813871053634) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 20 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend122: + + csrrw x0, mtvec, x31 + sd x25, 976(x6) +sd x15, 984(x6) + + # Testcase 124 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest124 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest124: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend124: + + csrrw x0, mtvec, x31 + sd x25, 992(x6) +sd x15, 1000(x6) + + # Testcase 126 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest126 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest126: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 30 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend126: + + csrrw x0, mtvec, x31 + sd x25, 1008(x6) +sd x15, 1016(x6) + + # Testcase 128 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest128 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest128: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend128: + + csrrw x0, mtvec, x31 + sd x25, 1024(x6) +sd x15, 1032(x6) + + # Testcase 130 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest130 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest130: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend130: + + csrrw x0, mtvec, x31 + sd x25, 1040(x6) +sd x15, 1048(x6) + + # Testcase 132 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest132 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest132: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 15 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend132: + + csrrw x0, mtvec, x31 + sd x25, 1056(x6) +sd x15, 1064(x6) + + # Testcase 134 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest134 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest134: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551614) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 15 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend134: + + csrrw x0, mtvec, x31 + sd x25, 1072(x6) +sd x15, 1080(x6) + + # Testcase 136 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest136 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest136: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend136: + + csrrw x0, mtvec, x31 + sd x25, 1088(x6) +sd x15, 1096(x6) + + # Testcase 138 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest138 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest138: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 31 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend138: + + csrrw x0, mtvec, x31 + sd x25, 1104(x6) +sd x15, 1112(x6) + + # Testcase 140 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest140 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest140: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend140: + + csrrw x0, mtvec, x31 + sd x25, 1120(x6) +sd x15, 1128(x6) + + # Testcase 142 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest142 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest142: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend142: + + csrrw x0, mtvec, x31 + sd x25, 1136(x6) +sd x15, 1144(x6) + + # Testcase 144 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest144 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest144: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend144: + + csrrw x0, mtvec, x31 + sd x25, 1152(x6) +sd x15, 1160(x6) + + # Testcase 146 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest146 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest146: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(18446744073709551615) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend146: + + csrrw x0, mtvec, x31 + sd x25, 1168(x6) +sd x15, 1176(x6) + + # Testcase 148 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest148 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest148: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend148: + + csrrw x0, mtvec, x31 + sd x25, 1184(x6) +sd x15, 1192(x6) + + # Testcase 150 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest150 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest150: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 10 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend150: + + csrrw x0, mtvec, x31 + sd x25, 1200(x6) +sd x15, 1208(x6) + + # Testcase 152 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest152 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest152: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend152: + + csrrw x0, mtvec, x31 + sd x25, 1216(x6) +sd x15, 1224(x6) + + # Testcase 154 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest154 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest154: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend154: + + csrrw x0, mtvec, x31 + sd x25, 1232(x6) +sd x15, 1240(x6) + + # Testcase 156 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest156 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest156: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 18 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend156: + + csrrw x0, mtvec, x31 + sd x25, 1248(x6) +sd x15, 1256(x6) + + # Testcase 158 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest158 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest158: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(2031149994725922250) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 18 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend158: + + csrrw x0, mtvec, x31 + sd x25, 1264(x6) +sd x15, 1272(x6) + + # Testcase 160 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest160 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest160: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend160: + + csrrw x0, mtvec, x31 + sd x25, 1280(x6) +sd x15, 1288(x6) + + # Testcase 162 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest162 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest162: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 14 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend162: + + csrrw x0, mtvec, x31 + sd x25, 1296(x6) +sd x15, 1304(x6) + + # Testcase 164 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest164 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest164: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend164: + + csrrw x0, mtvec, x31 + sd x25, 1312(x6) +sd x15, 1320(x6) + + # Testcase 166 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest166 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest166: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend166: + + csrrw x0, mtvec, x31 + sd x25, 1328(x6) +sd x15, 1336(x6) + + # Testcase 168 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest168 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest168: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend168: + + csrrw x0, mtvec, x31 + sd x25, 1344(x6) +sd x15, 1352(x6) + + # Testcase 170 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest170 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest170: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(17283091644588468686) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 16 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend170: + + csrrw x0, mtvec, x31 + sd x25, 1360(x6) +sd x15, 1368(x6) + + # Testcase 172 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest172 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest172: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend172: + + csrrw x0, mtvec, x31 + sd x25, 1376(x6) +sd x15, 1384(x6) + + # Testcase 174 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest174 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest174: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 25 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend174: + + csrrw x0, mtvec, x31 + sd x25, 1392(x6) +sd x15, 1400(x6) + + # Testcase 176 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest176 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest176: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend176: + + csrrw x0, mtvec, x31 + sd x25, 1408(x6) +sd x15, 1416(x6) + + # Testcase 178 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest178 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest178: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend178: + + csrrw x0, mtvec, x31 + sd x25, 1424(x6) +sd x15, 1432(x6) + + # Testcase 180 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest180 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest180: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 23 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend180: + + csrrw x0, mtvec, x31 + sd x25, 1440(x6) +sd x15, 1448(x6) + + # Testcase 182 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest182 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest182: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(4311727685417310105) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 23 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend182: + + csrrw x0, mtvec, x31 + sd x25, 1456(x6) +sd x15, 1464(x6) + + # Testcase 184 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest184 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest184: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrw x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend184: + + csrrw x0, mtvec, x31 + sd x25, 1472(x6) +sd x15, 1480(x6) + + # Testcase 186 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest186 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest186: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrwi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend186: + + csrrw x0, mtvec, x31 + sd x25, 1488(x6) +sd x15, 1496(x6) + + # Testcase 188 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest188 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest188: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrs x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend188: + + csrrw x0, mtvec, x31 + sd x25, 1504(x6) +sd x15, 1512(x6) + + # Testcase 190 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest190 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest190: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrc x0, mvendorid, x13 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend190: + + csrrw x0, mtvec, x31 + sd x25, 1520(x6) +sd x15, 1528(x6) + + # Testcase 192 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest192 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest192: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrsi x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend192: + + csrrw x0, mtvec, x31 + sd x25, 1536(x6) +sd x15, 1544(x6) + + # Testcase 194 + csrrs x31, mtvec, x0 + + auipc x30, 0 + addi x30, x30, 12 + j _jtest194 + + # Machine trap vector + + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + + mret + + # Actual test + _jtest194: + csrrw x0, mtvec, x30 + + # Start test code + li x25, 0x7BAD + + + li x13, MASK_XLEN(14804136700939100193) + csrrw x11, mvendorid, x0 + csrrci x0, mvendorid, 1 + csrrwi x12, mvendorid, 0 + sub x15, x11, x12 + + + # Finished test. Reset to old mtvec + _jend194: + + csrrw x0, mtvec, x31 + sd x25, 1552(x6) +sd x15, 1560(x6) + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 196, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S new file mode 100644 index 000000000..d509ae896 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SCAUSE.S @@ -0,0 +1,1396 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-SCAUSE.S +// dottolia@hmc.edu +// Created 2021-06-16 16:18:36.397499// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + add x7, x6, x0 + csrr x19, mtvec + + slli a0,a0,0x1f + slli a0,a0,0x1e + slli a0,a0,0x1d + slli a0,a0,0x1c + slli a0,a0,0x1b + slli a0,a0,0x1a + slli a0,a0,0x19 + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak + csrw mtvec, x1 + la x1, _j_s_trap_ebreak + csrw stvec, x1 + la x1, _j_u_trap_ebreak + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak + + # Machine mode traps + _j_m_trap_ebreak: + li x25, 0xBAD00003 + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak + mret + + # Supervisor mode traps + _j_s_trap_ebreak: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak: + j _j_goto_machine_mode_ebreak + + _j_goto_machine_mode_ebreak: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak: + + csrr x18, medeleg + li x9, 0b1111111111110111 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0xffffffff + csrw mideleg, x9 + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + la x28, _jtest0 + j _jdo0 + + _jtest0: + + csrr x25, scause + + + jr x27 + + _jdo0: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 0(x6) + + la x28, _jtest1 + j _jdo1 + + _jtest1: + + csrr x25, scause + + + jr x27 + + _jdo1: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 8(x6) + + la x28, _jtest2 + j _jdo2 + + _jtest2: + + csrr x25, scause + + + jr x27 + + _jdo2: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 16(x6) + + la x28, _jtest3 + j _jdo3 + + _jtest3: + + csrr x25, scause + + + jr x27 + + _jdo3: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 24(x6) + + la x28, _jtest4 + j _jdo4 + + _jtest4: + + csrr x25, scause + + + jr x27 + + _jdo4: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 32(x6) + + la x28, _jtest5 + j _jdo5 + + _jtest5: + + csrr x25, scause + + + jr x27 + + _jdo5: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 40(x6) + + la x28, _jtest6 + j _jdo6 + + _jtest6: + + csrr x25, scause + + + jr x27 + + _jdo6: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 48(x6) + + la x28, _jtest7 + j _jdo7 + + _jtest7: + + csrr x25, scause + + + jr x27 + + _jdo7: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 56(x6) + + la x28, _jtest8 + j _jdo8 + + _jtest8: + + csrr x25, scause + + + jr x27 + + _jdo8: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 64(x6) + + la x28, _jtest9 + j _jdo9 + + _jtest9: + + csrr x25, scause + + + jr x27 + + _jdo9: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 72(x6) + + la x28, _jtest10 + j _jdo10 + + _jtest10: + + csrr x25, scause + + + jr x27 + + _jdo10: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 80(x6) + + la x28, _jtest11 + j _jdo11 + + _jtest11: + + csrr x25, scause + + + jr x27 + + _jdo11: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 88(x6) + + la x28, _jtest12 + j _jdo12 + + _jtest12: + + csrr x25, scause + + + jr x27 + + _jdo12: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 96(x6) + + la x28, _jtest13 + j _jdo13 + + _jtest13: + + csrr x25, scause + + + jr x27 + + _jdo13: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 104(x6) + + la x28, _jtest14 + j _jdo14 + + _jtest14: + + csrr x25, scause + + + jr x27 + + _jdo14: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 112(x6) + + la x28, _jtest15 + j _jdo15 + + _jtest15: + + csrr x25, scause + + + jr x27 + + _jdo15: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 120(x6) + + la x28, _jtest16 + j _jdo16 + + _jtest16: + + csrr x25, scause + + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 128(x6) + + la x28, _jtest17 + j _jdo17 + + _jtest17: + + csrr x25, scause + + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 136(x6) + + la x28, _jtest18 + j _jdo18 + + _jtest18: + + csrr x25, scause + + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 144(x6) + + la x28, _jtest19 + j _jdo19 + + _jtest19: + + csrr x25, scause + + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 152(x6) + + la x28, _jtest20 + j _jdo20 + + _jtest20: + + csrr x25, scause + + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 160(x6) + + la x28, _jtest21 + j _jdo21 + + _jtest21: + + csrr x25, scause + + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 168(x6) + + la x28, _jtest22 + j _jdo22 + + _jtest22: + + csrr x25, scause + + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 176(x6) + + la x28, _jtest23 + j _jdo23 + + _jtest23: + + csrr x25, scause + + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 184(x6) + + la x28, _jtest24 + j _jdo24 + + _jtest24: + + csrr x25, scause + + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 192(x6) + + la x28, _jtest25 + j _jdo25 + + _jtest25: + + csrr x25, scause + + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 200(x6) + + la x28, _jtest26 + j _jdo26 + + _jtest26: + + csrr x25, scause + + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 208(x6) + + la x28, _jtest27 + j _jdo27 + + _jtest27: + + csrr x25, scause + + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 216(x6) + + la x28, _jtest28 + j _jdo28 + + _jtest28: + + csrr x25, scause + + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 224(x6) + + la x28, _jtest29 + j _jdo29 + + _jtest29: + + csrr x25, scause + + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 232(x6) + + la x28, _jtest30 + j _jdo30 + + _jtest30: + + csrr x25, scause + + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 240(x6) + + la x28, _jtest31 + j _jdo31 + + _jtest31: + + csrr x25, scause + + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 248(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + la x28, _jtest32 + j _jdo32 + + _jtest32: + + csrr x25, scause + + + jr x27 + + _jdo32: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 256(x6) + + la x28, _jtest33 + j _jdo33 + + _jtest33: + + csrr x25, scause + + + jr x27 + + _jdo33: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 264(x6) + + la x28, _jtest34 + j _jdo34 + + _jtest34: + + csrr x25, scause + + + jr x27 + + _jdo34: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 272(x6) + + la x28, _jtest35 + j _jdo35 + + _jtest35: + + csrr x25, scause + + + jr x27 + + _jdo35: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 280(x6) + + la x28, _jtest36 + j _jdo36 + + _jtest36: + + csrr x25, scause + + + jr x27 + + _jdo36: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 288(x6) + + la x28, _jtest37 + j _jdo37 + + _jtest37: + + csrr x25, scause + + + jr x27 + + _jdo37: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 296(x6) + + la x28, _jtest38 + j _jdo38 + + _jtest38: + + csrr x25, scause + + + jr x27 + + _jdo38: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 304(x6) + + la x28, _jtest39 + j _jdo39 + + _jtest39: + + csrr x25, scause + + + jr x27 + + _jdo39: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 312(x6) + + la x28, _jtest40 + j _jdo40 + + _jtest40: + + csrr x25, scause + + + jr x27 + + _jdo40: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 320(x6) + + la x28, _jtest41 + j _jdo41 + + _jtest41: + + csrr x25, scause + + + jr x27 + + _jdo41: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 328(x6) + + la x28, _jtest42 + j _jdo42 + + _jtest42: + + csrr x25, scause + + + jr x27 + + _jdo42: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 336(x6) + + la x28, _jtest43 + j _jdo43 + + _jtest43: + + csrr x25, scause + + + jr x27 + + _jdo43: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 344(x6) + + la x28, _jtest44 + j _jdo44 + + _jtest44: + + csrr x25, scause + + + jr x27 + + _jdo44: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 352(x6) + + la x28, _jtest45 + j _jdo45 + + _jtest45: + + csrr x25, scause + + + jr x27 + + _jdo45: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 360(x6) + + la x28, _jtest46 + j _jdo46 + + _jtest46: + + csrr x25, scause + + + jr x27 + + _jdo46: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 368(x6) + + la x28, _jtest47 + j _jdo47 + + _jtest47: + + csrr x25, scause + + + jr x27 + + _jdo47: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 376(x6) + + la x28, _jtest48 + j _jdo48 + + _jtest48: + + csrr x25, scause + + + jr x27 + + _jdo48: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 384(x6) + + la x28, _jtest49 + j _jdo49 + + _jtest49: + + csrr x25, scause + + + jr x27 + + _jdo49: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 392(x6) + + la x28, _jtest50 + j _jdo50 + + _jtest50: + + csrr x25, scause + + + jr x27 + + _jdo50: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 400(x6) + + la x28, _jtest51 + j _jdo51 + + _jtest51: + + csrr x25, scause + + + jr x27 + + _jdo51: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 408(x6) + + la x28, _jtest52 + j _jdo52 + + _jtest52: + + csrr x25, scause + + + jr x27 + + _jdo52: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 416(x6) + + la x28, _jtest53 + j _jdo53 + + _jtest53: + + csrr x25, scause + + + jr x27 + + _jdo53: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 424(x6) + + la x28, _jtest54 + j _jdo54 + + _jtest54: + + csrr x25, scause + + + jr x27 + + _jdo54: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 432(x6) + + la x28, _jtest55 + j _jdo55 + + _jtest55: + + csrr x25, scause + + + jr x27 + + _jdo55: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 440(x6) + + la x28, _jtest56 + j _jdo56 + + _jtest56: + + csrr x25, scause + + + jr x27 + + _jdo56: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 448(x6) + + la x28, _jtest57 + j _jdo57 + + _jtest57: + + csrr x25, scause + + + jr x27 + + _jdo57: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 456(x6) + + la x28, _jtest58 + j _jdo58 + + _jtest58: + + csrr x25, scause + + + jr x27 + + _jdo58: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 464(x6) + + la x28, _jtest59 + j _jdo59 + + _jtest59: + + csrr x25, scause + + + jr x27 + + _jdo59: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 472(x6) + + la x28, _jtest60 + j _jdo60 + + _jtest60: + + csrr x25, scause + + + jr x27 + + _jdo60: + li x25, 0xDEADBEA7 + li gp, 0 + + .fill 1, 4, 0 + + + sd x25, 480(x6) + + la x28, _jtest61 + j _jdo61 + + _jtest61: + + csrr x25, scause + + + jr x27 + + _jdo61: + li x25, 0xDEADBEA7 + li gp, 0 + + lw x0, 11(x0) + + + sd x25, 488(x6) + + la x28, _jtest62 + j _jdo62 + + _jtest62: + + csrr x25, scause + + + jr x27 + + _jdo62: + li x25, 0xDEADBEA7 + li gp, 0 + + sw x0, 11(x0) + + + sd x25, 496(x6) + + la x28, _jtest63 + j _jdo63 + + _jtest63: + + csrr x25, scause + + + jr x27 + + _jdo63: + li x25, 0xDEADBEA7 + li gp, 0 + + ecall + + + sd x25, 504(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 64, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S new file mode 100644 index 000000000..4b7fa07e8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-STVEC.S @@ -0,0 +1,1022 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-STVEC.S +// dottolia@hmc.edu +// Created 2021-06-15 11:28:06.482303// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + csrr x19, stvec + + + li x1, 2 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 0(x6) + + + li x1, 3 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 8(x6) + + + li x1, 2 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 16(x6) + + + li x1, 3 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 24(x6) + + + li x1, 6 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 32(x6) + + + li x1, 7 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 40(x6) + + + li x1, 6 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 48(x6) + + + li x1, 7 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 56(x6) + + + li x1, 10 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 64(x6) + + + li x1, 11 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 72(x6) + + + li x1, 10 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 80(x6) + + + li x1, 11 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 88(x6) + + + li x1, 14 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 96(x6) + + + li x1, 15 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 104(x6) + + + li x1, 14 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 112(x6) + + + li x1, 15 + csrw stvec, x1 + csrr x25, stvec + + sd x25, 120(x6) + + csrw stvec, x19 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_True + addi x1, x1, 1 # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_True + + # Machine mode traps + _j_m_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_True + + + _j_m_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_True + mret + + # Supervisor mode traps + _j_s_trap_ebreak_True: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_True + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_True + + + _j_s_trap_end_ebreak_True: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_True + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_True: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_True + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_True: + j _j_goto_machine_mode_ebreak_True + + _j_goto_machine_mode_ebreak_True: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_True in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_True: + + csrr x18, medeleg + li x9, 0b1111111111110111 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0xffffffff + csrw mideleg, x9 + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest16 + j _jdo16 + + _jtest16: + nop + + jr x27 + + _jdo16: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 128(x6) + + + la x28, _jtest17 + j _jdo17 + + _jtest17: + nop + + jr x27 + + _jdo17: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 136(x6) + + + la x28, _jtest18 + j _jdo18 + + _jtest18: + nop + + jr x27 + + _jdo18: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 144(x6) + + + la x28, _jtest19 + j _jdo19 + + _jtest19: + nop + + jr x27 + + _jdo19: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 152(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest20 + j _jdo20 + + _jtest20: + nop + + jr x27 + + _jdo20: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 160(x6) + + + la x28, _jtest21 + j _jdo21 + + _jtest21: + nop + + jr x27 + + _jdo21: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 168(x6) + + + la x28, _jtest22 + j _jdo22 + + _jtest22: + nop + + jr x27 + + _jdo22: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 176(x6) + + + la x28, _jtest23 + j _jdo23 + + _jtest23: + nop + + jr x27 + + _jdo23: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 184(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_True: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + + # add x7, x6, x0 + csrr x19, mtvec + + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 + + # Set up + la x1, _j_m_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_ebreak_False + # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_ebreak_False + # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_ebreak_False + + # Machine mode traps + _j_m_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_m_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_m_trap_end_ebreak_False + + + _j_m_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_ebreak_False + mret + + # Supervisor mode traps + _j_s_trap_ebreak_False: + + nop + nop + li x25, 0 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 1 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 2 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 3 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 4 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 5 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 6 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 7 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 8 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 9 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 10 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 11 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 12 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 13 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 14 + j _j_s_trap_end_ebreak_False + + nop + nop + li x25, 15 + j _j_s_trap_end_ebreak_False + + + _j_s_trap_end_ebreak_False: + + auipc x27, 0 + addi x27, x27, 12 + jr x28 + + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_ebreak_False + sret + + # Unused: user mode traps are no longer supported + _j_u_trap_ebreak_False: + li x25, 0xBAD00000 + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_ebreak_False + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with ebreak (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_ebreak_False: + j _j_goto_machine_mode_ebreak_False + + _j_goto_machine_mode_ebreak_False: + li x30, 1 # This will cause us to branch to _j_all_end_ebreak_False in the machine trap handler, which we'll get into by invoking... + ebreak # ... this instruction! + + # Run the actual tests! + _j_t_begin_ebreak_False: + + csrr x18, medeleg + li x9, 0b1111111111110111 + csrw medeleg, x9 + + csrr x16, mideleg + li x9, 0xffffffff + csrw mideleg, x9 + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + la x28, _jtest24 + j _jdo24 + + _jtest24: + nop + + jr x27 + + _jdo24: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 192(x6) + + + la x28, _jtest25 + j _jdo25 + + _jtest25: + nop + + jr x27 + + _jdo25: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 200(x6) + + + la x28, _jtest26 + j _jdo26 + + _jtest26: + nop + + jr x27 + + _jdo26: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 208(x6) + + + la x28, _jtest27 + j _jdo27 + + _jtest27: + nop + + jr x27 + + _jdo27: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 216(x6) + + li x1, 0b110000000000 + csrrc x31, mstatus, x1 + li x1, 0b0100000000000 + csrrs x31, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + + + li x1, 0b110000000000 + csrrc x31, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + + + la x28, _jtest28 + j _jdo28 + + _jtest28: + nop + + jr x27 + + _jdo28: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 224(x6) + + + la x28, _jtest29 + j _jdo29 + + _jtest29: + nop + + jr x27 + + _jdo29: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 232(x6) + + + la x28, _jtest30 + j _jdo30 + + _jtest30: + nop + + jr x27 + + _jdo30: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 240(x6) + + + la x28, _jtest31 + j _jdo31 + + _jtest31: + nop + + jr x27 + + _jdo31: + li x25, 0xDEADBEA7 + + ecall + + + sd x25, 248(x6) + + li x30, 1 + li gp, 0 + ebreak + _j_all_end_ebreak_False: + + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 32, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S new file mode 100644 index 000000000..1d651f577 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-UCAUSE.S @@ -0,0 +1,459 @@ +/////////////////////////////////////////// +// ../../../imperas-riscv-tests/riscv-test-suite/rv64p/src/WALLY-UCAUSE.S +// dottolia@hmc.edu +// Created 2021-04-20 15:11:17.438819// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + + csrr x31, mtvec + li x30, 0 + + la x1, _j_m_trap + csrw mtvec, x1 + la x1, _j_s_trap + csrw stvec, x1 + j _j_t_begin + + _j_m_trap: + csrrs x25, mcause, x0 + csrrs x1, mepc, x0 + addi x1, x1, 4 + csrrw x0, mepc, x1 + bnez x30, _j_all_end + mret + + _j_s_trap: + csrrs x25, scause, x0 + csrrs x1, sepc, x0 + addi x1, x1, 4 + csrrw x0, sepc, x1 + sret + + _j_t_begin: + + li x1, 0b110000000000 + csrrc x28, mstatus, x1 + li x1, 0b0000000000000 + csrrs x28, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in u mode... + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend0: + + sd x25, 0(x6) + + li x25, 0x7BAD + + ebreak + + + _jend1: + + sd x25, 8(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend2: + + sd x25, 16(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend3: + + sd x25, 24(x6) + + li x25, 0x7BAD + + ecall + + + _jend4: + + sd x25, 32(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend5: + + sd x25, 40(x6) + + li x25, 0x7BAD + + ebreak + + + _jend6: + + sd x25, 48(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend7: + + sd x25, 56(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend8: + + sd x25, 64(x6) + + li x25, 0x7BAD + + ecall + + + _jend9: + + sd x25, 72(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend10: + + sd x25, 80(x6) + + li x25, 0x7BAD + + ebreak + + + _jend11: + + sd x25, 88(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend12: + + sd x25, 96(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend13: + + sd x25, 104(x6) + + li x25, 0x7BAD + + ecall + + + _jend14: + + sd x25, 112(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend15: + + sd x25, 120(x6) + + li x25, 0x7BAD + + ebreak + + + _jend16: + + sd x25, 128(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend17: + + sd x25, 136(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend18: + + sd x25, 144(x6) + + li x25, 0x7BAD + + ecall + + + _jend19: + + sd x25, 152(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend20: + + sd x25, 160(x6) + + li x25, 0x7BAD + + ebreak + + + _jend21: + + sd x25, 168(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend22: + + sd x25, 176(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend23: + + sd x25, 184(x6) + + li x25, 0x7BAD + + ecall + + + _jend24: + + sd x25, 192(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend25: + + sd x25, 200(x6) + + li x25, 0x7BAD + + ebreak + + + _jend26: + + sd x25, 208(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend27: + + sd x25, 216(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend28: + + sd x25, 224(x6) + + li x25, 0x7BAD + + ecall + + + _jend29: + + sd x25, 232(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend30: + + sd x25, 240(x6) + + li x25, 0x7BAD + + ebreak + + + _jend31: + + sd x25, 248(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend32: + + sd x25, 256(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend33: + + sd x25, 264(x6) + + li x25, 0x7BAD + + ecall + + + _jend34: + + sd x25, 272(x6) + + li x25, 0x7BAD + + .fill 1, 4, 0 + + + _jend35: + + sd x25, 280(x6) + + li x25, 0x7BAD + + ebreak + + + _jend36: + + sd x25, 288(x6) + + li x25, 0x7BAD + + lw x0, 11(x0) + + + _jend37: + + sd x25, 296(x6) + + li x25, 0x7BAD + + sw x0, 11(x0) + + + _jend38: + + sd x25, 304(x6) + + li x25, 0x7BAD + + ecall + + + _jend39: + + sd x25, 312(x6) + + li x30, 1 + ecall + _j_all_end: + + csrw mtvec, x31 + # --------------------------------------------------------------------------------------------- + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 40, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END From f63c3264c2887a78dcddf1868f918e975be61219 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 00:40:11 +0000 Subject: [PATCH 076/199] tentatively add WALLY-AMO test to arch test infrastructure --- .../references/WALLY-AMO.reference_output | 72 +++++ .../rv64i_m/privilege/src/WALLY-AMO.S | 257 ++++++++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-AMO.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-AMO.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-AMO.reference_output new file mode 100644 index 000000000..edce96fe8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-AMO.reference_output @@ -0,0 +1,72 @@ +fffffffe +ffffffff +00000001 +00000000 +fffffffb +ffffffff +fffffffd +ffffffff +ffffffef +ffffffff +000007ef +00000000 +ffffffbf +ffffffff +ffffffff +ffffffff +fffffeff +ffffffff +fffffd7e +ffffffff +fffffeff +ffffffff +000007ff +00000000 +ffffefff +ffffffff +ffffefff +ffffffff +ffffefff +ffffffff +ffffefff +ffffffff +fffeffff +ffffffff +000007fa +00000000 +fffbffff +fff7ffff +00000001 +00000000 +ffefffff +ffdfffff +fff00001 +ffdfffff +ffbfffff +ff7fffff +000007cf +00000000 +feffffff +fdffffff +ffffffff +fdffffff +feffffff +f7ffffff +fefffc7e +f7ffffff +efffffff +dfffffff +000007ff +00000000 +efffffff +7fffffff +000007fd +00000000 +ffffffff +00000001 +ffffffff +00000001 +00000002 +00000004 +000007fa +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S new file mode 100644 index 000000000..c99065e49 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S @@ -0,0 +1,257 @@ +/////////////////////////////////////////// +// WALLY-AMO.S +// +// Tests Atomic AMO instructions +// +// David_Harris@hmc.edu 10 March 2021 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # Addresses for test data and results + la x6, wally_signature + la x31, test_data + + # Testcase 0: amoswap.w + li x7, 1 + amoswap.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be fffffffffffffffe (sign extended from test data) + sd x9, 8(x6) # should be 0000000000000001 (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 1: amoadd.w + li x7, 2 + amoadd.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be fffffffffffffffb (sign extended from test data) + sd x9, 8(x6) # should be fffffffffffffffd (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 2: amoand.w + li x7, 0x7ff + amoand.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be ffffffffffffffef (sign extended from test data) + sd x9, 8(x6) # should be 00000000000007ef (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 3: amoor.w + li x7, 0x44 + amoor.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be ffffffffffffffbf (sign extended from test data) + sd x9, 8(x6) # should be ffffffffffffffff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 4: amoxor.w + li x7, 0x381 + amoxor.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data) + sd x9, 8(x6) # should be fffffffffffffd7e (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 5: amomax.w + li x7, 0x7ff + amomax.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data) + sd x9, 8(x6) # should be 00000000000007ff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 6: amomin.w + li x7, 0x7fd + amomin.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data) + sd x9, 8(x6) # should be ffffffffffffefff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 7: amomaxu.w + li x7, 0x7fb + amomaxu.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data) + sd x9, 8(x6) # should be ffffffffffffefff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 8: amominu.w + li x7, 0x7fa + amominu.w x8, x7, (x31) + lw x9, 0(x31) + sd x8, 0(x6) # should be fffffffffffeffff (sign extended from test data) + sd x9, 8(x6) # should be 00000000000007fa (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + + # Testcase 9: amoswap.d + li x7, 1 + amoswap.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0xfff7fffffffbffff (directly read from test data) + sd x9, 8(x6) # should be 0000000000000001 (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 10: amoadd.d + li x7, 2 + amoadd.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0xffdfffffffefffff (directly read from test data) + sd x9, 8(x6) # should be 0xffdffffffff00001 (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 11: amoand.d + li x7, 0x7cf + amoand.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0xff7fffffffbfffff (directly read from test data) + sd x9, 8(x6) # should be 00000000000007cf (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 12: amoor.d + li x7, 0x0d000011 + amoor.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0xfdfffffffeffffff (directly read from test data) + sd x9, 8(x6) # should be 0xfdffffffffffffff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 13: amoxor.d + li x7, 0x381 + amoxor.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0xf7fffffffeffffff (directly read from test data) + sd x9, 8(x6) # should be 0xf7fffffffefffc7e (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 14: amomax.d + li x7, 0x7ff + amomax.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0xdfffffffefffffff (directly read from test data) + sd x9, 8(x6) # should be 00000000000007ff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 15: amomin.d + li x7, 0x7fd + amomin.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0x7fffffffefffffff (directly read from test data) + sd x9, 8(x6) # should be 00000000000007fd (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 16: amomaxu.d + li x7, 0x7fb + amomaxu.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0x00000001ffffffff (directly read from test data) + sd x9, 8(x6) # should be 0x00000001ffffffff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # Testcase 17: amominu.d + li x7, 0x7fa + amominu.d x8, x7, (x31) + ld x9, 0(x31) + sd x8, 0(x6) # should be 0x0000000400000002 (directly read from test data) + sd x9, 8(x6) # should be 00000000000007fa (stored by amo) + addi x31, x31, 8 + addi x6, x6, 16 + + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 8 +test_data: + .dword 0xfffffffdfffffffe + .dword 0xfffffff7fffffffb + .dword 0xffffffdfffffffef + .dword 0xffffff7fffffffbf + .dword 0xfffffdfffffffeff + .dword 0xfffff7fffffffeff + .dword 0x0fffdfffffffefff + .dword 0xffff7fffffffefff + .dword 0x3ffdfffffffeffff + .dword 0xfff7fffffffbffff + .dword 0xffdfffffffefffff + .dword 0xff7fffffffbfffff + .dword 0xfdfffffffeffffff + .dword 0xf7fffffffeffffff + .dword 0xdfffffffefffffff + .dword 0x7fffffffefffffff + .dword 0x00000001ffffffff + .dword 0x0000000400000002 + .dword 0x0000001000000008 + .dword 0x0000004000000020 + .dword 0x0000010000000080 + .dword 0x0000040000000200 + .dword 0x0000100000000800 + .dword 0x0000400000002000 + .dword 0x0000000100008000 + .dword 0x0004000000000002 + .dword 0x0000001000080000 + .dword 0x0040000000000020 + .dword 0x0000010000800000 + .dword 0x0400000000000200 + .dword 0x0000100008000000 + .dword 0x4000000000002000 + .dword 0x0000000080000000 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 6, 8, -1 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVMODEL_DATA_END From eb26bf69cad53896cf08093f10da7f01f67262c7 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 00:51:54 +0000 Subject: [PATCH 077/199] typo fix to checkpoint generator --- linux/testvector-generation/createGenCheckpointScript.py | 1 - 1 file changed, 1 deletion(-) diff --git a/linux/testvector-generation/createGenCheckpointScript.py b/linux/testvector-generation/createGenCheckpointScript.py index 2b5f1fd11..3b1890a7a 100755 --- a/linux/testvector-generation/createGenCheckpointScript.py +++ b/linux/testvector-generation/createGenCheckpointScript.py @@ -54,7 +54,6 @@ set logging off # Log main memory to a file print "GDB storing RAM to {ramPath}\\n" dump binary memory {ramPath} 0x80000000 0xffffffff -dump binary memory {ramPath} 0x80000000 0x80ffffff # Generate Trace Until End maintenance packet Qqemu.Logging:1 From 00ae804b6c47b37b33aa4b84343824d029cc0b0a Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 01:45:09 +0000 Subject: [PATCH 078/199] script for dumping out QEMU ram and bootrom state at ground 0 --- linux/testvector-generation/genInitMem.sh | 84 +++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100755 linux/testvector-generation/genInitMem.sh diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh new file mode 100755 index 000000000..e300c2f0c --- /dev/null +++ b/linux/testvector-generation/genInitMem.sh @@ -0,0 +1,84 @@ +#!/bin/bash +tcpPort=1235 +imageDir=$RISCV/buildroot/output/images +tvDir=$RISCV/linux-testvectors +rawRamFile="$tvDir/ramGDB.bin" +ramFile="$tvDir/ram.bin" +rawBootmemFile="$tvDir/bootmemGDB.bin" +bootmemFile="$tvDir/bootmem.bin" +rawUntrimmedBootmemFile="$tvDir/untrimmedBootmemFileGDB.bin" +untrimmedBootmemFile="$tvDir/untrimmedBootmemFile.bin" + +read -p "Warning: running this script will overwrite the contents of: + * $rawRamFile + * $ramFile + * $rawBootmemFile + * $bootmemFile + * $rawUntrimmedBootmemFile + * $untrimmedBootmemFile +Would you like to proceed? (y/n) " -n 1 -r +echo +if [[ $REPLY =~ ^[Yy]$ ]] +then + # Create Output Directory + echo "Elevating permissions to create memory files" + sudo mkdir -p $tvDir + sudo chown cad $tvDir + sudo touch $rawRamFile + sudo touch $ramFile + sudo touch $rawBootmemFile + sudo touch $bootmemFile + sudo touch $rawUntrimmedBootmemFile + sudo touch $untrimmedBootmemFile + sudo chmod a+rw $rawRamFile + sudo chmod a+rw $ramFile + sudo chmod a+rw $rawBootmemFile + sudo chmod a+rw $bootmemFile + sudo chmod a+rw $rawUntrimmedBootmemFile + sudo chmod a+rw $untrimmedBootmemFile + + # QEMU Simulation + echo "Launching QEMU in replay mode!" + (qemu-system-riscv64 \ + -M virt -dtb $RISCV/buildroot/output/images/wally-virt.dtb \ + -nographic \ + -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ + -gdb tcp::$tcpPort -S) \ + & riscv64-unknown-elf-gdb --quiet \ + -ex "set pagination off" \ + -ex "set logging overwrite on" \ + -ex "set logging redirect on" \ + -ex "set confirm off" \ + -ex "target extended-remote :$tcpPort" \ + -ex "maintenance packet Qqemu.PhyMemMode:1" \ + -ex "printf \"Creating $rawBootmemFile\n\"" \ + -ex "dump binary memory $rawBootmemFile 0x1000 0x1fff" \ + -ex "printf \"Creating $rawUntrimmedBootmemFile\n\"" \ + -ex "printf \"Warning - please verify that the second half of $rawUntrimmedBootmemFile is all 0s\n\"" \ + -ex "dump binary memory $rawUntrimmedBootmemFile 0x1000 0x2fff" \ + -ex "printf \"Creating $rawRamFile\n\"" \ + -ex "dump binary memory $rawRamFile 0x80000000 0xffffffff" \ + -ex "kill" \ + -ex "q" + + echo "Changing Endianness" + make fixBinMem + ./fixBinMem "$rawRamFile" "$ramFile" + ./fixBinMem "$rawBootmemFile" "$bootmemFile" + ./fixBinMem "$rawUntrimmedBootmemFile" "$untrimmedBootmemFile" + + # Cleanup + echo "Elevating permissions to restrict write access to memory files" + sudo chown cad $rawRamFile + sudo chown cad $ramFile + sudo chown cad $rawBootmemFile + sudo chown cad $bootmemFile + sudo chown cad $rawUntrimmedBootmemFile + sudo chown cad $untrimmedBootmemFile + sudo chmod o-w $rawRamFile + sudo chmod o-w $ramFile + sudo chmod o-w $rawBootmemFile + sudo chmod o-w $bootmemFile + sudo chmod o-w $rawUntrimmedBootmemFile + sudo chmod o-w $untrimmedBootmemFile +fi From a048dbb86b028be9703e8c114e301ef35fe2fd79 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 01:46:26 +0000 Subject: [PATCH 079/199] remove old testvector-generation folder --- .../testvector-generation/Makefile | 13 -- .../testvector-generation/analyzeTrace.py | 57 ----- .../testvector-generation/analyzeTrace.sh | 1 - .../testvector-generation/checkpointSweep.sh | 5 - .../testvector-generation/combineGDBs.py | 68 ------ .../testvector-generation/debug.gdb | 24 -- .../testvector-generation/debug.sh | 21 -- .../testvector-generation/fixBinMem | Bin 8784 -> 0 bytes .../testvector-generation/fixBinMem.c | 33 --- .../testvector-generation/fixTxtMem.py | 15 -- .../testvector-generation/genCheckpoint.gdb | 53 ----- .../testvector-generation/genCheckpoint.sh | 60 ----- .../testvector-generation/genInitMem.gdb | 44 ---- .../testvector-generation/genInitMem.sh | 27 --- .../testvector-generation/genSettings.sh | 11 - .../testvector-generation/genTrace.gdb | 24 -- .../testvector-generation/genTrace.sh | 24 -- .../testvector-generation/parseGDBtoTrace.py | 213 ------------------ .../testvector-generation/parseQemuToGDB.py | 136 ----------- .../testvector-generation/parseState.py | 99 -------- .../testvector-generation/remove_dup.awk | 20 -- 21 files changed, 948 deletions(-) delete mode 100644 tests/linux-testgen/testvector-generation/Makefile delete mode 100755 tests/linux-testgen/testvector-generation/analyzeTrace.py delete mode 100755 tests/linux-testgen/testvector-generation/analyzeTrace.sh delete mode 100755 tests/linux-testgen/testvector-generation/checkpointSweep.sh delete mode 100755 tests/linux-testgen/testvector-generation/combineGDBs.py delete mode 100755 tests/linux-testgen/testvector-generation/debug.gdb delete mode 100755 tests/linux-testgen/testvector-generation/debug.sh delete mode 100755 tests/linux-testgen/testvector-generation/fixBinMem delete mode 100644 tests/linux-testgen/testvector-generation/fixBinMem.c delete mode 100755 tests/linux-testgen/testvector-generation/fixTxtMem.py delete mode 100755 tests/linux-testgen/testvector-generation/genCheckpoint.gdb delete mode 100755 tests/linux-testgen/testvector-generation/genCheckpoint.sh delete mode 100755 tests/linux-testgen/testvector-generation/genInitMem.gdb delete mode 100755 tests/linux-testgen/testvector-generation/genInitMem.sh delete mode 100755 tests/linux-testgen/testvector-generation/genSettings.sh delete mode 100755 tests/linux-testgen/testvector-generation/genTrace.gdb delete mode 100755 tests/linux-testgen/testvector-generation/genTrace.sh delete mode 100755 tests/linux-testgen/testvector-generation/parseGDBtoTrace.py delete mode 100755 tests/linux-testgen/testvector-generation/parseQemuToGDB.py delete mode 100755 tests/linux-testgen/testvector-generation/parseState.py delete mode 100755 tests/linux-testgen/testvector-generation/remove_dup.awk diff --git a/tests/linux-testgen/testvector-generation/Makefile b/tests/linux-testgen/testvector-generation/Makefile deleted file mode 100644 index 8f9bff4bb..000000000 --- a/tests/linux-testgen/testvector-generation/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -SHELL = /bin/sh - -CFLAG = -Wall -g -CC = clang - -all: fixBinMem - -fixBinMem: fixBinMem.c - ${CC} ${CFLAGS} fixBinMem.c -o fixBinMem - chmod +x fixBinMem - -clean: - -rm -f fixBinMem diff --git a/tests/linux-testgen/testvector-generation/analyzeTrace.py b/tests/linux-testgen/testvector-generation/analyzeTrace.py deleted file mode 100755 index 629ac3be0..000000000 --- a/tests/linux-testgen/testvector-generation/analyzeTrace.py +++ /dev/null @@ -1,57 +0,0 @@ -#! /usr/bin/python3 -import sys,os -import matplotlib.pyplot as plt -import matplotlib.animation as animation -import matplotlib.ticker as ticker - -# Argument Parsing -if len(sys.argv) != 4: - sys.exit('Error analyzeTrace.py expects 3 args:\n ') -traceFile = sys.argv[1] -addressFile = sys.argv[2] -labelFile = sys.argv[3] -if not os.path.exists(traceFile): - sys.exit('Error trace file '+traceFile+'not found') -if not os.path.exists(addressFile): - sys.exit('Error address file '+addressFile+'not found') -if not os.path.exists(labelFile): - sys.exit('Error label file '+labelFile+'not found') - -print('Loading labels') -funcList=[] -with open(addressFile, 'r') as addresses, open(labelFile, 'r') as labels: - for address, label in zip(addresses, labels): - funcList.append([int(address.strip('\n'),16),label.strip('\n'),0]) - -def lookupAdr(address): - labelCount = len(funcList) - guessIndex = labelCount - guessAdr = funcList[guessIndex-1][0] - if address < funcList[0][0]: - return 0 - while (address < guessAdr): - guessIndex-=1 - if guessIndex == -1: - return 0 - guessAdr=funcList[guessIndex][0] - funcList[guessIndex][2] += 1 - #print(funcList[guessIndex][1]) - return 1 - -print('Parsing trace') -with open(traceFile, 'r') as trace: - iCount = 0 - for l in trace: - lookupAdr(int(l.split(' ')[0],16)) - iCount += 1 - if (iCount % 1e5==0): - print('Reached '+str(iCount/1e6)+' million instructions') - -print('Sorting by function frequency') -funcListSorted = sorted(funcList, key=lambda labelEntry: -labelEntry[2]) -with open('traceAnalysis.txt','w') as outFile: - outFile.write('Virtual Address \t'+('%-50s'%'Function')+'Occurences\n') - for labelEntry in funcListSorted: - addr = '%x' % labelEntry[0] - outFile.write(addr+'\t'+('%-50s' % labelEntry[1])+str(labelEntry[2])+'\n') -print('Logged results to traceAnalysis.txt') diff --git a/tests/linux-testgen/testvector-generation/analyzeTrace.sh b/tests/linux-testgen/testvector-generation/analyzeTrace.sh deleted file mode 100755 index c84660cfb..000000000 --- a/tests/linux-testgen/testvector-generation/analyzeTrace.sh +++ /dev/null @@ -1 +0,0 @@ - ./analyzeTrace.py ../linux-testvectors/all.txt ../linux-testvectors/vmlinux.objdump.addr ../linux-testvectors/vmlinux.objdump.lab diff --git a/tests/linux-testgen/testvector-generation/checkpointSweep.sh b/tests/linux-testgen/testvector-generation/checkpointSweep.sh deleted file mode 100755 index 01f05ea65..000000000 --- a/tests/linux-testgen/testvector-generation/checkpointSweep.sh +++ /dev/null @@ -1,5 +0,0 @@ -for index in {89..181} -do - instrs=$(($index*1000000)) - echo "y" | nice -n 5 ./genCheckpoint.sh $instrs -done diff --git a/tests/linux-testgen/testvector-generation/combineGDBs.py b/tests/linux-testgen/testvector-generation/combineGDBs.py deleted file mode 100755 index 5fe0b1979..000000000 --- a/tests/linux-testgen/testvector-generation/combineGDBs.py +++ /dev/null @@ -1,68 +0,0 @@ -#! /usr/bin/python3 - -instrs = 0 -def readBlock(f, start, end): - l = f.readline() - if not l: - quit() - while not (l.startswith(start) and 'in ' not in l): - l = f.readline() - if not l: - quit() - ret = l - while not l.startswith(end): - l = f.readline() - if not l: - quit() - ret += l - return ret.split('\n'), f.readline() - -with open('gdbcombined.txt', 'w') as out: - with open('/mnt/scratch/riscv_gp/riscv_gp.txt', 'r') as gp: - with open('/mnt/scratch/riscv_sp1/riscv_sp1.txt', 'r') as sp1: - with open('/mnt/scratch/riscv_sp2/riscv_sp2.txt', 'r') as sp2: - with open('/mnt/scratch/riscv_sp3/riscv_sp3.txt', 'r') as sp3: - with open('/mnt/scratch/riscv_decodepc_threads/riscv_decodepc.txt.disassembly', 'r') as inst: - inst.readline() - while(True): - instrs += 1 - g, i1 = readBlock(gp, 'ra', 't6') - p1, i2 = readBlock(sp1, 'mie', 'scounteren') - p2, i3 = readBlock(sp2, '0x', 'mideleg') - p3, i4 = readBlock(sp3, 'mcause', 'stvec') - instr = inst.readline() - if not instr: - quit() - while '...' in instr: - instr = inst.readline() - if not instr: - quit() - if i1 != i2 or i2 != i3 or i3 != i4 or int(p2[0].split()[0].split(':')[0], 16) != int(instr.split()[0].split(':')[0], 16): - print("error: PC was not the same") - print("instruction {}".format(instrs)) - print(i1) - print(i2) - print(i3) - print(i4) - print(p2[0]) - print(instr) - quit() - if "unimp" in instr: - instrs -= 1 - continue - out.write('=> {}'.format(instr.split(':')[2][1:].replace(' ', ':\t', 1))) - out.write(p2[0] + '\n') - out.write("zero 0x0 0\n") - out.write("\n".join(g)) - pc = p2[0].split()[0] - if pc.endswith(':'): - pc = pc[:-1] - out.write("pc {} {}\n".format(pc, pc)) - out.write("\n".join(p1)) - out.write("\n".join(p3)) - out.write("\n".join(p2[2:])) - out.write("-----\n") - if instrs % 10000 == 0: - print(instrs) - #if instrs >= 1000010: - # quit() diff --git a/tests/linux-testgen/testvector-generation/debug.gdb b/tests/linux-testgen/testvector-generation/debug.gdb deleted file mode 100755 index dbdf274a4..000000000 --- a/tests/linux-testgen/testvector-generation/debug.gdb +++ /dev/null @@ -1,24 +0,0 @@ -define debug - # Arguments - set $tcpPort=$arg0 - - # GDB config - set pagination off - set logging overwrite on - set logging redirect on - set confirm off - - # Connect to QEMU session - eval "target extended-remote :%d",$tcpPort - - # Symbol Files - file ../buildroot-image-output/vmlinux - - # Run until Linux login prompt - b do_idle - ignore 1 2 - c - - kill - q -end diff --git a/tests/linux-testgen/testvector-generation/debug.sh b/tests/linux-testgen/testvector-generation/debug.sh deleted file mode 100755 index e6c96f8bc..000000000 --- a/tests/linux-testgen/testvector-generation/debug.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/bash -source genSettings.sh -tcpPort=1237 - -# Run without GDB -($customQemu \ --M virt \ --m 128M \ --nographic \ --bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ --singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on) - -# Run with GDB -#($customQemu \ -#-M virt \ -#-nographic -serial /dev/null \ -#-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -#-singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on \ -#-gdb tcp::$tcpPort -S) \ -#& riscv64-unknown-elf-gdb -x debug.gdb -ex "debug $tcpPort" - diff --git a/tests/linux-testgen/testvector-generation/fixBinMem b/tests/linux-testgen/testvector-generation/fixBinMem deleted file mode 100755 index 563ed988d78611241ac015f656c16c9483981703..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8784 zcmeHMZ){W76~DI09|AZI&=O!YuN|oZQ;ZWr6ev(TiNj0hK$bsr(-vNw_&IUs*p~g= zgci1-6oi%1@?jsCrb&~gNlcoiPMS1SRU;Wy1KWqDovNX&9~gqwp+n7D#yqXyopawk zdCxD7R%x2F4_xcLbI%U4AC#?Fe6GHBE|ZQV~TL7pMHU-;22DCr@KdUZmtPUsPx7mg97_F>!b=@a()>|WrI_ab5K z{B2N_#ngRU3t_%{HD`f(d4_0{4l|;p_chQ%Kfh>l3Bevw-%9 zzGC**tblJ@0e>9uDz=4ny9Obrx0z?4e}}O;A{mKkVWudkqNKE7Qd7o)kr*H&WAT_k6m}@k+1jQwx*Oelum(H-5f#%E`Wt_+ zPPh|{rME<2CfZrA;B%FOJcnaKa}NRXAJ-5>N(5|dBQXeHT~p+uf~yZnkSk>B$v6y^Lai3s=^_a%oV0 z69whd?}M_Oc}Lg3DfA}~JPH1?bX7lSX1@cD47^j~1jzQ;73?p0>cG`95YV1ja$#ft zWeIjokk8K#EW8XVl{IW3rBgHmV=_4B{~T-0oXp9Y^x~ zugRc1-Jb=c4TjNQX4{3)F2kq`>|6(<*Rz{+qw{nAx6rEmYnt)$n>5GebN;LHbk_|z zGnc*e0DLGa(>3GE%(Q3xZ^_djKAUB7Z5|EI-e`e}0Qsa`KJ}3fedLi>=LG69&^iOH zHc-hxB?GNC&^iNk8K}oV%MG-}KpCPL{|xv$FK6DBGqc&9*t(4W;;ECoGb&Hth2GHz zf9mbQfh%EmWz8$tO?*B1p7&+)zN4L)`@a6p%m=={z`5G9B@#@@bM;7j13PXv{7IgD z;J}rd?fM*ypT4U-K{f)JJAusocCeA(_@O*?#U}6lIDH2f@HYp1-|`Lkj`@@;=Z!i) zgLTczw-G>pk8Q1H&74s z)J32YO#Q1sas9i*gu(A2CfiFr%r@b&ZCzVde%@B*LL5JIS+IrQC`!fU8N&sG@+}~r zKw+n=!&&`Y<(l#GN%riPXLj!1{uII}(+}~6455=+&Jl!yuDp1zy zbiHo(JF8!F_?^-8(Un|6ib zT4Q|}KGD$~-1QY-4v0ir?A~SN4wwafMR5nyisGx5=BL@117_644a#7rf;|t|!_cKsj_p8|7@MvF+7p4*m*(NvDQ1jg8Zw1O9h_j%ntysvb$K$ zvVJcj4xZAwUL|yY1vvHtUQ=M=F$2&)z~h4XHfU*ALderSGwNWP103b8{qTDsKPk>7 zJZ1s;>m28*1+R}+z#puDSHZwl**7oUW0A30F28*L+=lYS?(K$?T1rcY!|q|Ye|xU2 zM+tQH_9+U3i#v5BlG4nZ}Oi!@k_*f#ULQv{% z-o0l}aUlghbP*+(Oa_lD5VIza!);)2OjRIY9Xk#xCQboKtxz;F(He<$sbk#9jvil^ zU-2Jq2QPJ(DPN!%VoLir4*R+~+d#@x!Y>>Fg73cKmlfTb+}^{KLxCf$zJPM1qodc~ zr}X(+1AeT5UsDdJ(!2@!C8pPFzMNFlP*4k!q;a8Xky21fzulxuP^(12{U>yGDz1zM zW1*Q7GjFh*VQI^SHHe3 zENAZ2@i8qp1XN4vbd+*%ud5~#%njEJs@vDvSr11Z!HvYy?xA!9?%yLJ=0Om7 z(D4}9)2Wu!OT@XUfKi|Qk)BZ98)PgX8$<|FFdcH zDCyHV*(3BRKBM}r?SDn+w*tjP@!p`&r}z-{vCpjfuK|XBp?{d@+`TCDDel!vm(QOJ z6qxnteC`qsCrD9HmxX@MqEF}eNuf{vk{K)iLyJCrpU(^Zo~6K9w?Oriy&qfjDK5Ar zDx$cUgCS zi@vq~Yfz4V6;n6S`I7!$waODu^aIeXH0e`(Q;kL;k(|yMJmG(a0-QfoKgB`Pf6ym; ze}N3nUDBs`iT?kdN8^xaep9_P4=zBNxqgbPa@Z(HB(HM@PxvQLVAfxXzeEKxDGEw@ zL~|B>ItR-_-#Xq_{vqh2Eowjh;e;t5^r@X3gcsFIyaSv^|2+f -#include -#include -int main(int argc, char *argv[]) { - if (argc < 3){ - fprintf(stderr, "Expected 2 arguments: \n"); - exit(1); - } - char* rawGDBfilePath = argv[1]; - FILE* rawGDBfile; - if ((rawGDBfile = fopen(rawGDBfilePath,"rb"))==NULL) { - fprintf(stderr, "File not found: %s\n",rawGDBfilePath); - exit(1); - } - char* outFilePath = argv[2]; - FILE* outFile = fopen(outFilePath,"w"); - uint64_t qemuWord; - uint64_t verilogWord; - int bytesReturned=0; - do { - bytesReturned=fread(&qemuWord, 8, 1, rawGDBfile); - verilogWord = (((qemuWord>>0 )&0xff)<<56 | - ((qemuWord>>8 )&0xff)<<48 | - ((qemuWord>>16)&0xff)<<40 | - ((qemuWord>>24)&0xff)<<32 | - ((qemuWord>>32)&0xff)<<24 | - ((qemuWord>>40)&0xff)<<16 | - ((qemuWord>>48)&0xff)<<8 | - ((qemuWord>>56)&0xff)<<0); - fwrite(&verilogWord, 8, 1, outFile); - } while(bytesReturned!=0); - return 0; -} diff --git a/tests/linux-testgen/testvector-generation/fixTxtMem.py b/tests/linux-testgen/testvector-generation/fixTxtMem.py deleted file mode 100755 index 0e2fbf82c..000000000 --- a/tests/linux-testgen/testvector-generation/fixTxtMem.py +++ /dev/null @@ -1,15 +0,0 @@ -#! /usr/bin/python3 -import sys,os - -if len(sys.argv) != 3: - sys.exit('Error fix_mem.py expects 2 args:\n fix_mem.py ') -inputFile = sys.argv[1] -outputFile = sys.argv[2] -if not os.path.exists(inputFile): - sys.exit('Error input file '+inputFile+' not found') -print('Begin translating '+os.path.basename(inputFile)+' to '+os.path.basename(outputFile)) -with open(inputFile, 'r') as f: - with open(outputFile, 'w') as w: - for l in f: - w.write(f'{"".join([x[2:] for x in l.split()[:0:-1]])}\n') -print('Finished translating '+os.path.basename(inputFile)+' to '+os.path.basename(outputFile)+'!') diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.gdb b/tests/linux-testgen/testvector-generation/genCheckpoint.gdb deleted file mode 100755 index a77441398..000000000 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.gdb +++ /dev/null @@ -1,53 +0,0 @@ -define genCheckpoint - # GDB config - set pagination off - set logging overwrite on - set logging redirect on - set confirm off - - # Argument Parsing - set $tcpPort=$arg0 - set $instrCount=$arg1 - set $statePath=$arg2 - set $ramPath=$arg2 - set $checkPC=$arg3 - set $checkPCoccurences=$arg4 - eval "set $statePath = \"%s/stateGDB.txt\"", $statePath - eval "set $ramPath = \"%s/ramGDB.bin\"", $ramPath - - # Connect to QEMU session - eval "target extended-remote :%d",$tcpPort - - # QEMU Config - maintenance packet Qqemu.PhyMemMode:1 - - # Symbol file - file ../buildroot-image-output/vmlinux - - # Step over reset vector into actual code - stepi 100 - # Set breakpoint for where to stop - b do_idle - # Proceed to checkpoint - printf "GDB proceeding to checkpoint at %d instrs\n", $instrCount - #stepi $instrCount-1000 - eval "b *0x%s",$checkPC - ignore 2 $checkPCoccurences - c - - printf "Reached checkpoint at %d instrs\n", $instrCount - - # Log all registers to a file - printf "GDB storing state to %s\n", $statePath - eval "set logging file %s", $statePath - set logging on - info all-registers - set logging off - - # Log main memory to a file - printf "GDB storing RAM to %s\n", $ramPath - eval "dump binary memory %s 0x80000000 0xffffffff", $ramPath - - kill - q -end diff --git a/tests/linux-testgen/testvector-generation/genCheckpoint.sh b/tests/linux-testgen/testvector-generation/genCheckpoint.sh deleted file mode 100755 index 85102f877..000000000 --- a/tests/linux-testgen/testvector-generation/genCheckpoint.sh +++ /dev/null @@ -1,60 +0,0 @@ -#!/bin/bash - -source genSettings.sh -tcpPort=1236 - -# Parse Commandline Arg -if [ "$#" -ne 1 ]; then - echo "genCheckpoint requires 1 argument: " >&2 - exit 1 -fi -instrs=$1 -if ! [ "$instrs" -eq "$instrs" ] 2> /dev/null -then - echo "Error expected integer number of instructions, got $instrs" >&2 - exit 1 -fi -checkOutDir="$outDir/checkpoint$instrs" -checkIntermedDir="$checkOutDir/intermediate-outputs" - -read -p "This scripts is going to create a checkpoint at $instrs instrs. -Is that what you wanted? (y/n) " -n 1 -r -echo -if [[ $REPLY =~ ^[Yy]$ ]] -then - echo "Creating checkpoint at $instrs instructions!" - mkdir -p $checkOutDir - mkdir -p $checkIntermedDir - - # Identify instruction in trace - instr=$(sed "${instrs}q;d" "../linux-testvectors/all.txt") - echo "Found ${instrs}th instr: ${instr}" - pc=$(echo $instr | cut -d " " -f1) - asm=$(echo $instr | cut -d " " -f2) - occurences=$(($(head -$instrs "../linux-testvectors/all.txt" | grep -c "${pc} ${asm}")-1)) - echo "It occurs ${occurences} times before the ${instrs}th instr." - - # GDB+QEMU - echo "Starting QEMU with attached GDB script at $(date +%H:%M:%S)" - ($customQemu \ - -M virt \ - -nographic \ - -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ - -singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on,rr=replay,rrfile="$intermedDir/$recordFile" \ - -gdb tcp::$tcpPort -S) \ - & riscv64-unknown-elf-gdb --quiet \ - -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" \"$pc\" $occurences" - echo "Completed GDB script completed at $(date +%H:%M:%S)" - - # Post-Process GDB outputs - ./parseState.py "$checkOutDir" - echo "Changing Endianness at $(date +%H:%M:%S)" - make - ./fixBinMem "$checkIntermedDir/ramGDB.bin" "$checkOutDir/ram.bin" - echo "Creating truncated trace at $(date +%H:%M:%S)" - tail -n+$instrs "$outDir/$traceFile" > "$checkOutDir/$traceFile" - echo "Checkpoint completed at $(date +%H:%M:%S)" -else - echo "You can change the number of instructions by editing the \"instrs\" variable in this script." - echo "Have a nice day!" -fi diff --git a/tests/linux-testgen/testvector-generation/genInitMem.gdb b/tests/linux-testgen/testvector-generation/genInitMem.gdb deleted file mode 100755 index f4a776fde..000000000 --- a/tests/linux-testgen/testvector-generation/genInitMem.gdb +++ /dev/null @@ -1,44 +0,0 @@ -define genInitMem - # GDB config - set pagination off - set logging overwrite on - set logging redirect on - set confirm off - - # Argument Parsing - set $tcpPort=$arg0 - set $bootmemPath=$arg1 - set $untrimmedBootmemPath=$arg1 - set $ramPath=$arg1 - eval "set $bootmemPath = \"%s/bootmemGDB.txt\"", $bootmemPath - eval "set $untrimmedBootmemPath = \"%s/untrimmedBootmemGDB.txt\"", $untrimmedBootmemPath - eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath - - # Connect to QEMU session - eval "target extended-remote :%d",$tcpPort - - # QEMU Config - maintenance packet Qqemu.PhyMemMode:1 - - printf "Creating %s\n",$bootmemPath - eval "set logging file %s", $bootmemPath - set logging on - x/4096xb 0x1000 - set logging off - - printf "Creating %s\n",$untrimmedBootmemPath - printf "Warning - please verify that the second half of %s is all 0s\n",$untrimmedBootmemPath - eval "set logging file %s", $untrimmedBootmemPath - set logging on - x/8192xb 0x1000 - set logging off - - printf "Creating %s\n", $ramPath - eval "set logging file %s", $ramPath - set logging on - x/134217728xb 0x80000000 - set logging off - - kill - q -end diff --git a/tests/linux-testgen/testvector-generation/genInitMem.sh b/tests/linux-testgen/testvector-generation/genInitMem.sh deleted file mode 100755 index f82556f58..000000000 --- a/tests/linux-testgen/testvector-generation/genInitMem.sh +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/bash - -source genSettings.sh -tcpPort=1235 - -read -p "Warning: running this script will overwrite the contents of memory dumps needed for simulation. -Would you like to proceed? (y/n) " -n 1 -r -echo -if [[ $REPLY =~ ^[Yy]$ ]] -then - ($customQemu \ - -M virt \ - -nographic \ - -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ - -gdb tcp::$tcpPort -S 2>/dev/null >/dev/null) \ - & riscv64-unknown-elf-gdb -quiet -x genInitMem.gdb -ex "genInitMem $tcpPort \"$intermedDir\"" - - echo "Translating Mem from GDB to Questa format" - ./fixTxtMem.py "$intermedDir/bootmemGDB.txt" "$outDir/bootmem.txt" - ./fixTxtMem.py "$intermedDir/ramGDB.txt" "$outDir/ram.txt" - echo "Done" - - echo "Creating debugging objdump of linux image" - riscv64-unknown-elf-objdump -D $imageDir/vmlinux > $outDir/vmlinux.objdump - extractFunctionRadix.sh $outDir/vmlinux.objdump - echo "Done" -fi diff --git a/tests/linux-testgen/testvector-generation/genSettings.sh b/tests/linux-testgen/testvector-generation/genSettings.sh deleted file mode 100755 index 59490e358..000000000 --- a/tests/linux-testgen/testvector-generation/genSettings.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Warning! This is Tera-specific absolute path -# *** on the long term we'll want to include QEMU in the addins folder -export customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64" -export imageDir="../buildroot-image-output" -export outDir="../linux-testvectors" -export intermedDir="$outDir/intermediate-outputs" -export traceFile="all.txt" -export recordFile="all.qemu" -export tcpPort=1234 diff --git a/tests/linux-testgen/testvector-generation/genTrace.gdb b/tests/linux-testgen/testvector-generation/genTrace.gdb deleted file mode 100755 index 23624607d..000000000 --- a/tests/linux-testgen/testvector-generation/genTrace.gdb +++ /dev/null @@ -1,24 +0,0 @@ -define genTrace - # Arguments - set $tcpPort=$arg0 - - # GDB config - set pagination off - set logging overwrite on - set logging redirect on - set confirm off - - # Connect to QEMU session - eval "target extended-remote :%d",$tcpPort - - # Symbol Files - file ../buildroot-image-output/vmlinux - - # Run until Linux login prompt - b do_idle - ignore 1 2 - c - - kill - q -end diff --git a/tests/linux-testgen/testvector-generation/genTrace.sh b/tests/linux-testgen/testvector-generation/genTrace.sh deleted file mode 100755 index 4f2bae4c4..000000000 --- a/tests/linux-testgen/testvector-generation/genTrace.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/bash -source genSettings.sh -tcpPort=1234 - -read -p "Warning: running this script will overwrite the contents of: - $outDir/$traceFile - $outDir/$recordFile -Would you like to proceed? (y/n) " -n 1 -r -echo -if [[ $REPLY =~ ^[Yy]$ ]] -then - mkdir -p $outDir - mkdir -p $intermedDir - ($customQemu \ - -M virt \ - -nographic -serial /dev/null \ - -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ - -singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on,rr=record,rrfile="$intermedDir/$recordFile" \ - -d nochain,cpu,in_asm \ - -gdb tcp::$tcpPort -S \ - 2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py | ./remove_dup.awk > "$outDir/$traceFile") \ - & riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort" -fi - diff --git a/tests/linux-testgen/testvector-generation/parseGDBtoTrace.py b/tests/linux-testgen/testvector-generation/parseGDBtoTrace.py deleted file mode 100755 index 7c2c00245..000000000 --- a/tests/linux-testgen/testvector-generation/parseGDBtoTrace.py +++ /dev/null @@ -1,213 +0,0 @@ -#! /usr/bin/python3 -import sys, fileinput, re - -# Ross Thompson -# July 27, 2021 -# Rewrite of the linux trace parser. - - -InstrStartDelim = '=>' -InstrEndDelim = '-----' - -#InputFile = 'noparse.txt' -#InputFile = sys.stdin -#InputFile = 'temp.txt' -#OutputFile = 'parsedAll.txt' - -HUMAN_READABLE = False - -def toDict(lst): - 'Converts the list of register values to a dictionary' - dct= {} - for item in lst: - regTup = item.split() - dct[regTup[0]] = int(regTup[2], 10) - del dct['pc'] - return dct - -def whichClass(text, Regs): - 'Which instruction class?' - #print(text, Regs) - if text[0:2] == 'ld' or text[0:2] == 'lw' or text[0:2] == 'lh' or text[0:2] == 'lb': - return ('load', WhatAddr(text, Regs), None, WhatMemDestSource(text)) - elif text[0:2] == 'sd' or text[0:2] == 'sw' or text[0:2] == 'sh' or text[0:2] == 'sb': - return ('store', WhatAddr(text, Regs), WhatMemDestSource(text), None) - elif text[0:3] == 'amo': - return ('amo', WhatAddrAMO(text, Regs), WhatMemDestSource(text), WhatMemDestSource(text)) - elif text[0:2] == 'lr': - return ('lr', WhatAddrLR(text, Regs), None, WhatMemDestSource(text)) - elif text[0:2] == 'sc': - return ('sc', WhatAddrSC(text, Regs), WhatMemDestSource(text), None) - else: - return ('other', None, None, None) - -def whatChanged(dct0, dct1): - 'Compares two dictionaries of instrution registers and indicates which registers changed' - dct = {} - for key in dct0: - if (dct1[key] != dct0[key]): - dct[key] = dct1[key] - return dct - -def WhatMemDestSource(text): - ''''What is the destination register. Used to compute where the read data is - on a load or the write data on a store.''' - return text.split()[1].split(',')[0] - -def WhatAddr(text, Regs): - 'What is the data memory address?' - Imm = text.split(',')[1] - (Imm, Src) = Imm.split('(') - Imm = int(Imm.strip(), 10) - Src = Src.strip(')').strip() - RegVal = Regs[Src] - return Imm + RegVal - -def WhatAddrAMO(text, Regs): - 'What is the data memory address?' - Src = text.split('(')[1] - Src = Src.strip(')').strip() - return Regs[Src] - -def WhatAddrLR(text, Regs): - 'What is the data memory address?' - Src = text.split('(')[1] - Src = Src.strip(')').strip() - return Regs[Src] - -def WhatAddrSC(text, Regs): - 'What is the data memory address?' - Src = text.split('(')[1] - Src = Src.strip(')').strip() - return Regs[Src] - -def PrintInstr(instr, fp): - if instr[2] == None: - return - ChangedRegisters = instr[4] - GPR = '' - CSR = [] - for key in ChangedRegisters: - # filter out csr which are not checked. - if(key in RegNumber): - if(RegNumber[key] < 32): - # GPR - if(HUMAN_READABLE): - GPR = '{:-2d} {:016x}'.format(RegNumber[key], ChangedRegisters[key]) - else: - GPR = '{:d} {:x}'.format(RegNumber[key], ChangedRegisters[key]) - else: - if(HUMAN_READABLE): - CSR.extend([key, '{:016x}'.format(ChangedRegisters[key])]) - else: - CSR.extend([key, '{:x}'.format(ChangedRegisters[key])]) - - CSRStr = ' '.join(CSR) - - #print(instr) - - if (HUMAN_READABLE == True): - fp.write('{:016x} {:08x} {:25s}'.format(instr[0], instr[1], instr[2])) - if(len(GPR) != 0): - fp.write(' GPR {}'.format(GPR)) - if(instr[3] == 'load' or instr[3] == 'lr'): - fp.write(' MemR {:016x} {:016x} {:016x}'.format(instr[5], 0, instr[7])) - if(instr[3] == 'store'): - fp.write('\t\t\t MemW {:016x} {:016x} {:016x}'.format(instr[5], instr[6], 0)) - - if(len(CSR) != 0): - fp.write(' CSR {}'.format(CSRStr)) - else: - fp.write('{:x} {:x} {:s}'.format(instr[0], instr[1], instr[2].replace(' ', '_'))) - if(len(GPR) != 0): - fp.write(' GPR {}'.format(GPR)) - if(instr[3] == 'load' or instr[3] == 'lr'): - fp.write(' MemR {:x} {:x} {:x}'.format(instr[5], 0, instr[7])) - if(instr[3] == 'store'): - fp.write(' MemW {:x} {:x} {:x}'.format(instr[5], instr[6], 0)) - - if(len(CSR) != 0): - fp.write(' CSR {}'.format(CSRStr)) - fp.write('\n') - -# reg number -RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45} -# initial state -CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None] - -#with open (InputFile, 'r') as InputFileFP: -#lines = InputFileFP.readlines() -lineNum = 0 -StartLine = 0 -EndLine = 0 -numInstrs = 0 -#instructions = [] -MemAdr = 0 -lines = [] -for line in fileinput.input('-'): - lines.insert(lineNum, line) - if InstrStartDelim in line: - lineNum = 0 - StartLine = lineNum - elif InstrEndDelim in line: - EndLine = lineNum - (InstrBits, text) = lines[StartLine].split(':') - InstrBits = int(InstrBits.strip('=> '), 16) - text = text.strip() - PC = int(lines[StartLine+1].split(':')[0][2:], 16) - Regs = toDict(lines[StartLine+2:EndLine]) - (Class, Addr, WriteReg, ReadReg) = whichClass(text, Regs) - #print("CWR", Class, WriteReg, ReadReg) - PreviousInstr = CurrentInstr - - Changed = whatChanged(PreviousInstr[4], Regs) - - if (ReadReg !=None): ReadData = ReadReg - else: ReadData = None - - if (WriteReg !=None): WriteData = WriteReg - else: WriteData = None - - CurrentInstr = [PC, InstrBits, text, Class, Regs, Changed, Addr, WriteData, ReadData] - - #print(CurrentInstr[0:4], PreviousInstr[5], CurrentInstr[6:7], PreviousInstr[8]) - - # pc, instrbits, text and class come from the last line. - MoveInstrToRegWriteLst = PreviousInstr[0:4] - # updated registers come from the current line. - MoveInstrToRegWriteLst.append(CurrentInstr[5]) # destination regs - # memory address if present comes from the last line. - MoveInstrToRegWriteLst.append(PreviousInstr[6]) # MemAdrM - # write data from the previous line - #MoveInstrToRegWriteLst.append(PreviousInstr[7]) # WriteDataM - - if (PreviousInstr[7] != None): - MoveInstrToRegWriteLst.append(Regs[PreviousInstr[7]]) # WriteDataM - else: - MoveInstrToRegWriteLst.append(None) - - # read data from the current line - #MoveInstrToRegWriteLst.append(PreviousInstr[8]) # ReadDataM - if (PreviousInstr[8] != None): - MoveInstrToRegWriteLst.append(Regs[PreviousInstr[8]]) # ReadDataM - else: - MoveInstrToRegWriteLst.append(None) - - lines.clear() - #instructions.append(MoveInstrToRegWriteLst) - PrintInstr(MoveInstrToRegWriteLst, sys.stdout) - numInstrs +=1 - if (numInstrs % 1e4 == 0): - sys.stderr.write('Trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n') - sys.stderr.flush() - lineNum += 1 - - -#for instruction in instructions[1::]: - - -#with open(OutputFile, 'w') as OutputFileFP: -# print('opened file') - - - diff --git a/tests/linux-testgen/testvector-generation/parseQemuToGDB.py b/tests/linux-testgen/testvector-generation/parseQemuToGDB.py deleted file mode 100755 index eb3393ac4..000000000 --- a/tests/linux-testgen/testvector-generation/parseQemuToGDB.py +++ /dev/null @@ -1,136 +0,0 @@ -#! /usr/bin/python3 -import fileinput, sys - -sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n") -parseState = "idle" -beginPageFault = 0 -inPageFault = 0 -endPageFault = 0 -CSRs = {} -pageFaultCSRs = {} -regs = {} -pageFaultRegs = {} -instrs = {} -instrCount = 0 -returnAdr = 0 - -def printPC(l): - global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, instrCount - if not inPageFault: - inst = l.split() - if len(inst) > 3: - print(f'=> {inst[1]}:\t{inst[2]} {inst[3]}') - else: - print(f'=> {inst[1]}:\t{inst[2]}') - print(f'{inst[0]} 0x{inst[1]}') - instrCount += 1 - if ((instrCount % 100000) == 0): - sys.stderr.write("QEMU parser reached "+str(instrCount)+" instrs\n") - -def printCSRs(): - global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs - if not inPageFault: - for (csr,val) in CSRs.items(): - print('{}{}{:#x} {}'.format(csr, ' '*(15-len(csr)), val, val)) - print('-----') - -def parseCSRs(l): - global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs - if l.strip() and (not l.startswith("Disassembler")) and (not l.startswith("Please")): - # If we've hit the register file - if l.startswith(' x0/zero'): - parseState = "regFile" - if not inPageFault: - instr = instrs[CSRs["pc"]] - printPC(instr) - parseRegs(l) - # If we've hit a CSR - else: - csr = l.split()[0] - val = int(l.split()[1],16) - # Commented out this conditional because the pageFault instrs don't corrupt CSRs - #if inPageFault: - # Not sure if these CSRs should be updated or not during page fault. - #if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"): - # We do update some CSRs - # CSRs[csr] = val - #else: - # Others we preserve until changed later - # pageFaultCSRs[csr] = val - #elif pageFaultCSRs and (csr in pageFaultCSRs): - # if (val != pageFaultCSRs[csr]): - # del pageFaultCSRs[csr] - # CSRs[csr] = val - #else: - # CSRs[csr] = val - # - # However SEPC and STVAL do get corrupted upon exiting - if endPageFault and ((csr == 'sepc') or (csr == 'stval')): - CSRs[csr] = returnAdr - pageFaultCSRs[csr] = val - elif pageFaultCSRs and (csr in pageFaultCSRs): - if (val != pageFaultCSRs[csr]): - del pageFaultCSRs[csr] - CSRs[csr] = val - else: - CSRs[csr] = val - -def parseRegs(l): - global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, pageFaultRegs - if "pc" in l: - printCSRs() - # New non-disassembled instruction - parseState = "CSRs" - parseCSRs(l) - elif l.startswith('--------'): - # End of disassembled instruction - printCSRs() - parseState = "idle" - else: - s = l.split() - for i in range(0,len(s),2): - if '/' in s[i]: - reg = s[i].split('/')[1] - val = int(s[i+1], 16) - if inPageFault: - pageFaultRegs[reg] = val - else: - if pageFaultRegs and (reg in pageFaultRegs): - if (val != pageFaultRegs[reg]): - del pageFaultRegs[reg] - regs[reg] = val - else: - regs[reg] = val - val = regs[reg] - print('{}{}{:#x} {}'.format(reg, ' '*(15-len(reg)), val, val)) - else: - sys.stderr.write("Whoops. Expected a list of reg file regs; got:\n"+l) - -############# -# Main Code # -############# -for l in fileinput.input(): - #sys.stderr.write(l) - if l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'): - break - elif l.startswith('IN:'): - # New disassembled instr - parseState = "instr" - elif (parseState == "instr") and l.startswith('0x'): - if "out of bounds" in l: - sys.stderr.write("Detected QEMU page fault error\n") - beginPageFault = not inPageFault - if beginPageFault: - returnAdr = int(l.split()[0][2:-1], 16) - sys.stderr.write('Saving SEPC of '+hex(returnAdr)+'\n') - inPageFault = 1 - else: - endPageFault = inPageFault - inPageFault = 0 - adr = int(l.split()[0][2:-1], 16) - instrs[adr] = l - parseState = "CSRs" - elif parseState == "CSRs": - parseCSRs(l) - elif parseState == "regFile": - parseRegs(l) diff --git a/tests/linux-testgen/testvector-generation/parseState.py b/tests/linux-testgen/testvector-generation/parseState.py deleted file mode 100755 index 6f310c9cd..000000000 --- a/tests/linux-testgen/testvector-generation/parseState.py +++ /dev/null @@ -1,99 +0,0 @@ -#! /usr/bin/python3 -import sys, os - -################ -# Helper Funcs # -################ - -def tokenize(string): - tokens = [] - token = '' - whitespace = 0 - prevWhitespace = 0 - for char in string: - prevWhitespace = whitespace - whitespace = char in ' \t\n' - if (whitespace): - if ((not prevWhitespace) and (token != '')): - tokens.append(token) - token = '' - else: - token = token + char - return tokens - -############# -# Main Code # -############# -print("Begin parsing state.") - -# Parse Args -if len(sys.argv) != 2: - sys.exit('Error parseState.py expects 1 arg:\n parseState.py ') -outDir = sys.argv[1]+'/' -stateGDBpath = outDir+'intermediate-outputs/stateGDB.txt' -if not os.path.exists(stateGDBpath): - sys.exit('Error input file '+stateGDBpath+'not found') - -singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv'] -# priv (current privilege mode) isn't technically a CSR but we can log it with the same machinery -thirtyTwoBitCSRs = ['mcounteren','scounteren'] -listCSRs = ['hpmcounter','pmpaddr'] -pmpcfg = ['pmpcfg'] - -# Initialize List CSR files to empty -# (because later we'll open them in append mode) -for csr in listCSRs+pmpcfg: - outFileName = 'checkpoint-'+csr.upper() - outFile = open(outDir+outFileName, 'w') - outFile.close() - -# Initial State for Main Loop -currState = 'regFile' -regFileIndex = 0 -outFileName = 'checkpoint-RF' -outFile = open(outDir+outFileName, 'w') - -# Main Loop -with open(stateGDBpath, 'r') as stateGDB: - for line in stateGDB: - line = tokenize(line) - name = line[0] - val = line[1][2:] - if (currState == 'regFile'): - if (regFileIndex == 0 and name != 'zero'): - print('Whoops! Expected regFile registers to come first, starting with zero') - exit(1) - if (name != 'zero'): - # Wally doesn't need to know zero=0 - outFile.write(val+'\n') - regFileIndex += 1 - if (regFileIndex == 32): - outFile.close() - currState = 'CSRs' - elif (currState == 'CSRs'): - if name in singleCSRs: - outFileName = 'checkpoint-'+name.upper() - outFile = open(outDir+outFileName, 'w') - outFile.write(val+'\n') - outFile.close() - elif name in thirtyTwoBitCSRs: - outFileName = 'checkpoint-'+name.upper() - outFile = open(outDir+outFileName, 'w') - val = int(val,16) & 0xffffffff - outFile.write(hex(val)[2:]+'\n') - outFile.close() - elif name.strip('0123456789') in listCSRs: - outFileName = 'checkpoint-'+name.upper().strip('0123456789') - outFile = open(outDir+outFileName, 'a') - outFile.write(val+'\n') - outFile.close() - elif name.strip('0123456789') in pmpcfg: - outFileName = 'checkpoint-'+name.upper().strip('0123456789') - outFile = open(outDir+outFileName, 'a') - fourPmp = int(val,16) - for i in range(0,4): - byte = (fourPmp >> 8*i) & 0xff - outFile.write(hex(byte)[2:]+'\n') - outFile.close() - -print("Finished parsing state!") diff --git a/tests/linux-testgen/testvector-generation/remove_dup.awk b/tests/linux-testgen/testvector-generation/remove_dup.awk deleted file mode 100755 index 7963d76a6..000000000 --- a/tests/linux-testgen/testvector-generation/remove_dup.awk +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/awk -f - -BEGIN{ - old = "first" -} - -{ - if($1 != old){ - if(old != "first"){ - print oldAll - } - } - old=$1 - oldAll=$0 -} - -END{ - print oldAll -} - From a8e8cfb83837f815ae84af376f688a8ae2c2dfa9 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 03:11:43 +0000 Subject: [PATCH 080/199] switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv --- pipelined/config/buildroot/wally-config.vh | 1 - pipelined/regression/regression-wally | 8 ++--- pipelined/regression/sim-buildroot | 2 +- pipelined/regression/sim-buildroot-batch | 7 ++--- pipelined/regression/wally-pipelined-batch.do | 2 +- pipelined/regression/wally-pipelined.do | 2 +- pipelined/testbench/testbench-linux.sv | 30 ++++++++++++------- 7 files changed, 28 insertions(+), 24 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index de6c910dc..7644eb1aa 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -30,7 +30,6 @@ `define FPGA 1 `define QEMU 1 `define LINUX_FIX_READ {'h10000005} -`define LINUX_TEST_VECTORS "../../tests/linux-testgen/linux-testvectors/" // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 17782b9de..63088afb6 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -48,19 +48,19 @@ def getBuildrootTC(short): INSTR_LIMIT = 100000 # multiple of 100000 MAX_EXPECTED = 246000000 if short: - BRcmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c <> 3); + $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR); + $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR); $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"}; - ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"}; + ProgramAddrMapFile = {linuxImageDir,"vmlinux.objdump.addr"}; + ProgramLabelMapFile = {linuxImageDir,"vmlinux.objdump.lab"}; + // initialize bootrom + memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); + readResult = $fread(dut.uncore.bootrom.bootrom.RAM,memFile); + $fclose(memFile); + // initialize RAM + memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); + readResult = $fread(dut.uncore.ram.ram.RAM,memFile); + $fclose(memFile); if (CHECKPOINT==0) begin // normal - $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.ram.ram.RAM); - traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); - traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); + traceFileM = $fopen({testvectorDir,"all.txt"}, "r"); + traceFileE = $fopen({testvectorDir,"all.txt"}, "r"); InstrCountW = '0; end else begin // checkpoint $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT); - checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir}; + checkpointDir = {testvectorDir,checkpointDir}; //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM); - ramFile = $fopen({checkpointDir,"ram.bin"}, "rb"); - readResult = $fread(dut.uncore.ram.ram.RAM,ramFile); - $fclose(ramFile); traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); InstrCountW = CHECKPOINT; From da4d7de2bd4a8644526e15b01bf2428286c99232 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 03:13:01 +0000 Subject: [PATCH 081/199] add option to not generate a trace when making checkpoints --- .../createGenCheckpointScript.py | 17 +++++++++--- linux/testvector-generation/genCheckpoint.sh | 26 ++++++++++++------- 2 files changed, 31 insertions(+), 12 deletions(-) diff --git a/linux/testvector-generation/createGenCheckpointScript.py b/linux/testvector-generation/createGenCheckpointScript.py index 3b1890a7a..02d1bcc76 100755 --- a/linux/testvector-generation/createGenCheckpointScript.py +++ b/linux/testvector-generation/createGenCheckpointScript.py @@ -1,7 +1,7 @@ #! /usr/bin/python3 import sys -if len(sys.argv) != 8: +if len(sys.argv) != 9: sys.exit("""Error createGenCheckpointScript.py expects 7 args: @@ -9,7 +9,8 @@ if len(sys.argv) != 8: - """) + + """) tcpPort=sys.argv[1] vmlinux=sys.argv[2] @@ -18,6 +19,7 @@ statePath=sys.argv[4] ramPath=sys.argv[5] checkPC=sys.argv[6] checkPCoccurences=sys.argv[7] +genTrace=sys.argv[8] GDBscript = f""" # GDB config @@ -54,7 +56,10 @@ set logging off # Log main memory to a file print "GDB storing RAM to {ramPath}\\n" dump binary memory {ramPath} 0x80000000 0xffffffff - +""" +if (genTrace=="1"): + GDBscript+=\ +""" # Generate Trace Until End maintenance packet Qqemu.Logging:1 # Do this by setting an impossible breakpoint @@ -62,6 +67,12 @@ b *0x1000 del 1 c """ +else: + GDBscript+=\ +""" +kill +q +""" GDBscriptFile = open("genCheckpoint.gdb",'w') GDBscriptFile.write(GDBscript) GDBscriptFile.close() diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 2478bbcc6..c027e0761 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -6,11 +6,12 @@ recordFile="$tvDir/all.qemu" traceFile="$tvDir/all.txt" # Parse Commandline Arg -if [ "$#" -ne 1 ]; then - echo "genCheckpoint requires 1 argument: " >&2 +if [ "$#" -ne 2 ]; then + echo "genCheckpoint requires 2 arguments: " >&2 exit 1 fi instrs=$1 +genTrace=$2 if ! [ "$instrs" -eq "$instrs" ] 2> /dev/null then echo "Error expected integer number of instructions, got $instrs" >&2 @@ -24,8 +25,14 @@ rawStateFile="$checkPtDir/stateGDB.txt" rawRamFile="$checkPtDir/ramGDB.bin" ramFile="$checkPtDir/ram.bin" -read -p "This scripts is going to create a checkpoint at $instrs instrs. -Is that what you wanted? (y/n) " -n 1 -r +if [ $genTrace -eq "1" ]; then + read -p "This scripts is going to create a checkpoint at $instrs instrs. + AND it's going to start generating a trace at that checkpoint. + Is that what you wanted? (y/n) " -n 1 -r +else + read -p "This scripts is going to create a checkpoint at $instrs instrs. + Is that what you wanted? (y/n) " -n 1 -r +fi echo if [[ $REPLY =~ ^[Yy]$ ]] then @@ -36,8 +43,10 @@ then sudo mkdir -p $checkPtDir sudo chown -R cad:users $checkPtDir sudo chmod -R a+rw $checkPtDir - sudo touch $outTraceFile - sudo chmod a+rw $outTraceFile + if [ $genTrace -eq "1" ]; then + sudo touch $outTraceFile + sudo chmod a+rw $outTraceFile + fi sudo touch $interruptsFile sudo chmod a+rw $interruptsFile sudo touch $rawStateFile @@ -56,8 +65,7 @@ then echo "It occurs ${occurences} times before the ${instrs}th instr." # Create GDB script because GDB is terrible at handling arguments / variables - ./createGenCheckpointScript.py $tcpPort $imageDir/vmlinux $instrs $rawStateFile $rawRamFile $pc $occurences - + ./createGenCheckpointScript.py $tcpPort $imageDir/vmlinux $instrs $rawStateFile $rawRamFile $pc $occurences $genTrace # GDB+QEMU echo "Starting QEMU in replay mode with attached GDB script at $(date +%H:%M:%S)" (qemu-system-riscv64 \ @@ -77,7 +85,7 @@ then ./fixBinMem "$rawRamFile" "$ramFile" #echo "Creating truncated trace at $(date +%H:%M:%S)" #tail -n+$instrs "$tvDir/$traceFile" > "$checkPtDir/$traceFile" - echo "Checkpoint completed at $(date +%H:%M:%S)" + read -p "Checkpoint completed at $(date +%H:%M:%S)" -n 1 -r # Cleanup echo "Elevating permissions to restrict write access to $checkPtDir" From d2fa5fa645cca2bec394e5a2638cdc47adf28391 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 03:24:23 +0000 Subject: [PATCH 082/199] buildroot graphical sim bugfix --- pipelined/regression/wally-pipelined.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index e50173849..a90eeeb66 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -34,7 +34,7 @@ vlib work if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084 #-- Run the Simulation From 3eb229cda53e58313afe9e4620e63d681530e14c Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 03:38:48 +0000 Subject: [PATCH 083/199] copy over truncated trace into checkpoint if not freshly generating a trace --- linux/testvector-generation/genCheckpoint.sh | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index c027e0761..834ef6bb6 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -43,10 +43,8 @@ then sudo mkdir -p $checkPtDir sudo chown -R cad:users $checkPtDir sudo chmod -R a+rw $checkPtDir - if [ $genTrace -eq "1" ]; then - sudo touch $outTraceFile - sudo chmod a+rw $outTraceFile - fi + sudo touch $outTraceFile + sudo chmod a+rw $outTraceFile sudo touch $interruptsFile sudo chmod a+rw $interruptsFile sudo touch $rawStateFile @@ -83,8 +81,10 @@ then echo "Changing Endianness at $(date +%H:%M:%S)" make fixBinMem ./fixBinMem "$rawRamFile" "$ramFile" - #echo "Creating truncated trace at $(date +%H:%M:%S)" - #tail -n+$instrs "$tvDir/$traceFile" > "$checkPtDir/$traceFile" + if [ $genTrace -ne "1" ]; then + echo "Copying over a truncated trace" + tail -n+$instrs $traceFile > $outTraceFile + fi read -p "Checkpoint completed at $(date +%H:%M:%S)" -n 1 -r # Cleanup From eaa0fa8e3f91dfb6aba80f76dde12c6f6f3d082e Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 1 Mar 2022 03:48:31 +0000 Subject: [PATCH 084/199] checkpoint sweep script -- not sure if this deserves to be on the repo in the long run, but it is helpful --- linux/testvector-generation/checkpointSweep.sh | 5 +++++ 1 file changed, 5 insertions(+) create mode 100755 linux/testvector-generation/checkpointSweep.sh diff --git a/linux/testvector-generation/checkpointSweep.sh b/linux/testvector-generation/checkpointSweep.sh new file mode 100755 index 000000000..74ed9ecf5 --- /dev/null +++ b/linux/testvector-generation/checkpointSweep.sh @@ -0,0 +1,5 @@ +for index in {450..500} +do + instrs=$(($index*1000000)) + echo "y" | nice -n 5 ./genCheckpoint.sh $instrs 0 +done From 0693f7667672a931f99a7adc412c78d191ac94c3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 1 Mar 2022 18:02:45 +0000 Subject: [PATCH 085/199] Fixed march compiling privileged tests to support AMO tests. --- .../riscv-test-suite/rv32i_m/privilege/Makefile | 2 +- .../riscv-test-suite/rv64i_m/privilege/Makefile | 2 +- .../riscv-test-suite/rv64i_m/privilege/Makefrag | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile index fb2c55ad6..e177848be 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile @@ -1,3 +1,3 @@ include ../../Makefile.include -$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) +$(eval $(call compile_template,-march=rv32iac -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile index c5a3eabd4..d70717f01 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile @@ -1,3 +1,3 @@ include ../../Makefile.include -$(eval $(call compile_template,-march=rv64i -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) +$(eval $(call compile_template,-march=rv64iac -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index bdfaaa657..4b60965c2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -37,6 +37,7 @@ rv64i_sc_tests = \ WALLY-misa-01 \ WALLY-scratch-01 \ WALLY-sscratch-s-01 \ + WALLY-AMO \ # Don't simulate these because they rely on SoC features that Wally does not offer. target_tests_nosim = \ From 0ecfff7e3af84fdbc69dbf5ae6388b9db06731f8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 1 Mar 2022 20:58:08 +0000 Subject: [PATCH 086/199] FMA project ready to start --- pipelined/src/fma/fma.do | 14 ++-- pipelined/src/fma/fma16.sv | 143 ++------------------------------ pipelined/src/fma/sim-fma-batch | 1 + 3 files changed, 17 insertions(+), 141 deletions(-) create mode 100755 pipelined/src/fma/sim-fma-batch diff --git a/pipelined/src/fma/fma.do b/pipelined/src/fma/fma.do index 6f53eacce..001ae9730 100644 --- a/pipelined/src/fma/fma.do +++ b/pipelined/src/fma/fma.do @@ -12,12 +12,12 @@ vlog -lint -work worklib fma16.sv testbench.sv vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt vsim -lib worklib testbenchopt -add wave sim:/testbench/clk -add wave sim:/testbench/reset -add wave sim:/testbench/x -add wave sim:/testbench/y -add wave sim:/testbench/z -add wave sim:/testbench/result -add wave sim:/testbench/rexpected +add wave sim:/testbench_fma16/clk +add wave sim:/testbench_fma16/reset +add wave sim:/testbench_fma16/x +add wave sim:/testbench_fma16/y +add wave sim:/testbench_fma16/z +add wave sim:/testbench_fma16/result +add wave sim:/testbench_fma16/rexpected run -all \ No newline at end of file diff --git a/pipelined/src/fma/fma16.sv b/pipelined/src/fma/fma16.sv index d2f34430a..70d06a771 100644 --- a/pipelined/src/fma/fma16.sv +++ b/pipelined/src/fma/fma16.sv @@ -5,145 +5,20 @@ // Operation: general purpose multiply, add, fma, with optional negation // If mul=1, p = x * y. Else p = x. // If add=1, result = p + z. Else result = p. -// If negp or negz = 1, negate p or z to handle negations and subtractions -// fadd: mul = 0, add = 1, negp = negz = 0 -// fsub: mul = 0, add = 1, negp = 0, negz = 1 -// fmul: mul = 1, add = 0, negp = 0, negz = 0 -// fma: mul = 1, add = 1, negp = 0, negz = 0 +// If negr or negz = 1, negate result or z to handle negations and subtractions +// fadd: mul = 0, add = 1, negr = negz = 0 +// fsub: mul = 0, add = 1, negr = 0, negz = 1 +// fmul: mul = 1, add = 0, negr = 0, negz = 0 +// fmadd: mul = 1, add = 1, negr = 0, negz = 0 +// fmsub: mul = 1, add = 1, negr = 0, negz = 1 +// fnmadd: mul = 1, add = 1, negr = 1, negz = 0 +// fnmsub: mul = 1, add = 1, negr = 1, negz = 1 module fma16( input logic [15:0] x, y, z, - input logic mul, add, negp, negz, + input logic mul, add, negr, negz, input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn output logic [15:0] result); - logic [10:0] xm, ym, zm; - logic [4:0] xe, ye, ze; - logic xs, ys, zs; - logic zs1; // sign before optional negation - logic [21:0] pm; - logic [5:0] pe; - logic ps; // sign of product - logic [22:0] rm; - logic [6:0] re; - logic rs; - - unpack16 unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs - signadj16 signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations - mult16 m(mul, xm, ym, xe, ye, pm, pe); // p = x * y - add16 a(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p - postproc16 post(roundmode, rm, re, rs, result); // normalize, round, pack endmodule -module mult16( - input logic mul, - input logic [10:0] xm, ym, - input logic [4:0] xe, ye, - output logic [21:0] pm, - output logic [5:0] pe); - - // only multiply if mul = 1 - assign pm = mul ? xm * ym : {1'b0, xm, 10'b0}; // multiply mantiassas - assign pe = mul ? xe + ye : {1'b0, xe}; -endmodule - -module add16( - input logic add, - input logic [21:0] pm, - input logic [10:0] zm, - input logic [5:0] pe, - input logic [4:0] ze, - input logic ps, zs, - output logic [22:0] rm, - output logic [6:0] re, - output logic rs); - - logic [22:0] arm; - logic [6:0] are; - logic ars; - - /* - alignshift as(pe, ze, zm, zmaligned); - condneg cnp(pm, ps, pmn); - condneg cnz(zm, zs, zmn); - assign - */ - - // add or pass product through - assign rm = add ? arm : {1'b0, pm}; - assign re = add ? are : {1'b0, pe}; - assign rs = add ? ars : ps; -endmodule - -module postproc16( - input logic [1:0] roundmode, - input logic [22:0] rm, - input logic [6:0] re, - input logic rs, - output logic [15:0] result); - - logic [9:0] uf, uff; - logic [6:0] ue; - logic [6:0] ueb, uebiased; - - always_comb - if (rm[21]) begin // normalization right shift by 1 and bump up exponent; - ue = re + 7'b1; - uf = rm[20:11]; - end else begin // no normalization shift needed - ue = re; - uf = rm[19:10]; - end - - // overflow - always_comb begin - ueb = ue-7'd15; - if (ue >= 7'd46) begin // overflow -/* uebiased = 7'd30; - uff = 10'h3ff; */ - end else begin - uebiased = ue-7'd15; - uff = uf; - end - end - - assign result = {rs, uebiased[4:0], uff}; - - // add special case handling for zeros, NaN, Infinity -endmodule - -module signadj16( - input logic negx, negz, - input logic xs, ys, zs1, - output logic ps, zs); - - assign ps = xs ^ ys ^ negx; // sign of product - assign zs = zs1 ^ negz; // -endmodule - -module unpack16( - input logic [15:0] x, y, z, - output logic [10:0] xm, ym, zm, - output logic [4:0] xe, ye, ze, - output logic xs, ys, zs); - - unpacknum16 upx(x, xm, xe, xs); - unpacknum16 upy(y, ym, ye, ys); - unpacknum16 upz(z, zm, ze, zs); -endmodule - -module unpacknum16( - input logic [15:0] num, - output logic [10:0] m, - output logic [4:0] e, - output logic s); - - logic [9:0] f; // fraction without leading 1 - logic [4:0] eb; // biased exponent - - assign {s, eb, f} = num; // pull bit fields out of floating-point number - assign m = {1'b1, f}; // prepend leading 1 to fraction - assign e = eb; // leave bias in exponent *** -endmodule - - diff --git a/pipelined/src/fma/sim-fma-batch b/pipelined/src/fma/sim-fma-batch new file mode 100755 index 000000000..01c2472e9 --- /dev/null +++ b/pipelined/src/fma/sim-fma-batch @@ -0,0 +1 @@ +vsim -c -do "do fma.do" From e3ae7fabc708d75609a99cfe12f13a1cb041f4b8 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 05:41:20 +0000 Subject: [PATCH 087/199] fix AMO test --- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S index c99065e49..b12297902 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-AMO.S @@ -243,15 +243,15 @@ RVTEST_DATA_END RVMODEL_DATA_BEGIN # signature output wally_signature: -.fill 6, 8, -1 +.fill 36, 8, -1 #ifdef rvtest_mtrap_routine -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef +#mtrap_sigptr: +# .fill 64*(XLEN/32),4,0xdeadbeef #endif #ifdef rvtest_gpr_save -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef +#gpr_save: +# .fill 32*(XLEN/32),4,0xdeadbeef #endif RVMODEL_DATA_END From 29179c67871e1119cd3d93fda31fd17bd701fd56 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 07:09:37 +0000 Subject: [PATCH 088/199] add LRSC test and add wally64a to regression --- pipelined/regression/regression-wally | 2 +- pipelined/testbench/testbench.sv | 2 +- pipelined/testbench/tests.vh | 8 +- .../rv64i_m/privilege/Makefrag | 1 + .../references/WALLY-LRSC.reference_output | 24 +++ .../rv64i_m/privilege/src/WALLY-LRSC.S | 137 ++++++++++++++++++ 6 files changed, 168 insertions(+), 6 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-LRSC.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-LRSC.S diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 63088afb6..4c2d0d8b6 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -62,7 +62,7 @@ tc = TestCase( grepstr="400100000 instructions") #configs.append(tc) #temporarily removed until I make this checkpoint -tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] +tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] for test in tests64gc: tc = TestCase( name=test, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 7c582280f..c9dee2d31 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -91,7 +91,7 @@ logic [3:0] dummy; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64m": if (`M_SUPPORTED) tests = imperas64m; - "imperas64a": if (`A_SUPPORTED) tests = imperas64a; + "wally64a": if (`A_SUPPORTED) tests = wally64a; "imperas64c": if (`C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "testsBP64": tests = testsBP64; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index e8f8fd12d..1f2d006bd 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -44,10 +44,10 @@ string tvpaths[] = '{ "coremark.bare.riscv", "100000" }; - string imperas64a[] = '{ - `MYIMPERASTEST, - "rv64a/WALLY-AMO", "2110", - "rv64a/WALLY-LRSC", "2110" + string wally64a[] = '{ + `WALLYTEST, + "rv64i_m/privilege/WALLY-AMO", "2210", + "rv64i_m/privilege/WALLY-LRSC", "2410" }; string imperas32a[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 4b60965c2..adf328390 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -38,6 +38,7 @@ rv64i_sc_tests = \ WALLY-scratch-01 \ WALLY-sscratch-s-01 \ WALLY-AMO \ + WALLY-LRSC \ # Don't simulate these because they rely on SoC features that Wally does not offer. target_tests_nosim = \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-LRSC.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-LRSC.reference_output new file mode 100644 index 000000000..88088c5a9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-LRSC.reference_output @@ -0,0 +1,24 @@ +fffffffe +ffffffff +00000000 +00000000 +0000002a +00000000 +fffffffd +ffffffff +00000001 +00000000 +0000002a +00000000 +fffffffb +fffffff7 +00000000 +00000000 +0000002c +00000000 +ffffffef +ffffffdf +00000001 +00000000 +0000002c +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-LRSC.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-LRSC.S new file mode 100644 index 000000000..b38331a09 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-LRSC.S @@ -0,0 +1,137 @@ +/////////////////////////////////////////// +// WALLY-LRSC.S +// +// Tests Atomic LR / SC instructions +// +// David_Harris@hmc.edu 7 March 2021 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # Addresses for test data and results + la x6, wally_signature + la x31, test_data + + # Testcase 0: Do a successful load-reserved / store conditional word operation + li x11, 42 + lr.w x10, (x31) + sc.w x12, x11, (x31) + lw x13, 0(x31) + sd x10, 0(x6) # should be fffffffffffffffe (sign extended value read from test data) + sd x12, 8(x6) # should be 0000000000000000 (sc succeeded) + sd x13, 16(x6) # should be 000000000000002A (value written by SC, in hex) + + # Testcase 1: Do an unsuccessful load-reserved / store conditional word operation + addi x6, x6, 24 + addi x30, x31, 4 + li x11, 43 + lr.w x10, (x30) + sc.w x12, x11, (x31) # should fail because not reserved + lw x13, 0(x31) + sd x10, 0(x6) # should be fffffffffffffffd (sign extended value read from test data) + sd x12, 8(x6) # should be 0000000000000001 (sc failed) + sd x13, 16(x6) # should be 000000000000002A (previous value written by sc) + + # Testcase 2: Do a successful load-reserved / store conditional doubleword operation + addi x6, x6, 24 + addi x31, x30, 4 + li x11, 44 + lr.d x10, (x31) + sc.d x12, x11, (x31) + lw x13, 0(x31) + sd x10, 0(x6) # should be 0xfffffff7fffffffb (value read from test data) + sd x12, 8(x6) # should be 0000000000000000 (sc succeeded) + sd x13, 16(x6) # should be 000000000000002C (value written by SC) + + # Testcase 3: Do an unsuccessful load-reserved / store conditional doubleword operation + addi x6, x6, 24 + addi x30, x31, 8 + li x11, 45 + lr.d x10, (x30) + sc.d x12, x11, (x31) # should fail because not reserved + lw x13, 0(x31) + sd x10, 0(x6) # should be 0xffffffdfffffffef (sign extended value read from test data) + sd x12, 8(x6) # should be 0000000000000001 (sc failed) + sd x13, 16(x6) # should be 000000000000002C (previous value written by sc) + + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 8 +test_data: + + .dword 0xfffffffdfffffffe + .dword 0xfffffff7fffffffb + .dword 0xffffffdfffffffef + .dword 0xffffff7fffffffbf + .dword 0xfffffdfffffffeff + .dword 0xfffff7fffffffeff + .dword 0xffffdfffffffefff + .dword 0xffff7fffffffefff + .dword 0xfffdfffffffeffff + .dword 0xfff7fffffffbffff + .dword 0xffdfffffffefffff + .dword 0xff7fffffffbfffff + .dword 0xfdfffffffeffffff + .dword 0xf7fffffffeffffff + .dword 0xdfffffffefffffff + .dword 0x7fffffffefffffff + .dword 0x00000001ffffffff + .dword 0x0000000400000002 + .dword 0x0000001000000008 + .dword 0x0000004000000020 + .dword 0x0000010000000080 + .dword 0x0000040000000200 + .dword 0x0000100000000800 + .dword 0x0000400000002000 + .dword 0x0000000100008000 + .dword 0x0004000000000002 + .dword 0x0000001000080000 + .dword 0x0040000000000020 + .dword 0x0000010000800000 + .dword 0x0400000000000200 + .dword 0x0000100008000000 + .dword 0x4000000000002000 + .dword 0x0000000080000000 +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 12, 8, -1 + +RVMODEL_DATA_END From b6031bb15fc0e611b82db23e08a0be62b669bd27 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 16:00:19 +0000 Subject: [PATCH 089/199] fix buildroot checkpointing and add it back to regression --- pipelined/regression/regression-wally | 2 +- pipelined/testbench/testbench-linux.sv | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 4c2d0d8b6..9565c7295 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -60,7 +60,7 @@ tc = TestCase( variant="rv64gc", cmd="vsim > {} -c < Date: Wed, 2 Mar 2022 17:28:20 +0000 Subject: [PATCH 090/199] removed imperas-riscv-tests --- pipelined/src/fma/fma16_template.sv | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 pipelined/src/fma/fma16_template.sv diff --git a/pipelined/src/fma/fma16_template.sv b/pipelined/src/fma/fma16_template.sv new file mode 100644 index 000000000..70d06a771 --- /dev/null +++ b/pipelined/src/fma/fma16_template.sv @@ -0,0 +1,24 @@ +// fma16.sv +// David_Harris@hmc.edu 26 February 2022 +// 16-bit floating-point multiply-accumulate + +// Operation: general purpose multiply, add, fma, with optional negation +// If mul=1, p = x * y. Else p = x. +// If add=1, result = p + z. Else result = p. +// If negr or negz = 1, negate result or z to handle negations and subtractions +// fadd: mul = 0, add = 1, negr = negz = 0 +// fsub: mul = 0, add = 1, negr = 0, negz = 1 +// fmul: mul = 1, add = 0, negr = 0, negz = 0 +// fmadd: mul = 1, add = 1, negr = 0, negz = 0 +// fmsub: mul = 1, add = 1, negr = 0, negz = 1 +// fnmadd: mul = 1, add = 1, negr = 1, negz = 0 +// fnmsub: mul = 1, add = 1, negr = 1, negz = 1 + +module fma16( + input logic [15:0] x, y, z, + input logic mul, add, negr, negz, + input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn + output logic [15:0] result); + +endmodule + From 1bb73dad7dcb373390ae11c7362b03bb31c9fdfb Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 17:46:33 +0000 Subject: [PATCH 092/199] change main.config so that buildroot expects linux.config and busybox.config to be at $RISCV/buildroot --- linux/buildroot-config-src/main.config | 4 +- .../rv32i_m/privilege/Makefrag | 4 +- .../references/WALLY-AMO.reference_output | 20 ++ .../references/WALLY-LRSC.reference_output | 8 + .../rv32i_m/privilege/src/WALLY-AMO.S | 174 ++++++++++++++++++ .../rv32i_m/privilege/src/WALLY-LRSC.S | 115 ++++++++++++ 6 files changed, 322 insertions(+), 3 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-AMO.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-LRSC.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-AMO.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-LRSC.S diff --git a/linux/buildroot-config-src/main.config b/linux/buildroot-config-src/main.config index 060c8892e..bcdd727ff 100644 --- a/linux/buildroot-config-src/main.config +++ b/linux/buildroot-config-src/main.config @@ -430,7 +430,7 @@ BR2_LINUX_KERNEL_PATCH="" # BR2_LINUX_KERNEL_USE_DEFCONFIG is not set # BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="../buildroot-config-src/linux.config" +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="./linux.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="" BR2_LINUX_KERNEL_CUSTOM_LOGO_PATH="" BR2_LINUX_KERNEL_IMAGE=y @@ -473,7 +473,7 @@ BR2_LINUX_KERNEL_GZIP=y # Target packages # BR2_PACKAGE_BUSYBOX=y -BR2_PACKAGE_BUSYBOX_CONFIG="../buildroot-config-src/busybox.config" +BR2_PACKAGE_BUSYBOX_CONFIG="./busybox.config" BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="" # BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set # BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index 0b9dd696f..a4da7afc7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -35,7 +35,9 @@ rv32i_sc_tests = \ WALLY-minfo-01 \ WALLY-misa-01 \ WALLY-scratch-01 \ - WALLY-sscratch-s-01 + WALLY-sscratch-s-01 \ + WALLY-AMO \ + WALLY-LRSC target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-AMO.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-AMO.reference_output new file mode 100644 index 000000000..6d2c17395 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-AMO.reference_output @@ -0,0 +1,20 @@ +fffffffe +00000001 +fffffffb +fffffffd +ffffffef +000007ef +ffffffbf +ffffffff +fffffeff +fffffd7e +fffffeff +000007ff +ffffefff +ffffefff +ffffefff +ffffefff +fffeffff +000007fa +ffffffff +ffffffff diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-LRSC.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-LRSC.reference_output new file mode 100644 index 000000000..c40c4a22b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-LRSC.reference_output @@ -0,0 +1,8 @@ +fffffffe +00000000 +0000002a +fffffffd +00000001 +0000002a +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-AMO.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-AMO.S new file mode 100644 index 000000000..4d4d3fee9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-AMO.S @@ -0,0 +1,174 @@ +/////////////////////////////////////////// +// WALLY-AMO.S +// +// Tests Atomic AMO instructions +// +// David_Harris@hmc.edu 11 March 2021 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + la x31, test_data + + # Testcase 0: amoswap.w + li x7, 1 + amoswap.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffffe (sign extended from test data) + sw x9, 4(x6) # should be 00000001 (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 1: amoadd.w + li x7, 2 + amoadd.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffffb (sign extended from test data) + sw x9, 4(x6) # should be fffffffd (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 2: amoand.w + li x7, 0x7ff + amoand.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffffef (sign extended from test data) + sw x9, 4(x6) # should be 000007ef (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 3: amoor.w + li x7, 0x44 + amoor.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffffbf (sign extended from test data) + sw x9, 4(x6) # should be ffffffff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 4: amoxor.w + li x7, 0x381 + amoxor.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffeff (sign extended from test data) + sw x9, 4(x6) # should be fffffd7e (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 5: amomax.w + li x7, 0x7ff + amomax.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffffeff (sign extended from test data) + sw x9, 4(x6) # should be 000007ff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 6: amomin.w + li x7, 0x7fd + amomin.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffefff (sign extended from test data) + sw x9, 4(x6) # should be ffffefff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 7: amomaxu.w + li x7, 0x7fb + amomaxu.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be ffffefff (sign extended from test data) + sw x9, 4(x6) # should be ffffefff (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + + # Testcase 8: amominu.w + li x7, 0x7fa + amominu.w x8, x7, (x31) + lw x9, 0(x31) + sw x8, 0(x6) # should be fffeffff (sign extended from test data) + sw x9, 4(x6) # should be 000007fa (stored by amo) + addi x31, x31, 8 + addi x6, x6, 8 + # --------------------------------------------------------------------------------------------- +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 8 +test_data: + .dword 0xfffffffdfffffffe + .dword 0xfffffff7fffffffb + .dword 0xffffffdfffffffef + .dword 0xffffff7fffffffbf + .dword 0xfffffdfffffffeff + .dword 0xfffff7fffffffeff + .dword 0x0fffdfffffffefff + .dword 0xffff7fffffffefff + .dword 0x3ffdfffffffeffff + .dword 0xfff7fffffffbffff + .dword 0xffdfffffffefffff + .dword 0xff7fffffffbfffff + .dword 0xfdfffffffeffffff + .dword 0xf7fffffffeffffff + .dword 0xdfffffffefffffff + .dword 0x7fffffffefffffff + .dword 0x00000001ffffffff + .dword 0x0000000400000002 + .dword 0x0000001000000008 + .dword 0x0000004000000020 + .dword 0x0000010000000080 + .dword 0x0000040000000200 + .dword 0x0000100000000800 + .dword 0x0000400000002000 + .dword 0x0000000100008000 + .dword 0x0004000000000002 + .dword 0x0000001000080000 + .dword 0x0040000000000020 + .dword 0x0000010000800000 + .dword 0x0400000000000200 + .dword 0x0000100008000000 + .dword 0x4000000000002000 + .dword 0x0000000080000000 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 20, 4, -1 +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-LRSC.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-LRSC.S new file mode 100644 index 000000000..4078920bd --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-LRSC.S @@ -0,0 +1,115 @@ +/////////////////////////////////////////// +// WALLY-LRSC.S +// +// Tests Atomic LR / SC instructions +// +// David_Harris@hmc.edu 11 March 2021 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + + # --------------------------------------------------------------------------------------------- + # address for test results + la x6, wally_signature + la x31, test_data + + # Testcase 0: Do a successful load-reserved / store conditional word operation + li x11, 42 + lr.w x10, (x31) + sc.w x12, x11, (x31) + lw x13, 0(x31) + sw x10, 0(x6) # should be fffffffe (sign extended value read from test data) + sw x12, 4(x6) # should be 00000000 (sc succeeded) + sw x13, 8(x6) # should be 0000002A (value written by SC, in hex) + + # Testcase 1: Do an unsuccessful load-reserved / store conditional word operation + addi x6, x6, 12 + addi x30, x31, 4 + li x11, 43 + lr.w x10, (x30) + sc.w x12, x11, (x31) # should fail because not reserved + lw x13, 0(x31) + sw x10, 0(x6) # should be fffffffd (sign extended value read from test data) + sw x12, 4(x6) # should be 00000001 (sc failed) + sw x13, 8(x6) # should be 0000002A (previous value written by sc) + + # --------------------------------------------------------------------------------------------- + +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 8 +test_data: + .dword 0xfffffffdfffffffe + .dword 0xfffffff7fffffffb + .dword 0xffffffdfffffffef + .dword 0xffffff7fffffffbf + .dword 0xfffffdfffffffeff + .dword 0xfffff7fffffffeff + .dword 0xffffdfffffffefff + .dword 0xffff7fffffffefff + .dword 0xfffdfffffffeffff + .dword 0xfff7fffffffbffff + .dword 0xffdfffffffefffff + .dword 0xff7fffffffbfffff + .dword 0xfdfffffffeffffff + .dword 0xf7fffffffeffffff + .dword 0xdfffffffefffffff + .dword 0x7fffffffefffffff + .dword 0x00000001ffffffff + .dword 0x0000000400000002 + .dword 0x0000001000000008 + .dword 0x0000004000000020 + .dword 0x0000010000000080 + .dword 0x0000040000000200 + .dword 0x0000100000000800 + .dword 0x0000400000002000 + .dword 0x0000000100008000 + .dword 0x0004000000000002 + .dword 0x0000001000080000 + .dword 0x0040000000000020 + .dword 0x0000010000800000 + .dword 0x0400000000000200 + .dword 0x0000100008000000 + .dword 0x4000000000002000 + .dword 0x0000000080000000 + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 6, 4, -1 +RVMODEL_DATA_END From 4fe35aadf2b010f9157e8f6ce785dcde060980f9 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 17:54:55 +0000 Subject: [PATCH 093/199] add rv32a tests to regression --- pipelined/regression/regression-wally | 2 +- pipelined/testbench/testbench.sv | 2 +- pipelined/testbench/tests.vh | 73 ++++++++++++++------------- 3 files changed, 39 insertions(+), 38 deletions(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 9565c7295..b47aa7b63 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -70,7 +70,7 @@ for test in tests64gc: cmd="vsim > {} -c < Date: Wed, 2 Mar 2022 18:31:10 +0000 Subject: [PATCH 094/199] add CSRs to waveview --- pipelined/regression/wave.do | 72 +++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 29 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index aa078369d..b4d2d1b60 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -14,30 +14,30 @@ add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/StoreStallD add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -63,6 +63,24 @@ add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIE_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIP_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -351,8 +369,6 @@ add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SU add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK @@ -454,7 +470,6 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM -add wave -noupdate /testbench/dut/core/priv/priv/csr/MEPC_REGW add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr @@ -493,7 +508,6 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/NextPTE -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWWrite add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 5} {0 ns} 0} @@ -512,4 +526,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {224 ns} +WaveRestoreZoom {0 ns} {496 ns} From 6d7bc928afaf08e0e1e640366a8b5197a685425f Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 22:15:57 +0000 Subject: [PATCH 095/199] update SXL UXL bits in MSTATUS to match new QEMU trace --- pipelined/src/privileged/csrsr.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index e1f653b49..db77115f2 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -84,8 +84,8 @@ module csrsr ( assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported // SXL and UXL bits only matter for RV64. Set to 10 for RV64 if mode is supported, or 0 if not - assign STATUS_SXL = `S_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if supervisor mode supported - assign STATUS_UXL = `U_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if user mode supported + assign STATUS_SXL = `S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported + assign STATUS_UXL = `U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported assign STATUS_SUM = `S_SUPPORTED & `VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP From 11423d1d175e1cec3058ae8b717ab395b678aa53 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 22:44:19 +0000 Subject: [PATCH 096/199] but apparently QEMU doesn't show UXL in SSTATUS --- pipelined/src/privileged/csrsr.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index db77115f2..d7636a5ea 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -61,7 +61,7 @@ module csrsr ( STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0, STATUS_SPP, STATUS_MPIE, 1'b0, STATUS_SPIE, STATUS_UPIE, STATUS_MIE, 1'b0, STATUS_SIE, STATUS_UIE}; - assign SSTATUS_REGW = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ STATUS_UXL, /*9'b0, */ 12'b0, + assign SSTATUS_REGW = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ {`QEMU ? 2'b0 : STATUS_UXL}, /*9'b0, */ 12'b0, /*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0, STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE, 1'b0*/ 2'b0, STATUS_SPIE, STATUS_UPIE, From 87aad1d9535321280e61109f12257e9b20421cac Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Mar 2022 23:44:39 +0000 Subject: [PATCH 097/199] fix peripheral test and add it to regression --- pipelined/regression/regression-wally | 2 +- pipelined/testbench/tests.vh | 3 +-- .../rv64i_m/privilege/src/WALLY-PERIPH.S | 16 ++++++++-------- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index b47aa7b63..2e9e123f8 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -62,7 +62,7 @@ tc = TestCase( grepstr="400100000 instructions") configs.append(tc) -tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] +tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64priv", "wally64periph"] # , "imperas64mmu" "wally64i", #, "testsBP64"] for test in tests64gc: tc = TestCase( name=test, diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 7bcb22c3e..ca472207a 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1466,7 +1466,6 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-MSTATUS", "002070", "rv64i_m/privilege/WALLY-MTVEC", "002070", "rv64i_m/privilege/WALLY-MVENDORID", "003070", - "rv64i_m/privilege/WALLY-PERIPH", "0020f0", "rv64i_m/privilege/WALLY-PMA", "004080", "rv64i_m/privilege/WALLY-PMP", "004080", "rv64i_m/privilege/WALLY-SCAUSE", "002070", @@ -1478,7 +1477,7 @@ string imperas32f[] = '{ string wally64periph[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-PERIPH", "3110" + "rv64i_m/privilege/WALLY-PERIPH", "22f0" }; string wally32e[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S index de9e671ba..9a42f2193 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S @@ -33,7 +33,8 @@ RVTEST_CODE_BEGIN # --------------------------------------------------------------------------------------------- j main_code - +# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary +.align 2 ################### ################### trap_handler: ##### @@ -801,13 +802,6 @@ RVTEST_DATA_BEGIN .align 3 stack: .fill 16, 8, 0xdeadbeef -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -# signature output -wally_signature: -.fill 0x200, 8, 0x00000000 - #ifdef rvtest_mtrap_routine mtrap_sigptr: .fill 64*(XLEN/32),4,0xdeadbeef @@ -817,4 +811,10 @@ mtrap_sigptr: gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 0x200, 8, 0x00000000 RVMODEL_DATA_END From 8e83aaeced04b959ecb52753d2b31da2cd7f2b73 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 2 Mar 2022 23:47:01 +0000 Subject: [PATCH 098/199] fma file fixes --- pipelined/src/fma/fma16.sv | 24 ------------------------ pipelined/src/fma/fma16_template.sv | 24 ------------------------ 2 files changed, 48 deletions(-) delete mode 100644 pipelined/src/fma/fma16.sv delete mode 100644 pipelined/src/fma/fma16_template.sv diff --git a/pipelined/src/fma/fma16.sv b/pipelined/src/fma/fma16.sv deleted file mode 100644 index 70d06a771..000000000 --- a/pipelined/src/fma/fma16.sv +++ /dev/null @@ -1,24 +0,0 @@ -// fma16.sv -// David_Harris@hmc.edu 26 February 2022 -// 16-bit floating-point multiply-accumulate - -// Operation: general purpose multiply, add, fma, with optional negation -// If mul=1, p = x * y. Else p = x. -// If add=1, result = p + z. Else result = p. -// If negr or negz = 1, negate result or z to handle negations and subtractions -// fadd: mul = 0, add = 1, negr = negz = 0 -// fsub: mul = 0, add = 1, negr = 0, negz = 1 -// fmul: mul = 1, add = 0, negr = 0, negz = 0 -// fmadd: mul = 1, add = 1, negr = 0, negz = 0 -// fmsub: mul = 1, add = 1, negr = 0, negz = 1 -// fnmadd: mul = 1, add = 1, negr = 1, negz = 0 -// fnmsub: mul = 1, add = 1, negr = 1, negz = 1 - -module fma16( - input logic [15:0] x, y, z, - input logic mul, add, negr, negz, - input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn - output logic [15:0] result); - -endmodule - diff --git a/pipelined/src/fma/fma16_template.sv b/pipelined/src/fma/fma16_template.sv deleted file mode 100644 index 70d06a771..000000000 --- a/pipelined/src/fma/fma16_template.sv +++ /dev/null @@ -1,24 +0,0 @@ -// fma16.sv -// David_Harris@hmc.edu 26 February 2022 -// 16-bit floating-point multiply-accumulate - -// Operation: general purpose multiply, add, fma, with optional negation -// If mul=1, p = x * y. Else p = x. -// If add=1, result = p + z. Else result = p. -// If negr or negz = 1, negate result or z to handle negations and subtractions -// fadd: mul = 0, add = 1, negr = negz = 0 -// fsub: mul = 0, add = 1, negr = 0, negz = 1 -// fmul: mul = 1, add = 0, negr = 0, negz = 0 -// fmadd: mul = 1, add = 1, negr = 0, negz = 0 -// fmsub: mul = 1, add = 1, negr = 0, negz = 1 -// fnmadd: mul = 1, add = 1, negr = 1, negz = 0 -// fnmsub: mul = 1, add = 1, negr = 1, negz = 1 - -module fma16( - input logic [15:0] x, y, z, - input logic mul, add, negr, negz, - input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn - output logic [15:0] result); - -endmodule - From 6431ad4a8b976ec7c75c72080a09f002f6255086 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 3 Mar 2022 15:38:08 +0000 Subject: [PATCH 099/199] Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas --- pipelined/regression/Makefile | 2 +- pipelined/regression/makefile-memfile | 4 +++- pipelined/src/fma/fma.do | 2 +- pipelined/src/fma/{testbench.sv => testbench.v} | 0 4 files changed, 5 insertions(+), 3 deletions(-) rename pipelined/src/fma/{testbench.sv => testbench.v} (100%) diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile index 0176b7eca..302ee4a92 100644 --- a/pipelined/regression/Makefile +++ b/pipelined/regression/Makefile @@ -5,7 +5,7 @@ make allclean: make clean: make clean -C ../../addins/riscv-arch-test make clean -C ../../tests/wally-riscv-arch-test - make allclean -C ../../tests/imperas-riscv-tests +# make allclean -C ../../tests/imperas-riscv-tests make all: # *** Build old tests/imperas-riscv-tests for now; diff --git a/pipelined/regression/makefile-memfile b/pipelined/regression/makefile-memfile index 030cf8d57..33af19538 100644 --- a/pipelined/regression/makefile-memfile +++ b/pipelined/regression/makefile-memfile @@ -2,8 +2,10 @@ ROOT := ../.. SUFFIX := work ARCHDIR := $(ROOT)/addins/riscv-arch-test WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test +# IMPERASDIR := $(ROOT)/tests/imperas-riscv-tests +# ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX) IMPERASDIR := $(ROOT)/tests/imperas-riscv-tests -ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX) +ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) ELFFILES ?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf") MEMFILES ?= $(ELFFILES:.elf=.elf.memfile) diff --git a/pipelined/src/fma/fma.do b/pipelined/src/fma/fma.do index 001ae9730..9a7de1267 100644 --- a/pipelined/src/fma/fma.do +++ b/pipelined/src/fma/fma.do @@ -8,7 +8,7 @@ onbreak {resume} # create library vlib worklib -vlog -lint -work worklib fma16.sv testbench.sv +vlog -lint -work worklib fma16.sv testbench.v vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt vsim -lib worklib testbenchopt diff --git a/pipelined/src/fma/testbench.sv b/pipelined/src/fma/testbench.v similarity index 100% rename from pipelined/src/fma/testbench.sv rename to pipelined/src/fma/testbench.v From db7d3cfc0ec09c97e1569b180725a2a89cbd25dd Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 3 Mar 2022 11:28:22 -0800 Subject: [PATCH 100/199] Updated Makefile to reflect new Linux and Imperas situation. Updated setup to include Synopsys license file. --- Makefile | 6 +++--- setup.sh | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 0544fb8d1..1c67aad38 100644 --- a/Makefile +++ b/Makefile @@ -9,9 +9,9 @@ install: cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include - cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory - rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe - ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe + #cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory + #rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe + #ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe regression: make -C pipelined/regression diff --git a/setup.sh b/setup.sh index 3ec6c8408..b1425d7e1 100755 --- a/setup.sh +++ b/setup.sh @@ -24,7 +24,7 @@ export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verila export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler -# *** license +export SNPSLMD_LICENSE_FILE=27020@134.173.38.214 # Imperas; *** remove if not using; *** fix paths export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH # *** maybe take this out based on Imperas From 79ff8d3c80c88c2eafad78b80b5e191b29805ad5 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 4 Mar 2022 00:06:18 +0000 Subject: [PATCH 101/199] remove imperas32p tests --- pipelined/regression/regression-wally | 2 +- pipelined/testbench/testbench.sv | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 2e9e123f8..c638ed3c2 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -70,7 +70,7 @@ for test in tests64gc: cmd="vsim > {} -c < Date: Fri, 4 Mar 2022 00:07:31 +0000 Subject: [PATCH 102/199] LSU/Cache code review notes --- pipelined/src/cache/cache.sv | 1 - pipelined/src/cache/cachereplacementpolicy.sv | 1 + pipelined/src/cache/subcachelineread.sv | 4 +-- pipelined/src/ieu/controller.sv | 4 +-- pipelined/src/lsu/atomic.sv | 14 +++++----- pipelined/src/lsu/busdp.sv | 13 +++++---- pipelined/src/lsu/interlockfsm.sv | 5 ++-- pipelined/src/lsu/lsu.sv | 28 +++++++++++-------- pipelined/src/lsu/lsuvirtmen.sv | 5 ++-- 9 files changed, 41 insertions(+), 34 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 8a255c079..c9da5078f 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -171,7 +171,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( assign SetDirtyWay = SetDirty ? SelectedWay : '0; assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; - ///////////////////////////////////////////////////////////////////////////////////////////// // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index 80fc251c7..cb33480dc 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -46,6 +46,7 @@ module cachereplacementpolicy logic [SETLEN-1:0] RAdrD; logic LRUWriteEnD; + // *** high priority to clean up initial begin assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported"); end diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 111ec506f..9894b3665 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -54,12 +54,12 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( assign ReadDataLinePad = {Pad, ReadDataLine}; end else assign ReadDataLinePad = ReadDataLine; - genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux - assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)]; + assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)]; end // variable input mux + // *** maybe remove REPLAY config later after deciding which way is best assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]]; if(!`REPLAY) begin flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved); diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index 646d87074..c26551620 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -51,12 +51,12 @@ module controller( output logic [2:0] Funct3E, output logic MDUE, W64E, output logic JumpE, + output logic SCE, + output logic [1:0] AtomicE, // Memory stage control signals input logic StallM, FlushM, output logic [1:0] MemRWM, output logic CSRReadM, CSRWriteM, PrivilegedM, - output logic SCE, - output logic [1:0] AtomicE, output logic [1:0] AtomicM, output logic [2:0] Funct3M, output logic RegWriteM, // for Hazard Unit diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index 1191df350..6575a3bf6 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -46,14 +46,14 @@ module atomic ( output logic SquashSCW, output logic [1:0] LSURWM); - logic [`XLEN-1:0] AMOResult; + logic [`XLEN-1:0] AMOResult; logic MemReadM; - amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), - .result(AMOResult)); - mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); - assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; - lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, - .SquashSCW, .LSURWM); + amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), + .result(AMOResult)); + mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); + assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; // *** is DTLBMiss needed; might be par tof ignorerequest + lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, + .SquashSCW, .LSURWM); endmodule diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 66e41675d..49907bb5c 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -65,9 +65,11 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic BusStall, output logic BusCommittedM); - localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; + + // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem + // *** better name than DCacheBusWriteData genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer logic [WORDSPERLINE-1:0] CaptureWord; @@ -80,9 +82,8 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); - busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) - busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, - .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, - .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); - + busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( + .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, + .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, + .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); endmodule diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 43bf3d284..2475c3c2d 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -96,6 +96,9 @@ module interlockfsm( endcase end // always_comb + // *** change test to not propagate xs so that we can return to excluded code + // might have changed name to WALLY-MMU-SV39? + // signal to CPU it needs to wait on HPTW. /* -----\/----- EXCLUDED -----\/----- // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates @@ -119,12 +122,10 @@ module interlockfsm( endcase end - assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY); assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM)); assign IgnoreRequestTrapM = (InterlockCurrState == STATE_T0_READY & (TrapM)) | ((InterlockCurrState == STATE_T0_REPLAY) & (TrapM)); - endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index d980f0216..5af0f1b23 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -106,6 +106,8 @@ module lsu ( logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; + // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, + flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); assign IEUAdrExtM = {2'b00, IEUAdrM}; assign LSUStallM = DCacheStallM | InterlockStall | BusStall; @@ -117,14 +119,13 @@ module lsu ( if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, - .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, - .TrapM, .DCacheStallM, .SATP_REGW, .PCF, - .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, - .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, - .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, - .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, - .IgnoreRequestTLB, .IgnoreRequestTrapM); - + .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, + .TrapM, .DCacheStallM, .SATP_REGW, .PCF, + .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, + .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, + .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, + .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, + .IgnoreRequestTLB, .IgnoreRequestTrapM); end else begin assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; assign IgnoreRequestTrapM = TrapM; assign CPUBusy = StallW; assign PreLSURWM = MemRWM; @@ -186,7 +187,10 @@ module lsu ( logic SelUncachedAdr; assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; + // *** change to allow TIM and BUS. seaparate parameter for having bus (but have to have bus if have cache - check in testbench) if (`DMEM == `MEM_TIM) begin : dtim + // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. + // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, @@ -222,12 +226,12 @@ module lsu ( .s(SelUncachedAdr), .y(LSUBusHWDATA)); mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM), .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. if(CACHE_ENABLED) begin : dcache logic [1:0] RW, Atomic; - assign RW = CacheableM ? LSURWM : 2'b00; // AND gate + assign RW = CacheableM ? LSURWM : 2'b00; // AND gate // *** move and gates into cache assign Atomic = CacheableM ? LSUAtomicM : 2'b00; // AND gate cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( @@ -240,7 +244,7 @@ module lsu ( .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); - subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( + subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( // *** merge into cache .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); @@ -250,7 +254,7 @@ module lsu ( end end - if(`DMEM != `MEM_BUS) begin + if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS. Only produces byte write enable logic [`XLEN-1:0] ReadDataWordMaskedM; assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 0db6ebb16..2be89d27d 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -86,12 +86,13 @@ module lsuvirtmem( .clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF, .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, .InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); - hptw hptw( // *** remove logic from (), mention this in style guide CH3 + hptw hptw( .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM, - .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), + .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), // *** should it be HPTWReadDataM .DCacheStallM, .HPTWAdr, .HPTWRW, .HPTWSize); + // *** possible future optimization of simplifying page table entry with precomputed misalignment (Ross) low priority // multiplex the outputs to LSU mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM); From c3e59ae2df7ecd24f156a358a03eb2bcb8c6b139 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 4 Mar 2022 00:11:55 +0000 Subject: [PATCH 103/199] comment out nonfunctioning CSR-PERMISSIONS-M test --- pipelined/testbench/tests.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index ca472207a..8df95cd38 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1451,7 +1451,7 @@ string imperas32f[] = '{ string wally64priv[] = '{ `WALLYTEST, "rv64i_m/privilege/WALLY-CSR-permission-s-01", "004080", - "rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "005070", + //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "005070", "rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "003070", "rv64i_m/privilege/WALLY-CSR-permission-u-01", "005080", "rv64i_m/privilege/WALLY-MARCHID", "003070", From e4d18f18084ede5b17e1c57124355c8c6c658543 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 4 Mar 2022 03:57:19 +0000 Subject: [PATCH 104/199] removed more old 64priv tests --- pipelined/testbench/tests.vh | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 8df95cd38..8ae9bc196 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1452,27 +1452,27 @@ string imperas32f[] = '{ `WALLYTEST, "rv64i_m/privilege/WALLY-CSR-permission-s-01", "004080", //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "005070", - "rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "003070", + //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "003070", "rv64i_m/privilege/WALLY-CSR-permission-u-01", "005080", - "rv64i_m/privilege/WALLY-MARCHID", "003070", - "rv64i_m/privilege/WALLY-MCAUSE", "003070", + // "rv64i_m/privilege/WALLY-MARCHID", "003070", +/* "rv64i_m/privilege/WALLY-MCAUSE", "003070", "rv64i_m/privilege/WALLY-MEDELEG", "003070", "rv64i_m/privilege/WALLY-MHARTID", "003070", - "rv64i_m/privilege/WALLY-MIMPID", "003070", + "rv64i_m/privilege/WALLY-MIMPID", "003070",*/ "rv64i_m/privilege/WALLY-minfo-01", "004080", "rv64i_m/privilege/WALLY-misa-01", "004080", "rv64i_m/privilege/WALLY-MMU-SV39", "004080", "rv64i_m/privilege/WALLY-MMU-SV48", "004080", - "rv64i_m/privilege/WALLY-MSTATUS", "002070", +/* "rv64i_m/privilege/WALLY-MSTATUS", "002070", "rv64i_m/privilege/WALLY-MTVEC", "002070", - "rv64i_m/privilege/WALLY-MVENDORID", "003070", + "rv64i_m/privilege/WALLY-MVENDORID", "003070", */ "rv64i_m/privilege/WALLY-PMA", "004080", "rv64i_m/privilege/WALLY-PMP", "004080", - "rv64i_m/privilege/WALLY-SCAUSE", "002070", +// "rv64i_m/privilege/WALLY-SCAUSE", "002070", "rv64i_m/privilege/WALLY-scratch-01", "004080", - "rv64i_m/privilege/WALLY-sscratch-s-01", "004080", - "rv64i_m/privilege/WALLY-STVEC", "002070", - "rv64i_m/privilege/WALLY-UCAUSE", "002070" + "rv64i_m/privilege/WALLY-sscratch-s-01", "004080" +// "rv64i_m/privilege/WALLY-STVEC", "002070", +// "rv64i_m/privilege/WALLY-UCAUSE", "002070" }; string wally64periph[] = '{ From c13517f0cebc3df411f089049eec708d92a1f001 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 3 Mar 2022 21:00:07 -0800 Subject: [PATCH 105/199] Defined WALLY in setup as pointer to repository --- setup.sh | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/setup.sh b/setup.sh index b1425d7e1..925d87e83 100755 --- a/setup.sh +++ b/setup.sh @@ -1,11 +1,16 @@ #!/bin/bash -# wally-setup.sh +# setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 # Set up tools for riscv-wally echo "Executing Wally setup.sh" +# Path to Wally repository +WALLY=$(dirname ${BASH_SOURCE}) +export WALLY=$(cd "$WALLY" && pwd) +echo \$WALLY set to ${WALLY} + # Path to RISC-V Tools export RISCV=/opt/riscv # change this if you installed the tools in a different location @@ -16,8 +21,8 @@ export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/risc # Spike export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH export PATH=$PATH:$RISCV/bin -# exe2memfile -export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory +# utility functions in Wally repository +export PATH=$WALLY/bin:$PATH # Verilator export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator # ModelSim/Questa (vsim) @@ -26,6 +31,6 @@ export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Sieme export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler export SNPSLMD_LICENSE_FILE=27020@134.173.38.214 -# Imperas; *** remove if not using; *** fix paths -export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH # *** maybe take this out based on Imperas -export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas +# Imperas; put this in if you are using it +#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH +#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas From 99a0e2d73de7f839c301d9071a78ea55ba2f4cde Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 4 Mar 2022 05:09:02 +0000 Subject: [PATCH 106/199] Adjusted scripts to use --- bin/testlist.pl | 2 +- synthDC/Makefile | 2 +- tests/testgen/privileged/run.sh | 20 ++++++++++---------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/bin/testlist.pl b/bin/testlist.pl index 5b7accae7..745ff29e5 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -9,7 +9,7 @@ use warnings; import os; if ($#ARGV != 0) { - die("Usage: $0 workpath [e.g. $0 ~/riscv-wally/addins/riscv-arch-test/work") + die("Usage: $0 workpath [e.g. $0 $WALLY/addins/riscv-arch-test/work") } my $mypath = $ARGV[0]; my @dirs = glob($mypath.'/*/*'); diff --git a/synthDC/Makefile b/synthDC/Makefile index aafadb648..b359046eb 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -21,7 +21,7 @@ hash := $(shell git rev-parse --short HEAD) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash) export SAIFPOWER ?= 0 -CONFIGDIR ?= ~/riscv-wally/pipelined/config +CONFIGDIR ?= ${WALLY}/pipelined/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) print: diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh index 122e629e7..1fa3a9d01 100755 --- a/tests/testgen/privileged/run.sh +++ b/tests/testgen/privileged/run.sh @@ -11,21 +11,21 @@ printf "\n\n#####\nStarting tests for $1\n#####\n\n" if [[ "$2" != "-simonly" ]] then - cd ~/riscv-wally/pipelined/testgen/privileged + cd $WALLY/pipelined/testgen/privileged python3 "testgen-$1.py" printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n" if [[ "$2" == "-c" ]] then printf "\n\n###\nWARNING\nThis seems to not be outputting begin_signature at the moment... Probably won't work in modelsim...\n###\n\n\n" - cd ~/riscv-wally/imperas-riscv-tests/riscv-test-suite/rv64p/src + cd $WALLY/imperas-riscv-tests/riscv-test-suite/rv64p/src riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf" - cd ~/riscv-wally/imperas-riscv-tests/work/rv64p + cd $WALLY/imperas-riscv-tests/work/rv64p riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump elif [[ "$2" != "-nosim" ]] then - cd ~/riscv-wally/imperas-riscv-tests + cd $WALLY/imperas-riscv-tests make privileged exe2memfile.pl work/*/*.elf @@ -36,9 +36,9 @@ fi if [[ "$2" == "-simonly" ]] then printf "\n\n###\nWARNING\nThis seems to not be outputting begin_signature at the moment... Probably won't work in modelsim...\n###\n\n\n" - cd ~/riscv-wally/imperas-riscv-tests/riscv-test-suite/rv64p/src + cd $WALLY/imperas-riscv-tests/riscv-test-suite/rv64p/src riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf" - cd ~/riscv-wally/imperas-riscv-tests/work/rv64p + cd $WALLY/imperas-riscv-tests/work/rv64p riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump # riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-CAUSE".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-CAUSE.elf" @@ -48,14 +48,14 @@ fi if [[ "$2" == "-sim" || "$2" == "-simonly" ]] then printf "\n\n\n#####\nSimulating!\n#####\n\n" - cd ~/riscv-wally/pipelined/regression + cd $WALLY/pipelined/regression vsim -do wally-privileged.do -c fi -cd ~/riscv-wally/pipelined +cd $WALLY/pipelined printf "\n\n\n#####\nDone!\n#####\n\n" -cd ~/riscv-wally/imperas-riscv-tests/work +cd $WALLY/imperas-riscv-tests/work for isa in "rv64p" "rv32p"; do printf "$isa = '{" COMMA="" @@ -71,4 +71,4 @@ for isa in "rv64p" "rv32p"; do printf "\n};\n\n" done -cd ~/riscv-wally/pipelined \ No newline at end of file +cd $WALLY/pipelined \ No newline at end of file From cba6f10c195e0c974fa2670bc1cbdacb08a7c502 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 4 Mar 2022 05:16:20 +0000 Subject: [PATCH 107/199] Prettied up softfloat_demo --- examples/fp/softfloat_demo/softfloat_demo.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/examples/fp/softfloat_demo/softfloat_demo.c b/examples/fp/softfloat_demo/softfloat_demo.c index 111847a4f..918682ba2 100644 --- a/examples/fp/softfloat_demo/softfloat_demo.c +++ b/examples/fp/softfloat_demo/softfloat_demo.c @@ -16,13 +16,8 @@ void printF32 (char *msg, float32_t f) { sp conv; int i, j; conv.v = f.v; // use union to convert between hexadecimal and floating-point views - // Print out nicely - printf("%s: ", msg); - printf("0x%04x", (conv.v >> 16)); - printf("_"); - printf("%04x", (conv.v & 0xFFFF)); - printf(" = %g\n", conv.f); - //printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); + printf("%s: ", msg); // print out nicely + printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f); } void printFlags(void) { @@ -31,7 +26,7 @@ void printFlags(void) { int OF = (softfloat_exceptionFlags >> 2) % 2; int DZ = (softfloat_exceptionFlags >> 3) % 2; int NV = (softfloat_exceptionFlags >> 4) % 2; - printf ("exceptions: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", + printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", NX, UF, OF, DZ, NV); } From bffd4175675e7cceb5330b57158d2a860f177235 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 4 Mar 2022 07:21:18 -0800 Subject: [PATCH 108/199] Cleaned up printing and warnings in fpcalc.c --- examples/fp/fpcalc/Makefile | 2 +- examples/fp/fpcalc/fpcalc.c | 44 ++++++++++++++++++++----------------- 2 files changed, 25 insertions(+), 21 deletions(-) diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile index 4d0efe20e..196fdf3d2 100644 --- a/examples/fp/fpcalc/Makefile +++ b/examples/fp/fpcalc/Makefile @@ -1,7 +1,7 @@ # Makefile CC = gcc -CFLAGS = -O3 +CFLAGS = -O3 -Wno-format-overflow LIBS = -lm LFLAGS = -L. # Link against the riscv-isa-sim version of SoftFloat rather than diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index b8e180bf7..f41494c70 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -29,19 +29,23 @@ typedef union dp { int opSize = 0; -void long2binstr(long val, char *str, int bits) { - int i; - long masked; +void long2binstr(unsigned long val, char *str, int bits) { + int i, shamt; + unsigned long mask, masked; if (val == 0) { // just return zero str[0] = '0'; str[1] = 0; } else { - for (i=0; i> 16)); printf("_"); printf("%04x", (conv.v & 0xFF)); - printf(" = %g = %s: Biased Exp %d Fract 0x%lx\n", conv.f, sci, exp, fract); + printf(" = %g = %s: Biased Exp %ld Fract 0x%lx\n", conv.f, sci, exp, fract); //printf ("%s: 0x%08x = %g = %s: Biased Exp %d Fract 0x%lx\n", // msg, conv.v, conv.f, sci, exp, fract); } @@ -107,7 +111,7 @@ void printF64(char *msg, float64_t f) { long exp, fract; long mask; char sign; - char sci[80], fractstr[80]; + char sci[200], fractstr[200]; conv.v = f.v; // use union to convert between hexadecimal and floating-point views @@ -120,18 +124,18 @@ void printF64(char *msg, float64_t f) { else if (exp == 0 && fract != 0) sprintf(sci, "Denorm: %c0.%s x 2^-1022", sign, fractstr); else if (exp == 2047 && fract == 0) sprintf(sci, "%cinf", sign); else if (exp == 2047 && fract != 0) sprintf(sci, "NaN Payload: %c%s", sign, fractstr); - else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-1023); + else sprintf(sci, "%c1.%s x 2^%ld", sign, fractstr, exp-1023); //printf ("%s: 0x%016lx = %lg\n", msg, conv.v, conv.d); printf("%s: ", msg); - printf("0x%04x", (conv.v >> 48)); + printf("0x%04lx", (conv.v >> 48)); printf("_"); - printf("%04x", (conv.v >> 32) & 0xFFFF); + printf("%04lx", (conv.v >> 32) & 0xFFFF); printf("_"); - printf("%04x", (conv.v >> 16)); + printf("%04lx", (conv.v >> 16) & 0xFFFF); printf("_"); - printf("%04x", (conv.v & 0xFFFF)); - printf(" = %lg = %s: Biased Exp %d Fract 0x%lx\n", conv.d, sci, exp, fract); + printf("%04lx", (conv.v & 0xFFFF)); + printf(" = %lg = %s: Biased Exp %ld Fract 0x%lx\n", conv.d, sci, exp, fract); //printf ("%s: 0x%016lx = %lg = %s: Biased Exp %d Fract 0x%lx\n", // msg, conv.v, conv.d, sci, exp, fract); } @@ -204,7 +208,7 @@ int main(int argc, char *argv[]) { uint64_t xn, yn, zn; char op1, op2; - char cmd[80]; + char cmd[200]; softfloatInit(); From 60cbd1c9c13cedbdbf635b41a7745f98d726a01d Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 5 Mar 2022 17:21:34 -0800 Subject: [PATCH 109/199] fix "dirname: missing operand" bug from setup.sh --- setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.sh b/setup.sh index 925d87e83..de048ed60 100755 --- a/setup.sh +++ b/setup.sh @@ -7,7 +7,7 @@ echo "Executing Wally setup.sh" # Path to Wally repository -WALLY=$(dirname ${BASH_SOURCE}) +WALLY=$(dirname $0) export WALLY=$(cd "$WALLY" && pwd) echo \$WALLY set to ${WALLY} From 891ec82d815eafaaa9bf2ae465182ed44e95b589 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 5 Mar 2022 17:26:30 -0800 Subject: [PATCH 110/199] remove linux-testgen dir because it is now completely obsolete --- .../linux-testvectors/convert2bin.py | 13 - .../linux-testvectors/tvCopier.py | 62 -- .../linux-testvectors/tvLinker.sh | 3 - .../linux-testvectors/tvUnlinker.sh | 9 - .../linux-testgen/qemu-build-instructions.md | 10 - tests/linux-testgen/qemu-patches/README | 2 - tests/linux-testgen/qemu-patches/cpu.c | 722 ------------------ tests/linux-testgen/qemu-patches/virt.c | 451 ----------- tests/linux-testgen/wallyVirtIO.patch | 542 ------------- 9 files changed, 1814 deletions(-) delete mode 100755 tests/linux-testgen/linux-testvectors/convert2bin.py delete mode 100755 tests/linux-testgen/linux-testvectors/tvCopier.py delete mode 100755 tests/linux-testgen/linux-testvectors/tvLinker.sh delete mode 100755 tests/linux-testgen/linux-testvectors/tvUnlinker.sh delete mode 100644 tests/linux-testgen/qemu-build-instructions.md delete mode 100644 tests/linux-testgen/qemu-patches/README delete mode 100644 tests/linux-testgen/qemu-patches/cpu.c delete mode 100644 tests/linux-testgen/qemu-patches/virt.c delete mode 100644 tests/linux-testgen/wallyVirtIO.patch diff --git a/tests/linux-testgen/linux-testvectors/convert2bin.py b/tests/linux-testgen/linux-testvectors/convert2bin.py deleted file mode 100755 index 78349a5d6..000000000 --- a/tests/linux-testgen/linux-testvectors/convert2bin.py +++ /dev/null @@ -1,13 +0,0 @@ -#!/usr/bin/python3 - -asciiBinFile = 'ram.txt' -binFile = 'ram.bin' - -asciiBinFP = open(asciiBinFile, 'r') -binFP = open (binFile, 'wb') - -for line in asciiBinFP.readlines(): - binFP.write(int(line, 16).to_bytes(8, byteorder='little', signed=False)) - -asciiBinFP.close() -binFP.close() diff --git a/tests/linux-testgen/linux-testvectors/tvCopier.py b/tests/linux-testgen/linux-testvectors/tvCopier.py deleted file mode 100755 index d272e98c6..000000000 --- a/tests/linux-testgen/linux-testvectors/tvCopier.py +++ /dev/null @@ -1,62 +0,0 @@ -#!/usr/bin/python3 -# Copies Linux testvector files from Tera to ./ (which ought to be /riscv-wally/pipelined/linux-testgen/linux-testvectors/) -import os -from datetime import datetime - - -if not os.path.isfile('sshUname.txt'): - print("GREETINGS FRIEND") - print("Please supply your tera username in ./sshUname.txt") - exit(1) -sshUnameFile = open('sshUname.txt','r') -uname = sshUnameFile.readline().strip('\n') -tera = uname+'@tera.eng.hmc.edu' - -logFile = open('tvCopier.log', 'w') -def pyTee(line): - global logFile - print(line) - logFile.write(line+"\n") - -pyTee('Copying tvDateReporter.py from Tera') -os.system('scp '+tera+':/courses/e190ax/buildroot_boot/tvDateReporter.py ./') -pyTee('Running tvDateReporter.py Locally') -os.system('./tvDateReporter.py && mv tvDates.txt tvDatesLocal.txt') -pyTee('Running tvDateReporter.py on Tera') -os.system('ssh '+tera+' \"cd /courses/e190ax/buildroot_boot && ./tvDateReporter.py\"') -pyTee('Copying tvDates.txt from Tera') -os.system('scp '+tera+':/courses/e190ax/buildroot_boot/tvDates.txt ./') - -copyList = [] - -pyTee('_____________________________________________________________________') -pyTee('| File Name | Local_Date | Tera_Date | Update? |') -with open('tvDatesLocal.txt') as tvDatesLocal, open('tvDates.txt') as tvDatesTera_: - for tvDateLocal, tvDateTera_ in zip(tvDatesLocal,tvDatesTera_): - outString = '| ' - - tvDateLocal = tvDateLocal.strip('\n').split(' ') - tvDateTera_ = tvDateTera_.strip('\n').split(' ') - - tvFile = tvDateLocal[0] - outString += '{:<24}'.format(tvFile) - outString += '| '+tvDateLocal[1]+' | '+tvDateTera_[1] - - tvDateLocal = tvDateLocal[1].split('-') - tvDateTera_ = tvDateTera_[1].split('-') - - tvDateLocal = datetime(int(tvDateLocal[0]),int(tvDateLocal[1]),int(tvDateLocal[2])) - tvDateTera_ = datetime(int(tvDateTera_[0]),int(tvDateTera_[1]),int(tvDateTera_[2])) - - update = tvDateTera_ >= tvDateLocal - outString += ' | '+('yes' if update else 'no ') + ' |' - pyTee(outString) - if update: - copyList.append(tvFile) -pyTee('_____________________________________________________________________') - -for tvFile in copyList: - pyTee('Copying '+tvFile+' from Tera') - os.system('scp -r'+tera+':/courses/e190ax/buildroot_boot/'+tvFile+' ./') -pyTee('Done!') -logFile.close() diff --git a/tests/linux-testgen/linux-testvectors/tvLinker.sh b/tests/linux-testgen/linux-testvectors/tvLinker.sh deleted file mode 100755 index ff7dc3e5e..000000000 --- a/tests/linux-testgen/linux-testvectors/tvLinker.sh +++ /dev/null @@ -1,3 +0,0 @@ -echo "Warning: this script will only work if your repo is on Tera" -ln -s /courses/e190ax/linux-testvectors-shared/* ./ -echo "Done!" diff --git a/tests/linux-testgen/linux-testvectors/tvUnlinker.sh b/tests/linux-testgen/linux-testvectors/tvUnlinker.sh deleted file mode 100755 index acf155c00..000000000 --- a/tests/linux-testgen/linux-testvectors/tvUnlinker.sh +++ /dev/null @@ -1,9 +0,0 @@ -# This could be nice to use if you want to mess with the testvectors -# without corrupting the stable copies on Tera. -unlink all.txt -unlink bootmem.txt -unlink ram.txt -unlink vmlinux.objdump -unlink vmlinux.objdump.addr -unlink vmlinux.objdump.lab -echo "Done!" diff --git a/tests/linux-testgen/qemu-build-instructions.md b/tests/linux-testgen/qemu-build-instructions.md deleted file mode 100644 index fc866660b..000000000 --- a/tests/linux-testgen/qemu-build-instructions.md +++ /dev/null @@ -1,10 +0,0 @@ -cd -git clone https://github.com/qemu/qemu -cd qemu -git checkout dbdc621be937d9efe3e4dff994e54e8eea051f7a -git apply wallyVirtIO.patch # located in riscv-wally/pipelined/linux-testgen/wallyVirtIO.patch -sudo apt install ninja-build # or your equivalent -sudo apt install libglib2.0-dev # or your equivalent -sudo apt install libpixman-1-dev libcairo2-dev libpango1.0-dev libjpeg8-dev libgif-dev -./configure --target-list=riscv64-softmmu -make --jobs diff --git a/tests/linux-testgen/qemu-patches/README b/tests/linux-testgen/qemu-patches/README deleted file mode 100644 index 02f7e0766..000000000 --- a/tests/linux-testgen/qemu-patches/README +++ /dev/null @@ -1,2 +0,0 @@ -replace /qemu/target/riscv/cpu.c with the provided cpu.c -replace /qemu/hw/riscv/virt.c with the provided virt.c diff --git a/tests/linux-testgen/qemu-patches/cpu.c b/tests/linux-testgen/qemu-patches/cpu.c deleted file mode 100644 index 82aad33af..000000000 --- a/tests/linux-testgen/qemu-patches/cpu.c +++ /dev/null @@ -1,722 +0,0 @@ -/* - * QEMU RISC-V CPU - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2017-2018 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu/qemu-print.h" -#include "qemu/ctype.h" -#include "qemu/log.h" -#include "cpu.h" -#include "internals.h" -#include "exec/exec-all.h" -#include "qapi/error.h" -#include "qemu/error-report.h" -#include "hw/qdev-properties.h" -#include "migration/vmstate.h" -#include "fpu/softfloat-helpers.h" - -/* RISC-V CPU definitions */ - -static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; - -const char * const riscv_int_regnames[] = { - "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", - "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", - "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", - "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", - "x28/t3", "x29/t4", "x30/t5", "x31/t6" -}; - -const char * const riscv_fpr_regnames[] = { - "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", - "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", - "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", - "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", - "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", - "f30/ft10", "f31/ft11" -}; - -const char * const riscv_excp_names[] = { - "misaligned_fetch", - "fault_fetch", - "illegal_instruction", - "breakpoint", - "misaligned_load", - "fault_load", - "misaligned_store", - "fault_store", - "user_ecall", - "supervisor_ecall", - "hypervisor_ecall", - "machine_ecall", - "exec_page_fault", - "load_page_fault", - "reserved", - "store_page_fault", - "reserved", - "reserved", - "reserved", - "reserved", - "guest_exec_page_fault", - "guest_load_page_fault", - "reserved", - "guest_store_page_fault", -}; - -const char * const riscv_intr_names[] = { - "u_software", - "s_software", - "vs_software", - "m_software", - "u_timer", - "s_timer", - "vs_timer", - "m_timer", - "u_external", - "vs_external", - "h_external", - "m_external", - "reserved", - "reserved", - "reserved", - "reserved" -}; - -const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) -{ - if (async) { - return (cause < ARRAY_SIZE(riscv_intr_names)) ? - riscv_intr_names[cause] : "(unknown)"; - } else { - return (cause < ARRAY_SIZE(riscv_excp_names)) ? - riscv_excp_names[cause] : "(unknown)"; - } -} - -bool riscv_cpu_is_32bit(CPURISCVState *env) -{ - if (env->misa & RV64) { - return false; - } - - return true; -} - -static void set_misa(CPURISCVState *env, target_ulong misa) -{ - env->misa_mask = env->misa = misa; -} - -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver = priv_ver; -} - -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver = vext_ver; -} - -static void set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - -static void set_resetvec(CPURISCVState *env, int resetvec) -{ -#ifndef CONFIG_USER_ONLY - env->resetvec = resetvec; -#endif -} - -static void riscv_any_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); -} - -#if defined(TARGET_RISCV64) -static void rv64_base_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - set_misa(env, RV64); -} - -static void rv64_sifive_u_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); -} - -static void rv64_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} -#else -static void rv32_base_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - set_misa(env, RV32); -} - -static void rv32_sifive_u_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); -} - -static void rv32_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} - -static void rv32_ibex_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} - -static void rv32_imafcu_nommu_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, DEFAULT_RSTVEC); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} -#endif - -static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) -{ - ObjectClass *oc; - char *typename; - char **cpuname; - - cpuname = g_strsplit(cpu_model, ",", 1); - typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); - oc = object_class_by_name(typename); - g_strfreev(cpuname); - g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || - object_class_is_abstract(oc)) { - return NULL; - } - return oc; -} - -static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - int i; - -#if !defined(CONFIG_USER_ONLY) - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); - } -#endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); -#ifndef CONFIG_USER_ONLY - - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_is_32bit(env)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); - } - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", - (target_ulong)env->vsstatus); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); - } -#endif - - for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s " TARGET_FMT_lx, - riscv_int_regnames[i], env->gpr[i]); - if ((i & 3) == 3) { - qemu_fprintf(f, "\n"); - } - } - if (flags & CPU_DUMP_FPU) { - for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s %016" PRIx64, - riscv_fpr_regnames[i], env->fpr[i]); - if ((i & 3) == 3) { - qemu_fprintf(f, "\n"); - } - } - } -} - -static void riscv_cpu_set_pc(CPUState *cs, vaddr value) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - env->pc = value; -} - -static void riscv_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - env->pc = tb->pc; -} - -static bool riscv_cpu_has_work(CPUState *cs) -{ -#ifndef CONFIG_USER_ONLY - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - /* - * Definition of the WFI instruction requires it to ignore the privilege - * mode and delegation registers, but respect individual enables - */ - return (env->mip & env->mie) != 0; -#else - return true; -#endif -} - -void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, - target_ulong *data) -{ - env->pc = data[0]; -} - -static void riscv_cpu_reset(DeviceState *dev) -{ - CPUState *cs = CPU(dev); - RISCVCPU *cpu = RISCV_CPU(cs); - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPURISCVState *env = &cpu->env; - - mcc->parent_reset(dev); -#ifndef CONFIG_USER_ONLY - env->priv = PRV_M; - env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); - env->mcause = 0; - env->pc = env->resetvec; - env->two_stage_lookup = false; -#endif - cs->exception_index = EXCP_NONE; - env->load_res = -1; - set_default_nan_mode(1, &env->fp_status); -} - -static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) -{ - RISCVCPU *cpu = RISCV_CPU(s); - if (riscv_cpu_is_32bit(&cpu->env)) { - info->print_insn = print_insn_riscv32; - } else { - info->print_insn = print_insn_riscv64; - } -} - -static void riscv_cpu_realize(DeviceState *dev, Error **errp) -{ - CPUState *cs = CPU(dev); - RISCVCPU *cpu = RISCV_CPU(dev); - CPURISCVState *env = &cpu->env; - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); - int priv_version = PRIV_VERSION_1_11_0; - int vext_version = VEXT_VERSION_0_07_1; - target_ulong target_misa = env->misa; - Error *local_err = NULL; - - cpu_exec_realizefn(cs, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version = PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version = PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - } - - set_priv_version(env, priv_version); - set_vext_version(env, vext_version); - - if (cpu->cfg.mmu) { - set_feature(env, RISCV_FEATURE_MMU); - } - - if (cpu->cfg.pmp) { - set_feature(env, RISCV_FEATURE_PMP); - } - - set_resetvec(env, cpu->cfg.resetvec); - - /* If only XLEN is set for misa, then set misa from properties */ - if (env->misa == RV32 || env->misa == RV64) { - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & - cpu->cfg.ext_a & cpu->cfg.ext_f & - cpu->cfg.ext_d)) { - warn_report("Setting G will also set IMAFD"); - cpu->cfg.ext_i = true; - cpu->cfg.ext_m = true; - cpu->cfg.ext_a = true; - cpu->cfg.ext_f = true; - cpu->cfg.ext_d = true; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_i) { - target_misa |= RVI; - } - if (cpu->cfg.ext_e) { - target_misa |= RVE; - } - if (cpu->cfg.ext_m) { - target_misa |= RVM; - } - if (cpu->cfg.ext_a) { - target_misa |= RVA; - } - if (cpu->cfg.ext_f) { - target_misa |= RVF; - } - if (cpu->cfg.ext_d) { - target_misa |= RVD; - } - if (cpu->cfg.ext_c) { - target_misa |= RVC; - } - if (cpu->cfg.ext_s) { - target_misa |= RVS; - } - if (cpu->cfg.ext_u) { - target_misa |= RVU; - } - if (cpu->cfg.ext_h) { - target_misa |= RVH; - } - if (cpu->cfg.ext_v) { - target_misa |= RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { - vext_version = VEXT_VERSION_0_07_1; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v0.7.1\n"); - } - set_vext_version(env, vext_version); - } - - set_misa(env, target_misa); - } - - riscv_cpu_register_gdb_regs_for_features(cs); - - qemu_init_vcpu(cs); - cpu_reset(cs); - - mcc->parent_realize(dev, errp); -} - -static void riscv_cpu_init(Object *obj) -{ - RISCVCPU *cpu = RISCV_CPU(obj); - - cpu_set_cpustate_pointers(cpu); -} - -static Property riscv_cpu_properties[] = { - DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), - DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), - DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), - DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), - DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), - DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), - DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), - /* This is experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), - DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), - DEFINE_PROP_END_OF_LIST(), -}; - -static gchar *riscv_gdb_arch_name(CPUState *cs) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - - if (riscv_cpu_is_32bit(env)) { - return g_strdup("riscv:rv32"); - } else { - return g_strdup("riscv:rv64"); - } -} - -static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - - if (strcmp(xmlname, "riscv-csr.xml") == 0) { - return cpu->dyn_csr_xml; - } - - return NULL; -} - -#include "hw/core/tcg-cpu-ops.h" - -static struct TCGCPUOps riscv_tcg_ops = { - .initialize = riscv_translate_init, - .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .cpu_exec_interrupt = riscv_cpu_exec_interrupt, - .tlb_fill = riscv_cpu_tlb_fill, - -#ifndef CONFIG_USER_ONLY - .do_interrupt = riscv_cpu_do_interrupt, - .do_transaction_failed = riscv_cpu_do_transaction_failed, - .do_unaligned_access = riscv_cpu_do_unaligned_access, -#endif /* !CONFIG_USER_ONLY */ -}; - -static void riscv_cpu_class_init(ObjectClass *c, void *data) -{ - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); - CPUClass *cc = CPU_CLASS(c); - DeviceClass *dc = DEVICE_CLASS(c); - - device_class_set_parent_realize(dc, riscv_cpu_realize, - &mcc->parent_realize); - - device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); - - cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; - cc->dump_state = riscv_cpu_dump_state; - cc->set_pc = riscv_cpu_set_pc; - cc->gdb_read_register = riscv_cpu_gdb_read_register; - cc->gdb_write_register = riscv_cpu_gdb_write_register; - cc->gdb_num_core_regs = 33; -#if defined(TARGET_RISCV32) - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; -#elif defined(TARGET_RISCV64) - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; -#endif - cc->gdb_stop_before_watchpoint = true; - cc->disas_set_info = riscv_cpu_disas_set_info; -#ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; - /* For now, mark unmigratable: */ - cc->vmsd = &vmstate_riscv_cpu; - cc->write_elf64_note = riscv_cpu_write_elf64_note; - cc->write_elf32_note = riscv_cpu_write_elf32_note; -#endif - cc->gdb_arch_name = riscv_gdb_arch_name; - cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; - cc->tcg_ops = &riscv_tcg_ops; - - device_class_set_props(dc, riscv_cpu_properties); -} - -char *riscv_isa_string(RISCVCPU *cpu) -{ - int i; - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; - char *isa_str = g_new(char, maxlen); - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); - for (i = 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa & RV(riscv_exts[i])) { - *p++ = qemu_tolower(riscv_exts[i]); - } - } - *p = '\0'; - return isa_str; -} - -static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) -{ - ObjectClass *class_a = (ObjectClass *)a; - ObjectClass *class_b = (ObjectClass *)b; - const char *name_a, *name_b; - - name_a = object_class_get_name(class_a); - name_b = object_class_get_name(class_b); - return strcmp(name_a, name_b); -} - -static void riscv_cpu_list_entry(gpointer data, gpointer user_data) -{ - const char *typename = object_class_get_name(OBJECT_CLASS(data)); - int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); - - qemu_printf("%.*s\n", len, typename); -} - -void riscv_cpu_list(void) -{ - GSList *list; - - list = object_class_get_list(TYPE_RISCV_CPU, false); - list = g_slist_sort(list, riscv_cpu_list_compare); - g_slist_foreach(list, riscv_cpu_list_entry, NULL); - g_slist_free(list); -} - -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_CPU, \ - .instance_init = initfn \ - } - -static const TypeInfo riscv_cpu_type_infos[] = { - { - .name = TYPE_RISCV_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(RISCVCPU), - .instance_align = __alignof__(RISCVCPU), - .instance_init = riscv_cpu_init, - .abstract = true, - .class_size = sizeof(RISCVCPUClass), - .class_init = riscv_cpu_class_init, - }, - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), -#if defined(TARGET_RISCV32) - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), -#elif defined(TARGET_RISCV64) - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), -#endif -}; - -DEFINE_TYPES(riscv_cpu_type_infos) diff --git a/tests/linux-testgen/qemu-patches/virt.c b/tests/linux-testgen/qemu-patches/virt.c deleted file mode 100644 index 358208d1a..000000000 --- a/tests/linux-testgen/qemu-patches/virt.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * QEMU RISC-V VirtIO Board - * - * Copyright (c) 2017 SiFive, Inc. - * - * RISC-V machine with 16550a UART and VirtIO MMIO - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu/units.h" -#include "qemu/log.h" -#include "qemu/error-report.h" -#include "qapi/error.h" -#include "hw/boards.h" -#include "hw/loader.h" -#include "hw/sysbus.h" -#include "hw/qdev-properties.h" -#include "hw/char/serial.h" -#include "target/riscv/cpu.h" -#include "hw/riscv/riscv_hart.h" -#include "hw/riscv/virt.h" -#include "hw/riscv/boot.h" -#include "hw/riscv/numa.h" -#include "hw/intc/sifive_clint.h" -#include "hw/intc/sifive_plic.h" -#include "hw/misc/sifive_test.h" -#include "chardev/char.h" -#include "sysemu/arch_init.h" -#include "sysemu/device_tree.h" -#include "sysemu/sysemu.h" -#include "hw/pci/pci.h" -#include "hw/pci-host/gpex.h" -#include "hw/display/ramfb.h" - -static const MemMapEntry virt_memmap[] = { - [VIRT_MROM] = { 0x1000, 0xf000 }, - [VIRT_CLINT] = { 0x2000000, 0x10000 }, - [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, - [VIRT_UART0] = { 0x10000000, 0x100 }, - [VIRT_DRAM] = { 0x80000000, 0x0 }, -}; - -/* PCIe high mmio is fixed for RV32 */ -#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL -#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) - -/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ -#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) - -#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) - -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) -{ - void *fdt; - //int i, cpu, socket; - int cpu, socket; - MachineState *mc = MACHINE(s); - uint64_t addr, size; - uint32_t *clint_cells, *plic_cells; - unsigned long clint_addr, plic_addr; - uint32_t plic_phandle[MAX_NODES]; - uint32_t cpu_phandle, intc_phandle; - uint32_t phandle = 1, plic_mmio_phandle = 1; - char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; - - if (mc->dtb) { - fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); - if (!fdt) { - error_report("load_device_tree() failed"); - exit(1); - } - goto update_bootargs; - } else { - fdt = mc->fdt = create_device_tree(&s->fdt_size); - if (!fdt) { - error_report("create_device_tree() failed"); - exit(1); - } - } - - qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); - - qemu_fdt_add_subnode(fdt, "/soc"); - qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); - - qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", - SIFIVE_CLINT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { - clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(fdt, clust_name); - - plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); - clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); - - for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { - cpu_phandle = phandle++; - - cpu_name = g_strdup_printf("/cpus/cpu@%d", - s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(fdt, cpu_name); - if (is_32_bit) { - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); - } else { - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); - } - name = riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); - g_free(name); - qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(fdt, cpu_name, "reg", - s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); - qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); - - intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(fdt, intc_name); - intc_phandle = phandle++; - qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); - qemu_fdt_setprop_string(fdt, intc_name, "compatible", - "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); - - clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); - clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); - clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); - clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); - - plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); - plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); - plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); - plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); - - core_name = g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(fdt, core_name); - qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); - - g_free(core_name); - g_free(intc_name); - g_free(cpu_name); - } - - addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); - mem_name = g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(fdt, mem_name); - qemu_fdt_setprop_cells(fdt, mem_name, "reg", - addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); - g_free(mem_name); - - clint_addr = memmap[VIRT_CLINT].base + - (memmap[VIRT_CLINT].size * socket); - clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(fdt, clint_name); - qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, clint_name, "reg", - 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", - clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); - g_free(clint_name); - - plic_phandle[socket] = phandle++; - plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); - plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(fdt, plic_name); - qemu_fdt_setprop_cell(fdt, plic_name, - "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, plic_name, - "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); - qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", - plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(fdt, plic_name, "reg", - 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); - riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); - qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); - g_free(plic_name); - - g_free(clint_cells); - g_free(plic_cells); - g_free(clust_name); - } - - for (socket = 0; socket < riscv_socket_count(mc); socket++) { - if (socket == 0) { - plic_mmio_phandle = plic_phandle[socket]; - } - } - - riscv_socket_fdt_write_distance_matrix(mc, fdt); - - name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(fdt, name, "reg", - 0x0, memmap[VIRT_UART0].base, - 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); - qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); - - qemu_fdt_add_subnode(fdt, "/chosen"); - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); - g_free(name); - -update_bootargs: - if (cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } -} - -static void virt_machine_init(MachineState *machine) -{ - const MemMapEntry *memmap = virt_memmap; - RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); - MemoryRegion *system_memory = get_system_memory(); - MemoryRegion *main_mem = g_new(MemoryRegion, 1); - MemoryRegion *mask_rom = g_new(MemoryRegion, 1); - char *plic_hart_config, *soc_name; - size_t plic_hart_config_len; - target_ulong start_addr = memmap[VIRT_DRAM].base; - target_ulong firmware_end_addr, kernel_start_addr; - uint32_t fdt_load_addr; - uint64_t kernel_entry; - DeviceState *mmio_plic; - int i, j, base_hartid, hart_count; - - /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { - error_report("number of sockets/nodes should be less than %d", - VIRT_SOCKETS_MAX); - exit(1); - } - - /* Initialize sockets */ - mmio_plic = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { - if (!riscv_socket_check_hartids(machine, i)) { - error_report("discontinuous hartids in socket%d", i); - exit(1); - } - - base_hartid = riscv_socket_first_hartid(machine, i); - if (base_hartid < 0) { - error_report("can't find hartid base for socket%d", i); - exit(1); - } - - hart_count = riscv_socket_hart_count(machine, i); - if (hart_count < 0) { - error_report("can't find hart count for socket%d", i); - exit(1); - } - - soc_name = g_strdup_printf("soc%d", i); - object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], - TYPE_RISCV_HART_ARRAY); - g_free(soc_name); - object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", - machine->cpu_type, &error_abort); - object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", - base_hartid, &error_abort); - object_property_set_int(OBJECT(&s->soc[i]), "num-harts", - hart_count, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); - - /* Per-socket CLINT */ - sifive_clint_create( - memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, - memmap[VIRT_CLINT].size, base_hartid, hart_count, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, - SIFIVE_CLINT_TIMEBASE_FREQ, true); - - /* Per-socket PLIC hart topology configuration string */ - plic_hart_config_len = - (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; - plic_hart_config = g_malloc0(plic_hart_config_len); - for (j = 0; j < hart_count; j++) { - if (j != 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); - } - strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, - plic_hart_config_len); - plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); - } - - /* Per-socket PLIC */ - s->plic[i] = sifive_plic_create( - memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, - plic_hart_config, base_hartid, - VIRT_PLIC_NUM_SOURCES, - VIRT_PLIC_NUM_PRIORITIES, - VIRT_PLIC_PRIORITY_BASE, - VIRT_PLIC_PENDING_BASE, - VIRT_PLIC_ENABLE_BASE, - VIRT_PLIC_ENABLE_STRIDE, - VIRT_PLIC_CONTEXT_BASE, - VIRT_PLIC_CONTEXT_STRIDE, - memmap[VIRT_PLIC].size); - g_free(plic_hart_config); - - /* Try to use different PLIC instance based device type */ - if (i == 0) { - mmio_plic = s->plic[i]; - } - } - - if (riscv_is_32bit(&s->soc[0])) { -#if HOST_LONG_BITS == 64 - /* limit RAM size in a 32-bit system */ - if (machine->ram_size > 10 * GiB) { - machine->ram_size = 10 * GiB; - error_report("Limiting RAM size to 10 GiB"); - } -#endif - } - - /* register system main memory (actual RAM) */ - memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", - machine->ram_size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, - main_mem); - - /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); - - /* boot rom */ - memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", - memmap[VIRT_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, - mask_rom); - - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv32-generic-fw_dynamic.bin", - start_addr, NULL); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv64-generic-fw_dynamic.bin", - start_addr, NULL); - } - - if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], - firmware_end_addr); - - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); - } - } else { - /* - * If dynamic firmware is used, it doesn't know where is the next mode - * if kernel argument is not set. - */ - kernel_entry = 0; - } - - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); - /* load the reset vector */ - riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, - virt_memmap[VIRT_MROM].base, - virt_memmap[VIRT_MROM].size, kernel_entry, - fdt_load_addr, machine->fdt); - - serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, - serial_hd(0), DEVICE_LITTLE_ENDIAN); - -} - -static void virt_machine_instance_init(Object *obj) -{ -} - -static void virt_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "RISC-V VirtIO board"; - mc->init = virt_machine_init; - mc->max_cpus = VIRT_CPUS_MAX; - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; - mc->pci_allow_0_address = true; - mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; - mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; - mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; - mc->numa_mem_supported = true; - - machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); -} - -static const TypeInfo virt_machine_typeinfo = { - .name = MACHINE_TYPE_NAME("virt"), - .parent = TYPE_MACHINE, - .class_init = virt_machine_class_init, - .instance_init = virt_machine_instance_init, - .instance_size = sizeof(RISCVVirtState), -}; - -static void virt_machine_init_register_types(void) -{ - type_register_static(&virt_machine_typeinfo); -} - -type_init(virt_machine_init_register_types) - diff --git a/tests/linux-testgen/wallyVirtIO.patch b/tests/linux-testgen/wallyVirtIO.patch deleted file mode 100644 index 76a1d240e..000000000 --- a/tests/linux-testgen/wallyVirtIO.patch +++ /dev/null @@ -1,542 +0,0 @@ -diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c -index 4a3cd2599a..39b46e3122 100644 ---- a/hw/riscv/virt.c -+++ b/hw/riscv/virt.c -@@ -20,6 +20,7 @@ - - #include "qemu/osdep.h" - #include "qemu/units.h" -+#include "qemu/log.h" - #include "qemu/error-report.h" - #include "qapi/error.h" - #include "hw/boards.h" -@@ -44,19 +45,10 @@ - #include "hw/display/ramfb.h" - - static const MemMapEntry virt_memmap[] = { -- [VIRT_DEBUG] = { 0x0, 0x100 }, - [VIRT_MROM] = { 0x1000, 0xf000 }, -- [VIRT_TEST] = { 0x100000, 0x1000 }, -- [VIRT_RTC] = { 0x101000, 0x1000 }, - [VIRT_CLINT] = { 0x2000000, 0x10000 }, -- [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, - [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, - [VIRT_UART0] = { 0x10000000, 0x100 }, -- [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, -- [VIRT_FW_CFG] = { 0x10100000, 0x18 }, -- [VIRT_FLASH] = { 0x20000000, 0x4000000 }, -- [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, -- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, - [VIRT_DRAM] = { 0x80000000, 0x0 }, - }; - -@@ -67,139 +59,23 @@ static const MemMapEntry virt_memmap[] = { - /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ - #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) - --static MemMapEntry virt_high_pcie_memmap; -- - #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) - --static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, -- const char *name, -- const char *alias_prop_name) --{ -- /* -- * Create a single flash device. We use the same parameters as -- * the flash devices on the ARM virt board. -- */ -- DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); -- -- qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); -- qdev_prop_set_uint8(dev, "width", 4); -- qdev_prop_set_uint8(dev, "device-width", 2); -- qdev_prop_set_bit(dev, "big-endian", false); -- qdev_prop_set_uint16(dev, "id0", 0x89); -- qdev_prop_set_uint16(dev, "id1", 0x18); -- qdev_prop_set_uint16(dev, "id2", 0x00); -- qdev_prop_set_uint16(dev, "id3", 0x00); -- qdev_prop_set_string(dev, "name", name); -- -- object_property_add_child(OBJECT(s), name, OBJECT(dev)); -- object_property_add_alias(OBJECT(s), alias_prop_name, -- OBJECT(dev), "drive"); -- -- return PFLASH_CFI01(dev); --} -- --static void virt_flash_create(RISCVVirtState *s) --{ -- s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); -- s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); --} -- --static void virt_flash_map1(PFlashCFI01 *flash, -- hwaddr base, hwaddr size, -- MemoryRegion *sysmem) --{ -- DeviceState *dev = DEVICE(flash); -- -- assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); -- assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); -- qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); -- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -- -- memory_region_add_subregion(sysmem, base, -- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), -- 0)); --} -- --static void virt_flash_map(RISCVVirtState *s, -- MemoryRegion *sysmem) --{ -- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; -- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; -- -- virt_flash_map1(s->flash[0], flashbase, flashsize, -- sysmem); -- virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, -- sysmem); --} -- --static void create_pcie_irq_map(void *fdt, char *nodename, -- uint32_t plic_phandle) --{ -- int pin, dev; -- uint32_t -- full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; -- uint32_t *irq_map = full_irq_map; -- -- /* This code creates a standard swizzle of interrupts such that -- * each device's first interrupt is based on it's PCI_SLOT number. -- * (See pci_swizzle_map_irq_fn()) -- * -- * We only need one entry per interrupt in the table (not one per -- * possible slot) seeing the interrupt-map-mask will allow the table -- * to wrap to any number of devices. -- */ -- for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { -- int devfn = dev * 0x8; -- -- for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { -- int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); -- int i = 0; -- -- irq_map[i] = cpu_to_be32(devfn << 8); -- -- i += FDT_PCI_ADDR_CELLS; -- irq_map[i] = cpu_to_be32(pin + 1); -- -- i += FDT_PCI_INT_CELLS; -- irq_map[i++] = cpu_to_be32(plic_phandle); -- -- i += FDT_PLIC_ADDR_CELLS; -- irq_map[i] = cpu_to_be32(irq_nr); -- -- irq_map += FDT_INT_MAP_WIDTH; -- } -- } -- -- qemu_fdt_setprop(fdt, nodename, "interrupt-map", -- full_irq_map, sizeof(full_irq_map)); -- -- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", -- 0x1800, 0, 0, 0x7); --} -- - static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) - { - void *fdt; -- int i, cpu, socket; -+ //int i, cpu, socket; -+ int cpu, socket; - MachineState *mc = MACHINE(s); - uint64_t addr, size; - uint32_t *clint_cells, *plic_cells; - unsigned long clint_addr, plic_addr; - uint32_t plic_phandle[MAX_NODES]; -- uint32_t cpu_phandle, intc_phandle, test_phandle; -+ uint32_t cpu_phandle, intc_phandle; - uint32_t phandle = 1, plic_mmio_phandle = 1; -- uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; - char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; -- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; -- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; -- static const char * const clint_compat[2] = { -- "sifive,clint0", "riscv,clint0" -- }; -- static const char * const plic_compat[2] = { -- "sifive,plic-1.0.0", "riscv,plic0" -- }; - - if (mc->dtb) { - fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); -@@ -305,8 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - (memmap[VIRT_CLINT].size * socket); - clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(fdt, clint_name); -- qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", -- (char **)&clint_compat, ARRAY_SIZE(clint_compat)); -+ qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, clint_name, "reg", - 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", -@@ -322,8 +197,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, plic_name, - "#interrupt-cells", FDT_PLIC_INT_CELLS); -- qemu_fdt_setprop_string_array(fdt, plic_name, "compatible", -- (char **)&plic_compat, ARRAY_SIZE(plic_compat)); -+ qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); - qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", - plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); -@@ -342,95 +216,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - for (socket = 0; socket < riscv_socket_count(mc); socket++) { - if (socket == 0) { - plic_mmio_phandle = plic_phandle[socket]; -- plic_virtio_phandle = plic_phandle[socket]; -- plic_pcie_phandle = plic_phandle[socket]; -- } -- if (socket == 1) { -- plic_virtio_phandle = plic_phandle[socket]; -- plic_pcie_phandle = plic_phandle[socket]; -- } -- if (socket == 2) { -- plic_pcie_phandle = plic_phandle[socket]; - } - } - - riscv_socket_fdt_write_distance_matrix(mc, fdt); - -- for (i = 0; i < VIRTIO_COUNT; i++) { -- name = g_strdup_printf("/soc/virtio_mmio@%lx", -- (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, -- 0x0, memmap[VIRT_VIRTIO].size); -- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", -- plic_virtio_phandle); -- qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); -- g_free(name); -- } -- -- name = g_strdup_printf("/soc/pci@%lx", -- (long) memmap[VIRT_PCIE_ECAM].base); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); -- qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); -- qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); -- qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); -- qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); -- qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); -- qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, -- memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); -- qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); -- qemu_fdt_setprop_cells(fdt, name, "reg", 0, -- memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); -- qemu_fdt_setprop_sized_cells(fdt, name, "ranges", -- 1, FDT_PCI_RANGE_IOPORT, 2, 0, -- 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, -- 1, FDT_PCI_RANGE_MMIO, -- 2, memmap[VIRT_PCIE_MMIO].base, -- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, -- 1, FDT_PCI_RANGE_MMIO_64BIT, -- 2, virt_high_pcie_memmap.base, -- 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); -- -- create_pcie_irq_map(fdt, name, plic_pcie_phandle); -- g_free(name); -- -- test_phandle = phandle++; -- name = g_strdup_printf("/soc/test@%lx", -- (long)memmap[VIRT_TEST].base); -- qemu_fdt_add_subnode(fdt, name); -- { -- static const char * const compat[3] = { -- "sifive,test1", "sifive,test0", "syscon" -- }; -- qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat, -- ARRAY_SIZE(compat)); -- } -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_TEST].base, -- 0x0, memmap[VIRT_TEST].size); -- qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); -- test_phandle = qemu_fdt_get_phandle(fdt, name); -- g_free(name); -- -- name = g_strdup_printf("/soc/reboot"); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); -- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); -- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); -- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); -- g_free(name); -- -- name = g_strdup_printf("/soc/poweroff"); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); -- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); -- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); -- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); -- g_free(name); -- - name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); -@@ -445,102 +235,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); - g_free(name); - -- name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_RTC].base, -- 0x0, memmap[VIRT_RTC].size); -- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); -- qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); -- g_free(name); -- -- name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); -- qemu_fdt_add_subnode(mc->fdt, name); -- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); -- qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", -- 2, flashbase, 2, flashsize, -- 2, flashbase + flashsize, 2, flashsize); -- qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); -- g_free(name); -- - update_bootargs: - if (cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } - } - --static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, -- hwaddr ecam_base, hwaddr ecam_size, -- hwaddr mmio_base, hwaddr mmio_size, -- hwaddr high_mmio_base, -- hwaddr high_mmio_size, -- hwaddr pio_base, -- DeviceState *plic) --{ -- DeviceState *dev; -- MemoryRegion *ecam_alias, *ecam_reg; -- MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; -- qemu_irq irq; -- int i; -- -- dev = qdev_new(TYPE_GPEX_HOST); -- -- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -- -- ecam_alias = g_new0(MemoryRegion, 1); -- ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); -- memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", -- ecam_reg, 0, ecam_size); -- memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); -- -- mmio_alias = g_new0(MemoryRegion, 1); -- mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); -- memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", -- mmio_reg, mmio_base, mmio_size); -- memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); -- -- /* Map high MMIO space */ -- high_mmio_alias = g_new0(MemoryRegion, 1); -- memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", -- mmio_reg, high_mmio_base, high_mmio_size); -- memory_region_add_subregion(get_system_memory(), high_mmio_base, -- high_mmio_alias); -- -- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); -- -- for (i = 0; i < GPEX_NUM_IRQS; i++) { -- irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); -- -- sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); -- gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); -- } -- -- return dev; --} -- --static FWCfgState *create_fw_cfg(const MachineState *mc) --{ -- hwaddr base = virt_memmap[VIRT_FW_CFG].base; -- hwaddr size = virt_memmap[VIRT_FW_CFG].size; -- FWCfgState *fw_cfg; -- char *nodename; -- -- fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, -- &address_space_memory); -- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); -- -- nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); -- qemu_fdt_add_subnode(mc->fdt, nodename); -- qemu_fdt_setprop_string(mc->fdt, nodename, -- "compatible", "qemu,fw-cfg-mmio"); -- qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", -- 2, base, 2, size); -- qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); -- g_free(nodename); -- return fw_cfg; --} -- - static void virt_machine_init(MachineState *machine) - { - const MemMapEntry *memmap = virt_memmap; -@@ -554,7 +254,7 @@ static void virt_machine_init(MachineState *machine) - target_ulong firmware_end_addr, kernel_start_addr; - uint32_t fdt_load_addr; - uint64_t kernel_entry; -- DeviceState *mmio_plic, *virtio_plic, *pcie_plic; -+ DeviceState *mmio_plic; - int i, j, base_hartid, hart_count; - - /* Check socket count limit */ -@@ -565,7 +265,7 @@ static void virt_machine_init(MachineState *machine) - } - - /* Initialize sockets */ -- mmio_plic = virtio_plic = pcie_plic = NULL; -+ mmio_plic = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { - if (!riscv_socket_check_hartids(machine, i)) { - error_report("discontinuous hartids in socket%d", i); -@@ -634,15 +334,6 @@ static void virt_machine_init(MachineState *machine) - /* Try to use different PLIC instance based device type */ - if (i == 0) { - mmio_plic = s->plic[i]; -- virtio_plic = s->plic[i]; -- pcie_plic = s->plic[i]; -- } -- if (i == 1) { -- virtio_plic = s->plic[i]; -- pcie_plic = s->plic[i]; -- } -- if (i == 2) { -- pcie_plic = s->plic[i]; - } - } - -@@ -654,13 +345,6 @@ static void virt_machine_init(MachineState *machine) - error_report("Limiting RAM size to 10 GiB"); - } - #endif -- virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; -- virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; -- } else { -- virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; -- virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; -- virt_high_pcie_memmap.base = -- ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); - } - - /* register system main memory (actual RAM) */ -@@ -681,10 +365,12 @@ static void virt_machine_init(MachineState *machine) - - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr = riscv_find_and_load_firmware(machine, -- RISCV32_BIOS_BIN, start_addr, NULL); -+ "opensbi-riscv32-generic-fw_dynamic.bin", -+ start_addr, NULL); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, -- RISCV64_BIOS_BIN, start_addr, NULL); -+ "opensbi-riscv64-generic-fw_dynamic.bin", -+ start_addr, NULL); - } - - if (machine->kernel_filename) { -@@ -712,21 +398,6 @@ static void virt_machine_init(MachineState *machine) - kernel_entry = 0; - } - -- if (drive_get(IF_PFLASH, 0, 0)) { -- /* -- * Pflash was supplied, let's overwrite the address we jump to after -- * reset to the base of the flash. -- */ -- start_addr = virt_memmap[VIRT_FLASH].base; -- } -- -- /* -- * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device -- * tree cannot be altered and we get FDT_ERR_NOSPACE. -- */ -- s->fw_cfg = create_fw_cfg(machine); -- rom_set_fw(s->fw_cfg); -- - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); -@@ -736,41 +407,10 @@ static void virt_machine_init(MachineState *machine) - virt_memmap[VIRT_MROM].size, kernel_entry, - fdt_load_addr, machine->fdt); - -- /* SiFive Test MMIO device */ -- sifive_test_create(memmap[VIRT_TEST].base); -- -- /* VirtIO MMIO devices */ -- for (i = 0; i < VIRTIO_COUNT; i++) { -- sysbus_create_simple("virtio-mmio", -- memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, -- qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); -- } -- -- gpex_pcie_init(system_memory, -- memmap[VIRT_PCIE_ECAM].base, -- memmap[VIRT_PCIE_ECAM].size, -- memmap[VIRT_PCIE_MMIO].base, -- memmap[VIRT_PCIE_MMIO].size, -- virt_high_pcie_memmap.base, -- virt_high_pcie_memmap.size, -- memmap[VIRT_PCIE_PIO].base, -- DEVICE(pcie_plic)); -- -- serial_mm_init(system_memory, memmap[VIRT_UART0].base, -+ serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, - serial_hd(0), DEVICE_LITTLE_ENDIAN); - -- sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, -- qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); -- -- virt_flash_create(s); -- -- for (i = 0; i < ARRAY_SIZE(s->flash); i++) { -- /* Map legacy -drive if=pflash to machine properties */ -- pflash_cfi01_legacy_drive(s->flash[i], -- drive_get(IF_PFLASH, 0, i)); -- } -- virt_flash_map(s, system_memory); - } - - static void virt_machine_instance_init(Object *obj) -diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c -index 991a6bb760..401028b8d9 100644 ---- a/target/riscv/cpu.c -+++ b/target/riscv/cpu.c -@@ -269,6 +269,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); -+ - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - } From 4eb46785fc060bd29de46da1561be2be563630c4 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 5 Mar 2022 18:04:00 -0800 Subject: [PATCH 111/199] change genInitMem.sh to check for sufficient directory privileges rather than invoke sudo --- linux/testvector-generation/genInitMem.sh | 44 +++++++---------------- 1 file changed, 13 insertions(+), 31 deletions(-) diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index e300c2f0c..3e0aef83a 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -20,24 +20,18 @@ Would you like to proceed? (y/n) " -n 1 -r echo if [[ $REPLY =~ ^[Yy]$ ]] then - # Create Output Directory - echo "Elevating permissions to create memory files" - sudo mkdir -p $tvDir - sudo chown cad $tvDir - sudo touch $rawRamFile - sudo touch $ramFile - sudo touch $rawBootmemFile - sudo touch $bootmemFile - sudo touch $rawUntrimmedBootmemFile - sudo touch $untrimmedBootmemFile - sudo chmod a+rw $rawRamFile - sudo chmod a+rw $ramFile - sudo chmod a+rw $rawBootmemFile - sudo chmod a+rw $bootmemFile - sudo chmod a+rw $rawUntrimmedBootmemFile - sudo chmod a+rw $untrimmedBootmemFile + if [ ! -d "$tvDir" ]; then + echo "Error: linux testvector directory $tvDir not found!">&2 + echo "Please create it.">&2 + exit 1 + fi + test -w $RISCV/linux-testvectors + if [ ! $? -eq 0 ]; then + echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 + echo "Please chmod it.">&2 + exit 1 + fi - # QEMU Simulation echo "Launching QEMU in replay mode!" (qemu-system-riscv64 \ -M virt -dtb $RISCV/buildroot/output/images/wally-virt.dtb \ @@ -67,18 +61,6 @@ then ./fixBinMem "$rawBootmemFile" "$bootmemFile" ./fixBinMem "$rawUntrimmedBootmemFile" "$untrimmedBootmemFile" - # Cleanup - echo "Elevating permissions to restrict write access to memory files" - sudo chown cad $rawRamFile - sudo chown cad $ramFile - sudo chown cad $rawBootmemFile - sudo chown cad $bootmemFile - sudo chown cad $rawUntrimmedBootmemFile - sudo chown cad $untrimmedBootmemFile - sudo chmod o-w $rawRamFile - sudo chmod o-w $ramFile - sudo chmod o-w $rawBootmemFile - sudo chmod o-w $bootmemFile - sudo chmod o-w $rawUntrimmedBootmemFile - sudo chmod o-w $untrimmedBootmemFile + echo "genInitMem.sh completed!" + echo "You may consider restricting write access to $tvDir now." fi From 1fc7856c36c9506522d3bf8675d59dc737ff935d Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 5 Mar 2022 19:02:07 -0800 Subject: [PATCH 112/199] add extractFunctionRadix step to buildroot Makefile --- linux/buildroot-scripts/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile index 53673c9c2..5589fe517 100644 --- a/linux/buildroot-scripts/Makefile +++ b/linux/buildroot-scripts/Makefile @@ -12,7 +12,7 @@ generate: disassemble: mkdir -p ${DIS} # disassemblies - make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump ${DIS}/busybox.objdump + make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump ${DIS}/busybox.objdump ${DIS}/vmlinux.objdump.addr # filesystem make ${DIS}/rootfs/bin/busybox # mkdir -p ${DIS}/rootfs @@ -24,6 +24,9 @@ ${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf ${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux riscv64-unknown-elf-objdump -D ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump +${DIS}/vmlinux.objdump.addr: ${DIS}/vmlinux.objdump + -cd ${DIS}; extractFunctionRadix.sh vmlinux.objdump + ${DIS}/busybox.objdump: ${DIS}/rootfs/bin/busybox riscv64-unknown-elf-objdump -D ${DIS}/rootfs/bin/busybox >> ${DIS}/busybox.objdump From 7391c6d3385a589545be055318348d1f790f08c2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 6 Mar 2022 13:29:35 +0000 Subject: [PATCH 113/199] Checked in fma16_template.v --- examples/fp/fpcalc/fpcalc.c | 2 +- pipelined/src/fma/fma16_template.v | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 pipelined/src/fma/fma16_template.v diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index b8e180bf7..b29b4c8ef 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -128,7 +128,7 @@ void printF64(char *msg, float64_t f) { printf("_"); printf("%04x", (conv.v >> 32) & 0xFFFF); printf("_"); - printf("%04x", (conv.v >> 16)); + printf("%04x", (conv.v >> 16) & 0xFFFF); printf("_"); printf("%04x", (conv.v & 0xFFFF)); printf(" = %lg = %s: Biased Exp %d Fract 0x%lx\n", conv.d, sci, exp, fract); diff --git a/pipelined/src/fma/fma16_template.v b/pipelined/src/fma/fma16_template.v new file mode 100644 index 000000000..70d06a771 --- /dev/null +++ b/pipelined/src/fma/fma16_template.v @@ -0,0 +1,24 @@ +// fma16.sv +// David_Harris@hmc.edu 26 February 2022 +// 16-bit floating-point multiply-accumulate + +// Operation: general purpose multiply, add, fma, with optional negation +// If mul=1, p = x * y. Else p = x. +// If add=1, result = p + z. Else result = p. +// If negr or negz = 1, negate result or z to handle negations and subtractions +// fadd: mul = 0, add = 1, negr = negz = 0 +// fsub: mul = 0, add = 1, negr = 0, negz = 1 +// fmul: mul = 1, add = 0, negr = 0, negz = 0 +// fmadd: mul = 1, add = 1, negr = 0, negz = 0 +// fmsub: mul = 1, add = 1, negr = 0, negz = 1 +// fnmadd: mul = 1, add = 1, negr = 1, negz = 0 +// fnmsub: mul = 1, add = 1, negr = 1, negz = 1 + +module fma16( + input logic [15:0] x, y, z, + input logic mul, add, negr, negz, + input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn + output logic [15:0] result); + +endmodule + From 64d4cad2889c179f477271a25857271a6932c035 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 6 Mar 2022 13:39:53 +0000 Subject: [PATCH 114/199] Restored setup.sh to use . Working for David. Not sure what is happening for Ben - are you on Bash? --- setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.sh b/setup.sh index de048ed60..925d87e83 100755 --- a/setup.sh +++ b/setup.sh @@ -7,7 +7,7 @@ echo "Executing Wally setup.sh" # Path to Wally repository -WALLY=$(dirname $0) +WALLY=$(dirname ${BASH_SOURCE}) export WALLY=$(cd "$WALLY" && pwd) echo \$WALLY set to ${WALLY} From 70ddc98d1915752b4942ce2c1398a15474277faf Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 12:48:53 -0800 Subject: [PATCH 115/199] Revert "fix "dirname: missing operand" bug from setup.sh" This reverts commit 60cbd1c9c13cedbdbf635b41a7745f98d726a01d. --- setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.sh b/setup.sh index de048ed60..925d87e83 100755 --- a/setup.sh +++ b/setup.sh @@ -7,7 +7,7 @@ echo "Executing Wally setup.sh" # Path to Wally repository -WALLY=$(dirname $0) +WALLY=$(dirname ${BASH_SOURCE}) export WALLY=$(cd "$WALLY" && pwd) echo \$WALLY set to ${WALLY} From b1120069a091a67493147362eeed06ff52720f81 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 13:12:20 -0800 Subject: [PATCH 116/199] generate $WALLY in a way that works for bash and zsh --- setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.sh b/setup.sh index 925d87e83..0d990d9da 100755 --- a/setup.sh +++ b/setup.sh @@ -7,7 +7,7 @@ echo "Executing Wally setup.sh" # Path to Wally repository -WALLY=$(dirname ${BASH_SOURCE}) +WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) export WALLY=$(cd "$WALLY" && pwd) echo \$WALLY set to ${WALLY} From efee8d3a22fd42f3c5458e23f795fe9141bc3d3f Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 13:18:53 -0800 Subject: [PATCH 117/199] change from clang to gcc when compiling testvector-generation executables --- linux/testvector-generation/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/testvector-generation/Makefile b/linux/testvector-generation/Makefile index 8f3441e5a..54f95f20e 100644 --- a/linux/testvector-generation/Makefile +++ b/linux/testvector-generation/Makefile @@ -1,7 +1,7 @@ SHELL = /bin/sh CFLAG = -Wall -g -CC = clang +CC = gcc all: fixBinMem silencePipe From e3f735cc1a3a5c4d22aea831c7ff602a52c286ec Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 13:30:19 -0800 Subject: [PATCH 118/199] recommend sudo commands without automatically executing them in genInitMem.sh --- linux/testvector-generation/genInitMem.sh | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index 3e0aef83a..d1e28fa33 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -22,13 +22,15 @@ if [[ $REPLY =~ ^[Yy]$ ]] then if [ ! -d "$tvDir" ]; then echo "Error: linux testvector directory $tvDir not found!">&2 - echo "Please create it.">&2 + echo "Please create it. For example:">&2 + echo " sudo mkdir -p $tvDir">&2 exit 1 fi test -w $RISCV/linux-testvectors if [ ! $? -eq 0 ]; then echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 - echo "Please chmod it.">&2 + echo "Please chmod it. For example:">&2 + echo " sudo chmod a+rw $tvDir">&2 exit 1 fi @@ -62,5 +64,8 @@ then ./fixBinMem "$rawUntrimmedBootmemFile" "$untrimmedBootmemFile" echo "genInitMem.sh completed!" - echo "You may consider restricting write access to $tvDir now." + echo "You may want to restrict write access to $tvDir now and give cad ownership of it." + echo "Run the following:" + echo " sudo chown -R cad:cad $tvDir" + echo " sudo chmod -R go-w $tvDir" fi From bb90644fb2e7e3757cf12813844d1dcb9c756705 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 13:55:19 -0800 Subject: [PATCH 119/199] add path to Modelsim on vlsi --- setup.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/setup.sh b/setup.sh index 0d990d9da..c5ba9ebf3 100755 --- a/setup.sh +++ b/setup.sh @@ -27,6 +27,7 @@ export PATH=$WALLY/bin:$PATH export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator # ModelSim/Questa (vsim) export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim +export PATH=/cad/mentor/questa_sim-2022.1_1/questasim/bin:$PATH # Change this for your path to Modelsim export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler export SNPSLMD_LICENSE_FILE=27020@134.173.38.214 From 742b9d884d4f7e16733f3cc9b4bac07ccf68f6d3 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:04:30 -0800 Subject: [PATCH 120/199] remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI --- ...n-on-logging-mid-execution-using-GDB.patch | 53 ------------------- .../createGenCheckpointScript.py | 21 ++------ linux/testvector-generation/genCheckpoint.sh | 23 +++----- 3 files changed, 10 insertions(+), 87 deletions(-) delete mode 100644 linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch diff --git a/linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch b/linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch deleted file mode 100644 index 1b0e1d4aa..000000000 --- a/linux/testvector-generation/0001-bens-hack-to-turn-on-logging-mid-execution-using-GDB.patch +++ /dev/null @@ -1,53 +0,0 @@ -From f9882bd274bde82d8c38a9c31692b6ee33d8cd9a Mon Sep 17 00:00:00 2001 -From: root -Date: Mon, 28 Feb 2022 22:48:29 +0000 -Subject: [PATCH] bens hack to turn on logging mid-execution using GDB - ---- - gdbstub.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/gdbstub.c b/gdbstub.c -index 141d7bc4ec..98ecce1b67 100644 ---- a/gdbstub.c -+++ b/gdbstub.c -@@ -2317,6 +2317,23 @@ static void handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx) - } - put_packet("OK"); - } -+ -+static void handle_set_qemu_logging(GArray *params, void *user_ctx) -+{ -+ if (!params->len) { -+ put_packet("E22"); -+ return; -+ } -+ -+ int log_mask; -+ if (!get_param(params, 0)->val_ul) { -+ log_mask = 0; -+ } else { -+ log_mask = CPU_LOG_TB_IN_ASM | CPU_LOG_INT | CPU_LOG_TB_CPU | CPU_LOG_TB_NOCHAIN; -+ } -+ qemu_set_log(log_mask); -+ put_packet("OK"); -+} - #endif - - static const GdbCmdParseEntry gdb_gen_query_set_common_table[] = { -@@ -2430,6 +2447,12 @@ static const GdbCmdParseEntry gdb_gen_set_table[] = { - .cmd_startswith = 1, - .schema = "l0" - }, -+ { -+ .handler = handle_set_qemu_logging, -+ .cmd = "qemu.Logging:", -+ .cmd_startswith = 1, -+ .schema = "l0" -+ }, - #endif - }; - --- -2.27.0 - diff --git a/linux/testvector-generation/createGenCheckpointScript.py b/linux/testvector-generation/createGenCheckpointScript.py index 02d1bcc76..264a2ee6e 100755 --- a/linux/testvector-generation/createGenCheckpointScript.py +++ b/linux/testvector-generation/createGenCheckpointScript.py @@ -1,7 +1,7 @@ #! /usr/bin/python3 import sys -if len(sys.argv) != 9: +if len(sys.argv) != 8: sys.exit("""Error createGenCheckpointScript.py expects 7 args: @@ -9,8 +9,7 @@ if len(sys.argv) != 9: - - """) + """) tcpPort=sys.argv[1] vmlinux=sys.argv[2] @@ -19,7 +18,6 @@ statePath=sys.argv[4] ramPath=sys.argv[5] checkPC=sys.argv[6] checkPCoccurences=sys.argv[7] -genTrace=sys.argv[8] GDBscript = f""" # GDB config @@ -56,20 +54,7 @@ set logging off # Log main memory to a file print "GDB storing RAM to {ramPath}\\n" dump binary memory {ramPath} 0x80000000 0xffffffff -""" -if (genTrace=="1"): - GDBscript+=\ -""" -# Generate Trace Until End -maintenance packet Qqemu.Logging:1 -# Do this by setting an impossible breakpoint -b *0x1000 -del 1 -c -""" -else: - GDBscript+=\ -""" + kill q """ diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 834ef6bb6..87e295414 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -6,12 +6,11 @@ recordFile="$tvDir/all.qemu" traceFile="$tvDir/all.txt" # Parse Commandline Arg -if [ "$#" -ne 2 ]; then - echo "genCheckpoint requires 2 arguments: " >&2 +if [ "$#" -ne 1 ]; then + echo "genCheckpoint requires 1 argument: " >&2 exit 1 fi instrs=$1 -genTrace=$2 if ! [ "$instrs" -eq "$instrs" ] 2> /dev/null then echo "Error expected integer number of instructions, got $instrs" >&2 @@ -25,14 +24,8 @@ rawStateFile="$checkPtDir/stateGDB.txt" rawRamFile="$checkPtDir/ramGDB.bin" ramFile="$checkPtDir/ram.bin" -if [ $genTrace -eq "1" ]; then - read -p "This scripts is going to create a checkpoint at $instrs instrs. - AND it's going to start generating a trace at that checkpoint. - Is that what you wanted? (y/n) " -n 1 -r -else - read -p "This scripts is going to create a checkpoint at $instrs instrs. - Is that what you wanted? (y/n) " -n 1 -r -fi +read -p "This scripts is going to create a checkpoint at $instrs instrs. +Is that what you wanted? (y/n) " -n 1 -r echo if [[ $REPLY =~ ^[Yy]$ ]] then @@ -63,7 +56,7 @@ then echo "It occurs ${occurences} times before the ${instrs}th instr." # Create GDB script because GDB is terrible at handling arguments / variables - ./createGenCheckpointScript.py $tcpPort $imageDir/vmlinux $instrs $rawStateFile $rawRamFile $pc $occurences $genTrace + ./createGenCheckpointScript.py $tcpPort $imageDir/vmlinux $instrs $rawStateFile $rawRamFile $pc $occurences # GDB+QEMU echo "Starting QEMU in replay mode with attached GDB script at $(date +%H:%M:%S)" (qemu-system-riscv64 \ @@ -81,10 +74,8 @@ then echo "Changing Endianness at $(date +%H:%M:%S)" make fixBinMem ./fixBinMem "$rawRamFile" "$ramFile" - if [ $genTrace -ne "1" ]; then - echo "Copying over a truncated trace" - tail -n+$instrs $traceFile > $outTraceFile - fi + echo "Copying over a truncated trace" + tail -n+$instrs $traceFile > $outTraceFile read -p "Checkpoint completed at $(date +%H:%M:%S)" -n 1 -r # Cleanup From 91f327e1099df93fcac6a97eb922802d7e1deefc Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:16:23 -0800 Subject: [PATCH 121/199] small bugfix to suggested sudo commands for linux testvectors --- linux/testvector-generation/genInitMem.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index d1e28fa33..7917d725e 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -30,7 +30,7 @@ then if [ ! $? -eq 0 ]; then echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 echo "Please chmod it. For example:">&2 - echo " sudo chmod a+rw $tvDir">&2 + echo " sudo chmod -R a+rw $tvDir">&2 exit 1 fi From e57b5208dc5342fbafec8a12ef7206a93c2bbcfe Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:24:50 -0800 Subject: [PATCH 122/199] replace sudo's in genTrace.sh with suggested commands --- linux/testvector-generation/genTrace.sh | 38 ++++++++++++++----------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh index 6c3548be5..4c31ce6b6 100755 --- a/linux/testvector-generation/genTrace.sh +++ b/linux/testvector-generation/genTrace.sh @@ -13,32 +13,36 @@ Would you like to proceed? (y/n) " -n 1 -r echo if [[ $REPLY =~ ^[Yy]$ ]] then - # Create Output Directory - echo "Elevating permissions to create $traceFile, $interruptsFile" - sudo mkdir -p $tvDir - sudo chown cad $tvDir - sudo touch $traceFile - sudo touch $interruptsFile - sudo chmod a+rw $traceFile - sudo chmod a+rw $interruptsFile + if [ ! -d "$tvDir" ]; then + echo "Error: linux testvector directory $tvDir not found!">&2 + echo "Please create it. For example:">&2 + echo " sudo mkdir -p $tvDir">&2 + exit 1 + fi + test -w $RISCV/linux-testvectors + if [ ! $? -eq 0 ]; then + echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 + echo "Please chmod it. For example:">&2 + echo " sudo chmod -R a+rw $tvDir">&2 + exit 1 + fi - # Compile Devicetree from Source - dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb + touch $traceFile + touch $interruptsFile # QEMU Simulation echo "Launching QEMU in replay mode!" (qemu-system-riscv64 \ - -M virt -dtb ../devicetree/wally-virt.dtb \ + -M virt -dtb $imageDir/wally-virt.dtb \ -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ -d nochain,cpu,in_asm,int \ 2>&1 >/dev/null | ./parseQEMUtoGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) - # Cleanup - echo "Elevating permissions to restrict write access to $traceFile, $interruptsFile" - sudo chown cad $traceFile - sudo chown cad $interruptsFile - sudo chmod o-w $traceFile - sudo chmod o-w $interruptsFile + echo "genTrace.sh completed!" + echo "You may want to restrict write access to $tvDir now and give cad ownership of it." + echo "Run the following:" + echo " sudo chown -R cad:cad $tvDir" + echo " sudo chmod -R go-w $tvDir" fi From 8f2e67984f547c657d1dd1c4f5c4a68c81338091 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:31:55 -0800 Subject: [PATCH 123/199] replace sudo's with suggestions in genRecording.sh --- linux/testvector-generation/genRecording.sh | 36 ++++++++++++--------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/linux/testvector-generation/genRecording.sh b/linux/testvector-generation/genRecording.sh index d7319413a..f9538e145 100755 --- a/linux/testvector-generation/genRecording.sh +++ b/linux/testvector-generation/genRecording.sh @@ -8,26 +8,30 @@ Would you like to proceed? (y/n) " -n 1 -r echo if [[ $REPLY =~ ^[Yy]$ ]] then - # Create Output Directory - echo "Elevating permissions to create $recordFile" - sudo mkdir -p $tvDir - sudo chown cad $tvDir - sudo touch $recordFile - sudo chmod a+rw $recordFile + if [ ! -d "$tvDir" ]; then + echo "Error: linux testvector directory $tvDir not found!">&2 + echo "Please create it. For example:">&2 + echo " sudo mkdir -p $tvDir">&2 + exit 1 + fi + test -w $tvDir + if [ ! $? -eq 0 ]; then + echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 + echo "Please chmod it. For example:">&2 + echo " sudo chmod -R a+rw $tvDir">&2 + exit 1 + fi - # Compile Devicetree from Source - dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb - - # QEMU Simulation - echo "Launching QEMU!" + echo "Launching QEMU in record mode!" qemu-system-riscv64 \ - -M virt -dtb ../devicetree/wally-virt.dtb \ + -M virt -dtb $imageDir/wally-virt.dtb \ -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile - # Cleanup - echo "Elevating permissions to restrict write access to $recordFile" - sudo chown cad $recordFile - sudo chmod o-w $recordFile + echo "genRecording.sh completed!" + echo "You may want to restrict write access to $tvDir now and give cad ownership of it." + echo "Run the following:" + echo " sudo chown -R cad:cad $tvDir" + echo " sudo chmod -R go-w $tvDir" fi From 7182ec228fd24e47cbdaf2a34a6f5a73740a6fe6 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:33:53 -0800 Subject: [PATCH 124/199] better to use $tvDir variable rather than abs path --- linux/testvector-generation/genInitMem.sh | 2 +- linux/testvector-generation/genTrace.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index 7917d725e..27a3f004a 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -26,7 +26,7 @@ then echo " sudo mkdir -p $tvDir">&2 exit 1 fi - test -w $RISCV/linux-testvectors + test -w $tvDir if [ ! $? -eq 0 ]; then echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 echo "Please chmod it. For example:">&2 diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh index 4c31ce6b6..91485e383 100755 --- a/linux/testvector-generation/genTrace.sh +++ b/linux/testvector-generation/genTrace.sh @@ -19,7 +19,7 @@ then echo " sudo mkdir -p $tvDir">&2 exit 1 fi - test -w $RISCV/linux-testvectors + test -w $tvDir if [ ! $? -eq 0 ]; then echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 echo "Please chmod it. For example:">&2 From f64b7776ede67d1dc8be142596daf28600ba59f7 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:37:12 -0800 Subject: [PATCH 125/199] give genCheckpoint the same de-sudo'ing treatement --- linux/testvector-generation/genCheckpoint.sh | 39 +++++++++----------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 87e295414..748dab934 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -30,23 +30,20 @@ echo if [[ $REPLY =~ ^[Yy]$ ]] then echo "Creating checkpoint at $instrs instructions!" + if [ ! -d "$tvDir" ]; then + echo "Error: linux testvector directory $tvDir not found!">&2 + echo "Please create it. For example:">&2 + echo " sudo mkdir -p $tvDir">&2 + exit 1 + fi + test -w $tvDir + if [ ! $? -eq 0 ]; then + echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 + echo "Please chmod it. For example:">&2 + echo " sudo chmod -R a+rw $tvDir">&2 + exit 1 + fi - # Create Output Directory - echo "Elevating permissions to create $checkPtDir and stuff inside it" - sudo mkdir -p $checkPtDir - sudo chown -R cad:users $checkPtDir - sudo chmod -R a+rw $checkPtDir - sudo touch $outTraceFile - sudo chmod a+rw $outTraceFile - sudo touch $interruptsFile - sudo chmod a+rw $interruptsFile - sudo touch $rawStateFile - sudo chmod a+rw $rawStateFile - sudo touch $rawRamFile - sudo chmod a+rw $rawRamFile - sudo touch $ramFile - sudo chmod a+rw $ramFile - # Identify instruction in trace instr=$(sed "${instrs}q;d" "$traceFile") echo "Found ${instrs}th instr: ${instr}" @@ -76,11 +73,11 @@ then ./fixBinMem "$rawRamFile" "$ramFile" echo "Copying over a truncated trace" tail -n+$instrs $traceFile > $outTraceFile - read -p "Checkpoint completed at $(date +%H:%M:%S)" -n 1 -r - # Cleanup - echo "Elevating permissions to restrict write access to $checkPtDir" - sudo chown -R cad:users $checkPtDir - sudo chmod -R go-w $checkPtDir + echo "Checkpoint completed at $(date +%H:%M:%S)" + echo "You may want to restrict write access to $tvDir now and give cad ownership of it." + echo "Run the following:" + echo " sudo chown -R cad:cad $tvDir" + echo " sudo chmod -R go-w $tvDir" fi From d007208aa9c255c1868199a83a4777db3a5dfb8a Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:40:26 -0800 Subject: [PATCH 126/199] no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit --- linux/testvector-generation/genCheckpoint.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 748dab934..c845bc33c 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -62,7 +62,7 @@ then -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ -gdb tcp::$tcpPort -S \ - 2>&1 1>./qemu-serial | ./parseQEMUtoGDB/parseQEMUtoGDB_run.py | ./parseGDBtoTrace/parseGDBtoTrace_run.py $interruptsFile | ./remove_dup.awk > $outTraceFile) \ + 2>&1 1>./qemu-serial | ./parseQEMUtoGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $outTraceFile) \ & riscv64-unknown-elf-gdb --quiet -ex "source genCheckpoint.gdb" echo "Completed GDB script at $(date +%H:%M:%S)" From 11e9bbf3e4ffe975452d54140be0693b153d8158 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:51:25 -0800 Subject: [PATCH 127/199] needed to initialize checkpoint directory --- linux/testvector-generation/genCheckpoint.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index c845bc33c..792925b7e 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -44,6 +44,8 @@ then exit 1 fi + mkdir -p $checkPtDir + # Identify instruction in trace instr=$(sed "${instrs}q;d" "$traceFile") echo "Found ${instrs}th instr: ${instr}" From bea2faeda6b933c834189888b61a97933d9daa2e Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:54:35 -0800 Subject: [PATCH 128/199] remove vestigial silencePipe mechanism --- linux/testvector-generation/Makefile | 6 +----- linux/testvector-generation/silencePipe.c | 21 --------------------- 2 files changed, 1 insertion(+), 26 deletions(-) delete mode 100644 linux/testvector-generation/silencePipe.c diff --git a/linux/testvector-generation/Makefile b/linux/testvector-generation/Makefile index 54f95f20e..c31aae39d 100644 --- a/linux/testvector-generation/Makefile +++ b/linux/testvector-generation/Makefile @@ -3,15 +3,11 @@ SHELL = /bin/sh CFLAG = -Wall -g CC = gcc -all: fixBinMem silencePipe +all: fixBinMem fixBinMem: fixBinMem.c ${CC} ${CFLAGS} fixBinMem.c -o fixBinMem chmod +x fixBinMem -silencePipe: silencePipe.c - ${CC} ${CFLAGS} silencePipe.c -o silencePipe - chmod +x silencePipe clean: -rm -f fixBinMem - -rm -f silencePipe diff --git a/linux/testvector-generation/silencePipe.c b/linux/testvector-generation/silencePipe.c deleted file mode 100644 index 3ffeb14b4..000000000 --- a/linux/testvector-generation/silencePipe.c +++ /dev/null @@ -1,21 +0,0 @@ -#include -#include - -int main(void) -{ - char *line = NULL; - size_t len = 0; - while (1) { - FILE* controlFile = fopen("silencePipe.control", "r"); - char silenceChar = getc(controlFile); - fclose(controlFile); - ssize_t lineSize = getline(&line, &len, stdin); - if (silenceChar!='1') { - printf("%s",line); - } else { - fprintf(stderr,"%s",line); - } - } - free(line); - return 0; -} From 483aad2a059786c8c3cb981c22e9a445985e73eb Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 6 Mar 2022 14:55:51 -0800 Subject: [PATCH 129/199] update checkpointSweep in accordance to having removed trace parsing feature --- linux/testvector-generation/checkpointSweep.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/testvector-generation/checkpointSweep.sh b/linux/testvector-generation/checkpointSweep.sh index 74ed9ecf5..c1543677c 100755 --- a/linux/testvector-generation/checkpointSweep.sh +++ b/linux/testvector-generation/checkpointSweep.sh @@ -1,5 +1,5 @@ for index in {450..500} do instrs=$(($index*1000000)) - echo "y" | nice -n 5 ./genCheckpoint.sh $instrs 0 + echo "y" | nice -n 5 ./genCheckpoint.sh $instrs done From a68c1c8cb195d3042a2b52fb218c8deb24b6bc98 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Thu, 3 Mar 2022 00:22:14 +0000 Subject: [PATCH 130/199] modified makefile --- synthDC/Makefile | 8 ++++++-- synthDC/extractSummary.py | 2 ++ 2 files changed, 8 insertions(+), 2 deletions(-) mode change 100644 => 100755 synthDC/extractSummary.py diff --git a/synthDC/Makefile b/synthDC/Makefile index b359046eb..9f380584b 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -1,6 +1,6 @@ # # Makefile for synthesis -# +# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 NAME := synth # defaults @@ -26,6 +26,7 @@ CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) print: echo $(CONFIGFILESTRIM) + echo $(DIRS) default: @echo "Basic synthesis procedure for Wally:" @@ -38,10 +39,13 @@ rv%.log: rv% echo $< -DIRS = rv32e rv32gc rv64ic rv64gc rv32ic +DIRS = rv64gc #rv32e rv32gc rv64ic rv64gc rv32ic # DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic # CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig +copy: + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) + @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) del: @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py old mode 100644 new mode 100755 index e9fa69772..8462a2456 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -1,3 +1,5 @@ +#!/usr/bin/python3 +# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 import glob import re import csv From bc049e804226c0cfe457a4317fe45994748028f1 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Mon, 7 Mar 2022 00:08:47 +0000 Subject: [PATCH 131/199] updated makefile to speed up synth --- synthDC/Makefile | 20 ++++++-------------- synthDC/extractSummary.py | 6 ++++-- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 9f380584b..9bbb41c49 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -39,13 +39,16 @@ rv%.log: rv% echo $< -DIRS = rv64gc #rv32e rv32gc rv64ic rv64gc rv32ic +DIRS = rv32e rv32gc rv64ic rv64gc rv32ic # DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic # CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig copy: @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) + @$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) + @$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) + @$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) del: @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) @@ -59,39 +62,28 @@ configs: $(DIRS) $(DIRS): #turn off FPU rm -rf $(CONFIGDIR)/$@_FPUoff - cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_FPUoff + cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh # PMP 16 rm -rf $(CONFIGDIR)/$@_PMP16 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 - # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP16/wally-config.vh - # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP16/wally-config.vh sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh # PMP 0 rm -rf $(CONFIGDIR)/$@_PMP0 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 - # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP0/wally-config.vh - # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP0/wally-config.vh sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh # No Virtual Memory rm -rf $(CONFIGDIR)/$@_noVirtMem - # cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_noVirtMem - # sed -i 's/1 *<< *3/0 <_PMP0< 3/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh - # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh - # sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noVirtMem sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh #no muldiv rm -rf $(CONFIGDIR)/$@_noMulDiv cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv - # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - # sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - # sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 8462a2456..85ab99ec6 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -4,7 +4,7 @@ import glob import re import csv -field_names = [ 'Name', 'Critical Path Length', 'Cell Area'] +field_names = [ 'Name', 'Critical Path Length', 'Cell Area', 'Synth Time'] data = [] for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypipelinedcore_qor.rep"): f = open(name, 'r') @@ -15,7 +15,9 @@ for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypi pathLen = re.search("Length: *(.*?)\\n", line).group(1) if "Cell Area" in line: area = re.search("Area: *(.*?)\\n", line).group(1) - data += [{'Name' : trimName, 'Critical Path Length': pathLen, 'Cell Area' : area}] + if "Overall Compile Time" in line: + time = re.search("Time: *(.*?)\\n", line).group(1) + data += [{'Name' : trimName, 'Critical Path Length': pathLen, 'Cell Area' : area, 'Synth Time' :time}] with open('Summary.csv', 'w') as csvfile: writer = csv.DictWriter(csvfile, fieldnames=field_names) From 94a57fb6eb65be08b199e825d8e526eefacac3c3 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Mon, 7 Mar 2022 17:12:43 +0000 Subject: [PATCH 132/199] modified synth script to take config from outputdir --- synthDC/Makefile | 2 +- synthDC/scripts/synth.tcl | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 9bbb41c49..b6d066d2e 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -39,7 +39,7 @@ rv%.log: rv% echo $< -DIRS = rv32e rv32gc rv64ic rv64gc rv32ic +DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic # DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic # CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 3146e14ed..04366ed6c 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -22,7 +22,7 @@ set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) -eval file copy -force ${cfg} {hdl/} +# eval file copy -force ${cfg} {hdl/} eval file copy -force ${cfg} $outputDir eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} @@ -34,7 +34,7 @@ if { $saifpower == 1 } { } # Verilog files -set my_verilog_files [glob hdl/*] +set my_verilog_files [glob hdl/* outputDir/wally-config.vh] # Set toplevel set my_toplevel $::env(DESIGN) From a218a3d9fac8093d05e74e9093ca861d709e5b39 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Mon, 7 Mar 2022 17:32:08 +0000 Subject: [PATCH 133/199] undid changes to synth script --- synthDC/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index b6d066d2e..b1452f0e2 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -90,8 +90,9 @@ $(DIRS): allsynth: $(CONFIGFILESTRIM) $(CONFIGFILESTRIM): - make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1 --jobs + make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1 + synth: @echo "DC Synthesis" @mkdir -p hdl/ From c15517d334c247e45a84fbe8a79beacc7b8501c8 Mon Sep 17 00:00:00 2001 From: Shreya Sanghai Date: Mon, 7 Mar 2022 17:36:05 +0000 Subject: [PATCH 134/199] removed reminant changes --- synthDC/scripts/synth.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 04366ed6c..3146e14ed 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -22,7 +22,7 @@ set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) -# eval file copy -force ${cfg} {hdl/} +eval file copy -force ${cfg} {hdl/} eval file copy -force ${cfg} $outputDir eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} @@ -34,7 +34,7 @@ if { $saifpower == 1 } { } # Verilog files -set my_verilog_files [glob hdl/* outputDir/wally-config.vh] +set my_verilog_files [glob hdl/*] # Set toplevel set my_toplevel $::env(DESIGN) From 4bf95714eb0b0b2694035f7e0a69a2bbbd798d63 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 7 Mar 2022 19:52:19 +0000 Subject: [PATCH 135/199] add debug.sh --- linux/testvector-generation/debug.sh | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100755 linux/testvector-generation/debug.sh diff --git a/linux/testvector-generation/debug.sh b/linux/testvector-generation/debug.sh new file mode 100755 index 000000000..c667429cf --- /dev/null +++ b/linux/testvector-generation/debug.sh @@ -0,0 +1,14 @@ +#!/bin/bash +imageDir=$RISCV/buildroot/output/images +tvDir=$RISCV/linux-testvectors +tcpPort=1239 + +# QEMU Simulation +(qemu-system-riscv64 \ +-M virt -dtb $imageDir/wally-virt.dtb \ +-nographic \ +-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ +-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \ +> ./qemu-serial) # \ +#-gdb tcp::$tcpPort -S \ +#& riscv64-unknown-elf-gdb -quiet -x debug.gdb -ex "debug $tcpPort \"$imageDir/vmlinux\"" From 409dd4870672cdc5fffe4810c5922a2307f16cea Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 7 Mar 2022 11:56:04 -0800 Subject: [PATCH 136/199] modify debug.sh to not rely on external GDB script --- linux/testvector-generation/debug.sh | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/linux/testvector-generation/debug.sh b/linux/testvector-generation/debug.sh index c667429cf..748f6e023 100755 --- a/linux/testvector-generation/debug.sh +++ b/linux/testvector-generation/debug.sh @@ -9,6 +9,13 @@ tcpPort=1239 -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \ -> ./qemu-serial) # \ -#-gdb tcp::$tcpPort -S \ -#& riscv64-unknown-elf-gdb -quiet -x debug.gdb -ex "debug $tcpPort \"$imageDir/vmlinux\"" +> ./qemu-serial \ +-gdb tcp::$tcpPort -S) \ +& riscv64-unknown-elf-gdb -quiet \ +-ex "set pagination off" \ +-ex "set logging overwrite on" \ +-ex "set logging redirect on" \ +-ex "set confirm off" \ +-ex "target extended-remote :$tcpPort" \ +-ex "maintenance packet Qqemu.PhyMemMode:1" \ +-ex "file $imageDir/vmlinux" From 097301635a15f4a93fe29830dbe9fca7235600f1 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 7 Mar 2022 17:59:49 -0800 Subject: [PATCH 137/199] change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state --- .../createGenCheckpointScript.py | 63 -------------- linux/testvector-generation/genCheckpoint.sh | 55 +++++++++++- linux/testvector-generation/parsePlicState.py | 87 +++++++++++++++++++ linux/testvector-generation/parseState.py | 4 +- linux/testvector-generation/parseUartState.py | 53 +++++++++++ 5 files changed, 193 insertions(+), 69 deletions(-) delete mode 100755 linux/testvector-generation/createGenCheckpointScript.py create mode 100755 linux/testvector-generation/parsePlicState.py create mode 100755 linux/testvector-generation/parseUartState.py diff --git a/linux/testvector-generation/createGenCheckpointScript.py b/linux/testvector-generation/createGenCheckpointScript.py deleted file mode 100755 index 264a2ee6e..000000000 --- a/linux/testvector-generation/createGenCheckpointScript.py +++ /dev/null @@ -1,63 +0,0 @@ -#! /usr/bin/python3 -import sys - -if len(sys.argv) != 8: - sys.exit("""Error createGenCheckpointScript.py expects 7 args: - - - - - - - """) - -tcpPort=sys.argv[1] -vmlinux=sys.argv[2] -instrCount=sys.argv[3] -statePath=sys.argv[4] -ramPath=sys.argv[5] -checkPC=sys.argv[6] -checkPCoccurences=sys.argv[7] - -GDBscript = f""" -# GDB config -set pagination off -set logging overwrite on -set logging redirect on -set confirm off - -# Connect to QEMU session -target extended-remote :{tcpPort} - -# QEMU Config -maintenance packet Qqemu.PhyMemMode:1 - -# Symbol file -file {vmlinux} - -# Step over reset vector into actual code -stepi 100 -# Proceed to checkpoint -print "GDB proceeding to checkpoint at {instrCount} instrs, pc {checkPC}\\n" -b *0x{checkPC} -ignore 1 {checkPCoccurences} -c -print "Reached checkpoint at {instrCount} instrs\\n" - -# Log all registers to a file -printf "GDB storing state to {statePath}\\n" -set logging file {statePath} -set logging on -info all-registers -set logging off - -# Log main memory to a file -print "GDB storing RAM to {ramPath}\\n" -dump binary memory {ramPath} 0x80000000 0xffffffff - -kill -q -""" -GDBscriptFile = open("genCheckpoint.gdb",'w') -GDBscriptFile.write(GDBscript) -GDBscriptFile.close() diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 792925b7e..1ca309be7 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -19,8 +19,11 @@ fi checkPtDir="$tvDir/checkpoint$instrs" outTraceFile="$checkPtDir/all.txt" -interruptsFile="$checkPtDir/interrupts.txt" rawStateFile="$checkPtDir/stateGDB.txt" +rawUartStateFile="$checkPtDir/uartStateGDB.txt" +uartStateFile="$checkPtDir/checkpoint-UART" +rawPlicStateFile="$checkPtDir/plicStateGDB.txt" +plicStateFile="$checkPtDir/checkpoint-PLIC" rawRamFile="$checkPtDir/ramGDB.bin" ramFile="$checkPtDir/ram.bin" @@ -55,7 +58,48 @@ then echo "It occurs ${occurences} times before the ${instrs}th instr." # Create GDB script because GDB is terrible at handling arguments / variables - ./createGenCheckpointScript.py $tcpPort $imageDir/vmlinux $instrs $rawStateFile $rawRamFile $pc $occurences + cat > genCheckpoint.gdb <<- end_of_script + set pagination off + set logging overwrite on + set logging redirect on + set confirm off + target extended-remote :$tcpPort + maintenance packet Qqemu.PhyMemMode:1 + file $imageDir/vmlinux + # Step over reset vector into actual code + stepi 100 + shell echo \"GDB proceeding to checkpoint at $instrs instrs, pc $pc\" + b *0x$pc + ignore 1 $occurences + c + shell echo \"Reached checkpoint at $instrs instrs\" + shell echo \"GDB storing CPU state to $rawStateFile\" + set logging file $rawStateFile + set logging on + info all-registers + set logging off + shell echo \"GDB storing UART state to $rawUartStateFile\" + set logging file $rawUartStateFile + set logging on + x/8xb 0x10000000 + set logging off + shell echo \"GDB storing PLIC state to $rawPlicStateFile\" + shell echo \"Note: this dumping assumes a maximum of 63 PLIC sources\" + set logging file $rawPlicStateFile + set logging on + # Priority Levels for sources 1 thru 63 + x/63xw 0x0C000004 + # Interrupt Enables + x/2xw 0x0C020000 + # Global Priority Threshold + x/1xw 0x0C200000 + set logging off + shell echo \"GDB storing RAM to $rawRamFile\" + dump binary memory $rawRamFile 0x80000000 0xffffffff + kill + q +end_of_script + # GDB+QEMU echo "Starting QEMU in replay mode with attached GDB script at $(date +%H:%M:%S)" (qemu-system-riscv64 \ @@ -64,12 +108,15 @@ then -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ -gdb tcp::$tcpPort -S \ - 2>&1 1>./qemu-serial | ./parseQEMUtoGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $outTraceFile) \ - & riscv64-unknown-elf-gdb --quiet -ex "source genCheckpoint.gdb" + 1>./qemu-serial) \ + & riscv64-unknown-elf-gdb --quiet -x genCheckpoint.gdb + echo "Completed GDB script at $(date +%H:%M:%S)" # Post-Process GDB outputs ./parseState.py "$checkPtDir" + ./parseUartState.py "$rawUartStateFile" "$uartStateFile" + ./parsePlicState.py "$rawPlicStateFile" "$plicStateFile" echo "Changing Endianness at $(date +%H:%M:%S)" make fixBinMem ./fixBinMem "$rawRamFile" "$ramFile" diff --git a/linux/testvector-generation/parsePlicState.py b/linux/testvector-generation/parsePlicState.py new file mode 100755 index 000000000..8655409d1 --- /dev/null +++ b/linux/testvector-generation/parsePlicState.py @@ -0,0 +1,87 @@ +#! /usr/bin/python3 +import sys, os + +################ +# Helper Funcs # +################ + +def tokenize(string): + tokens = [] + token = '' + whitespace = 0 + prevWhitespace = 0 + for char in string: + prevWhitespace = whitespace + whitespace = char in ' \t\n' + if (whitespace): + if ((not prevWhitespace) and (token != '')): + tokens.append(token) + token = '' + else: + token = token + char + return tokens + +############# +# Main Code # +############# +print("Begin parsing PLIC state.") + +# Parse Args +if len(sys.argv) != 3: + sys.exit('Error parsePlicState.py expects 2 args: ') +rawPlicStateFile=sys.argv[1] +outPlicStateFile=sys.argv[2] +if not os.path.exists(rawPlicStateFile): + sys.exit('Error input file '+rawPlicStateFile+'not found') + +# Main Loop +with open(rawPlicStateFile, 'r') as rawPlicStateFile: + plicIntPriorityArray=[] + # 0x0C000004 thru 0x0C000010 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000014 thru 0x0C000020 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000024 thru 0x0C000030 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000034 thru 0x0C000040 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000044 thru 0x0C000050 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000054 thru 0x0C000060 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000064 thru 0x0C000070 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000074 thru 0x0C000080 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000084 thru 0x0C000090 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C000094 thru 0x0C0000a0 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C0000a4 thru 0x0C0000b0 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C0000b4 thru 0x0C0000c0 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C0000c4 thru 0x0C0000d0 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C0000d4 thru 0x0C0000e0 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C0000e4 thru 0x0C0000f0 + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C0000f4 thru 0x0C0000fc + plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + + # 0x0C020000 thru 0x0C020004 + plicIntEnable = tokenize(rawPlicStateFile.readline())[1:] + + # 0x0C200000 + plicIntPriorityThreshold = tokenize(rawPlicStateFile.readline())[1:] + +with open(outPlicStateFile, 'w') as outPlicStateFile: + for word in plicIntPriorityArray: + outPlicStateFile.write(word[2:]+'\n') + for word in plicIntEnable: + outPlicStateFile.write(word[2:]+'\n') + for word in plicIntPriorityThreshold: + outPlicStateFile.write(word[2:]+'\n') + +print("Finished parsing PLIC state!") diff --git a/linux/testvector-generation/parseState.py b/linux/testvector-generation/parseState.py index 5275597c4..abc36fb2f 100755 --- a/linux/testvector-generation/parseState.py +++ b/linux/testvector-generation/parseState.py @@ -24,7 +24,7 @@ def tokenize(string): ############# # Main Code # ############# -print("Begin parsing state.") +print("Begin parsing CPU state.") # Parse Args if len(sys.argv) != 2: @@ -96,4 +96,4 @@ with open(stateGDBpath, 'r') as stateGDB: outFile.write(hex(byte)[2:]+'\n') outFile.close() -print("Finished parsing state!") +print("Finished parsing CPU state!") diff --git a/linux/testvector-generation/parseUartState.py b/linux/testvector-generation/parseUartState.py new file mode 100755 index 000000000..0b7d1cf7f --- /dev/null +++ b/linux/testvector-generation/parseUartState.py @@ -0,0 +1,53 @@ +#! /usr/bin/python3 +import sys, os + +################ +# Helper Funcs # +################ + +def tokenize(string): + tokens = [] + token = '' + whitespace = 0 + prevWhitespace = 0 + for char in string: + prevWhitespace = whitespace + whitespace = char in ' \t\n' + if (whitespace): + if ((not prevWhitespace) and (token != '')): + tokens.append(token) + token = '' + else: + token = token + char + return tokens + +############# +# Main Code # +############# +print("Begin parsing UART state.") + +# Parse Args +if len(sys.argv) != 3: + sys.exit('Error parseUartState.py expects 2 args: ') +rawUartStateFile=sys.argv[1] +outUartStateFile=sys.argv[2] +if not os.path.exists(rawUartStateFile): + sys.exit('Error input file '+rawUartStateFile+'not found') + +# Main Loop +with open(rawUartStateFile, 'r') as rawUartStateFile: + with open(outUartStateFile, 'w') as outUartStateFile: + uartBytes = tokenize(rawUartStateFile.readline())[1:] + # Stores + # 0: RBR / Divisor Latch Low + # 1: IER / Divisor Latch High + # 2: IIR + # 3: LCR + # 4: MCR + # 5: LSR + # 6: MSR + # 7: SCR + for uartByte in uartBytes: + outUartStateFile.write(uartByte[2:]+'\n') + +print("Finished parsing UART state!") From 92e1583db51be37d4cfe3c2360cf81efb5085bdf Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 7 Mar 2022 20:04:08 -0800 Subject: [PATCH 138/199] change testbench-linux.sv to use new shared location of disassembly files --- pipelined/testbench/testbench-linux.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 0c58f7b72..d9ab6ecde 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -314,8 +314,8 @@ module testbench; $sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT); $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - ProgramAddrMapFile = {linuxImageDir,"vmlinux.objdump.addr"}; - ProgramLabelMapFile = {linuxImageDir,"vmlinux.objdump.lab"}; + ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"}; + ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"}; // initialize bootrom memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); readResult = $fread(dut.uncore.bootrom.bootrom.RAM,memFile); From bfaf49647387dea783e8215cf04cd3267647e6b5 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 7 Mar 2022 22:12:08 -0800 Subject: [PATCH 139/199] change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers --- linux/testvector-generation/genCheckpoint.sh | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 1ca309be7..8f4d0a111 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -79,9 +79,21 @@ then info all-registers set logging off shell echo \"GDB storing UART state to $rawUartStateFile\" + # Save value of LCR + set \$LCR=*0x10000003 & 0xff set logging file $rawUartStateFile set logging on - x/8xb 0x10000000 + # Change LCR to set DLAB=0 to be able to read RBR and IER + set {char}0x10000003 &= ~0x80 + x/1xb 0x10000000 + x/1xb 0x10000001 + x/1xb 0x10000002 + # But log original value of LCR + printf "0x10000003:\t0x%02x\n", \$LCR + x/1xb 0x10000004 + x/1xb 0x10000005 + x/1xb 0x10000006 + x/1xb 0x10000007 set logging off shell echo \"GDB storing PLIC state to $rawPlicStateFile\" shell echo \"Note: this dumping assumes a maximum of 63 PLIC sources\" @@ -115,8 +127,8 @@ end_of_script # Post-Process GDB outputs ./parseState.py "$checkPtDir" - ./parseUartState.py "$rawUartStateFile" "$uartStateFile" - ./parsePlicState.py "$rawPlicStateFile" "$plicStateFile" + ./parseUartState.py "$checkPtDir" + ./parsePlicState.py "$checkPtDir" echo "Changing Endianness at $(date +%H:%M:%S)" make fixBinMem ./fixBinMem "$rawRamFile" "$ramFile" From 742e8d98cd995bd7d4ff4bf96274439053818555 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 7 Mar 2022 23:48:47 -0800 Subject: [PATCH 140/199] fix up PLIC and UART checkpointing --- linux/testvector-generation/parsePlicState.py | 26 ++++++++++----- linux/testvector-generation/parseUartState.py | 33 +++++++++---------- pipelined/testbench/testbench-linux.sv | 26 +++++++++++++++ 3 files changed, 58 insertions(+), 27 deletions(-) diff --git a/linux/testvector-generation/parsePlicState.py b/linux/testvector-generation/parsePlicState.py index 8655409d1..a3c3787c8 100755 --- a/linux/testvector-generation/parsePlicState.py +++ b/linux/testvector-generation/parsePlicState.py @@ -21,20 +21,26 @@ def tokenize(string): token = token + char return tokens +def stripZeroes(num): + num = num.strip('0') + if num=='': + return '0' + else: + return num + ############# # Main Code # ############# print("Begin parsing PLIC state.") # Parse Args -if len(sys.argv) != 3: - sys.exit('Error parsePlicState.py expects 2 args: ') -rawPlicStateFile=sys.argv[1] -outPlicStateFile=sys.argv[2] +if len(sys.argv) != 2: + sys.exit('Error parsePlicState.py expects 1 arg: ') +outDir = sys.argv[1]+'/' +rawPlicStateFile = outDir+'plicStateGDB.txt' if not os.path.exists(rawPlicStateFile): sys.exit('Error input file '+rawPlicStateFile+'not found') -# Main Loop with open(rawPlicStateFile, 'r') as rawPlicStateFile: plicIntPriorityArray=[] # 0x0C000004 thru 0x0C000010 @@ -76,12 +82,14 @@ with open(rawPlicStateFile, 'r') as rawPlicStateFile: # 0x0C200000 plicIntPriorityThreshold = tokenize(rawPlicStateFile.readline())[1:] -with open(outPlicStateFile, 'w') as outPlicStateFile: +with open(outDir+'checkpoint-PLIC_INT_PRIORITY', 'w') as outFile: for word in plicIntPriorityArray: - outPlicStateFile.write(word[2:]+'\n') + outFile.write(stripZeroes(word[2:])+'\n') +with open(outDir+'checkpoint-PLIC_INT_ENABLE', 'w') as outFile: for word in plicIntEnable: - outPlicStateFile.write(word[2:]+'\n') + outFile.write(stripZeroes(word[2:])) +with open(outDir+'checkpoint-PLIC_THRESHOLD', 'w') as outFile: for word in plicIntPriorityThreshold: - outPlicStateFile.write(word[2:]+'\n') + outFile.write(stripZeroes(word[2:])+'\n') print("Finished parsing PLIC state!") diff --git a/linux/testvector-generation/parseUartState.py b/linux/testvector-generation/parseUartState.py index 0b7d1cf7f..611937054 100755 --- a/linux/testvector-generation/parseUartState.py +++ b/linux/testvector-generation/parseUartState.py @@ -27,27 +27,24 @@ def tokenize(string): print("Begin parsing UART state.") # Parse Args -if len(sys.argv) != 3: - sys.exit('Error parseUartState.py expects 2 args: ') -rawUartStateFile=sys.argv[1] -outUartStateFile=sys.argv[2] +if len(sys.argv) != 2: + sys.exit('Error parseUartState.py expects 1 arg: ') +outDir = sys.argv[1]+'/' +rawUartStateFile = outDir+'uartStateGDB.txt' if not os.path.exists(rawUartStateFile): sys.exit('Error input file '+rawUartStateFile+'not found') -# Main Loop with open(rawUartStateFile, 'r') as rawUartStateFile: - with open(outUartStateFile, 'w') as outUartStateFile: - uartBytes = tokenize(rawUartStateFile.readline())[1:] - # Stores - # 0: RBR / Divisor Latch Low - # 1: IER / Divisor Latch High - # 2: IIR - # 3: LCR - # 4: MCR - # 5: LSR - # 6: MSR - # 7: SCR - for uartByte in uartBytes: - outUartStateFile.write(uartByte[2:]+'\n') + uartBytes = [] + for i in range(0,8): + uartBytes += tokenize(rawUartStateFile.readline())[1:] +with open(outDir+'checkpoint-UART_IER', 'w') as outFile: + outFile.write(uartBytes[1][2:]) +with open(outDir+'checkpoint-UART_LCR', 'w') as outFile: + outFile.write(uartBytes[3][2:]) +with open(outDir+'checkpoint-UART_MCR', 'w') as outFile: + outFile.write(uartBytes[4][2:]) +with open(outDir+'checkpoint-UART_SCR', 'w') as outFile: + outFile.write(uartBytes[7][2:]) print("Finished parsing UART state!") diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index d9ab6ecde..8723d6b9c 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -214,6 +214,15 @@ module testbench; `define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE `define PRIV dut.core.priv.priv.privmodereg.q `define INSTRET dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2] + `define UART dut.uncore.uart.uart.u + `define UART_IER `UART.IER + `define UART_LCR `UART.LCR + `define UART_MCR `UART.MCR + `define UART_SCR `UART.SCR + `define PLIC dut.uncore.plic.plic + `define PLIC_INT_PRIORITY `PLIC.intPriority + `define PLIC_INT_ENABLE `PLIC.intEn + `define PLIC_THRESHOLD `PLIC.intThreshold // Common Macros `define checkCSR(CSR) \ begin \ @@ -301,6 +310,23 @@ module testbench; `INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(PRIV, [1:0]); `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0); + // Many UART registers are difficult to initialize because under the hood + // they are not simple registers. Instead some are generated by interesting + // combinational blocks such that they depend upon a variety of different + // underlying flops. See for example how RBR might be the actual RXBR + // register, but it could also just as well be 0 or the tail of the fifo + // array. + //`INIT_CHECKPOINT_VAL(UART_RBR, [7:0]); + `INIT_CHECKPOINT_VAL(UART_IER, [7:0]); + //`INIT_CHECKPOINT_VAL(UART_IIR, [7:0]); + `INIT_CHECKPOINT_VAL(UART_LCR, [7:0]); + `INIT_CHECKPOINT_VAL(UART_MCR, [4:0]); + //`INIT_CHECKPOINT_VAL(UART_LSR, [7:0]); + //`INIT_CHECKPOINT_VAL(UART_MSR, [7:0]); + `INIT_CHECKPOINT_VAL(UART_SCR, [7:0]); + `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); + `INIT_CHECKPOINT_VAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1]); + `INIT_CHECKPOINT_VAL(PLIC_THRESHOLD, [2:0]); integer memFile; integer readResult; From 099fc34c106577d5ead9c7bfdef287ba0aa2baab Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 8 Mar 2022 09:52:17 -0800 Subject: [PATCH 141/199] change genTrace to dump UART output to file so we can see how far parsing got --- linux/testvector-generation/genTrace.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh index 91485e383..5c79ee3d0 100755 --- a/linux/testvector-generation/genTrace.sh +++ b/linux/testvector-generation/genTrace.sh @@ -38,7 +38,7 @@ then -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \ -d nochain,cpu,in_asm,int \ - 2>&1 >/dev/null | ./parseQEMUtoGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) + 2>&1 >./qemu-serial | ./parseQEMUtoGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) echo "genTrace.sh completed!" echo "You may want to restrict write access to $tvDir now and give cad ownership of it." From 7b96b3f73c0830db1301487d5afb6e1a882fc6e8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Mar 2022 16:34:02 -0600 Subject: [PATCH 142/199] Moved cacheable signal into cache. --- pipelined/src/cache/cache.sv | 6 +++++- pipelined/src/cache/cachefsm.sv | 18 +++++++++--------- pipelined/src/ifu/ifu.sv | 7 ++----- pipelined/src/lsu/lsu.sv | 7 ++----- 4 files changed, 18 insertions(+), 20 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index c9da5078f..0b6184f23 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -51,6 +51,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // lsu control input logic IgnoreRequestTLB, input logic IgnoreRequestTrapM, + input logic Cacheable, // Bus fsm interface output logic CacheFetchLine, output logic CacheWriteLine, @@ -99,6 +100,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic ResetOrFlushAdr, ResetOrFlushWay; logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; + logic [1:0] CacheRW, CacheAtomic; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -174,8 +176,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// + assign CacheRW = Cacheable ? RW : 2'b00; + assign CacheAtomic = Cacheable ? Atomic : 2'b00; cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, - .RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, + .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index df05e6cbc..b98ecf7dd 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -34,8 +34,8 @@ module cachefsm (input logic clk, input logic reset, // inputs from IEU - input logic [1:0] RW, - input logic [1:0] Atomic, + input logic [1:0] CacheRW, + input logic [1:0] CacheAtomic, input logic FlushCache, // hazard inputs input logic CPUBusy, @@ -109,10 +109,10 @@ module cachefsm // using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB. assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. - assign AMO = Atomic[1] & (&RW); + assign AMO = CacheAtomic[1] & (&CacheRW); assign DoAMO = AMO & ~IgnoreRequest; - assign DoRead = RW[1] & ~IgnoreRequest; - assign DoWrite = RW[0] & ~IgnoreRequest; + assign DoRead = CacheRW[1] & ~IgnoreRequest; + assign DoWrite = CacheRW[0] & ~IgnoreRequest; assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit; assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit; @@ -145,7 +145,7 @@ module cachefsm STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_MISS_WRITE_CACHE_LINE; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; - STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; + STATE_MISS_READ_WORD: if(CacheRW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; else NextState = STATE_MISS_READ_WORD_DELAY; STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; @@ -213,14 +213,14 @@ module cachefsm // handle cpu stall. assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY; assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) | - (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | RW[1]) & CPUBusy) | + (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | CacheRW[1]) & CPUBusy) | (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. // use the raw requests as we don't want IgnoreRequestTrapM in the critical path - (CurrState == STATE_READY & ((AMO | RW[0]) & CacheHit)) | // changes if store delay hazard removed - (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | + (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed + (CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_DONE) | diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 62518b263..a14537dfd 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -210,9 +210,6 @@ module ifu ( if(CACHE_ENABLED) begin : icache - logic [1:0] IFURWF; - assign IFURWF = CacheableF ? 2'b10 : 2'b00; - cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0)) @@ -221,10 +218,10 @@ module ifu ( .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(), .ReadDataLine(ReadDataLine), - .save, .restore, + .save, .restore, .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .FinalWriteData('0), - .RW(IFURWF), + .RW(2'b10), .Atomic('0), .FlushCache('0), .NextAdr(PCNextFSpill[11:0]), .PAdr(PCPF), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 5af0f1b23..0dde84461 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -230,14 +230,11 @@ module lsu ( if(CACHE_ENABLED) begin : dcache - logic [1:0] RW, Atomic; - assign RW = CacheableM ? LSURWM : 2'b00; // AND gate // *** move and gates into cache - assign Atomic = CacheableM ? LSUAtomicM : 2'b00; // AND gate cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .save, .restore, .RW, .Atomic, + .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .FinalWriteData(FinalWriteDataM), + .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM), From d78ba777a4c40a48ab7d1975fb2ec3ac18dcecf9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Mar 2022 16:38:48 -0600 Subject: [PATCH 143/199] Added parameter to spillsupport. --- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/ifu/spillsupport.sv | 41 ++++++++++++++++--------------- 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index a14537dfd..35dfa4135 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -124,7 +124,7 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport - spillsupport spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF, + spillsupport #(CACHE_ENABLED) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF, .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index db9ed8e28..56bd3a78c 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -32,30 +32,30 @@ `include "wally-config.vh" -module spillsupport ( - input logic clk, - input logic reset, - input logic StallF, - input logic [`XLEN-1:0] PCF, - input logic [`XLEN-3:0] PCPlusUpperF, - input logic [`XLEN-1:0] PCNextF, - input logic [31:0] InstrRawF, - input logic IFUCacheBusStallF, - input logic ITLBMissF, - input logic InstrDAPageFaultF, - output logic [`XLEN-1:0] PCNextFSpill, - output logic [`XLEN-1:0] PCFSpill, - output logic SelNextSpillF, - output logic [31:0] PostSpillInstrRawF, - output logic CompressedF); +module spillsupport #(parameter CACHE_ENABLED) + (input logic clk, + input logic reset, + input logic StallF, + input logic [`XLEN-1:0] PCF, + input logic [`XLEN-3:0] PCPlusUpperF, + input logic [`XLEN-1:0] PCNextF, + input logic [31:0] InstrRawF, + input logic IFUCacheBusStallF, + input logic ITLBMissF, + input logic InstrDAPageFaultF, + output logic [`XLEN-1:0] PCNextFSpill, + output logic [`XLEN-1:0] PCFSpill, + output logic SelNextSpillF, + output logic [31:0] PostSpillInstrRawF, + output logic CompressedF); - localparam integer SPILLTHRESHOLD = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/32 : 1; + localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; logic [`XLEN-1:0] PCPlus2F; logic TakeSpillF; logic SpillF; logic SelSpillF, SpillSaveF; - logic [15:0] SpillDataLine0; + logic [15:0] SpillDataLine0, SavedInstr; typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; @@ -86,11 +86,12 @@ module spillsupport ( assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallF); assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF; - + assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16]; + flopenr #(16) SpillInstrReg(.clk(clk), .en(SpillSaveF), .reset(reset), - .d((`IMEM == `MEM_CACHE) ? InstrRawF[15:0] : InstrRawF[31:16]), + .d(SavedInstr), .q(SpillDataLine0)); mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF), From 3ec32d7ce880492af9bf2f114260217552b715a0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Mar 2022 16:58:26 -0600 Subject: [PATCH 144/199] Removed unused signal. --- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/busdp.sv | 1 - pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 35dfa4135..c2df13806 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -201,7 +201,7 @@ module ifu ( .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), .DCacheBusWriteData(ICacheBusWriteData), .LSUPAdrM(PCPF), - .FinalWriteDataM(), .SelUncachedAdr, + .SelUncachedAdr, .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 49907bb5c..90f84cd76 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -56,7 +56,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) // lsu interface input logic [`PA_BITS-1:0] LSUPAdrM, - input logic [`XLEN-1:0] FinalWriteDataM, input logic IgnoreRequest, input logic [1:0] LSURWM, input logic CPUBusy, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 0dde84461..843efdd62 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -216,7 +216,7 @@ module lsu ( .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, - .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .FinalWriteDataM, + .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); From c8f2dce026b5cf160eda33f4aa44e723bfa33d43 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 8 Mar 2022 23:18:18 +0000 Subject: [PATCH 145/199] fma16_testgen.c test cases --- pipelined/src/fma/fma16_testgen.c | 93 ++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 3 deletions(-) diff --git a/pipelined/src/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c index b294552e6..a5f3e083b 100644 --- a/pipelined/src/fma/fma16_testgen.c +++ b/pipelined/src/fma/fma16_testgen.c @@ -11,6 +11,7 @@ typedef union sp { // lists of tests, terminated with 0x8000 uint16_t easyExponents[] = {15, 0x8000}; uint16_t medExponents[] = {1, 14, 15, 16, 20, 30, 0x8000}; +uint16_t allExponents[] = {1, 15, 16, 30, 31, 0x8000}; uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1 uint16_t medFracts[] = {0, 0x200, 0x001, 0x3FF, 0x8000}; uint16_t zeros[] = {0x0000, 0x8000}; @@ -107,8 +108,8 @@ void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, fclose(fptr); } -void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc) { - int i, j, numCases; +void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) { + int i, j, k, numCases; float16_t x, y, z; float16_t cases[100000]; FILE *fptr; @@ -122,7 +123,72 @@ void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc) x.v = cases[i].v; for (j=0; j Date: Tue, 8 Mar 2022 23:29:29 +0000 Subject: [PATCH 146/199] Added more test cases and rounding modes to fma test generator --- pipelined/src/fma/fma16_testgen.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/pipelined/src/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c index a5f3e083b..a9a26d803 100644 --- a/pipelined/src/fma/fma16_testgen.c +++ b/pipelined/src/fma/fma16_testgen.c @@ -38,7 +38,7 @@ float convFloat(float16_t f16) { void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int zeroAllowed, int infAllowed, int nanAllowed) { float16_t result; int op; - char calc[80]; + char calc[80], flags[80]; float32_t x32, y32, z32, r32; float xf, yf, zf, rf; float16_t smallest; @@ -48,8 +48,15 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add if (negp) x.v ^= 0x8000; // flip sign of x to negate p if (negz) z.v ^= 0x8000; // flip sign of z to negate z op = mul<<3 | add<<2 | negp<<1 | negz; + softfloat_exceptionFlags = 0; // clear exceptions result = f16_mulAdd(x, y, z); + sprintf(flags, "NV: %d OF: %d UF: %d NX: %d", + (softfloat_exceptionFlags >> 4) % 2, + (softfloat_exceptionFlags >> 2) % 2, + (softfloat_exceptionFlags >> 1) % 2, + (softfloat_exceptionFlags) % 2); + // convert to floats for printing xf = convFloat(x); yf = convFloat(y); @@ -68,7 +75,7 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: "); if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed) fprintf(fptr, "// Skip inf: "); if (resultmag.v > 0x7C00 && !nanAllowed) fprintf(fptr, "// Skip NaN: "); - fprintf(fptr, "%04x_%04x_%04x_%02x_%04x // %s\n", x.v, y.v, z.v, op, result.v, calc); + fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%02x // %s %s\n", x.v, y.v, z.v, op, result.v, softfloat_exceptionFlags, calc, flags); } void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases, From 75e93baaeed20329e4e56a9cbf25e745ea210ebd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Mar 2022 17:41:02 -0600 Subject: [PATCH 147/199] Marked signals for name changes. --- pipelined/src/lsu/busdp.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 90f84cd76..e80de5bde 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -44,14 +44,14 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic LSUBusRead, output logic [2:0] LSUBusSize, input logic [2:0] LSUFunct3M, - output logic [`PA_BITS-1:0] LSUBusAdr, + output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, // cache interface. input logic [`PA_BITS-1:0] DCacheBusAdr, input logic DCacheFetchLine, input logic DCacheWriteLine, output logic DCacheBusAck, - output logic [LINELEN-1:0] DCacheBusWriteData, + output logic [LINELEN-1:0] DCacheBusWriteData, //*** change name. output logic SelUncachedAdr, // lsu interface From 0310fe858fa91cbc00d761764bfc40dbbe3561cd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Mar 2022 18:05:25 -0600 Subject: [PATCH 148/199] Comments. --- pipelined/src/lsu/lsu.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 843efdd62..ddf0f77dc 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -253,7 +253,10 @@ module lsu ( if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS. Only produces byte write enable logic [`XLEN-1:0] ReadDataWordMaskedM; + // ** there is definitely a sww bug with memory mapped i/o. check wally64priv. assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate + // *** consider moving this AND gate into the sww. + //assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address. subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); From 95bb4cc8a8f5cbcf5045d314c54260eadc74bfbf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Mar 2022 23:38:58 -0600 Subject: [PATCH 149/199] Minor cleanup to interlockfsm. --- pipelined/src/lsu/interlockfsm.sv | 6 ++++-- pipelined/src/lsu/lsuvirtmen.sv | 6 +++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 2475c3c2d..05de62175 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -44,7 +44,7 @@ module interlockfsm( input logic DCacheStallM, output logic InterlockStall, - output logic SelReplayCPURequest, + output logic SelReplayMemE, output logic SelHPTW, output logic IgnoreRequestTLB, output logic IgnoreRequestTrapM); @@ -122,7 +122,9 @@ module interlockfsm( endcase end - assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY); + assign SelReplayMemE = (InterlockCurrState == STATE_T0_REPLAY & DCacheStallM) | + (InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) | + (InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF); assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM)); diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 2be89d27d..83176470e 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -73,7 +73,7 @@ module lsuvirtmem( logic [`PA_BITS-1:0] HPTWAdr; logic [1:0] HPTWRW; logic [2:0] HPTWSize; - logic SelReplayCPURequest; + logic SelReplayMemE; logic [11:0] PreLSUAdrE; logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF; logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM; @@ -85,7 +85,7 @@ module lsuvirtmem( interlockfsm interlockfsm ( .clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF, .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, - .InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); + .InterlockStall, .SelReplayMemE, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); hptw hptw( .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, @@ -104,7 +104,7 @@ module lsuvirtmem( if(`HPTW_WRITES_SUPPORTED) mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM); else assign LSUWriteDataM = WriteDataM; - mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache. + mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayMemE, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache. // always block interrupts when using the hardware page table walker. assign CPUBusy = StallW & ~SelHPTW; From 89e0830883d8c01d925aeab0757b2c380835d97e Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 9 Mar 2022 13:58:17 +0000 Subject: [PATCH 150/199] Updated testbench to read expected flags --- pipelined/src/fma/fma16_testgen.c | 7 +++++-- pipelined/src/fma/testbench.v | 22 ++++++++++++---------- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/pipelined/src/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c index a9a26d803..f63f59106 100644 --- a/pipelined/src/fma/fma16_testgen.c +++ b/pipelined/src/fma/fma16_testgen.c @@ -37,7 +37,7 @@ float convFloat(float16_t f16) { void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int zeroAllowed, int infAllowed, int nanAllowed) { float16_t result; - int op; + int op, flagVals; char calc[80], flags[80]; float32_t x32, y32, z32, r32; float xf, yf, zf, rf; @@ -56,6 +56,9 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add (softfloat_exceptionFlags >> 2) % 2, (softfloat_exceptionFlags >> 1) % 2, (softfloat_exceptionFlags) % 2); + // pack these four flags into one nibble, discarding DZ flag + flagVals = softfloat_exceptionFlags & 0x7 | ((softfloat_exceptionFlags >> 1) & 0x8); + // convert to floats for printing xf = convFloat(x); @@ -75,7 +78,7 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: "); if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed) fprintf(fptr, "// Skip inf: "); if (resultmag.v > 0x7C00 && !nanAllowed) fprintf(fptr, "// Skip NaN: "); - fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%02x // %s %s\n", x.v, y.v, z.v, op, result.v, softfloat_exceptionFlags, calc, flags); + fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%01x // %s %s\n", x.v, y.v, z.v, op, result.v, flagVals, calc, flags); } void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases, diff --git a/pipelined/src/fma/testbench.v b/pipelined/src/fma/testbench.v index 2767c4899..bef7eca41 100644 --- a/pipelined/src/fma/testbench.v +++ b/pipelined/src/fma/testbench.v @@ -1,12 +1,14 @@ /* verilator lint_off STMTDLY */ module testbench_fma16; - logic clk, reset; - logic [15:0] x, y, z, rexpected, result; - logic [7:0] ctrl; - logic mul, add, negp, negz; - logic [1:0] roundmode; - logic [31:0] vectornum, errors; - logic [71:0] testvectors[10000:0]; + reg clk, reset; + reg [15:0] x, y, z, rexpected; + wire [15:0] result; + reg [7:0] ctrl; + reg [3:0] flagsexpected; + reg mul, add, negp, negz; + reg [1:0] roundmode; + reg [31:0] vectornum, errors; + reg [75:0] testvectors[10000:0]; // instantiate device under test fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result); @@ -20,7 +22,7 @@ module testbench_fma16; // at start of test, load vectors and pulse reset initial begin - $readmemh("work/fmul_2.tv", testvectors); + $readmemh("work/fmul_0.tv", testvectors); vectornum = 0; errors = 0; reset = 1; #22; reset = 0; end @@ -28,14 +30,14 @@ module testbench_fma16; // apply test vectors on rising edge of clk always @(posedge clk) begin - #1; {x, y, z, ctrl, rexpected} = testvectors[vectornum]; + #1; {x, y, z, ctrl, rexpected, flagsexpected} = testvectors[vectornum]; {roundmode, mul, add, negp, negz} = ctrl[5:0]; end // check results on falling edge of clk always @(negedge clk) if (~reset) begin // skip during reset - if (result !== rexpected) begin // check result + if (result !== rexpected) begin // check result // *** should also add tests on flags eventually $display("Error: inputs %h * %h + %h", x, y, z); $display(" result = %h (%h expected)", result, rexpected); errors = errors + 1; From 27f09ffb3371710cffd7b13ee2e006407faceaf4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 9 Mar 2022 17:49:28 +0000 Subject: [PATCH 151/199] Refactored SRAM bit write enable --- pipelined/src/fma/fma16_testgen.c | 47 ++++++++++++++++--------------- pipelined/src/ifu/SRAM2P1R1W.sv | 9 ++++-- 2 files changed, 31 insertions(+), 25 deletions(-) diff --git a/pipelined/src/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c index f63f59106..c114eaf99 100644 --- a/pipelined/src/fma/fma16_testgen.c +++ b/pipelined/src/fma/fma16_testgen.c @@ -35,7 +35,7 @@ float convFloat(float16_t f16) { return res; } -void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int zeroAllowed, int infAllowed, int nanAllowed) { +void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) { float16_t result; int op, flagVals; char calc[80], flags[80]; @@ -47,7 +47,8 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add if (!add) z.v = 0x0000; // force z to 0 to avoid add if (negp) x.v ^= 0x8000; // flip sign of x to negate p if (negz) z.v ^= 0x8000; // flip sign of z to negate z - op = mul<<3 | add<<2 | negp<<1 | negz; + op = roundingMode << 4 | mul<<3 | add<<2 | negp<<1 | negz; +// printf("op = %02x rm %d mul %d add %d negp %d negz %d\n", op, roundingMode, mul, add, negp, negz); softfloat_exceptionFlags = 0; // clear exceptions result = f16_mulAdd(x, y, z); @@ -94,7 +95,7 @@ void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t * } } -void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) { +void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) { int i, j, k, numCases; float16_t x, y, z; float16_t cases[100000]; @@ -111,14 +112,14 @@ void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, y.v = cases[j].v; for (k=0; k<=sgn; k++) { y.v ^= (k<<15); - genCase(fptr, x, y, z, 1, 0, 0, 0, zeroAllowed, infAllowed, nanAllowed); + genCase(fptr, x, y, z, 1, 0, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed); } } } fclose(fptr); } -void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) { +void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) { int i, j, k, numCases; float16_t x, y, z; float16_t cases[100000]; @@ -135,7 +136,7 @@ void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, z.v = cases[j].v; for (k=0; k<=sgn; k++) { z.v ^= (k<<15); - genCase(fptr, x, y, z, 0, 1, 0, 0, zeroAllowed, infAllowed, nanAllowed); + genCase(fptr, x, y, z, 0, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed); } } } @@ -143,7 +144,7 @@ void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, } -void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) { +void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) { int i, j, k, l, numCases; float16_t x, y, z; float16_t cases[100000]; @@ -161,7 +162,7 @@ void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, z.v = cases[k].v; for (l=0; l<=sgn; l++) { z.v ^= (l<<15); - genCase(fptr, x, y, z, 1, 1, 0, 0, zeroAllowed, infAllowed, nanAllowed); + genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed); } } } @@ -169,7 +170,7 @@ void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, fclose(fptr); } -void genSpecialTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) { +void genSpecialTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) { int i, j, k, sx, sy, sz, numCases; float16_t x, y, z; float16_t cases[100000]; @@ -194,7 +195,7 @@ void genSpecialTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *de y.v ^= (sy<<15); for (sz=0; sz<=sgn; sz++) { z.v ^= (sz<<15); - genCase(fptr, x, y, z, 1, 1, 0, 0, zeroAllowed, infAllowed, nanAllowed); + genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed); } } } @@ -210,30 +211,30 @@ int main() softfloatInit(); // configure softfloat modes // Test cases: multiplication - genMulTests(easyExponents, easyFracts, 0, "fmul_0", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0); - genMulTests(medExponents, medFracts, 0, "fmul_1", "// Multiply with various exponents and unsigned fractions, RZ", 0, 0, 0); - genMulTests(medExponents, medFracts, 1, "fmul_2", "// Multiply with various exponents and signed fractions, RZ", 0, 0, 0); + genMulTests(easyExponents, easyFracts, 0, "fmul_0", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0); + genMulTests(medExponents, medFracts, 0, "fmul_1", "// Multiply with various exponents and unsigned fractions, RZ", 0, 0, 0, 0); + genMulTests(medExponents, medFracts, 1, "fmul_2", "// Multiply with various exponents and signed fractions, RZ", 0, 0, 0, 0); // Test cases: addition - genAddTests(easyExponents, easyFracts, 0, "fadd_0", "// Add with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0); - genAddTests(medExponents, medFracts, 0, "fadd_1", "// Add with various exponents and unsigned fractions, RZ", 0, 0, 0); - genAddTests(medExponents, medFracts, 1, "fadd_2", "// Add with various exponents and signed fractions, RZ", 0, 0, 0); + genAddTests(easyExponents, easyFracts, 0, "fadd_0", "// Add with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0); + genAddTests(medExponents, medFracts, 0, "fadd_1", "// Add with various exponents and unsigned fractions, RZ", 0, 0, 0, 0); + genAddTests(medExponents, medFracts, 1, "fadd_2", "// Add with various exponents and signed fractions, RZ", 0, 0, 0, 0); // Test cases: FMA - genFMATests(easyExponents, easyFracts, 0, "fma_0", "// FMA with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0); - genFMATests(medExponents, medFracts, 0, "fma_1", "// FMA with various exponents and unsigned fractions, RZ", 0, 0, 0); - genFMATests(medExponents, medFracts, 1, "fma_2", "// FMA with various exponents and signed fractions, RZ", 0, 0, 0); + genFMATests(easyExponents, easyFracts, 0, "fma_0", "// FMA with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0); + genFMATests(medExponents, medFracts, 0, "fma_1", "// FMA with various exponents and unsigned fractions, RZ", 0, 0, 0, 0); + genFMATests(medExponents, medFracts, 1, "fma_2", "// FMA with various exponents and signed fractions, RZ", 0, 0, 0, 0); // Test cases: Zero, Infinity, NaN - genSpecialTests(allExponents, medFracts, 1, "fma_special_rz", "// FMA with special cases, RZ", 1, 1, 1); + genSpecialTests(allExponents, medFracts, 1, "fma_special_rz", "// FMA with special cases, RZ", 0, 1, 1, 1); // Full test cases with other rounding modes softfloat_roundingMode = softfloat_round_near_even; - genSpecialTests(allExponents, medFracts, 1, "fma_special_rne", "// FMA with special cases, RNE", 1, 1, 1); + genSpecialTests(allExponents, medFracts, 1, "fma_special_rne", "// FMA with special cases, RNE", 1, 1, 1, 1); softfloat_roundingMode = softfloat_round_min; - genSpecialTests(allExponents, medFracts, 1, "fma_special_rm", "// FMA with special cases, RM", 1, 1, 1); + genSpecialTests(allExponents, medFracts, 1, "fma_special_rm", "// FMA with special cases, RM", 2, 1, 1, 1); softfloat_roundingMode = softfloat_round_max; - genSpecialTests(allExponents, medFracts, 1, "fma_special_rp", "// FMA with special cases, RP", 1, 1, 1); + genSpecialTests(allExponents, medFracts, 1, "fma_special_rp", "// FMA with special cases, RP", 3, 1, 1, 1); return 0; } diff --git a/pipelined/src/ifu/SRAM2P1R1W.sv b/pipelined/src/ifu/SRAM2P1R1W.sv index 19d95ee58..93c26981c 100644 --- a/pipelined/src/ifu/SRAM2P1R1W.sv +++ b/pipelined/src/ifu/SRAM2P1R1W.sv @@ -67,6 +67,7 @@ module SRAM2P1R1W logic [WIDTH-1:0] WD1Q; logic [WIDTH-1:0] mem[2**DEPTH-1:0]; + logic [WIDTH-1:0] bwe; // SRAMs address busses are always registered first. @@ -99,13 +100,17 @@ module SRAM2P1R1W assign RD1 = mem[RA1Q]; // write port + assign bwe = {WIDTH{WEN1Q}} & BitWEN1; + always_ff @(posedge clk) begin + mem[WA1Q] <= WD1Q & bwe | mem[WA1Q] & ~bwe; +/* genvar index; - for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite + for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite always_ff @(posedge clk) begin if (WEN1Q & BitWEN1[index]) begin mem[WA1Q][index] <= WD1Q[index]; end - end + end*/ end endmodule From bc2b757952706098ec56e1b6c83c4a01c5bf8d92 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 9 Mar 2022 19:09:20 +0000 Subject: [PATCH 152/199] bit write update --- pipelined/src/ifu/SRAM2P1R1W.sv | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/pipelined/src/ifu/SRAM2P1R1W.sv b/pipelined/src/ifu/SRAM2P1R1W.sv index 93c26981c..513b7a364 100644 --- a/pipelined/src/ifu/SRAM2P1R1W.sv +++ b/pipelined/src/ifu/SRAM2P1R1W.sv @@ -101,17 +101,8 @@ module SRAM2P1R1W // write port assign bwe = {WIDTH{WEN1Q}} & BitWEN1; - always_ff @(posedge clk) begin + always_ff @(posedge clk) mem[WA1Q] <= WD1Q & bwe | mem[WA1Q] & ~bwe; -/* - genvar index; - for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite - always_ff @(posedge clk) begin - if (WEN1Q & BitWEN1[index]) begin - mem[WA1Q][index] <= WD1Q[index]; - end - end*/ - end endmodule From 7a129c75cd1a85c2c00290f74aeb7eaf0f947063 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 15:48:31 -0600 Subject: [PATCH 153/199] Added byte write enables to cache SRAMs. --- pipelined/src/cache/cache.sv | 5 +++-- pipelined/src/cache/cacheway.sv | 9 ++++++--- pipelined/src/cache/sram1p1rw.sv | 19 ++++++++++++++++--- pipelined/src/ifu/ifu.sv | 1 + pipelined/src/lsu/lsu.sv | 6 ++++-- pipelined/src/uncore/subwordwrite.sv | 6 +++++- pipelined/src/uncore/uncore.sv | 2 +- 7 files changed, 36 insertions(+), 12 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 0b6184f23..a4b64fed6 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -41,6 +41,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( input logic InvalidateCacheM, input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] PAdr, // physical address + input logic [(`XLEN-1)/8:0] ByteWEN, input logic [`XLEN-1:0] FinalWriteData, output logic CacheCommitted, output logic CacheStall, @@ -50,7 +51,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( output logic save, restore, // lsu control input logic IgnoreRequestTLB, - input logic IgnoreRequestTrapM, + input logic IgnoreRequestTrapM, input logic Cacheable, // Bus fsm interface output logic CacheFetchLine, @@ -114,7 +115,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .RAdr, .PAdr, .CacheWriteData, + .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteWEN, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Invalidate(InvalidateCacheM)); diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index d9dfdfff4..4a0694e7d 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic VictimWay, input logic FlushWay, input logic Invalidate, - + input logic [(`XLEN-1)/8:0] ByteWEN, output logic [LINELEN-1:0] ReadDataLineWay, output logic HitWay, @@ -69,6 +69,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, logic [$clog2(NUMLINES)-1:0] RAdrD; logic [2**LOGWPL-1:0] MemPAdrDecoded; logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; + logic [(`XLEN-1)/8:0] FinalByteWEN; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux @@ -77,13 +78,15 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND + //assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR + assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, - .Adr(RAdr), .ReadData(ReadTag), + .Adr(RAdr), .ReadData(ReadTag), .ByteWEN('1), .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay)); // AND portion of distributed tag multiplexer @@ -102,7 +105,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr), .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]), - .WriteEnable(SelectedWriteWordEn[words])); + .WriteEnable(SelectedWriteWordEn[words]), .ByteWEN(FinalByteWEN)); end // AND portion of distributed read multiplexers diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 33f022a86..06581d0c3 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -38,18 +38,31 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( input logic [$clog2(DEPTH)-1:0] Adr, input logic [WIDTH-1:0] CacheWriteData, input logic WriteEnable, + input logic [(WIDTH-1)/8:0] ByteWEN, output logic [WIDTH-1:0] ReadData); logic [WIDTH-1:0] StoredData[DEPTH-1:0]; logic [$clog2(DEPTH)-1:0] AdrD; logic WriteEnableD; + always_ff @(posedge clk) AdrD <= Adr; + + genvar index; + for(index = 0; index < WIDTH/8; index++) begin always_ff @(posedge clk) begin - AdrD <= Adr; - if (WriteEnable) begin - StoredData[Adr] <= #1 CacheWriteData; + if (WriteEnable & ByteWEN[index]) begin + StoredData[Adr][8*(index+1)-1:8*index] <= #1 CacheWriteData[8*(index+1)-1:8*index]; end end + end + // if not a multiple of 8, MSByte is not 8 bits long. + if(WIDTH%8 != 0) begin + always_ff @(posedge clk) begin + if (WriteEnable & ByteWEN[WIDTH/8]) begin + StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; + end + end + end assign ReadData = StoredData[AdrD]; endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c2df13806..888115f23 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -220,6 +220,7 @@ module ifu ( .CacheWriteLine(), .ReadDataLine(ReadDataLine), .save, .restore, .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), + .ByteWEN('0), .FinalWriteData('0), .RW(2'b10), .Atomic('0), .FlushCache('0), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index ddf0f77dc..71cea1913 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -105,7 +105,8 @@ module lsu ( logic LSUBusWriteCrit; logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; - + logic [(`XLEN-1)/8:0] FinalByteWENM; + // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); @@ -234,6 +235,7 @@ module lsu ( .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), + .ByteWEN(FinalByteWENM), .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), @@ -259,7 +261,7 @@ module lsu ( //assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address. subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM)); end else assign FinalWriteDataM = FinalAMOWriteDataM; diff --git a/pipelined/src/uncore/subwordwrite.sv b/pipelined/src/uncore/subwordwrite.sv index f984038b1..bfc4684f2 100644 --- a/pipelined/src/uncore/subwordwrite.sv +++ b/pipelined/src/uncore/subwordwrite.sv @@ -35,14 +35,17 @@ module subwordwrite ( input logic [2:0] HADDRD, input logic [3:0] HSIZED, input logic [`XLEN-1:0] HWDATAIN, - output logic [`XLEN-1:0] HWDATA + output logic [`XLEN-1:0] HWDATA, + output logic [`XLEN/8-1:0] ByteWEN ); logic [`XLEN-1:0] WriteDataSubwordDuplicated; + if (`XLEN == 64) begin:sww logic [7:0] ByteMaskM; // Compute write mask + assign ByteWEN = ByteMaskM; always_comb case(HSIZED[1:0]) 2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[HADDRD[2:0]] = 1; end // sb @@ -81,6 +84,7 @@ module subwordwrite ( end else begin:sww // 32-bit logic [3:0] ByteMaskM; // Compute write mask + assign ByteWEN = ByteMaskM; always_comb case(HSIZED[1:0]) 2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[HADDRD[1:0]] = 1; end // sb diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index f2cd40a23..5968898bf 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -95,7 +95,7 @@ module uncore ( subwordwrite sww( .HRDATA, .HADDRD, .HSIZED, - .HWDATAIN, .HWDATA); + .HWDATAIN, .HWDATA, .ByteWEN()); else assign HWDATA = HWDATAIN; From 67ef46ea92571c5427ac73d52c8d808225581602 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 16:11:39 -0600 Subject: [PATCH 154/199] Partially working byte write enables. Works for cache, but not dtim or bus only. --- pipelined/src/cache/cacheway.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 5 +++-- pipelined/src/uncore/uncore.sv | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 4a0694e7d..30f42039d 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -78,8 +78,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND - //assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR - assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR + assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR + //assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 71cea1913..1b44e803c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -253,10 +253,11 @@ module lsu ( end end - if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS. Only produces byte write enable + if(1) begin // *** always, not just with no MEM_BUS. Only produces byte write enable logic [`XLEN-1:0] ReadDataWordMaskedM; // ** there is definitely a sww bug with memory mapped i/o. check wally64priv. - assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate + //assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate + assign ReadDataWordMaskedM = '0; // AND-gate // *** consider moving this AND gate into the sww. //assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address. subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 5968898bf..776850e65 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -91,7 +91,7 @@ module uncore ( assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; // subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache. - if(`DMEM == `MEM_BUS) + if(0) subwordwrite sww( .HRDATA, .HADDRD, .HSIZED, From d8e71e8e35d94885df5027a7471a64d88a024007 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 17:02:52 -0600 Subject: [PATCH 155/199] Progress on the path to getting all configs working with byte write enables. --- pipelined/src/lsu/lsu.sv | 13 +++------ pipelined/src/uncore/ram.sv | 48 +++++++++++++++++++++++++++++----- pipelined/src/uncore/uncore.sv | 11 +++----- 3 files changed, 48 insertions(+), 24 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1b44e803c..85dc1c49c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -253,18 +253,11 @@ module lsu ( end end - if(1) begin // *** always, not just with no MEM_BUS. Only produces byte write enable - logic [`XLEN-1:0] ReadDataWordMaskedM; - // ** there is definitely a sww bug with memory mapped i/o. check wally64priv. - //assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate - assign ReadDataWordMaskedM = '0; // AND-gate - // *** consider moving this AND gate into the sww. - //assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address. - subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), + if(1) begin + subwordwrite subwordwrite(.HRDATA('0), .HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM)); - end else - assign FinalWriteDataM = FinalAMOWriteDataM; + end subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index 07c080255..c5719f2c7 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -38,6 +38,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( input logic HREADY, input logic [1:0] HTRANS, input logic [`XLEN-1:0] HWDATA, + input logic [3:0] HSIZED, output logic [`XLEN-1:0] HREADRam, output logic HRESPRam, HREADYRam ); @@ -53,6 +54,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( logic initTrans; logic memwrite; logic [3:0] busycount; + logic [`XLEN/8-1:0] ByteMaskM; if(`FPGA) begin:ram initial begin @@ -104,6 +106,33 @@ module ram #(parameter BASE=0, RANGE = 65535) ( end // initial begin end // if (FPGA) + if(`XLEN == 64) begin + always_comb begin + case(HSIZED[1:0]) + 2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[A[2:0]] = 1; end // sb + 2'b01: case (A[2:1]) + 2'b00: ByteMaskM = 8'b0000_0011; + 2'b01: ByteMaskM = 8'b0000_1100; + 2'b10: ByteMaskM = 8'b0011_0000; + 2'b11: ByteMaskM = 8'b1100_0000; + endcase + 2'b10: if (A[2]) ByteMaskM = 8'b11110000; + else ByteMaskM = 8'b00001111; + 2'b11: ByteMaskM = 8'b1111_1111; + endcase + end + end else begin + always_comb begin + case(HSIZED[1:0]) + 2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[A[1:0]] = 1; end // sb + 2'b01: if (A[1]) ByteMaskM = 4'b1100; + else ByteMaskM = 4'b0011; + 2'b10: ByteMaskM = 4'b1111; + default: ByteMaskM = 4'b1111; + endcase + end + end + assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); // *** this seems like a weird way to use reset @@ -148,17 +177,24 @@ module ram #(parameter BASE=0, RANGE = 65535) ( -----/\----- EXCLUDED -----/\----- */ /* verilator lint_off WIDTH */ + genvar index; + always_ff @(posedge HCLK) + HWADDR <= #1 A; if (`XLEN == 64) begin:ramrw - always_ff @(posedge HCLK) begin - HWADDR <= #1 A; + always_ff @(posedge HCLK) HREADRam0 <= #1 RAM[A[31:3]]; - if (memwrite & risingHREADYRam) RAM[HWADDR[31:3]] <= #1 HWDATA; + for(index = 0; index < `XLEN/8; index++) begin + always_ff @(posedge HCLK) begin + if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:3]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index]; + end end end else begin - always_ff @(posedge HCLK) begin:ramrw - HWADDR <= #1 A; + always_ff @(posedge HCLK) HREADRam0 <= #1 RAM[A[31:2]]; - if (memwrite & risingHREADYRam) RAM[HWADDR[31:2]] <= #1 HWDATA; + for(index = 0; index < `XLEN/8; index++) begin + always_ff @(posedge HCLK) begin:ramrw + if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:2]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index]; + end end end /* verilator lint_on WIDTH */ diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 776850e65..16fa38df6 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -91,12 +91,7 @@ module uncore ( assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; // subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache. - if(0) - subwordwrite sww( - .HRDATA, - .HADDRD, .HSIZED, - .HWDATAIN, .HWDATA, .ByteWEN()); - else assign HWDATA = HWDATAIN; + assign HWDATA = HWDATAIN; // generate @@ -106,7 +101,7 @@ module uncore ( .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( .HCLK, .HRESETn, .HSELRam, .HADDR, - .HWRITE, .HREADY, + .HWRITE, .HREADY, .HSIZED, .HTRANS, .HWDATA, .HREADRam, .HRESPRam, .HREADYRam); end @@ -116,7 +111,7 @@ module uncore ( bootrom( .HCLK, .HRESETn, .HSELRam(HSELBootRom), .HADDR, - .HWRITE, .HREADY, .HTRANS, + .HWRITE, .HREADY, .HTRANS, .HSIZED, .HWDATA, .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom)); end From 396c97fc36f72403c46922f548b55bd954d1a114 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 17:26:32 -0600 Subject: [PATCH 156/199] Byte write enables are passing all configs now. --- pipelined/src/generic/flop/simpleram.sv | 10 +++- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/dtim.sv | 3 +- pipelined/src/lsu/lsu.sv | 10 ++-- pipelined/src/uncore/ram.sv | 27 +--------- pipelined/src/uncore/subwordwrite.sv | 5 +- pipelined/src/uncore/swwbytemask.sv | 66 +++++++++++++++++++++++++ 7 files changed, 84 insertions(+), 39 deletions(-) create mode 100644 pipelined/src/uncore/swwbytemask.sv diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv index 3ad367bd5..492bb4612 100644 --- a/pipelined/src/generic/flop/simpleram.sv +++ b/pipelined/src/generic/flop/simpleram.sv @@ -34,6 +34,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( input logic clk, input logic [31:0] a, input logic we, + input logic [`XLEN/8-1:0] FinalByteWENM, input logic [`XLEN-1:0] wd, output logic [`XLEN-1:0] rd ); @@ -45,9 +46,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( logic [31:adrlsb] adrmsbs; assign adrmsbs = a[31:adrlsb]; - always_ff @(posedge clk) begin + always_ff @(posedge clk) rd <= RAM[adrmsbs]; - if (we) RAM[adrmsbs] <= #1 wd; + + genvar index; + for(index = 0; index < `XLEN/8; index++) begin + always_ff @(posedge clk) begin + if (we & FinalByteWENM[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; + end end endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 888115f23..2f118b4a3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -175,7 +175,7 @@ module ifu ( if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), - .TrapM(1'b0), .FinalWriteDataM(), + .TrapM(1'b0), .FinalWriteDataM(), .FinalByteWENM('0), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 7fbdd42f1..70a19367e 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -37,6 +37,7 @@ module dtim( input logic [`XLEN-1:0] IEUAdrE, input logic TrapM, input logic [`XLEN-1:0] FinalWriteDataM, + input logic [`XLEN/8-1:0] FinalByteWENM, output logic [`XLEN-1:0] ReadDataWordM, output logic BusStall, output logic LSUBusWrite, @@ -49,7 +50,7 @@ module dtim( output logic DCacheAccess); simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( - .clk, + .clk, .FinalByteWENM, .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** .we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. .wd(FinalWriteDataM), .rd(ReadDataWordM)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 85dc1c49c..8fd94c177 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -194,7 +194,7 @@ module lsu ( // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, + .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .FinalByteWENM, .DCacheMiss, .DCacheAccess); assign SelUncachedAdr = '0; // value does not matter. end else begin : bus @@ -253,11 +253,9 @@ module lsu ( end end - if(1) begin - subwordwrite subwordwrite(.HRDATA('0), .HADDRD(LSUPAdrM[2:0]), - .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM)); - end + subwordwrite subwordwrite(.HADDRD(LSUPAdrM[2:0]), + .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM)); subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index c5719f2c7..a7ff06a19 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -106,32 +106,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( end // initial begin end // if (FPGA) - if(`XLEN == 64) begin - always_comb begin - case(HSIZED[1:0]) - 2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[A[2:0]] = 1; end // sb - 2'b01: case (A[2:1]) - 2'b00: ByteMaskM = 8'b0000_0011; - 2'b01: ByteMaskM = 8'b0000_1100; - 2'b10: ByteMaskM = 8'b0011_0000; - 2'b11: ByteMaskM = 8'b1100_0000; - endcase - 2'b10: if (A[2]) ByteMaskM = 8'b11110000; - else ByteMaskM = 8'b00001111; - 2'b11: ByteMaskM = 8'b1111_1111; - endcase - end - end else begin - always_comb begin - case(HSIZED[1:0]) - 2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[A[1:0]] = 1; end // sb - 2'b01: if (A[1]) ByteMaskM = 4'b1100; - else ByteMaskM = 4'b0011; - 2'b10: ByteMaskM = 4'b1111; - default: ByteMaskM = 4'b1111; - endcase - end - end + swbytemask swbytemask(.HSIZED, .HADDRD(A), .ByteMask(ByteMaskM)); assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); diff --git a/pipelined/src/uncore/subwordwrite.sv b/pipelined/src/uncore/subwordwrite.sv index bfc4684f2..28d74051f 100644 --- a/pipelined/src/uncore/subwordwrite.sv +++ b/pipelined/src/uncore/subwordwrite.sv @@ -31,7 +31,6 @@ `include "wally-config.vh" module subwordwrite ( - input logic [`XLEN-1:0] HRDATA, input logic [2:0] HADDRD, input logic [3:0] HSIZED, input logic [`XLEN-1:0] HWDATAIN, @@ -70,7 +69,7 @@ module subwordwrite ( endcase always_comb begin - HWDATA=HRDATA; + HWDATA='0; if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0]; if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8]; if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16]; @@ -104,7 +103,7 @@ module subwordwrite ( endcase always_comb begin - HWDATA=HRDATA; + HWDATA='0; if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0]; if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8]; if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16]; diff --git a/pipelined/src/uncore/swwbytemask.sv b/pipelined/src/uncore/swwbytemask.sv new file mode 100644 index 000000000..df90ad8ee --- /dev/null +++ b/pipelined/src/uncore/swwbytemask.sv @@ -0,0 +1,66 @@ +/////////////////////////////////////////// +// ram.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: On-chip RAM, external to core +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module swbytemask ( + input logic [3:0] HSIZED, + input logic [31:0] HADDRD, + output logic [`XLEN/8-1:0] ByteMask); + + + if(`XLEN == 64) begin + always_comb begin + case(HSIZED[1:0]) + 2'b00: begin ByteMask = 8'b00000000; ByteMask[HADDRD[2:0]] = 1; end // sb + 2'b01: case (HADDRD[2:1]) + 2'b00: ByteMask = 8'b0000_0011; + 2'b01: ByteMask = 8'b0000_1100; + 2'b10: ByteMask = 8'b0011_0000; + 2'b11: ByteMask = 8'b1100_0000; + endcase + 2'b10: if (HADDRD[2]) ByteMask = 8'b11110000; + else ByteMask = 8'b00001111; + 2'b11: ByteMask = 8'b1111_1111; + endcase + end + end else begin + always_comb begin + case(HSIZED[1:0]) + 2'b00: begin ByteMask = 4'b0000; ByteMask[HADDRD[1:0]] = 1; end // sb + 2'b01: if (HADDRD[1]) ByteMask = 4'b1100; + else ByteMask = 4'b0011; + 2'b10: ByteMask = 4'b1111; + default: ByteMask = 4'b1111; + endcase + end + end + +endmodule From d0cf41dbe434ec950daaa95ce4eab10e013b98ac Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:13:35 -0600 Subject: [PATCH 157/199] Simplified byte write enable logic. --- pipelined/src/uncore/ram.sv | 2 +- pipelined/src/uncore/subwordwrite.sv | 44 ++++++---------------------- pipelined/src/uncore/swwbytemask.sv | 2 +- 3 files changed, 11 insertions(+), 37 deletions(-) diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index a7ff06a19..7eef08a71 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -106,7 +106,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( end // initial begin end // if (FPGA) - swbytemask swbytemask(.HSIZED, .HADDRD(A), .ByteMask(ByteMaskM)); + swbytemask swbytemask(.HSIZED, .HADDRD(A[2:0]), .ByteMask(ByteMaskM)); assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); diff --git a/pipelined/src/uncore/subwordwrite.sv b/pipelined/src/uncore/subwordwrite.sv index 28d74051f..474035a9b 100644 --- a/pipelined/src/uncore/subwordwrite.sv +++ b/pipelined/src/uncore/subwordwrite.sv @@ -31,34 +31,20 @@ `include "wally-config.vh" module subwordwrite ( - input logic [2:0] HADDRD, - input logic [3:0] HSIZED, - input logic [`XLEN-1:0] HWDATAIN, - output logic [`XLEN-1:0] HWDATA, + input logic [2:0] HADDRD, + input logic [3:0] HSIZED, + input logic [`XLEN-1:0] HWDATAIN, + output logic [`XLEN-1:0] HWDATA, output logic [`XLEN/8-1:0] ByteWEN -); + ); - logic [`XLEN-1:0] WriteDataSubwordDuplicated; + logic [`XLEN-1:0] WriteDataSubwordDuplicated; + logic [(`XLEN/8)-1:0] ByteMaskM; + swbytemask swbytemask(.HSIZED, .HADDRD, .ByteMask(ByteMaskM)); + assign ByteWEN = ByteMaskM; if (`XLEN == 64) begin:sww - logic [7:0] ByteMaskM; - // Compute write mask - assign ByteWEN = ByteMaskM; - always_comb - case(HSIZED[1:0]) - 2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[HADDRD[2:0]] = 1; end // sb - 2'b01: case (HADDRD[2:1]) - 2'b00: ByteMaskM = 8'b00000011; - 2'b01: ByteMaskM = 8'b00001100; - 2'b10: ByteMaskM = 8'b00110000; - 2'b11: ByteMaskM = 8'b11000000; - endcase - 2'b10: if (HADDRD[2]) ByteMaskM = 8'b11110000; - else ByteMaskM = 8'b00001111; - 2'b11: ByteMaskM = 8'b11111111; - endcase - // Handle subword writes always_comb case(HSIZED[1:0]) @@ -81,18 +67,6 @@ module subwordwrite ( end end else begin:sww // 32-bit - logic [3:0] ByteMaskM; - // Compute write mask - assign ByteWEN = ByteMaskM; - always_comb - case(HSIZED[1:0]) - 2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[HADDRD[1:0]] = 1; end // sb - 2'b01: if (HADDRD[1]) ByteMaskM = 4'b1100; - else ByteMaskM = 4'b0011; - 2'b10: ByteMaskM = 4'b1111; - default: ByteMaskM = 4'b111; // shouldn't happen - endcase - // Handle subword writes always_comb case(HSIZED[1:0]) diff --git a/pipelined/src/uncore/swwbytemask.sv b/pipelined/src/uncore/swwbytemask.sv index df90ad8ee..570477c7b 100644 --- a/pipelined/src/uncore/swwbytemask.sv +++ b/pipelined/src/uncore/swwbytemask.sv @@ -32,7 +32,7 @@ module swbytemask ( input logic [3:0] HSIZED, - input logic [31:0] HADDRD, + input logic [2:0] HADDRD, output logic [`XLEN/8-1:0] ByteMask); From 1aa87c9f3a94f83849c802eea22c30ac200aee66 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:15:25 -0600 Subject: [PATCH 158/199] Moved subwordwrite to lsu directory. --- pipelined/src/{uncore => lsu}/subwordwrite.sv | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/{uncore => lsu}/subwordwrite.sv (100%) diff --git a/pipelined/src/uncore/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv similarity index 100% rename from pipelined/src/uncore/subwordwrite.sv rename to pipelined/src/lsu/subwordwrite.sv From 654c4d1148c4356bb9a4e00bac367261676e8916 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:17:44 -0600 Subject: [PATCH 159/199] simplified uncore's name for HWDATA. --- pipelined/src/uncore/uncore.sv | 7 +------ pipelined/src/wally/wallypipelinedsoc.sv | 2 +- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 16fa38df6..d90a30d7c 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -38,7 +38,7 @@ module uncore ( input logic HCLK, HRESETn, input logic TIMECLK, input logic [31:0] HADDR, - input logic [`AHBW-1:0] HWDATAIN, + input logic [`AHBW-1:0] HWDATA, input logic HWRITE, input logic [2:0] HSIZE, input logic [2:0] HBURST, @@ -68,7 +68,6 @@ module uncore ( output logic [63:0] MTIME_CLINT ); - logic [`XLEN-1:0] HWDATA; logic [`XLEN-1:0] HREADRam, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC; logic [8:0] HSELRegions; @@ -90,10 +89,6 @@ module uncore ( // unswizzle HSEL signals assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; - // subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache. - assign HWDATA = HWDATAIN; - - // generate // on-chip RAM if (`RAM_SUPPORTED) begin : ram diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index a311d6c64..1b7f38311 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -92,7 +92,7 @@ module wallypipelinedsoc ( ); uncore uncore(.HCLK, .HRESETn, .TIMECLK, - .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, + .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .HSELEXT, From 63b1ea88c9f190a30260310239f44d0d7dc418e5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:26:58 -0600 Subject: [PATCH 160/199] Signal name cleanup. --- pipelined/src/cache/cache.sv | 4 ++-- pipelined/src/cache/cacheway.sv | 11 +++++------ pipelined/src/cache/sram1p1rw.sv | 6 +++--- pipelined/src/generic/flop/simpleram.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/lsu/dtim.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 8 ++++---- pipelined/src/lsu/subwordwrite.sv | 4 ++-- 8 files changed, 22 insertions(+), 23 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index a4b64fed6..fe685dc0e 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -41,7 +41,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( input logic InvalidateCacheM, input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] PAdr, // physical address - input logic [(`XLEN-1)/8:0] ByteWEN, + input logic [(`XLEN-1)/8:0] ByteWe, input logic [`XLEN-1:0] FinalWriteData, output logic CacheCommitted, output logic CacheStall, @@ -115,7 +115,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteWEN, + .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteWe, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Invalidate(InvalidateCacheM)); diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 30f42039d..fa3a0b68f 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic VictimWay, input logic FlushWay, input logic Invalidate, - input logic [(`XLEN-1)/8:0] ByteWEN, + input logic [(`XLEN-1)/8:0] ByteWe, output logic [LINELEN-1:0] ReadDataLineWay, output logic HitWay, @@ -69,7 +69,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, logic [$clog2(NUMLINES)-1:0] RAdrD; logic [2**LOGWPL-1:0] MemPAdrDecoded; logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; - logic [(`XLEN-1)/8:0] FinalByteWEN; + logic [(`XLEN-1)/8:0] FinalByteWe; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux @@ -78,15 +78,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND - assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR - //assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR + assign FinalByteWe = SetValidWay ? '1 : ByteWe; // OR ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, - .Adr(RAdr), .ReadData(ReadTag), .ByteWEN('1), + .Adr(RAdr), .ReadData(ReadTag), .ByteWe('1), .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay)); // AND portion of distributed tag multiplexer @@ -105,7 +104,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr), .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]), - .WriteEnable(SelectedWriteWordEn[words]), .ByteWEN(FinalByteWEN)); + .WriteEnable(SelectedWriteWordEn[words]), .ByteWe(FinalByteWe)); end // AND portion of distributed read multiplexers diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 06581d0c3..229fb49a2 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -38,7 +38,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( input logic [$clog2(DEPTH)-1:0] Adr, input logic [WIDTH-1:0] CacheWriteData, input logic WriteEnable, - input logic [(WIDTH-1)/8:0] ByteWEN, + input logic [(WIDTH-1)/8:0] ByteWe, output logic [WIDTH-1:0] ReadData); logic [WIDTH-1:0] StoredData[DEPTH-1:0]; @@ -50,7 +50,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( genvar index; for(index = 0; index < WIDTH/8; index++) begin always_ff @(posedge clk) begin - if (WriteEnable & ByteWEN[index]) begin + if (WriteEnable & ByteWe[index]) begin StoredData[Adr][8*(index+1)-1:8*index] <= #1 CacheWriteData[8*(index+1)-1:8*index]; end end @@ -58,7 +58,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( // if not a multiple of 8, MSByte is not 8 bits long. if(WIDTH%8 != 0) begin always_ff @(posedge clk) begin - if (WriteEnable & ByteWEN[WIDTH/8]) begin + if (WriteEnable & ByteWe[WIDTH/8]) begin StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; end end diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv index 492bb4612..9d17bfe56 100644 --- a/pipelined/src/generic/flop/simpleram.sv +++ b/pipelined/src/generic/flop/simpleram.sv @@ -34,7 +34,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( input logic clk, input logic [31:0] a, input logic we, - input logic [`XLEN/8-1:0] FinalByteWENM, + input logic [`XLEN/8-1:0] ByteWe, input logic [`XLEN-1:0] wd, output logic [`XLEN-1:0] rd ); @@ -52,7 +52,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( genvar index; for(index = 0; index < `XLEN/8; index++) begin always_ff @(posedge clk) begin - if (we & FinalByteWENM[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; + if (we & ByteWe[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; end end endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2f118b4a3..12b20a322 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -175,7 +175,7 @@ module ifu ( if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), - .TrapM(1'b0), .FinalWriteDataM(), .FinalByteWENM('0), + .TrapM(1'b0), .FinalWriteDataM(), .ByteWeM('0), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); @@ -220,7 +220,7 @@ module ifu ( .CacheWriteLine(), .ReadDataLine(ReadDataLine), .save, .restore, .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteWEN('0), + .ByteWe('0), .FinalWriteData('0), .RW(2'b10), .Atomic('0), .FlushCache('0), diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 70a19367e..dc2e0e126 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -37,7 +37,7 @@ module dtim( input logic [`XLEN-1:0] IEUAdrE, input logic TrapM, input logic [`XLEN-1:0] FinalWriteDataM, - input logic [`XLEN/8-1:0] FinalByteWENM, + input logic [`XLEN/8-1:0] ByteWeM, output logic [`XLEN-1:0] ReadDataWordM, output logic BusStall, output logic LSUBusWrite, @@ -50,7 +50,7 @@ module dtim( output logic DCacheAccess); simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( - .clk, .FinalByteWENM, + .clk, .ByteWe(ByteWeM), .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** .we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. .wd(FinalWriteDataM), .rd(ReadDataWordM)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 8fd94c177..7d543c242 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -105,7 +105,7 @@ module lsu ( logic LSUBusWriteCrit; logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; - logic [(`XLEN-1)/8:0] FinalByteWENM; + logic [(`XLEN-1)/8:0] ByteWeM; // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, @@ -194,7 +194,7 @@ module lsu ( // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .FinalByteWENM, + .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteWeM, .DCacheMiss, .DCacheAccess); assign SelUncachedAdr = '0; // value does not matter. end else begin : bus @@ -235,7 +235,7 @@ module lsu ( .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .ByteWEN(FinalByteWENM), + .ByteWe(ByteWeM), .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), @@ -255,7 +255,7 @@ module lsu ( subwordwrite subwordwrite(.HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM)); + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWeM); subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 474035a9b..6756f3128 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -35,14 +35,14 @@ module subwordwrite ( input logic [3:0] HSIZED, input logic [`XLEN-1:0] HWDATAIN, output logic [`XLEN-1:0] HWDATA, - output logic [`XLEN/8-1:0] ByteWEN + output logic [`XLEN/8-1:0] ByteWeM ); logic [`XLEN-1:0] WriteDataSubwordDuplicated; logic [(`XLEN/8)-1:0] ByteMaskM; swbytemask swbytemask(.HSIZED, .HADDRD, .ByteMask(ByteMaskM)); - assign ByteWEN = ByteMaskM; + assign ByteWeM = ByteMaskM; if (`XLEN == 64) begin:sww // Handle subword writes From 6d914def08364f482c8feb8b2a6efbba9ecf59e8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:44:50 -0600 Subject: [PATCH 161/199] Name cleanup. --- pipelined/src/cache/cache.sv | 4 ++-- pipelined/src/cache/cacheway.sv | 10 +++++----- pipelined/src/cache/sram1p1rw.sv | 6 +++--- pipelined/src/generic/flop/simpleram.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/lsu/dtim.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 16 +++++++++------- pipelined/src/lsu/subwordwrite.sv | 8 +++----- .../{uncore/swwbytemask.sv => lsu/swbytemask.sv} | 0 9 files changed, 28 insertions(+), 28 deletions(-) rename pipelined/src/{uncore/swwbytemask.sv => lsu/swbytemask.sv} (100%) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index fe685dc0e..0d380356f 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -41,7 +41,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( input logic InvalidateCacheM, input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] PAdr, // physical address - input logic [(`XLEN-1)/8:0] ByteWe, + input logic [(`XLEN-1)/8:0] ByteMask, input logic [`XLEN-1:0] FinalWriteData, output logic CacheCommitted, output logic CacheStall, @@ -115,7 +115,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteWe, + .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Invalidate(InvalidateCacheM)); diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index fa3a0b68f..d9a478612 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic VictimWay, input logic FlushWay, input logic Invalidate, - input logic [(`XLEN-1)/8:0] ByteWe, + input logic [(`XLEN-1)/8:0] ByteMask, output logic [LINELEN-1:0] ReadDataLineWay, output logic HitWay, @@ -69,7 +69,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, logic [$clog2(NUMLINES)-1:0] RAdrD; logic [2**LOGWPL-1:0] MemPAdrDecoded; logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; - logic [(`XLEN-1)/8:0] FinalByteWe; + logic [(`XLEN-1)/8:0] FinalByteMask; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux @@ -78,14 +78,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND - assign FinalByteWe = SetValidWay ? '1 : ByteWe; // OR + assign FinalByteMask = SetValidWay ? '1 : ByteMask; // OR ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, - .Adr(RAdr), .ReadData(ReadTag), .ByteWe('1), + .Adr(RAdr), .ReadData(ReadTag), .ByteMask('1), .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay)); // AND portion of distributed tag multiplexer @@ -104,7 +104,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr), .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]), - .WriteEnable(SelectedWriteWordEn[words]), .ByteWe(FinalByteWe)); + .WriteEnable(SelectedWriteWordEn[words]), .ByteMask(FinalByteMask)); end // AND portion of distributed read multiplexers diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 229fb49a2..5ecb7374a 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -38,7 +38,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( input logic [$clog2(DEPTH)-1:0] Adr, input logic [WIDTH-1:0] CacheWriteData, input logic WriteEnable, - input logic [(WIDTH-1)/8:0] ByteWe, + input logic [(WIDTH-1)/8:0] ByteMask, output logic [WIDTH-1:0] ReadData); logic [WIDTH-1:0] StoredData[DEPTH-1:0]; @@ -50,7 +50,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( genvar index; for(index = 0; index < WIDTH/8; index++) begin always_ff @(posedge clk) begin - if (WriteEnable & ByteWe[index]) begin + if (WriteEnable & ByteMask[index]) begin StoredData[Adr][8*(index+1)-1:8*index] <= #1 CacheWriteData[8*(index+1)-1:8*index]; end end @@ -58,7 +58,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( // if not a multiple of 8, MSByte is not 8 bits long. if(WIDTH%8 != 0) begin always_ff @(posedge clk) begin - if (WriteEnable & ByteWe[WIDTH/8]) begin + if (WriteEnable & ByteMask[WIDTH/8]) begin StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; end end diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv index 9d17bfe56..42411f977 100644 --- a/pipelined/src/generic/flop/simpleram.sv +++ b/pipelined/src/generic/flop/simpleram.sv @@ -34,7 +34,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( input logic clk, input logic [31:0] a, input logic we, - input logic [`XLEN/8-1:0] ByteWe, + input logic [`XLEN/8-1:0] ByteMask, input logic [`XLEN-1:0] wd, output logic [`XLEN-1:0] rd ); @@ -52,7 +52,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( genvar index; for(index = 0; index < `XLEN/8; index++) begin always_ff @(posedge clk) begin - if (we & ByteWe[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; + if (we & ByteMask[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; end end endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 12b20a322..735269bc9 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -175,7 +175,7 @@ module ifu ( if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), - .TrapM(1'b0), .FinalWriteDataM(), .ByteWeM('0), + .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); @@ -220,7 +220,7 @@ module ifu ( .CacheWriteLine(), .ReadDataLine(ReadDataLine), .save, .restore, .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteWe('0), + .ByteMask('0), .FinalWriteData('0), .RW(2'b10), .Atomic('0), .FlushCache('0), diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index dc2e0e126..bbbe664df 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -37,7 +37,7 @@ module dtim( input logic [`XLEN-1:0] IEUAdrE, input logic TrapM, input logic [`XLEN-1:0] FinalWriteDataM, - input logic [`XLEN/8-1:0] ByteWeM, + input logic [`XLEN/8-1:0] ByteMaskM, output logic [`XLEN-1:0] ReadDataWordM, output logic BusStall, output logic LSUBusWrite, @@ -50,7 +50,7 @@ module dtim( output logic DCacheAccess); simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( - .clk, .ByteWe(ByteWeM), + .clk, .ByteMask(ByteMaskM), .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** .we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. .wd(FinalWriteDataM), .rd(ReadDataWordM)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 7d543c242..bb8a6af61 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -105,7 +105,7 @@ module lsu ( logic LSUBusWriteCrit; logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; - logic [(`XLEN-1)/8:0] ByteWeM; + logic [(`XLEN-1)/8:0] ByteMaskM; // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, @@ -194,7 +194,7 @@ module lsu ( // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteWeM, + .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .DCacheMiss, .DCacheAccess); assign SelUncachedAdr = '0; // value does not matter. end else begin : bus @@ -235,7 +235,7 @@ module lsu ( .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .ByteWe(ByteWeM), + .ByteMask(ByteMaskM), .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), @@ -253,10 +253,6 @@ module lsu ( end end - subwordwrite subwordwrite(.HADDRD(LSUPAdrM[2:0]), - .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWeM); - subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); @@ -272,4 +268,10 @@ module lsu ( end else begin:lrsc assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM; end + + subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), + .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteMaskM); + + endmodule diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 6756f3128..2140d0b52 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -31,18 +31,16 @@ `include "wally-config.vh" module subwordwrite ( - input logic [2:0] HADDRD, + input logic [2:0] LSUPAdrM, input logic [3:0] HSIZED, input logic [`XLEN-1:0] HWDATAIN, output logic [`XLEN-1:0] HWDATA, - output logic [`XLEN/8-1:0] ByteWeM + output logic [`XLEN/8-1:0] ByteMaskM ); logic [`XLEN-1:0] WriteDataSubwordDuplicated; - logic [(`XLEN/8)-1:0] ByteMaskM; - swbytemask swbytemask(.HSIZED, .HADDRD, .ByteMask(ByteMaskM)); - assign ByteWeM = ByteMaskM; + swbytemask swbytemask(.HSIZED, .HADDRD(LSUPAdrM), .ByteMask(ByteMaskM)); if (`XLEN == 64) begin:sww // Handle subword writes diff --git a/pipelined/src/uncore/swwbytemask.sv b/pipelined/src/lsu/swbytemask.sv similarity index 100% rename from pipelined/src/uncore/swwbytemask.sv rename to pipelined/src/lsu/swbytemask.sv From 257015a2df3ff51421ae3766e57ef9416dc393a0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:50:03 -0600 Subject: [PATCH 162/199] Name changes. --- pipelined/src/lsu/lsu.sv | 3 +- pipelined/src/lsu/subwordwrite.sv | 57 ++++++++++++++++--------------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index bb8a6af61..70d96ee0b 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -270,8 +270,7 @@ module lsu ( end subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), - .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteMaskM); + .LSUFunct3M, .FinalAMOWriteDataM, .FinalWriteDataM, .ByteMaskM); endmodule diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 2140d0b52..ce850ab72 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -32,54 +32,55 @@ module subwordwrite ( input logic [2:0] LSUPAdrM, - input logic [3:0] HSIZED, - input logic [`XLEN-1:0] HWDATAIN, - output logic [`XLEN-1:0] HWDATA, + input logic [2:0] LSUFunct3M, + input logic [`XLEN-1:0] FinalAMOWriteDataM, + output logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN/8-1:0] ByteMaskM ); logic [`XLEN-1:0] WriteDataSubwordDuplicated; - swbytemask swbytemask(.HSIZED, .HADDRD(LSUPAdrM), .ByteMask(ByteMaskM)); + swbytemask swbytemask(.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HADDRD(LSUPAdrM), + .ByteMask(ByteMaskM)); if (`XLEN == 64) begin:sww // Handle subword writes always_comb - case(HSIZED[1:0]) - 2'b00: WriteDataSubwordDuplicated = {8{HWDATAIN[7:0]}}; // sb - 2'b01: WriteDataSubwordDuplicated = {4{HWDATAIN[15:0]}}; // sh - 2'b10: WriteDataSubwordDuplicated = {2{HWDATAIN[31:0]}}; // sw - 2'b11: WriteDataSubwordDuplicated = HWDATAIN; // sw + case(LSUFunct3M[1:0]) + 2'b00: WriteDataSubwordDuplicated = {8{FinalAMOWriteDataM[7:0]}}; // sb + 2'b01: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[15:0]}}; // sh + 2'b10: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[31:0]}}; // sw + 2'b11: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw endcase always_comb begin - HWDATA='0; - if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0]; - if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8]; - if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16]; - if (ByteMaskM[3]) HWDATA[31:24] = WriteDataSubwordDuplicated[31:24]; - if (ByteMaskM[4]) HWDATA[39:32] = WriteDataSubwordDuplicated[39:32]; - if (ByteMaskM[5]) HWDATA[47:40] = WriteDataSubwordDuplicated[47:40]; - if (ByteMaskM[6]) HWDATA[55:48] = WriteDataSubwordDuplicated[55:48]; - if (ByteMaskM[7]) HWDATA[63:56] = WriteDataSubwordDuplicated[63:56]; + FinalWriteDataM='0; + if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0]; + if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8]; + if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16]; + if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24]; + if (ByteMaskM[4]) FinalWriteDataM[39:32] = WriteDataSubwordDuplicated[39:32]; + if (ByteMaskM[5]) FinalWriteDataM[47:40] = WriteDataSubwordDuplicated[47:40]; + if (ByteMaskM[6]) FinalWriteDataM[55:48] = WriteDataSubwordDuplicated[55:48]; + if (ByteMaskM[7]) FinalWriteDataM[63:56] = WriteDataSubwordDuplicated[63:56]; end end else begin:sww // 32-bit // Handle subword writes always_comb - case(HSIZED[1:0]) - 2'b00: WriteDataSubwordDuplicated = {4{HWDATAIN[7:0]}}; // sb - 2'b01: WriteDataSubwordDuplicated = {2{HWDATAIN[15:0]}}; // sh - 2'b10: WriteDataSubwordDuplicated = HWDATAIN; // sw - default: WriteDataSubwordDuplicated = HWDATAIN; // shouldn't happen + case(LSUFunct3M[1:0]) + 2'b00: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[7:0]}}; // sb + 2'b01: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[15:0]}}; // sh + 2'b10: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw + default: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // shouldn't happen endcase always_comb begin - HWDATA='0; - if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0]; - if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8]; - if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16]; - if (ByteMaskM[3]) HWDATA[31:24] = WriteDataSubwordDuplicated[31:24]; + FinalWriteDataM='0; + if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0]; + if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8]; + if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16]; + if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24]; end end From 7f0c5cc8473a4d6fdf3985f3bf81e73e57222886 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:56:37 -0600 Subject: [PATCH 163/199] atomic cleanup. --- pipelined/src/lsu/atomic.sv | 3 +-- pipelined/src/lsu/interlockfsm.sv | 12 ++++++------ pipelined/src/lsu/lsu.sv | 4 +--- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index 6575a3bf6..32864ba02 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -41,7 +41,6 @@ module atomic ( input logic [1:0] LSUAtomicM, input logic [1:0] PreLSURWM, input logic IgnoreRequest, - input logic DTLBMissM, output logic [`XLEN-1:0] FinalAMOWriteDataM, output logic SquashSCW, output logic [1:0] LSURWM); @@ -52,7 +51,7 @@ module atomic ( amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), .result(AMOResult)); mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); - assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; // *** is DTLBMiss needed; might be par tof ignorerequest + assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, .SquashSCW, .LSURWM); diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 05de62175..a6cf2846e 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -56,7 +56,7 @@ module interlockfsm( logic AnyCPUReqM; typedef enum logic[2:0] {STATE_T0_READY, - STATE_T0_REPLAY, + STATE_T1_REPLAY, STATE_T3_DTLB_MISS, STATE_T4_ITLB_MISS, STATE_T5_ITLB_MISS, @@ -82,13 +82,13 @@ module interlockfsm( else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS; else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS; else InterlockNextState = STATE_T0_READY; - STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY; + STATE_T1_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T1_REPLAY; else InterlockNextState = STATE_T0_READY; - STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; + STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T1_REPLAY; else InterlockNextState = STATE_T3_DTLB_MISS; STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; else InterlockNextState = STATE_T4_ITLB_MISS; - STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; + STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T1_REPLAY; else InterlockNextState = STATE_T5_ITLB_MISS; STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; else InterlockNextState = STATE_T7_DITLB_MISS; @@ -122,12 +122,12 @@ module interlockfsm( endcase end - assign SelReplayMemE = (InterlockCurrState == STATE_T0_REPLAY & DCacheStallM) | + assign SelReplayMemE = (InterlockCurrState == STATE_T1_REPLAY & DCacheStallM) | (InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) | (InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF); assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM)); assign IgnoreRequestTrapM = (InterlockCurrState == STATE_T0_READY & (TrapM)) | - ((InterlockCurrState == STATE_T0_REPLAY) & (TrapM)); + ((InterlockCurrState == STATE_T1_REPLAY) & (TrapM)); endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 70d96ee0b..ceae77f61 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -259,12 +259,10 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// - - // *** why does this need DTLBMissM? if (`A_SUPPORTED) begin:atomic atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, - .DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM); + .FinalAMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM; end From 52cc8526006c08e1f5a1b5c3e2b53468f24698db Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 10:43:54 -0600 Subject: [PATCH 164/199] removed unused parameter. --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 9 +++++---- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 0d380356f..9992650ef 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" -module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( +module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( input logic clk, input logic reset, // cpu side diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 735269bc9..cf380a0ed 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -212,7 +212,7 @@ module ifu ( if(CACHE_ENABLED) begin : icache cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), - .NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0)) + .NUMWAYS(`ICACHE_NUMWAYS)) icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0), .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index ceae77f61..004ce3722 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -225,14 +225,11 @@ module lsu ( .s(SelUncachedAdr), .y(ReadDataWordMuxM)); mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA)); - mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM), - .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. if(CACHE_ENABLED) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( + .NUMWAYS(`DCACHE_NUMWAYS)) dcache( .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .ByteMask(ByteMaskM), @@ -243,6 +240,10 @@ module lsu ( .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); + mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM), + .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), + .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( // *** merge into cache .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); From a18f06c20b754a2bd09bfa2989f34ac6a96a55af Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 11:03:36 -0600 Subject: [PATCH 165/199] Moved subcacheline read inside the cache. --- pipelined/src/cache/cache.sv | 20 +++++++++++++++++--- pipelined/src/ifu/ifu.sv | 13 ++++--------- pipelined/src/lsu/lsu.sv | 17 ++++------------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 9992650ef..876470a20 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" -module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( +module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTERVAL) ( input logic clk, input logic reset, // cpu side @@ -48,7 +48,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( // to performance counters to cpu output logic CacheMiss, output logic CacheAccess, - output logic save, restore, // lsu control input logic IgnoreRequestTLB, input logic IgnoreRequestTrapM, @@ -57,9 +56,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( output logic CacheFetchLine, output logic CacheWriteLine, input logic CacheBusAck, + input logic [LOGWPL-1:0] WordCount, + input logic LSUBusWriteCrit, output logic [`PA_BITS-1:0] CacheBusAdr, input logic [LINELEN-1:0] CacheBusWriteData, - output logic [LINELEN-1:0] ReadDataLine); + output logic [WORDLEN-1:0] ReadDataWord); // Cache parameters localparam LINEBYTELEN = LINELEN/8; @@ -102,6 +103,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [1:0] CacheRW, CacheAtomic; + logic [LINELEN-1:0] ReadDataLine; + logic [`PA_BITS-1:0] WordOffsetAddr; + logic save, restore; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -139,6 +143,16 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved); mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); end else assign HitWayFinal = HitWay; + + + mux2 #(`PA_BITS) WordAdrrMux(.d0(PAdr), + .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), + .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + + subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread( // *** merge into cache + .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, + .ReadDataLine, .ReadDataWord); + ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index cf380a0ed..743dfbfc1 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -188,7 +188,6 @@ module ifu ( logic [LINELEN-1:0] ICacheBusWriteData; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; - logic save,restore; logic [31:0] temp; logic SelUncachedAdr; @@ -212,15 +211,15 @@ module ifu ( if(CACHE_ENABLED) begin : icache cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), - .NUMWAYS(`ICACHE_NUMWAYS)) + .NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16)) icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0), .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), - .CacheWriteLine(), .ReadDataLine(ReadDataLine), - .save, .restore, .Cacheable(CacheableF), + .CacheWriteLine(), .ReadDataWord(FinalInstrRawF), + .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteMask('0), + .ByteMask('0), .WordCount('0), .LSUBusWriteCrit('0), .FinalWriteData('0), .RW(2'b10), .Atomic('0), .FlushCache('0), @@ -228,10 +227,6 @@ module ifu ( .PAdr(PCPF), .CacheCommitted(), .InvalidateCacheM(InvalidateICacheM)); - subcachelineread #(LINELEN, 32, 16) subcachelineread( - .clk, .reset, .PAdr(PCPF), .save, .restore, - .ReadDataLine, .ReadDataWord(FinalInstrRawF)); - end else begin : passthrough assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0; assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 004ce3722..26f428f5d 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -207,8 +207,6 @@ module lsu ( logic DCacheWriteLine; logic DCacheFetchLine; logic DCacheBusAck; - logic save, restore; - logic [`PA_BITS-1:0] WordOffsetAddr; logic SelBus; logic [LOGWPL-1:0] WordCount; @@ -229,24 +227,17 @@ module lsu ( if(CACHE_ENABLED) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(`DCACHE_NUMWAYS)) dcache( - .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), + .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN)) dcache( + .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .ByteMask(ByteMaskM), + .ByteMask(ByteMaskM), .WordCount, .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), - .CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM), + .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); - mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM), - .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. - - subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( // *** merge into cache - .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, - .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); end else begin : passthrough assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0; From b7a680ec2ad1fea84b4745051685581042629c44 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 12:44:04 -0600 Subject: [PATCH 166/199] Moved subcachelineread inside the cache. There is some ugliness to still resolve. --- pipelined/src/cache/cache.sv | 20 ++++++++++++-------- pipelined/src/cache/subcachelineread.sv | 6 +++--- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 3 +-- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 876470a20..dadebc69d 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" -module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTERVAL) ( +module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTERVAL, DCACHE) ( input logic clk, input logic reset, // cpu side @@ -104,7 +104,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [1:0] CacheRW, CacheAtomic; logic [LINELEN-1:0] ReadDataLine; - logic [`PA_BITS-1:0] WordOffsetAddr; + logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; logic save, restore; ///////////////////////////////////////////////////////////////////////////////////////////// @@ -145,13 +145,17 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER end else assign HitWayFinal = HitWay; - mux2 #(`PA_BITS) WordAdrrMux(.d0(PAdr), - .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + // like to fix this. + if(DCACHE) + mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), + .d1(WordCount), .s(LSUBusWriteCrit), + .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; + - subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread( // *** merge into cache - .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, - .ReadDataLine, .ReadDataWord); + subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread( + .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, + .ReadDataLine, .ReadDataWord); ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 9894b3665..47fc993a3 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -30,10 +30,10 @@ `include "wally-config.vh" -module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( +module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( input logic clk, input logic reset, - input logic [`PA_BITS-1:0] PAdr, + input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, input logic save, restore, input logic [LINELEN-1:0] ReadDataLine, output logic [WORDLEN-1:0] ReadDataWord); @@ -60,7 +60,7 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( end // variable input mux // *** maybe remove REPLAY config later after deciding which way is best - assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]]; + assign ReadDataWordRaw = ReadDataLineSets[PAdr]; if(!`REPLAY) begin flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved); mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved, diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 743dfbfc1..f59af0abe 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -211,7 +211,7 @@ module ifu ( if(CACHE_ENABLED) begin : icache cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), - .NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16)) + .NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0), .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 26f428f5d..702913813 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -227,7 +227,7 @@ module lsu ( if(CACHE_ENABLED) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN)) dcache( + .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .ByteMask(ByteMaskM), .WordCount, @@ -238,7 +238,6 @@ module lsu ( .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); - end else begin : passthrough assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0; assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; From 6e24a807f64212d717a573277fab557e4d98ade3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 13:05:47 -0600 Subject: [PATCH 167/199] mild cleanup. --- pipelined/src/cache/cache.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index dadebc69d..02f2c0407 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -152,12 +152,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; - subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread( .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, .ReadDataLine, .ReadDataWord); - ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// From 88897da30b2e066cbb8795d700b299c4edd23320 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 11 Mar 2022 19:09:16 +0000 Subject: [PATCH 168/199] Added interrupt support (not exiting correctly yet), macros for causing traps. --- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 228 +++++++++++++++--- 1 file changed, 191 insertions(+), 37 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index e569ce570..99e000fad 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -55,12 +55,17 @@ RVTEST_CODE_BEGIN .endm -.macro TRAP_HANDLER MODE, VECTORED=1 // default to vectored tests - // Set up the exception Handler, keeping the original handler in x4. +.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0 + // MODE decides which mode this trap handler will be taken in (M or S mode) + // Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1) + // vs Using the non-vector approach the rest of the trap handler takes (0) + // DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1) + // vs not saving that info to the signature (0) - // trap handler setup + + // Set up the exception Handler, keeping the original handler in x4. la x1, trap_handler_\MODE\() -.if (\VECTORED == 1) +.if (\VECTORED\() == 1) ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts .endif @@ -115,17 +120,18 @@ trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code - .4byte s_soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. - .4byte segfault_\MODE\() // 2: reserved - .4byte m_soft_interrupt_\MODE\() // 3: breakpoint - .4byte segfault_\MODE\() // 4: reserved - .4byte s_time_interrupt_\MODE\() // 5: load access fault - .4byte segfault_\MODE\() // 6: reserved - .4byte m_time_interrupt_\MODE\() // 7: store access fault - .4byte segfault_\MODE\() // 8: reserved - .4byte s_ext_interrupt_\MODE\() // 9: ecall from S-mode - .4byte segfault_\MODE\() // 10: reserved - .4byte m_ext_interrupt_\MODE\() // 11: ecall from M-mode + // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way + j s_soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. + j segfault_\MODE\() // 2: reserved + j m_soft_interrupt_\MODE\() // 3: breakpoint + j segfault_\MODE\() // 4: reserved + j s_time_interrupt_\MODE\() // 5: load access fault + j segfault_\MODE\() // 6: reserved + j m_time_interrupt_\MODE\() // 7: store access fault + j segfault_\MODE\() // 8: reserved + j s_ext_interrupt_\MODE\() // 9: ecall from S-mode + j segfault_\MODE\() // 10: reserved + j m_ext_interrupt_\MODE\() // 11: ecall from M-mode // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): @@ -139,12 +145,34 @@ trap_unvectored_\MODE\(): addi x6, x6, 8 addi x16, x16, 8 // update pointers for logging results +.if (\DEBUG\() == 1) // record extra information (MTVAL, some status bits) about traps + csrr x1, \MODE\()tval + sd x1, 0(x16) + addi x6, x6, 8 + addi x16, x16, 8 + + csrr x1, \MODE\()status +.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register. + li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE. +.else + li x5, 0x122 // mask bits to select SPP, SPIE, and SIE. +.endif + + and x5, x5, x1 + sd x5, 0(x16) // store masked out status bits to the output + addi x6, x6, 8 + addi x16, x16, 8 + +.endif + // Respond to trap based on cause // All interrupts should return after being logged + csrr x1, \MODE\()cause li x5, 0x8000000000000000 // if msb is set, it is an interrupt and x5, x5, x1 bnez x5, trapreturn_\MODE\() // return from interrupt // Other trap handling is specified in the vector Table + csrr x1, \MODE\()cause slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table la x5, exception_vector_table_\MODE\() add x5, x5, x1 // compute address of vector in Table @@ -171,16 +199,16 @@ trapreturn_\MODE\(): // lw x5, 0(x1) // read the faulting instruction // li x1, 3 // check bottom 2 bits of instruction to see if compressed // and x5, x5, x1 // mask the other bits -// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed +// beq x5, x1, trapreturn_uncompressed_\MODE\() // if 11, the instruction is return_uncompressed -// trapreturn_compressed: +// trapreturn_compressed_\MODE\(): // csrr x1, mepc // get the mepc again // addi x1, x1, 2 // add 2 to find the next instruction -// j trapreturn_specified // and return +// j trapreturn_specified_\MODE\() // and return -// trapreturn_uncompressed: -// csrr x1, mepc // get the mepc again -// addi x1, x1, 4 // add 4 to find the next instruction +// trapreturn_uncompressed_\MODE\(): +// csrr x1, mepc // get the mepc again +// addi x1, x1, 4 // add 4 to find the next instruction trapreturn_specified_\MODE\(): // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc) @@ -224,6 +252,7 @@ trapreturn_finished_\MODE\(): csrw \MODE\()epc, x1 // update the epc with address of next instruction ld x5, -16(sp) // restore registers from stack before returning ld x1, -8(sp) + csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled \MODE\()ret // return from trap ecallhandler_\MODE\(): @@ -257,10 +286,14 @@ ecallhandler_changetousermode_\MODE\(): csrc mstatus, x1 j trapreturn_\MODE\() -instrfault_\MODE\(): - ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page) +instrpagefault_\MODE\(): + ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address) j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page) +instrfault_\MODE\(): + ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address) + j trapreturn_finished_\MODE\() // return to the code after recording the mcause + illegalinstr_\MODE\(): j trapreturn_\MODE\() // return to the code after recording the mcause @@ -268,23 +301,63 @@ accessfault_\MODE\(): // *** What do I have to do here? j trapreturn_\MODE\() -s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet +addr_misaligned_\MODE\(): j trapreturn_\MODE\() +breakpt_\MODE\(): + j trapreturn_\MODE\() + +s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet + li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. + sd x5, 0(x16) + addi x6, x6, 8 + addi x16, x16, 8 + la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT + sw x0, 0(x28) + j trap_unvectored_\MODE\() + m_soft_interrupt_\MODE\(): - j trapreturn_\MODE\() + li x5, 0x7EC + sd x5, 0(x16) + addi x6, x6, 8 + addi x16, x16, 8 + la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT + sw x0, 0(x28) + j trap_unvectored_\MODE\() s_time_interrupt_\MODE\(): - j trapreturn_\MODE\() + li x5, 0x7EC + sd x5, 0(x16) + addi x6, x6, 8 + addi x16, x16, 8 + j trap_unvectored_\MODE\() m_time_interrupt_\MODE\(): - j trapreturn_\MODE\() + li x5, 0x7EC + sd x5, 0(x16) + addi x6, x6, 8 + addi x16, x16, 8 + j trap_unvectored_\MODE\() s_ext_interrupt_\MODE\(): - j trapreturn_\MODE\() + li x5, 0x7EC + sd x5, 0(x16) + addi x6, x6, 8 + addi x16, x16, 8 + li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits + sw x0, 8(x28) // disable the first pin as an output + sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt) + j trap_unvectored_\MODE\() m_ext_interrupt_\MODE\(): - j trapreturn_\MODE\() + li x5, 0x7EC + sd x5, 0(x16) + addi x6, x6, 8 + addi x16, x16, 8 + li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits + sw x0, 8(x28) // disable the first pin as an output + sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt) + j trap_unvectored_\MODE\() // Table of trap behavior @@ -294,19 +367,19 @@ m_ext_interrupt_\MODE\(): .align 3 // aligns this data table to an 8 byte boundary exception_vector_table_\MODE\(): - .8byte segfault_\MODE\() // 0: instruction address misaligned + .8byte addr_misaligned_\MODE\() // 0: instruction address misaligned .8byte instrfault_\MODE\() // 1: instruction access fault .8byte illegalinstr_\MODE\() // 2: illegal instruction - .8byte segfault_\MODE\() // 3: breakpoint - .8byte segfault_\MODE\() // 4: load address misaligned + .8byte breakpt_\MODE\() // 3: breakpoint + .8byte addr_misaligned_\MODE\() // 4: load address misaligned .8byte accessfault_\MODE\() // 5: load access fault - .8byte segfault_\MODE\() // 6: store address misaligned + .8byte addr_misaligned_\MODE\() // 6: store address misaligned .8byte accessfault_\MODE\() // 7: store access fault .8byte ecallhandler_\MODE\() // 8: ecall from U-mode .8byte ecallhandler_\MODE\() // 9: ecall from S-mode .8byte segfault_\MODE\() // 10: reserved .8byte ecallhandler_\MODE\() // 11: ecall from M-mode - .8byte instrfault_\MODE\() // 12: instruction page fault + .8byte instrpagefault_\MODE\() // 12: instruction page fault .8byte trapreturn_\MODE\() // 13: load page fault .8byte segfault_\MODE\() // 14: reserved .8byte trapreturn_\MODE\() // 15: store page fault @@ -438,7 +511,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // they generally do not fault or cause issues as long as these modes are enabled // *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not? -.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE +.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0 li a0, 2 // determine trap handler behavior (go to machine mode) li a1, \RETURN_VPN // return VPN li a2, \RETURN_PAGETYPE // return page types @@ -446,7 +519,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // now in S mode .endm -.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE +.macro GOTO_S_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0 li a0, 3 // determine trap handler behavior (go to supervisor mode) li a1, \RETURN_VPN // return VPN li a2, \RETURN_PAGETYPE // return page types @@ -454,7 +527,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // now in S mode .endm -.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE +.macro GOTO_U_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0 li a0, 4 // determine trap handler behavior (go to user mode) li a1, \RETURN_VPN // return VPN li a2, \RETURN_PAGETYPE // return page types @@ -554,6 +627,87 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a addi x16, x16, 8 .endm +// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines +// This effectively includes everything that isn't to do with page faults (virtual memory) + +.macro CAUSE_INSTR_ADDR_MISALIGNED + // cause a misaligned address trap + auipc x28, 0 // get current PC, which is aligned + addi x28, x28, 0x1 // add 1 to pc to create misaligned address + jalr x28 // cause instruction address midaligned trap +.endm + +.macro CAUSE_INSTR_ACCESS + la x28, 0x0 // address zero is an address with no memory + jalr x28 // cause instruction access trap +.endm + +.macro CAUSE_ILLEGAL_INSTR + .word 0x00000000 // a 32 bit zros is an illegal instruction +.endm + +.macro CAUSE_BREAKPNT // **** + ebreak +.endm + +.macro CAUSE_LOAD_ADDR_MISALIGNED + auipc x28, 0 // get current PC, which is aligned + addi x28, x28, 1 + lw x29, 0(x28) // load from a misaligned address +.endm + +.macro CAUSE_LOAD_ACC + la x28, 0 // 0 is an address with no memory + lw x29, 0(x28) // load from unimplemented address +.endm + +.macro CAUSE_STORE_ADDR_MISALIGNED + auipc x28, 0 // get current PC, which is aligned + addi x28, x28, 1 + sw x29, 0(x28) // store to a misaligned address +.endm + +.macro CAUSE_STORE_ACC + la x28, 0 // 0 is an address with no memory + sw x29, 0(x28) // store to unimplemented address +.endm + +.macro CAUSE_ECALL + // *** ASSUMES you have already gone to the mode you need to call this from. + ecall +.endm + +.macro CAUSE_TIME_INTERRUPT + // The following code works for both RV32 and RV64. + // RV64 alone would be easier using double-word adds and stores + li x28, 0x100 // Desired offset from the present time + la x29, 0x02004000 // MTIMECMP register in CLINT + la x30, 0x0200BFF8 // MTIME register in CLINT + lw x7, 0(x30) // low word of MTIME + lw x31, 4(x30) // high word of MTIME + add x28, x7, x28 // add desired offset to the current time + bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) + addi x31, x31, 1 // if wrap, increment most significant word + sw x31,4(x29) // store into most significant word of MTIMECMP +nowrap: + sw x28, 0(x29) // store into least significant word of MTIMECMP + loop: j loop // wait until interrupt occurs +.endm + +.macro CAUSE_SOFT_INTERRUPT + la x28, 0x02000000 // MSIP register in CLINT + li x29, 1 // 1 in the lsb + sw x29, 0(x28) // Write MSIP bit +.endm + +.macro CAUSE_EXT_INTERRUPT + li x28, 0x10060000 // load base GPIO memory location + li x29, 0x1 + sw x29, 8(x28) // enable the first pin as an output + sw x29, 28(x28) // set first pin to high interrupt enable + sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt) +.endm + .macro END_TESTS // invokes one final ecall to return to machine mode then terminates this program, so the output is // 0x8: termination called from U mode From 026354f09f3e9f0a901e19b4d61702c61b0ef810 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 11 Mar 2022 19:09:40 +0000 Subject: [PATCH 169/199] removed compressed instructions from gcc make for privilege tests --- .../riscv-test-suite/rv64i_m/privilege/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile index d70717f01..27e6ec971 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile @@ -1,3 +1,5 @@ include ../../Makefile.include +RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests + $(eval $(call compile_template,-march=rv64iac -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) From 9d0a9f07470a75fa88f130f9837c49faf74ede15 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 11 Mar 2022 20:00:54 +0000 Subject: [PATCH 170/199] added preliminary files for trap/priv tests. These DO NOT pass make yet because if interrrupt handling problems --- .../WALLY-mtvec-01.reference_output | 1024 ++++++++++++++++ .../WALLY-stvec-01.reference_output | 1024 ++++++++++++++++ .../references/WALLY-trap-01.reference_output | 1082 +++++++++++++++++ .../WALLY-trap-s-01.reference_output | 1024 ++++++++++++++++ .../WALLY-trap-u-01.reference_output | 1024 ++++++++++++++++ .../rv64i_m/privilege/src/WALLY-mtvec-01.S | 45 + .../rv64i_m/privilege/src/WALLY-stvec-01.S | 55 + .../rv64i_m/privilege/src/WALLY-trap-01.S | 76 ++ .../rv64i_m/privilege/src/WALLY-trap-s-01.S | 85 ++ .../rv64i_m/privilege/src/WALLY-trap-u-01.S | 84 ++ 10 files changed, 5523 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output 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11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000003 # mcause from Breakpoint +00000000 +00000000 # mtval of breakpoint instruction adress (*** Determined from make) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000004 # mcause from load address misaligned +00000000 +00000000 # mtval of misaligned address (*** Determined from make) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000005 # mcause from load access +00000000 +00000000 # mtval of address with access faulting instr (*** Determined from make) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000006 # mcause from store misaligned +00000000 +00000000 # mtval of address with misaligned store instr (*** Determined from make) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000007 # mcause from store access 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S new file mode 100644 index 000000000..b90291bc8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// +// WALLY-unvectored-interrupt +// +// Author: Kip Macsai-Goren +// +// Created 2022-03-11 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +// test 5.3.1.5 Unvectored interrupt tests + +TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. + +li x28, 0x8 +csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode +// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts + +// cause traps, ensuring that we DONT go through the vectored part of the trap handler +// *** this assumes that interrupt code 0 remains reserved + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S new file mode 100644 index 000000000..688c78910 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -0,0 +1,55 @@ +/////////////////////////////////////////// +// +// WALLY-unvectored-interrupt +// +// Author: Kip Macsai-Goren +// +// Created 2022-03-11 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +// test 5.3.1.5 Unvectored interrupt tests + +TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. + +// li x28, 0x8 +// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode +// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts + +WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF + +GOTO_S_MODE + +// cause traps, ensuring that we DONT go through the vectored part of the trap handler +// *** this assumes that interrupt code 0 remains reserved + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + +GOTO_U_MODE + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S new file mode 100644 index 000000000..be1ca6509 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -0,0 +1,76 @@ +/////////////////////////////////////////// +// +// WALLY-trap +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-20 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps + +li x28, 0x8 +csrs mstatus, x28 // set mstatus.MIE bit to 1 +// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts + +// test 5.3.1.4 Basic trap tests + +// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) +CAUSE_INSTR_ACCESS +CAUSE_ILLEGAL_INSTR +CAUSE_BREAKPNT +CAUSE_LOAD_ADDR_MISALIGNED +CAUSE_LOAD_ACC +CAUSE_STORE_ADDR_MISALIGNED +CAUSE_STORE_ACC +GOTO_U_MODE // Causes M mode ecall +GOTO_S_MODE // Causes U mode ecall +GOTO_M_MODE // Causes S mode ecall + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + +// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode + +WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF +WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF + +// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) +CAUSE_INSTR_ACCESS +CAUSE_ILLEGAL_INSTR +CAUSE_BREAKPNT +CAUSE_LOAD_ADDR_MISALIGNED +CAUSE_LOAD_ACC +CAUSE_STORE_ADDR_MISALIGNED +CAUSE_STORE_ACC +CAUSE_ECALL // M mode ecall +// GOTO_U_MODE // leave these untested since we only need to ensure that from M mode are not delegated +// GOTO_S_MODE + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + +END_TESTS + +TEST_STACK_AND_DATA + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S new file mode 100644 index 000000000..9a813d9a2 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -0,0 +1,85 @@ +/////////////////////////////////////////// +// +// WALLY-trap-s +// +// Author: Kip Macsai-Goren +// +// Created 2022-03-11 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +// test 5.3.1.4 Basic trap tests + +TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well + +// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg + +GOTO_S_MODE + +li x28, 0x8 +csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode +// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts + + +// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) +CAUSE_INSTR_ACCESS +CAUSE_ILLEGAL_INSTR +CAUSE_BREAKPNT +CAUSE_LOAD_ADDR_MISALIGNED +CAUSE_LOAD_ACC +CAUSE_STORE_ADDR_MISALIGNED +CAUSE_STORE_ACC +CAUSE_ECALL + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + + +// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler +// We can tell which one becuase the different trap handler modes write different bits of the status register +// to the output when debug is on. + +GOTO_M_MODE // so we can write the delegate registers + +WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF +WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF + +GOTO_S_MODE + +// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) +CAUSE_INSTR_ACCESS +CAUSE_ILLEGAL_INSTR +CAUSE_BREAKPNT +CAUSE_LOAD_ADDR_MISALIGNED +CAUSE_LOAD_ACC +CAUSE_STORE_ADDR_MISALIGNED +CAUSE_STORE_ACC +CAUSE_ECALL + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + +END_TESTS + +TEST_STACK_AND_DATA + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S new file mode 100644 index 000000000..498c2ee3b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -0,0 +1,84 @@ +/////////////////////////////////////////// +// +// WALLY-trap-u +// +// Author: Kip Macsai-Goren +// +// Created 2022-03-11 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +// test 5.3.1.4 Basic trap tests + +TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well + +// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg + +GOTO_U_MODE + +// li x28, 0x8 +// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode +// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts + + +// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) +CAUSE_INSTR_ACCESS +CAUSE_ILLEGAL_INSTR +CAUSE_BREAKPNT +CAUSE_LOAD_ADDR_MISALIGNED +CAUSE_LOAD_ACC +CAUSE_STORE_ADDR_MISALIGNED +CAUSE_STORE_ACC +CAUSE_ECALL + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + + +// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler +// We can tell which one becuase the different trap handler modes write different bits of the status register +// to the output when debug is on. + +GOTO_M_MODE // so we can write the delegate registers + +WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF +WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF + +GOTO_U_MODE + +// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) +CAUSE_INSTR_ACCESS +CAUSE_ILLEGAL_INSTR +CAUSE_BREAKPNT +CAUSE_LOAD_ADDR_MISALIGNED +CAUSE_LOAD_ACC +CAUSE_STORE_ADDR_MISALIGNED +CAUSE_STORE_ACC +CAUSE_ECALL + +// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken +// CAUSE_EXT_INTERRUPT + +END_TESTS + +TEST_STACK_AND_DATA From 9dce2a06794b0ddb6a50910b641b7624ebcc0968 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 14:58:21 -0600 Subject: [PATCH 171/199] Towards allowing dtim + bus. --- pipelined/src/cache/cache.sv | 3 +-- pipelined/src/cache/subcachelineread.sv | 5 +---- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 -- pipelined/src/lsu/lsu.sv | 3 ++- 5 files changed, 5 insertions(+), 10 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 02f2c0407..067bfb740 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -144,12 +144,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); end else assign HitWayFinal = HitWay; - // like to fix this. if(DCACHE) mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), .d1(WordCount), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + .y(WordOffsetAddr)); else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread( diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 47fc993a3..2a3395ea5 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -39,11 +39,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( output logic [WORDLEN-1:0] ReadDataWord); localparam WORDSPERLINE = LINELEN/MUXINTERVAL; + // pad is for icache. Muxing extends over the cacheline boundary. localparam PADLEN = WORDLEN-MUXINTERVAL; - // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can - // easily build a variable input mux. - // *** move this to LSU and IFU, also remove mux from busdp into LSU. - // *** give this a module name to match block diagram logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad; logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0]; logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f59af0abe..87015f395 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -177,7 +177,7 @@ module ifu ( dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), - .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), + .BusCommittedM(), .DCacheStallM(ICacheStallF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); end else begin : bus diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index bbbe664df..38a12c752 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -43,7 +43,6 @@ module dtim( output logic LSUBusWrite, output logic LSUBusRead, output logic BusCommittedM, - output logic [`XLEN-1:0] ReadDataWordMuxM, output logic DCacheStallM, output logic DCacheCommittedM, output logic DCacheMiss, @@ -58,7 +57,6 @@ module dtim( // since we have a local memory the bus connections are all disabled. // There are no peripherals supported. assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0; - assign ReadDataWordMuxM = ReadDataWordM; assign {DCacheStallM, DCacheCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 702913813..9fa50115e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -194,9 +194,10 @@ module lsu ( // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM, + .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .DCacheMiss, .DCacheAccess); assign SelUncachedAdr = '0; // value does not matter. + assign ReadDataWordMuxM = ReadDataWordM; end else begin : bus localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN; From 67ff8f27f45b6cae3c64b1f04080f7702f252264 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 15:18:56 -0600 Subject: [PATCH 172/199] Can now support the following memory and bus configurations. 1. dtim/irom only 2. bus only 3. dtim/irom + bus 4. caches + bus --- pipelined/config/buildroot/wally-config.vh | 2 ++ pipelined/config/fpga/wally-config.vh | 2 ++ pipelined/config/rv32e/wally-config.vh | 6 ++++-- pipelined/config/rv32gc/wally-config.vh | 2 ++ pipelined/config/rv32ic/wally-config.vh | 2 ++ pipelined/config/rv64BP/wally-config.vh | 2 ++ pipelined/config/rv64gc/wally-config.vh | 2 ++ pipelined/config/rv64ic/wally-config.vh | 2 ++ pipelined/config/shared/wally-constants.vh | 2 +- pipelined/src/ifu/ifu.sv | 9 ++++++--- pipelined/src/lsu/lsu.sv | 11 ++++++----- 11 files changed, 31 insertions(+), 11 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 7644eb1aa..390481161 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -49,6 +49,8 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE +`define DBUS 1 +`define IBUS 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index a1dc805b3..56ca71c91 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -49,6 +49,8 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE +`define DBUS 1 +`define IBUS 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index c532ce167..ccbcb7283 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -49,8 +49,10 @@ `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 // *** replace with MEM_BUS -`define DMEM `MEM_BUS -`define IMEM `MEM_BUS +`define DMEM `MEM_NONE +`define IMEM `MEM_NONE +`define DBUS 1 +`define IBUS 1 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 47f9d100d..07bc20100 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -49,6 +49,8 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE +`define DBUS 1 +`define IBUS 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 7ccb04758..53669422b 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -49,6 +49,8 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_TIM `define IMEM `MEM_TIM +`define DBUS 0 +`define IBUS 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 0d2439f56..892794e0f 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -51,6 +51,8 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE +`define DBUS 1 +`define IBUS 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 1f61ab5ba..a3f1f7944 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -50,6 +50,8 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE +`define DBUS 1 +`define IBUS 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 73c11dbda..10dcf34c3 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -50,6 +50,8 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_TIM `define IMEM `MEM_TIM +`define DBUS 0 +`define IBUS 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh index de934ee32..4bae2c1b6 100644 --- a/pipelined/config/shared/wally-constants.vh +++ b/pipelined/config/shared/wally-constants.vh @@ -50,7 +50,7 @@ `define SV39 8 `define SV48 9 -`define MEM_BUS 1 +`define MEM_NONE 1 `define MEM_TIM 2 `define MEM_CACHE 3 diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 87015f395..b2eb00399 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -176,11 +176,12 @@ module ifu ( if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), - .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), + .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .BusCommittedM(), .DCacheStallM(ICacheStallF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); - end else begin : bus + end + if (`IBUS) begin : bus localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS : `XLEN; localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; @@ -231,7 +232,9 @@ module ifu ( assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0; assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF; end - end + end else begin : nobus // block: bus + assign AllInstrRawF = FinalInstrRawF; + end assign IFUCacheBusStallF = ICacheStallF | BusStall; assign IFUStallF = IFUCacheBusStallF | SelNextSpillF; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 9fa50115e..1d0588b46 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -82,7 +82,6 @@ module lsu ( input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. ); - localparam CACHE_ENABLED = `DMEM == `MEM_CACHE; logic [`XLEN+1:0] IEUAdrExtM; logic [`PA_BITS-1:0] LSUPAdrM; logic DTLBMissM; @@ -196,9 +195,9 @@ module lsu ( .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .DCacheMiss, .DCacheAccess); - assign SelUncachedAdr = '0; // value does not matter. - assign ReadDataWordMuxM = ReadDataWordM; - end else begin : bus + end + if (`DBUS) begin : bus + localparam CACHE_ENABLED = `DMEM == `MEM_CACHE; localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN; localparam integer LOGWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1; @@ -225,7 +224,6 @@ module lsu ( mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA)); - if(CACHE_ENABLED) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( @@ -243,6 +241,9 @@ module lsu ( assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0; assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; end + end else begin: nobus // block: bus + assign {LSUBusHWDATA, SelUncachedAdr} = '0; + assign ReadDataWordMuxM = ReadDataWordM; end subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), From 7a25d577ba0ed61b3164a2dfaaa53988206d272c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 15:41:53 -0600 Subject: [PATCH 173/199] Added new asserts to testbench. --- pipelined/testbench/testbench.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 33c29548f..775a21a7f 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -359,6 +359,8 @@ module riscvassertions; // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); + assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); end endmodule From 86cc758354571190f2dcb34192cd00131cd02ab9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 18:09:22 -0600 Subject: [PATCH 174/199] cleanup of ram.sv --- pipelined/src/lsu/lsu.sv | 3 +-- pipelined/src/uncore/ram.sv | 8 ++------ 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1d0588b46..2e20b3a2e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -106,7 +106,7 @@ module lsu ( logic [`XLEN-1:0] LSUWriteDataM; logic [(`XLEN-1)/8:0] ByteMaskM; - // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, + // *** TO DO: Burst mode flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); assign IEUAdrExtM = {2'b00, IEUAdrM}; @@ -187,7 +187,6 @@ module lsu ( logic SelUncachedAdr; assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; - // *** change to allow TIM and BUS. seaparate parameter for having bus (but have to have bus if have cache - check in testbench) if (`DMEM == `MEM_TIM) begin : dtim // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index 7eef08a71..e9b0af32d 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -48,7 +48,6 @@ module ram #(parameter BASE=0, RANGE = 65535) ( logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)]; logic [31:0] HWADDR, A; - logic [`XLEN-1:0] HREADRam0; logic prevHREADYRam, risingHREADYRam; logic initTrans; @@ -157,7 +156,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( HWADDR <= #1 A; if (`XLEN == 64) begin:ramrw always_ff @(posedge HCLK) - HREADRam0 <= #1 RAM[A[31:3]]; + HREADRam <= #1 RAM[A[31:3]]; for(index = 0; index < `XLEN/8; index++) begin always_ff @(posedge HCLK) begin if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:3]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index]; @@ -165,7 +164,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( end end else begin always_ff @(posedge HCLK) - HREADRam0 <= #1 RAM[A[31:2]]; + HREADRam <= #1 RAM[A[31:2]]; for(index = 0; index < `XLEN/8; index++) begin always_ff @(posedge HCLK) begin:ramrw if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:2]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index]; @@ -174,8 +173,5 @@ module ram #(parameter BASE=0, RANGE = 65535) ( end /* verilator lint_on WIDTH */ - //assign HREADRam = HREADYRam ? HREADRam0 : `XLEN'bz; - // *** Ross Thompson: removed tristate as fpga synthesis removes. - assign HREADRam = HREADRam0; endmodule From ee4b38dce378407f4b8dc5e7b37d334ec3335fa4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 12 Mar 2022 00:46:11 -0600 Subject: [PATCH 175/199] dtim writes are supressed on non cacheable operation. --- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/dtim.sv | 37 +++++++++++++++++++------------------ pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index b2eb00399..6adc5ad2d 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -177,7 +177,7 @@ module ifu ( dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), - .BusCommittedM(), .DCacheStallM(ICacheStallF), + .BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); end diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 38a12c752..6ca5be4a6 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -30,28 +30,29 @@ `include "wally-config.vh" module dtim( - input logic clk, reset, - input logic CPUBusy, - input logic [1:0] LSURWM, - input logic [`XLEN-1:0] IEUAdrM, - input logic [`XLEN-1:0] IEUAdrE, - input logic TrapM, - input logic [`XLEN-1:0] FinalWriteDataM, - input logic [`XLEN/8-1:0] ByteMaskM, - output logic [`XLEN-1:0] ReadDataWordM, - output logic BusStall, - output logic LSUBusWrite, - output logic LSUBusRead, - output logic BusCommittedM, - output logic DCacheStallM, - output logic DCacheCommittedM, - output logic DCacheMiss, - output logic DCacheAccess); + input logic clk, reset, + input logic CPUBusy, + input logic [1:0] LSURWM, + input logic [`XLEN-1:0] IEUAdrM, + input logic [`XLEN-1:0] IEUAdrE, + input logic TrapM, + input logic [`XLEN-1:0] FinalWriteDataM, + input logic [`XLEN/8-1:0] ByteMaskM, + input logic Cacheable, + output logic [`XLEN-1:0] ReadDataWordM, + output logic BusStall, + output logic LSUBusWrite, + output logic LSUBusRead, + output logic BusCommittedM, + output logic DCacheStallM, + output logic DCacheCommittedM, + output logic DCacheMiss, + output logic DCacheAccess); simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( .clk, .ByteMask(ByteMaskM), .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** - .we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. + .we(LSURWM[0] & Cacheable & ~TrapM), // have to ignore write if Trap. .wd(FinalWriteDataM), .rd(ReadDataWordM)); // since we have a local memory the bus connections are all disabled. diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2e20b3a2e..aa617db68 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -192,7 +192,7 @@ module lsu ( // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .DCacheStallM, .DCacheCommittedM, .ByteMaskM, + .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .Cacheable(CacheableM), .DCacheMiss, .DCacheAccess); end if (`DBUS) begin : bus From e3d01c875b3af6bfa64d9a5a404b0b5495a49406 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Sat, 19 Mar 2022 19:39:03 +0000 Subject: [PATCH 176/199] FMA parameterized and FMA testbench reworked --- addins/riscv-arch-test | 2 +- pipelined/config/rv64fp/BTBPredictor.txt | 1024 +++++++++++++++++ pipelined/config/rv64fp/twoBitPredictor.txt | 1024 +++++++++++++++++ pipelined/config/rv64fp/wally-config.vh | 134 +++ pipelined/config/shared/wally-shared.vh | 43 +- pipelined/fpu-testfloat/FMA/tbgen/tb.sv | 376 +++--- pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh | 2 +- pipelined/src/fpu/fcmp.sv | 1 + pipelined/src/fpu/{cvtfp.sv => fcvtfp.sv} | 3 +- pipelined/src/fpu/{fcvt.sv => fcvtint.sv} | 5 +- pipelined/src/fpu/fma.sv | 805 ++++++++++--- pipelined/src/fpu/fpu.sv | 5 +- pipelined/src/fpu/unpack.sv | 361 ++++++ pipelined/src/fpu/unpacking.sv | 95 -- pipelined/testbench/fp/tests/fma-testbench.sv | 279 +++++ pipelined/testbench/fp/tests/fma.do | 50 + pipelined/testbench/fp/tests/sim-fma | 1 + pipelined/testbench/fp/tests/sim-fma-batch | 1 + tests/fp/create_vectors128fma.sh | 31 + tests/fp/create_vectors16fma.sh | 31 + tests/fp/create_vectors32fma.sh | 31 + tests/fp/create_vectors64fma.sh | 31 + tests/fp/run_all.sh | 4 + 23 files changed, 3927 insertions(+), 412 deletions(-) create mode 100644 pipelined/config/rv64fp/BTBPredictor.txt create mode 100644 pipelined/config/rv64fp/twoBitPredictor.txt create mode 100644 pipelined/config/rv64fp/wally-config.vh rename pipelined/src/fpu/{cvtfp.sv => fcvtfp.sv} (98%) rename pipelined/src/fpu/{fcvt.sv => fcvtint.sv} (98%) create mode 100644 pipelined/src/fpu/unpack.sv delete mode 100644 pipelined/src/fpu/unpacking.sv create mode 100644 pipelined/testbench/fp/tests/fma-testbench.sv create mode 100644 pipelined/testbench/fp/tests/fma.do create mode 100755 pipelined/testbench/fp/tests/sim-fma create mode 100755 pipelined/testbench/fp/tests/sim-fma-batch create mode 100755 tests/fp/create_vectors128fma.sh create mode 100755 tests/fp/create_vectors16fma.sh create mode 100755 tests/fp/create_vectors32fma.sh create mode 100755 tests/fp/create_vectors64fma.sh diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/config/rv64fp/BTBPredictor.txt b/pipelined/config/rv64fp/BTBPredictor.txt new file mode 100644 index 000000000..b761147c6 --- /dev/null +++ b/pipelined/config/rv64fp/BTBPredictor.txt @@ -0,0 +1,1024 @@ +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 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+00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh new file mode 100644 index 000000000..249af8485 --- /dev/null +++ b/pipelined/config/rv64fp/wally-config.vh @@ -0,0 +1,134 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// include shared configuration +`include "wally-shared.vh" + +`define FPGA 0 +`define QEMU 0 +`define DESIGN_COMPILER 0 + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +// IEEE 754 compliance +`define IEEE754 1 + +// MISA RISC-V configuration per specification +`define MISA (32'h00000104 | 1 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +`define ZICSR_SUPPORTED 1 +`define ZIFENCEI_SUPPORTED 1 +`define COUNTERS 32 +`define ZICOUNTERS_SUPPORTED 1 + +/// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define DMEM `MEM_CACHE +`define IMEM `MEM_CACHE +`define VIRTMEM_SUPPORTED 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 + +// TLB configuration. Entries should be a power of 2 +`define ITLB_ENTRIES 32 +`define DTLB_ENTRIES 32 + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 4096 +`define DCACHE_LINELENINBITS 256 +`define ICACHE_NUMWAYS 4 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_LINELENINBITS 256 + +// Integer Divider Configuration +// DIV_BITSPERCYCLE must be 1, 2, or 4 +`define DIV_BITSPERCYCLE 4 + +// Legal number of PMP entries are 0, 16, or 64 +`define PMP_ENTRIES 64 + +// Address space +`define RESET_VECTOR 64'h0000000080000000 + +// Bus Interface width +`define AHBW 64 + +// Peripheral Physiccal Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +`define BOOTROM_SUPPORTED 1'b1 +`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTROM_RANGE 56'h00000FFF +`define RAM_SUPPORTED 1'b1 +`define RAM_BASE 56'h80000000 +`define RAM_RANGE 56'h7FFFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 56'h02000000 +`define CLINT_RANGE 56'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 56'h10060000 +`define GPIO_RANGE 56'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 56'h10000000 +`define UART_RANGE 56'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 56'h0C000000 +`define PLIC_RANGE 56'h03FFFFFF +`define SDC_SUPPORTED 1'b0 +`define SDC_BASE 56'h00012100 +`define SDC_RANGE 56'h0000001F + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 1 + +// Hardware configuration +`define UART_PRESCALE 1 + +// Interrupt configuration +`define PLIC_NUM_SRC 10 +// comment out the following if >=32 sources +`define PLIC_NUM_SRC_LT_32 +`define PLIC_GPIO_ID 3 +`define PLIC_UART_ID 10 + +`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" +`define BPRED_ENABLED 1 +`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define TESTSBP 0 + +`define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 277814f80..198a4ab2e 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -50,10 +50,47 @@ // Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) `define PMPCFG_ENTRIES (`PMP_ENTRIES/8) + +// Floating-point half-precision +`define ZFH_SUPPORTED 0 + +// Floating point constants for Quad, Double, Single, and Half precisions +`define Q_LEN 128 +`define Q_NE 15 +`define Q_NF 112 +`define Q_BIAS 16383 +`define D_LEN 64 +`define D_NE 11 +`define D_NF 52 +`define D_BIAS 1023 +`define S_LEN 32 +`define S_NE 8 +`define S_NF 23 +`define S_BIAS 127 +`define H_LEN 16 +`define H_NE 5 +`define H_NF 10 +`define H_BIAS 15 + // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits -`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32) -`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8) -`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23) +`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) +`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) +`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) +`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) + +// Floating point constants needed for FPU paramerterization +`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED) +`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) +`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) +`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2) +`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) +`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) +`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2) +`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) // Disable spurious Verilator warnings diff --git a/pipelined/fpu-testfloat/FMA/tbgen/tb.sv b/pipelined/fpu-testfloat/FMA/tbgen/tb.sv index 57c4e2ff0..5532aa634 100644 --- a/pipelined/fpu-testfloat/FMA/tbgen/tb.sv +++ b/pipelined/fpu-testfloat/FMA/tbgen/tb.sv @@ -1,10 +1,33 @@ -//`include "../../../config/old/rv64icfd/wally-config.vh" +`include "../../../config/old/rv64icfd/wally-config.vh" -`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32) -`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8) -`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23) -`define XLEN 64 +// `define FLEN (`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : `F_SUPPORTED ? 32 : 16) +// `define NE (`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : `F_SUPPORTED ? 8 : 5) +// `define NF (`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : `F_SUPPORTED ? 23 : 10) +// `define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) +// `define BIAS (`Q_SUPPORTED ? 16383 : `D_SUPPORTED ? 1023 : `F_SUPPORTED ? 127 : 15) +// `define XLEN 64 +// `define IEEE754 1 +`define Q_SUPPORTED 1 +// `define D_SUPPORTED 0 +// `define F_SUPPORTED 0 +`define H_SUPPORTED 0 +`define FPSIZES ((`Q_SUPPORTED&`D_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) ? 4 : (`Q_SUPPORTED&`D_SUPPORTED&`F_SUPPORTED) | (`Q_SUPPORTED&`D_SUPPORTED&`H_SUPPORTED) | (`Q_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) | (`D_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) ? 3 : (`Q_SUPPORTED&`D_SUPPORTED) | (`Q_SUPPORTED&`F_SUPPORTED) | (`Q_SUPPORTED&`H_SUPPORTED) | (`D_SUPPORTED&`F_SUPPORTED) | (`D_SUPPORTED&`H_SUPPORTED) | (`F_SUPPORTED&`H_SUPPORTED) ? 2 : 1) +`define LEN1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 64 : (`F_SUPPORTED & (`FLEN !== 32)) ? 32 : 16) +`define NE1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 11 : (`F_SUPPORTED & (`FLEN !== 32)) ? 8 : 5) +`define NF1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 52 : (`F_SUPPORTED & (`FLEN !== 32)) ? 23 : 10) +`define FMT1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 1 : (`F_SUPPORTED & (`FLEN !== 32)) ? 0 : 2) +`define BIAS1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 1023 : (`F_SUPPORTED & (`FLEN !== 32)) ? 127 : 15) +`define LEN2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 32 : 16) +`define NE2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 8 : 5) +`define NF2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 23 : 10) +`define FMT2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 0 : 2) +`define BIAS2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 127 : 15) +`define LEN3 16 +`define NE3 5//make constants for the constants ie 11/8/5 ect +`define NF3 10 // always support less hten max - maybe halfs +`define FMT3 2 +`define BIAS3 15 module testbench3(); logic [31:0] errors=0; @@ -15,33 +38,17 @@ module testbench3(); logic [`FLEN-1:0] ans; logic [7:0] flags; logic [2:0] FrmE; - logic FmtE; + logic [`FPSIZES/3:0] FmtE; logic [`FLEN-1:0] FMAResM; logic [4:0] FMAFlgM; -integer fp; logic [2:0] FOpCtrlE; logic [2*`NF+1:0] ProdManE; logic [3*`NF+5:0] AlignedAddendE; logic [`NE+1:0] ProdExpE; logic AddendStickyE; logic KillProdE; -// logic XZeroE; -// logic YZeroE; -// logic ZZeroE; -// logic XDenormE; -// logic YDenormE; -// logic ZDenormE; -// logic XInfE; -// logic YInfE; -// logic ZInfE; -// logic XNaNE; -// logic YNaNE; -// logic ZNaNE; logic wnan; -// logic XNaNE; -// logic YNaNE; -// logic ZNaNE; logic ansnan, clk; @@ -52,88 +59,86 @@ assign FOpCtrlE = 3'b0; // down - 010 // up - 011 // nearest max mag - 100 -assign FrmE = 3'b000; -assign FmtE = 1'b1; +assign FrmE = 3'b010; +assign FmtE = (`FPSIZES/3+1)'(1); logic [`FLEN-1:0] X, Y, Z; // logic FmtE; // logic [2:0] FOpCtrlE; logic XSgnE, YSgnE, ZSgnE; logic [`NE-1:0] XExpE, YExpE, ZExpE; - logic [`NF-1:0] XFracE, YFracE, ZFracE; - logic XAssumed1E, YAssumed1E, ZAssumed1E; + logic [`NF:0] XManE, YManE, ZManE; logic XNormE; + logic XExpMaxE; logic XNaNE, YNaNE, ZNaNE; logic XSNaNE, YSNaNE, ZSNaNE; logic XDenormE, YDenormE, ZDenormE; logic XZeroE, YZeroE, ZZeroE; logic [`NE-1:0] BiasE; logic XInfE, YInfE, ZInfE; - logic XExpMaxE; - //***rename to make significand = 1.frac m = significand - logic XFracZero, YFracZero, ZFracZero; // input fraction zero - logic XExpZero, YExpZero, ZExpZero; // input exponent zero logic [`FLEN-1:0] Addend; // value to add (Z or zero) - logic YExpMaxE, ZExpMaxE; // input exponent all 1s + logic YExpMaxE, ZExpMaxE, Mult; // input exponent all 1s - assign Addend = FOpCtrlE[2] ? (`FLEN)'(0) : Z; // Z is only used in the FMA, and is set to Zero if a multiply opperation - assign XSgnE = FmtE ? X[`FLEN-1] : X[31]; - assign YSgnE = FmtE ? Y[`FLEN-1] : Y[31]; - assign ZSgnE = FmtE ? Addend[`FLEN-1] : Addend[31]; + assign Mult = 1'b0; + unpacking unpacking(.*); - assign XExpE = FmtE ? X[62:52] : {X[30], {3{~X[30]&~XExpZero|XExpMaxE}}, X[29:23]}; - assign YExpE = FmtE ? Y[62:52] : {Y[30], {3{~Y[30]&~YExpZero|YExpMaxE}}, Y[29:23]}; - assign ZExpE = FmtE ? Addend[62:52] : {Addend[30], {3{~Addend[30]&~ZExpZero|ZExpMaxE}}, Addend[29:23]}; +// assign wnan = XNaNE|YNaNE|ZNaNE; +// assign ansnan = FmtE ? &ans[`FLEN-2:`NF] && |ans[`NF-1:0] : &ans[30:23] && |ans[22:0]; + + if (`FPSIZES === 1) begin + assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); + assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); + end else if (`FPSIZES === 2) begin + assign ansnan = FmtE ? &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]) : &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); + assign wnan = FmtE ? &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]) : &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); + end else if (`FPSIZES === 3) begin + always_comb begin + case (FmtE) + `FMT: begin + assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); + assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); - assign XFracE = FmtE ? X[`NF-1:0] : {X[22:0], 29'b0}; - assign YFracE = FmtE ? Y[`NF-1:0] : {Y[22:0], 29'b0}; - assign ZFracE = FmtE ? Addend[`NF-1:0] : {Addend[22:0], 29'b0}; + end + `FMT1: begin + assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); + assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); - assign XAssumed1E = FmtE ? |X[62:52] : |X[30:23]; - assign YAssumed1E = FmtE ? |Y[62:52] : |Y[30:23]; - assign ZAssumed1E = FmtE ? |Z[62:52] : |Z[30:23]; + end + `FMT2: begin + assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]); + assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); + end + default: begin + assign ansnan = 0; + assign wnan = 0; + end + endcase + end - assign XExpZero = ~XAssumed1E; - assign YExpZero = ~YAssumed1E; - assign ZExpZero = ~ZAssumed1E; - - assign XFracZero = ~|XFracE; - assign YFracZero = ~|YFracE; - assign ZFracZero = ~|ZFracE; + end else begin + always_comb begin + case (FmtE) + `FMT: begin + assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); + assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); - assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23]; - assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23]; - assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23]; - - assign XNormE = ~(XExpMaxE|XExpZero); - - assign XNaNE = XExpMaxE & ~XFracZero; - assign YNaNE = YExpMaxE & ~YFracZero; - assign ZNaNE = ZExpMaxE & ~ZFracZero; + end + `FMT1: begin + assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); + assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); - assign XSNaNE = XNaNE&~XFracE[`NF-1]; - assign YSNaNE = YNaNE&~YFracE[`NF-1]; - assign ZSNaNE = ZNaNE&~ZFracE[`NF-1]; - - assign XDenormE = XExpZero & ~XFracZero; - assign YDenormE = YExpZero & ~YFracZero; - assign ZDenormE = ZExpZero & ~ZFracZero; - - assign XInfE = XExpMaxE & XFracZero; - assign YInfE = YExpMaxE & YFracZero; - assign ZInfE = ZExpMaxE & ZFracZero; - - assign XZeroE = XExpZero & XFracZero; - assign YZeroE = YExpZero & YFracZero; - assign ZZeroE = ZExpZero & ZFracZero; - - assign BiasE = 13'h3ff; - -assign wnan = FmtE ? &FMAResM[`FLEN-2:`NF] & |FMAResM[`NF-1:0] : &FMAResM[30:23] & |FMAResM[22:0]; -// assign XNaNE = FmtE ? &X[62:52] & |X[51:0] : &X[62:55] & |X[54:32]; -// assign YNaNE = FmtE ? &Y[62:52] & |Y[51:0] : &Y[62:55] & |Y[54:32]; -// assign ZNaNE = FmtE ? &Z[62:52] & |Z[51:0] : &Z[62:55] & |Z[54:32]; -assign ansnan = FmtE ? &ans[`FLEN-2:`NF] & |ans[`NF-1:0] : &ans[30:23] & |ans[22:0]; + end + `FMT2: begin + assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]); + assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); + end + `FMT3: begin + assign ansnan = &ans[`LEN3-2:`NF3]&(|ans[`NF3-1:0]); + assign wnan = &FMAResM[`LEN3-2:`NF3]&(|FMAResM[`NF3-1:0]); + end + endcase + end + end // instantiate device under test logic [3*`NF+5:0] SumE, SumM; @@ -141,16 +146,16 @@ assign ansnan = FmtE ? &ans[`FLEN-2:`NF] & |ans[`NF-1:0] : &ans[30:23] & |ans[22 logic NegSumE, NegSumM; logic ZSgnEffE, ZSgnEffM; logic PSgnE, PSgnM; - logic [8:0] NormCntE, NormCntM; + logic [$clog2(3*`NF+7)-1:0] NormCntE, NormCntM; - fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE({XAssumed1E,XFracE}), .YManE({YAssumed1E,YFracE}), .ZManE({ZAssumed1E,ZFracE}), + fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, .ProdExpE, .AddendStickyE, .KillProdE); -fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM({XAssumed1E,XFracE}), .YManM({YAssumed1E,YFracE}), .ZManM({ZAssumed1E,ZFracE}), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE), +fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM(XManE), .YManM(YManE), .ZManM(ZManE), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE), // .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM, .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), - .FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM); + .FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM, .Mult); // produce clock @@ -168,61 +173,156 @@ fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZEx always @(posedge clk) begin #1; - if (FmtE==1'b1) {X, Y, Z, ans, flags} = testvectors[vectornum]; - else begin X = {{32{1'b1}}, testvectors[vectornum][135:104]}; - Y = {{32{1'b1}}, testvectors[vectornum][103:72]}; - Z = {{32{1'b1}}, testvectors[vectornum][71:40]}; - ans = {{32{1'b1}}, testvectors[vectornum][39:8]}; - flags = testvectors[vectornum][7:0]; + if (`FPSIZES === 3 | `FPSIZES === 4) begin + if (FmtE==2'b11) {X, Y, Z, ans, flags} = testvectors[vectornum]; + else if (FmtE==2'b01) begin + X = {{`FLEN-64{1'b1}}, testvectors[vectornum][263:200]}; + Y = {{`FLEN-64{1'b1}}, testvectors[vectornum][199:136]}; + Z = {{`FLEN-64{1'b1}}, testvectors[vectornum][135:72]}; + ans = {{`FLEN-64{1'b1}}, testvectors[vectornum][71:8]}; + flags = testvectors[vectornum][7:0]; + end + else if (FmtE==2'b00) begin + X = {{`FLEN-32{1'b1}}, testvectors[vectornum][135:104]}; + Y = {{`FLEN-32{1'b1}}, testvectors[vectornum][103:72]}; + Z = {{`FLEN-32{1'b1}}, testvectors[vectornum][71:40]}; + ans = {{`FLEN-32{1'b1}}, testvectors[vectornum][39:8]}; + flags = testvectors[vectornum][7:0]; + end + else begin + X = {{`FLEN-16{1'b1}}, testvectors[vectornum][71:56]}; + Y = {{`FLEN-16{1'b1}}, testvectors[vectornum][55:40]}; + Z = {{`FLEN-16{1'b1}}, testvectors[vectornum][39:24]}; + ans = {{`FLEN-16{1'b1}}, testvectors[vectornum][23:8]}; + flags = testvectors[vectornum][7:0]; + end + end + else begin + if (FmtE==1'b1) {X, Y, Z, ans, flags} = testvectors[vectornum]; + else if (FmtE==1'b0) begin + X = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+4*(`LEN1)-1:8+3*(`LEN1)]}; + Y = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+3*(`LEN1)-1:8+2*(`LEN1)]}; + Z = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+2*(`LEN1)-1:8+(`LEN1)]}; + ans = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+(`LEN1-1):8]}; + flags = testvectors[vectornum][7:0]; + end end end // check results on falling edge of clk always @(negedge clk) begin - - if((FmtE==1'b1) & (FMAFlgM != flags[4:0] | (!wnan & (FMAResM != ans)) | (wnan & ansnan & ~((XNaNE & (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) | (YNaNE & (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]})) | (ZNaNE & (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) | (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin - // fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w"); - // if((FmtE==1'b1) & (FMAFlgM != flags[4:0] | (FMAResM != ans))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero "); - if(XDenormE) $display( "xdenorm "); - if(YDenormE) $display( "ydenorm "); - if(ZDenormE) $display( "zdenorm "); - if(FMAFlgM[4] != 0) $display( "invld "); - if(FMAFlgM[2] != 0) $display( "ovrflw "); - if(FMAFlgM[1] != 0) $display( "unflw "); - if(FMAResM[`FLEN] & FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] == 0) $display( "FMAResM=-inf "); - if(~FMAResM[`FLEN] & FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] == 0) $display( "FMAResM=+inf "); - if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] != 0 & ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); - if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] != 0 & FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); - if(ans[`FLEN] & ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] == 0) $display( "ans=-inf "); - if(~ans[`FLEN] & ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] == 0) $display( "ans=+inf "); - if(ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] != 0 & ~ans[`NF-1]) $display( "ans=sigNaN "); - if(ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] != 0 & ans[`NF-1]) $display( "ans=qutNaN "); - errors = errors + 1; - //if (errors == 10) - $stop; - end - if((FmtE==1'b0)&(FMAFlgM != flags[4:0] | (!wnan & (FMAResM != ans)) | (wnan & ansnan & ~(((XNaNE & (FMAResM[30:0] == {X[30:23],1'b1,X[21:0]})) | (YNaNE & (FMAResM[30:0] == {Y[30:23],1'b1,Y[21:0]})) | (ZNaNE & (FMAResM[30:0] == {Z[30:23],1'b1,Z[21:0]})) | (FMAResM[30:0] == ans[30:0]))) ))) begin - $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); - if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero "); - if(~(|X[30:23]) & |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) & |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) & |Z[22:0]) $display( "zdenorm "); - if(FMAFlgM[4] != 0) $display( "invld "); - if(FMAFlgM[2] != 0) $display( "ovrflw "); - if(FMAFlgM[1] != 0) $display( "unflw "); - if(FMAResM == 64'hFF80000000000000) $display( "FMAResM=-inf "); - if(FMAResM == 64'h7F80000000000000) $display( "FMAResM=+inf "); - if(&FMAResM[30:23] & |FMAResM[22:0] & ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] & |FMAResM[22:0] & FMAResM[22] ) $display( "FMAResM=qutNaN "); - if(ans == 64'hFF80000000000000) $display( "ans=-inf "); - if(ans == 64'h7F80000000000000) $display( "ans=+inf "); - if(&ans[30:23] & |ans[22:0] & ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] & |ans[22:0] & ans[22]) $display( "ans=qutNaN "); - errors = errors + 1; - if (errors == 10) - $stop; - end + if (`FPSIZES === 1 | `FPSIZES === 2) begin + if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0]))))) begin + // fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w"); + // if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (FMAResM !== ans))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(XDenormE) $display( "xdenorm "); + if(YDenormE) $display( "ydenorm "); + if(ZDenormE) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf "); + if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf "); + if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); + if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); + if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf "); + if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf "); + if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN "); + if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN "); + errors = errors + 1; + //if (errors === 10) + $stop; + end + if((FmtE==1'b0)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[`LEN1-2:0] === {X[`LEN1-2:`NF1],1'b1,X[`NF1-2:0]})) || (YNaNE && (FMAResM[`LEN1-2:0] === {Y[`LEN1-2:`NF1],1'b1,Y[`NF1-2:0]})) || (ZNaNE && (FMAResM[`LEN1-2:0] === {Z[`LEN1-2:`NF1],1'b1,Z[`NF1-2:0]})) || (FMAResM[`LEN1-2:0] === ans[`LEN1-2:0]))) ))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + errors = errors + 1; + // if (errors === 9) + $stop; + end + end else begin + + if((FmtE==2'b11) & (FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0]))))) begin + // fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w"); + // if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (FMAResM !== ans))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(XDenormE) $display( "xdenorm "); + if(YDenormE) $display( "ydenorm "); + if(ZDenormE) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf "); + if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf "); + if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); + if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); + if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf "); + if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf "); + if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN "); + if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN "); + errors = errors + 1; + //if (errors === 10) + $stop; + end + if((FmtE==1'b01)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[64-2:0] === {X[64-2:52],1'b1,X[52-2:0]})) || (YNaNE && (FMAResM[64-2:0] === {Y[64-2:52],1'b1,Y[52-2:0]})) || (ZNaNE && (FMAResM[64-2:0] === {Z[64-2:52],1'b1,Z[52-2:0]})) || (FMAResM[62:0] === ans[62:0]))) ))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + errors = errors + 1; + // if (errors === 9) + $stop; + end + if((FmtE==2'b00)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[32-2:0] === {X[32-2:23],1'b1,X[23-2:0]})) || (YNaNE && (FMAResM[32-2:0] === {Y[32-2:23],1'b1,Y[23-2:0]})) || (ZNaNE && (FMAResM[32-2:0] === {Z[32-2:23],1'b1,Z[23-2:0]})) || (FMAResM[30:0] === ans[30:0]))) ))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + errors = errors + 1; + // if (errors === 9) + $stop; + end + if((FmtE==2'b10)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[16-2:0] === {X[16-2:10],1'b1,X[10-2:0]})) || (YNaNE && (FMAResM[16-2:0] === {Y[16-2:10],1'b1,Y[10-2:0]})) || (ZNaNE && (FMAResM[16-2:0] === {Z[16-2:10],1'b1,Z[10-2:0]})) || (FMAResM[14:0] === ans[14:0]))) ))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + errors = errors + 1; + // if (errors === 9) + $stop; + end + end + vectornum = vectornum + 1; if (testvectors[vectornum] === 194'bx) begin $display("%d tests completed with %d errors", vectornum, errors); diff --git a/pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh b/pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh index 0741e9d6d..8620f3b03 100755 --- a/pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh +++ b/pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh @@ -1,3 +1,3 @@ -testfloat_gen f64_mulAdd -tininessafter -n 6133248 -rnear_even -seed 113355 -level 1 > testFloat +testfloat_gen f128_mulAdd -tininessafter -n 6133248 -rmin -seed 113355 -level 1 > testFloat tr -d ' ' < testFloat > testFloatNoSpace diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 3b058772c..1fbcae5e2 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -42,6 +42,7 @@ module fcmp ( // - if negitive - no // - if positive - yes // note: LT does -0 < 0 + //*** compare Exp and Man together assign LT = XSgnE^YSgnE ? XSgnE : XExpE==YExpE ? ((XManE> AlignCnt; AddendStickyE = |(ZManShifted[`NF-1:0]); @@ -356,7 +378,7 @@ endmodule module loa( //https://ieeexplore.ieee.org/abstract/document/930098 input logic [3*`NF+6:0] A, // addend input logic [2*`NF+1:0] P, // product - output logic [8:0] NormCntE // normalization shift count for the positive result + output logic [$clog2(3*`NF+7)-1:0] NormCntE // normalization shift count for the positive result ); logic [3*`NF+6:0] T; @@ -389,14 +411,14 @@ module loa( //https://ieeexplore.ieee.org/abstract/document/930098 endmodule module lzc( - input logic [3*`NF+6:0] f, - output logic [8:0] NormCntE // normalization shift + input logic [3*`NF+6:0] f, + output logic [$clog2(3*`NF+7)-1:0] NormCntE // normalization shift ); - logic [8:0] i; + logic [$clog2(3*`NF+7)-1:0] i; always_comb begin i = 0; - while (~f[3*`NF+6-i] & $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one + while (~f[3*`NF+6-i] & $unsigned(i) <= $unsigned($clog2(3*`NF+7)'(3)*($clog2(3*`NF+7))'(`NF)+($clog2(3*`NF+7))'(6))) i = i+1; // search for leading one NormCntE = i; end endmodule @@ -410,27 +432,27 @@ endmodule module fma2( - input logic XSgnM, YSgnM, // input signs - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents - input logic [`NF:0] XManM, YManM, ZManM, // input mantissas - input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic FmtM, // precision 1 = double 0 = single - input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias - input logic AddendStickyM, // sticky bit that is calculated during alignment - input logic KillProdM, // set the product to zero before addition if the product is too small to matter - input logic XZeroM, YZeroM, ZZeroM, // inputs are zero - input logic XInfM, YInfM, ZInfM, // inputs are infinity - input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN - input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs - input logic [3*`NF+5:0] SumM, // the positive sum - input logic NegSumM, // was the sum negitive - input logic InvZM, // do you invert Z - input logic ZSgnEffM, // the modified Z sign - depends on instruction - input logic PSgnM, // the product's sign - input logic Mult, // multiply opperation - input logic [8:0] NormCntM, // the normalization shift count - output logic [`FLEN-1:0] FMAResM, // FMA final result - output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact} + input logic XSgnM, YSgnM, // input signs + input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents + input logic [`NF:0] XManM, YManM, ZManM, // input mantissas + input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude + input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single + input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias + input logic AddendStickyM, // sticky bit that is calculated during alignment + input logic KillProdM, // set the product to zero before addition if the product is too small to matter + input logic XZeroM, YZeroM, ZZeroM, // inputs are zero + input logic XInfM, YInfM, ZInfM, // inputs are infinity + input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN + input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs + input logic [3*`NF+5:0] SumM, // the positive sum + input logic NegSumM, // was the sum negitive + input logic InvZM, // do you invert Z + input logic ZSgnEffM, // the modified Z sign - depends on instruction + input logic PSgnM, // the product's sign + input logic Mult, // multiply opperation + input logic [$clog2(3*`NF+7)-1:0] NormCntM, // the normalization shift count + output logic [`FLEN-1:0] FMAResM, // FMA final result + output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact} @@ -548,28 +570,27 @@ endmodule module normalize( - input logic [3*`NF+5:0] SumM, // the positive sum - input logic [`NE-1:0] ZExpM, // exponent of Z - input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias - input logic [8:0] NormCntM, // normalization shift count - input logic FmtM, // precision 1 = double 0 = single - input logic KillProdM, // is the product set to zero - input logic AddendStickyM, // the sticky bit caclulated from the aligned addend - input logic NegSumM, // was the sum negitive - output logic [`NF+2:0] NormSum, // normalized sum - output logic SumZero, // is the sum zero - output logic NormSumSticky, UfSticky, // sticky bits - output logic [`NE+1:0] SumExp, // exponent of the normalized sum - output logic ResultDenorm // is the result denormalized + input logic [3*`NF+5:0] SumM, // the positive sum + input logic [`NE-1:0] ZExpM, // exponent of Z + input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias + input logic [$clog2(3*`NF+7)-1:0] NormCntM, // normalization shift count + input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single + input logic KillProdM, // is the product set to zero + input logic AddendStickyM, // the sticky bit caclulated from the aligned addend + input logic NegSumM, // was the sum negitive + output logic [`NF+2:0] NormSum, // normalized sum + output logic SumZero, // is the sum zero + output logic NormSumSticky, UfSticky, // sticky bits + output logic [`NE+1:0] SumExp, // exponent of the normalized sum + output logic ResultDenorm // is the result denormalized ); - logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results - logic [8:0] DenormShift; // right shift if the result is denormalized //***change this later - logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction - logic [3*`NF+8:0] SumShifted; // the shifted sum before LZA correction - logic [`NE+1:0] SumExpTmpTmp; // the exponent of the normalized sum with the `FLEN bias - logic PreResultDenorm; // is the result denormalized - calculated before LZA corection - logic PreResultDenorm2; // is the result denormalized - calculated before LZA corection - logic LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction + logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results + logic [$clog2(3*`NF+7)-1:0] DenormShift; // right shift if the result is denormalized //***change this later + logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction + logic [3*`NF+8:0] SumShifted; // the shifted sum before LZA correction + logic [`NE+1:0] SumExpTmpTmp; // the exponent of the normalized sum with the `FLEN bias + logic PreResultDenorm; // is the result denormalized - calculated before LZA corection + logic LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction /////////////////////////////////////////////////////////////////////////////// // Normalization @@ -580,14 +601,89 @@ module normalize( // calculate the sum's exponent assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); - assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; + + //convert the sum's exponent into the propper percision + if (`FPSIZES == 1) begin + assign SumExpTmp = SumExpTmpTmp; + + end else if (`FPSIZES == 2) begin + assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS1))&{`NE+2{|SumExpTmpTmp}}; + + end else if (`FPSIZES == 3) begin + always_comb begin + case (FmtM) + `FMT: assign SumExpTmp = SumExpTmpTmp; + `FMT1: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS1)&{`NE+2{|SumExpTmpTmp}}; + `FMT2: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS2)&{`NE+2{|SumExpTmpTmp}}; + default: assign SumExpTmp = `NE+2'bx; + endcase + end + + end else begin + always_comb begin + case (FmtM) + 2'h3: assign SumExpTmp = SumExpTmpTmp; + 2'h1: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`D_BIAS)&{`NE+2{|SumExpTmpTmp}}; + 2'h0: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`S_BIAS)&{`NE+2{|SumExpTmpTmp}}; + 2'h2: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`H_BIAS)&{`NE+2{|SumExpTmpTmp}}; + endcase + end + + end - logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL; - assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; - assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd2))); - assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127); - assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd25+13'd1023-13'd127)) | ~|SumExpTmpTmp; - assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; + // determine if the result is denormalized + + if (`FPSIZES == 1) begin + logic Sum0LEZ, Sum0GEFL; + assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; + assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF)-(`NE+2)'(2)); + assign PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; + + end else if (`FPSIZES == 2) begin + logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL; + assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; + assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF)-(`NE+2)'(2)); + assign Sum1LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)); + assign Sum1GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF1+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)) | ~|SumExpTmpTmp; + assign PreResultDenorm = (FmtM ? Sum0LEZ : Sum1LEZ) & (FmtM ? Sum0GEFL : Sum1GEFL) & ~SumZero; + + end else if (`FPSIZES == 3) begin + logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL; + assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; + assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF)-(`NE+2)'(2)); + assign Sum1LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)); + assign Sum1GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF1+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)) | ~|SumExpTmpTmp; + assign Sum2LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`BIAS2)); + assign Sum2GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF2+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`BIAS2)) | ~|SumExpTmpTmp; + always_comb begin + case (FmtM) + `FMT: assign PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; + `FMT1: assign PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; + `FMT2: assign PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; + default: assign PreResultDenorm = 1'bx; + endcase + end + + end else begin + logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL; + assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; + assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF )-(`NE+2)'(2)); + assign Sum1LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`D_BIAS)); + assign Sum1GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`D_NF+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`D_BIAS)) | ~|SumExpTmpTmp; + assign Sum2LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`S_BIAS)); + assign Sum2GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`S_NF+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`S_BIAS)) | ~|SumExpTmpTmp; + assign Sum3LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`H_BIAS)); + assign Sum3GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`H_NF+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`H_BIAS)) | ~|SumExpTmpTmp; + always_comb begin + case (FmtM) + 2'h3: assign PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; + 2'h1: assign PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; + 2'h0: assign PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; + 2'h2: assign PreResultDenorm = Sum3LEZ & Sum3GEFL & ~SumZero; + endcase + end + + end // 010. when should be 001. // - shift left one @@ -599,45 +695,66 @@ module normalize( // Determine the shift needed for denormal results // - if not denorm add 1 to shift out the leading 1 - assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; + assign DenormShift = PreResultDenorm ? SumExpTmp[$clog2(3*`NF+7)-1:0] : 1; // Normalize the sum assign SumShifted = {3'b0, SumM} << NormCntM+DenormShift; // LZA correction assign LZAPlus1 = SumShifted[3*`NF+7]; assign LZAPlus2 = SumShifted[3*`NF+8]; // the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone - assign CorrSumShifted = LZAPlus1&~KillProdM ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0]; + assign CorrSumShifted = LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0]; assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3]; + // Calculate the sticky bit - assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | (|CorrSumShifted[136:2*`NF+3]&~FmtM); + if (`FPSIZES == 1) begin + assign NormSumSticky = |CorrSumShifted[2*`NF+2:0]; + + end else if (`FPSIZES == 2) begin + // 3*NF+5 - NF1 - 3 + assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | + (|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&~FmtM); + + end else if (`FPSIZES == 3) begin + assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | + (|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&((FmtM==`FMT1)|(FmtM==`FMT2))) | + (|CorrSumShifted[3*`NF+2-`NF2:3*`NF+3-`NF1]&(FmtM==`FMT2)); + + end else begin + assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | + (|CorrSumShifted[3*`NF+2-`D_NF:2*`NF+3]&((FmtM==1)|(FmtM==0)|(FmtM==2))) | + (|CorrSumShifted[3*`NF+2-`S_NF:3*`NF+3-`D_NF]&((FmtM==0)|(FmtM==2))) | + (|CorrSumShifted[3*`NF+2-`H_NF:3*`NF+3-`S_NF]&(FmtM==2)); + + end + assign UfSticky = AddendStickyM | NormSumSticky; // Determine sum's exponent // if plus1 If plus2 if said denorm but norm plus 1 if said denorm but norm plus 2 - assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~ResultDenorm&PreResultDenorm2&~KillProdM}+{12'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}}; + assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~ResultDenorm&PreResultDenorm&~KillProdM}+{12'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}}; // recalculate if the result is denormalized - assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7]; + assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7]; endmodule module fmaround( - input logic FmtM, // precision 1 = double 0 = single - input logic [2:0] FrmM, // rounding mode - input logic UfSticky, // sticky bit for underlow calculation - input logic [`NF+2:0] NormSum, // normalized sum - input logic AddendStickyM, // addend's sticky bit - input logic NormSumSticky, // normalized sum's sticky bit - input logic ZZeroM, // is Z zero - input logic InvZM, // invert Z - input logic [`NE+1:0] SumExp, // exponent of the normalized sum - input logic ResultSgnTmp, // the result's sign - output logic CalcPlus1, UfPlus1, // do you add or subtract on from the result - output logic [`NE+1:0] FullResultExp, // ResultExp with bits to determine sign and overflow - output logic [`NF-1:0] ResultFrac, // Result fraction - output logic [`NE-1:0] ResultExp, // Result exponent - output logic Sticky, // sticky bit - output logic [`FLEN:0] RoundAdd, // how much to add to the result - output logic Round, Guard, UfLSBNormSum // bits needed to calculate rounding + input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single + input logic [2:0] FrmM, // rounding mode + input logic UfSticky, // sticky bit for underlow calculation + input logic [`NF+2:0] NormSum, // normalized sum + input logic AddendStickyM, // addend's sticky bit + input logic NormSumSticky, // normalized sum's sticky bit + input logic ZZeroM, // is Z zero + input logic InvZM, // invert Z + input logic [`NE+1:0] SumExp, // exponent of the normalized sum + input logic ResultSgnTmp, // the result's sign + output logic CalcPlus1, UfPlus1, // do you add or subtract on from the result + output logic [`NE+1:0] FullResultExp, // ResultExp with bits to determine sign and overflow + output logic [`NF-1:0] ResultFrac, // Result fraction + output logic [`NE-1:0] ResultExp, // Result exponent + output logic Sticky, // sticky bit + output logic [`FLEN:0] RoundAdd, // how much to add to the result + output logic Round, Guard, UfLSBNormSum // bits needed to calculate rounding ); logic LSBNormSum; // bit used for rounding - least significant bit of the normalized sum logic SubBySmallNum, UfSubBySmallNum; // was there supposed to be a subtraction by a small number @@ -676,18 +793,146 @@ module fmaround( // 101 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number) // 110/111 - Plus1 - // determine guard, round, and least significant bit of the result - assign Guard = FmtM ? NormSum[2] : NormSum[31]; - assign Round = FmtM ? NormSum[1] : NormSum[30]; - assign LSBNormSum = FmtM ? NormSum[3] : NormSum[32]; + if (`FPSIZES == 1) begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[2]; + assign Round = NormSum[1]; + assign LSBNormSum = NormSum[3]; + + // used to determine underflow flag + assign UfGuard = NormSum[1]; + assign UfRound = NormSum[0]; + assign UfLSBNormSum = NormSum[2]; + + // determine sticky + assign Sticky = UfSticky | NormSum[0]; + + end else if (`FPSIZES == 2) begin + // \/-------------NF---------------, + // | NF1 | 3 | | + // '-------NF1------^ + + // determine guard, round, and least significant bit of the result + assign Guard = FmtM ? NormSum[2] : NormSum[`NF-`NF1+2]; + assign Round = FmtM ? NormSum[1] : NormSum[`NF-`NF1+1]; + assign LSBNormSum = FmtM ? NormSum[3] : NormSum[`NF-`NF1+3]; + + // used to determine underflow flag + assign UfGuard = FmtM ? NormSum[1] : NormSum[`NF-`NF1+1]; + assign UfRound = FmtM ? NormSum[0] : NormSum[`NF-`NF1]; + assign UfLSBNormSum = FmtM ? NormSum[2] : NormSum[`NF-`NF1+2]; + + // determine sticky + assign Sticky = UfSticky | (FmtM ? NormSum[0] : NormSum[`NF-`NF1]); + + end else if (`FPSIZES == 3) begin + always_comb begin + case (FmtM) + `FMT: begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[2]; + assign Round = NormSum[1]; + assign LSBNormSum = NormSum[3]; + // used to determine underflow flag + assign UfGuard = NormSum[1]; + assign UfRound = NormSum[0]; + assign UfLSBNormSum = NormSum[2]; + // determine sticky + assign Sticky = UfSticky | NormSum[0]; + end + `FMT1: begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[`NF-`NF1+2]; + assign Round = NormSum[`NF-`NF1+1]; + assign LSBNormSum = NormSum[`NF-`NF1+3]; + // used to determine underflow flag + assign UfGuard = NormSum[`NF-`NF1+1]; + assign UfRound = NormSum[`NF-`NF1]; + assign UfLSBNormSum = NormSum[`NF-`NF1+2]; + // determine sticky + assign Sticky = UfSticky | NormSum[`NF-`NF1]; + end + `FMT2: begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[`NF-`NF2+2]; + assign Round = NormSum[`NF-`NF2+1]; + assign LSBNormSum = NormSum[`NF-`NF2+3]; + // used to determine underflow flag + assign UfGuard = NormSum[`NF-`NF2+1]; + assign UfRound = NormSum[`NF-`NF2]; + assign UfLSBNormSum = NormSum[`NF-`NF2+2]; + // determine sticky + assign Sticky = UfSticky | NormSum[`NF-`NF2]; + end + default: begin + assign Guard = 1'bx; + assign Round = 1'bx; + assign LSBNormSum = 1'bx; + assign UfGuard = 1'bx; + assign UfRound = 1'bx; + assign UfLSBNormSum = 1'bx; + assign Sticky = 1'bx; + end + endcase + end + + end else begin + always_comb begin + case (FmtM) + 2'h3: begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[2]; + assign Round = NormSum[1]; + assign LSBNormSum = NormSum[3]; + // used to determine underflow flag + assign UfGuard = NormSum[1]; + assign UfRound = NormSum[0]; + assign UfLSBNormSum = NormSum[2]; + // determine sticky + assign Sticky = UfSticky | NormSum[0]; + end + 2'h1: begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[`NF-`D_NF+2]; + assign Round = NormSum[`NF-`D_NF+1]; + assign LSBNormSum = NormSum[`NF-`D_NF+3]; + // used to determine underflow flag + assign UfGuard = NormSum[`NF-`D_NF+1]; + assign UfRound = NormSum[`NF-`D_NF]; + assign UfLSBNormSum = NormSum[`NF-`D_NF+2]; + // determine sticky + assign Sticky = UfSticky | NormSum[`NF-`D_NF]; + end + 2'h0: begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[`NF-`S_NF+2]; + assign Round = NormSum[`NF-`S_NF+1]; + assign LSBNormSum = NormSum[`NF-`S_NF+3]; + // used to determine underflow flag + assign UfGuard = NormSum[`NF-`S_NF+1]; + assign UfRound = NormSum[`NF-`S_NF]; + assign UfLSBNormSum = NormSum[`NF-`S_NF+2]; + // determine sticky + assign Sticky = UfSticky | NormSum[`NF-`S_NF]; + end + 2'h2: begin + // determine guard, round, and least significant bit of the result + assign Guard = NormSum[`NF-`H_NF+2]; + assign Round = NormSum[`NF-`H_NF+1]; + assign LSBNormSum = NormSum[`NF-`H_NF+3]; + // used to determine underflow flag + assign UfGuard = NormSum[`NF-`H_NF+1]; + assign UfRound = NormSum[`NF-`H_NF]; + assign UfLSBNormSum = NormSum[`NF-`H_NF+2]; + // determine sticky + assign Sticky = UfSticky | NormSum[`NF-`H_NF]; + end + endcase + end + + end - // used to determine underflow flag - assign UfGuard = FmtM ? NormSum[1] : NormSum[30]; - assign UfRound = FmtM ? NormSum[0] : NormSum[29]; - assign UfLSBNormSum = FmtM ? NormSum[2] : NormSum[31]; - // determine sticky - assign Sticky = UfSticky | NormSum[0]; // Deterimine if a small number was supposed to be subtrated assign SubBySmallNum = AddendStickyM & InvZM & ~(NormSumSticky|UfRound) & ~ZZeroM; //***here assign UfSubBySmallNum = AddendStickyM & InvZM & ~(NormSumSticky) & ~ZZeroM; //***here @@ -729,10 +974,40 @@ module fmaround( assign Minus1 = CalcMinus1 & (Sticky | Guard | Round); // Compute rounded result - assign RoundAdd = FmtM ? Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1} : - Minus1 ? {{36{1'b1}}, 29'b0} : {35'b0, Plus1, 29'b0}; - assign NormSumTruncated = {NormSum[`NF+2:32], NormSum[31:3]&{29{FmtM}}}; + if (`FPSIZES == 1) begin + assign RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{`FLEN{1'b0}}, Plus1}; + end else if (`FPSIZES == 2) begin + // \/FLEN+1 + // | NE+2 | NF | + // '-NE+2-^----NF1----^ + // `FLEN+1-`NE-2-`NF1 = FLEN-1-NE-NF1 + assign RoundAdd = FmtM ? Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1} : + Minus1 ? {{`NE+2+`NF1{1'b1}}, (`FLEN-1-`NE-`NF1)'(0)} : {(`NE+1+`NF1)'(0), Plus1, (`FLEN-1-`NE-`NF1)'(0)}; + + end else if (`FPSIZES == 3) begin + always_comb begin + case (FmtM) + `FMT: assign RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; + `FMT1: assign RoundAdd = Minus1 ? {{`NE+2+`NF1{1'b1}}, (`FLEN-1-`NE-`NF1)'(0)} : {(`NE+1+`NF1)'(0), Plus1, (`FLEN-1-`NE-`NF1)'(0)}; + `FMT2: assign RoundAdd = Minus1 ? {{`NE+2+`NF2{1'b1}}, (`FLEN-1-`NE-`NF2)'(0)} : {(`NE+1+`NF2)'(0), Plus1, (`FLEN-1-`NE-`NF2)'(0)}; + default: assign RoundAdd = (`FLEN+1)'(0); + endcase + end + + end else begin + always_comb begin + case (FmtM) + 2'h3: assign RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; + 2'h1: assign RoundAdd = Minus1 ? {{`NE+2+`D_NF{1'b1}}, (`FLEN-1-`NE-`D_NF)'(0)} : {(`NE+1+`D_NF)'(0), Plus1, (`FLEN-1-`NE-`D_NF)'(0)}; + 2'h0: assign RoundAdd = Minus1 ? {{`NE+2+`S_NF{1'b1}}, (`FLEN-1-`NE-`S_NF)'(0)} : {(`NE+1+`S_NF)'(0), Plus1, (`FLEN-1-`NE-`S_NF)'(0)}; + 2'h2: assign RoundAdd = Minus1 ? {{`NE+2+`H_NF{1'b1}}, (`FLEN-1-`NE-`H_NF)'(0)} : {(`NE+1+`H_NF)'(0), Plus1, (`FLEN-1-`NE-`H_NF)'(0)}; + endcase + end + + end + + assign NormSumTruncated = NormSum[`NF+2:3]; assign {FullResultExp, ResultFrac} = {SumExp, NormSumTruncated} + RoundAdd; assign ResultExp = FullResultExp[`NE-1:0]; @@ -748,7 +1023,7 @@ module fmaflags( input logic [`NE+1:0] SumExp, // exponent of the normalized sum input logic ZSgnEffM, PSgnM, // the product and modified Z signs input logic Round, Guard, UfLSBNormSum, Sticky, UfPlus1, // bits used to determine rounding - input logic FmtM, // precision 1 = double 0 = single + input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single output logic Invalid, Overflow, Underflow, // flags used to select the result output logic [4:0] FMAFlgM // FMA flags ); @@ -771,8 +1046,34 @@ module fmaflags( assign Invalid = SigNaN | ((XInfM | YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM); // Set Overflow flag if the number is too big to be represented - // - Don't set the overflow flag if an overflowed result isn't outputed - assign GtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[7:0] | FullResultExp[8]; + // - Don't set the overflow flag if an overflowed result isn't outputed + if (`FPSIZES == 1) begin + assign GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; + + end else if (`FPSIZES == 2) begin + assign GtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[`NE1-1:0] | FullResultExp[`NE1]; + + end else if (`FPSIZES == 3) begin + always_comb begin + case (FmtM) + `FMT: assign GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; + `FMT1: assign GtMaxExp = &FullResultExp[`NE1-1:0] | FullResultExp[`NE1]; + `FMT2: assign GtMaxExp = &FullResultExp[`NE2-1:0] | FullResultExp[`NE2]; + default: assign GtMaxExp = 1'bx; + endcase + end + + end else begin + always_comb begin + case (FmtM) + 2'h3: assign GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; + 2'h1: assign GtMaxExp = &FullResultExp[`D_NE-1:0] | FullResultExp[`D_NE]; + 2'h0: assign GtMaxExp = &FullResultExp[`S_NE-1:0] | FullResultExp[`S_NE]; + 2'h2: assign GtMaxExp = &FullResultExp[`H_NE-1:0] | FullResultExp[`H_NE]; + endcase + end + + end assign Overflow = GtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); // Set Underflow flag if the number is too small to be represented in normal numbers @@ -793,57 +1094,227 @@ endmodule module resultselect( - input logic XSgnM, YSgnM, // input signs - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents - input logic [`NF:0] XManM, YManM, ZManM, // input mantissas - input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic FmtM, // precision 1 = double 0 = single - input logic AddendStickyM, // sticky bit that is calculated during alignment - input logic KillProdM, // set the product to zero before addition if the product is too small to matter - input logic XInfM, YInfM, ZInfM, // inputs are infinity - input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN - input logic ZSgnEffM, // the modified Z sign - depends on instruction - input logic PSgnM, // the product's sign - input logic ResultSgn, // the result's sign - input logic CalcPlus1, // rounding bits - input logic [`FLEN:0] RoundAdd, // how much to add to the result - input logic Invalid, Overflow, Underflow, // flags - input logic ResultDenorm, // is the result denormalized - input logic [`NE-1:0] ResultExp, // Result exponent - input logic [`NF-1:0] ResultFrac, // Result fraction - output logic [`FLEN-1:0] FMAResM // FMA final result + input logic XSgnM, YSgnM, // input signs + input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents + input logic [`NF:0] XManM, YManM, ZManM, // input mantissas + input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude + input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single + input logic AddendStickyM, // sticky bit that is calculated during alignment + input logic KillProdM, // set the product to zero before addition if the product is too small to matter + input logic XInfM, YInfM, ZInfM, // inputs are infinity + input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN + input logic ZSgnEffM, // the modified Z sign - depends on instruction + input logic PSgnM, // the product's sign + input logic ResultSgn, // the result's sign + input logic CalcPlus1, // rounding bits + input logic [`FLEN:0] RoundAdd, // how much to add to the result + input logic Invalid, Overflow, Underflow, // flags + input logic ResultDenorm, // is the result denormalized + input logic [`NE-1:0] ResultExp, // Result exponent + input logic [`NF-1:0] ResultFrac, // Result fraction + output logic [`FLEN-1:0] FMAResM // FMA final result ); - logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results + logic InfSgn; + logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InfResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult, NormResult; // possible results + assign InfSgn = ZInfM ? ZSgnEffM : PSgnM; + if (`FPSIZES == 1) begin + if(`IEEE754) begin + assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; + assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; + assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; + assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end else begin + assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; + assign KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + assign UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; + assign InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; + assign NormResult = {ResultSgn, ResultExp, ResultFrac}; + + end else if (`FPSIZES == 2) begin //will the format conversion in killprod work in other conversions? + if(`IEEE754) begin + assign XNaNResult = FmtM ? {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; + assign YNaNResult = FmtM ? {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; + assign ZNaNResult = FmtM ? {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; + assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end else begin + assign XNaNResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end + + assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} : + ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : + {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; + assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign InfResult = FmtM ? {InfSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; + assign NormResult = FmtM ? {ResultSgn, ResultExp, ResultFrac} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; + + end else if (`FPSIZES == 3) begin + always_comb begin + case (FmtM) + `FMT: begin + if(`IEEE754) begin + assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; + assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; + assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; + assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end else begin + assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end + + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; + assign KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + assign UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; + assign InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; + assign NormResult = {ResultSgn, ResultExp, ResultFrac}; + end + `FMT1: begin + if(`IEEE754) begin + assign XNaNResult = {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; + assign YNaNResult = {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; + assign ZNaNResult = {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; + assign InvalidResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end else begin + assign XNaNResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : + {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; + assign KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + assign UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; + assign NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; + end + `FMT2: begin + if(`IEEE754) begin + assign XNaNResult = {{`FLEN-`LEN2{1'b1}}, XSgnM, {`NE2{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF2]}; + assign YNaNResult = {{`FLEN-`LEN2{1'b1}}, YSgnM, {`NE2{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF2]}; + assign ZNaNResult = {{`FLEN-`LEN2{1'b1}}, ZSgnEffM, {`NE2{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF2]}; + assign InvalidResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + end else begin + assign XNaNResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + end + + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : + {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, (`NF2)'(0)}; + assign KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; + assign UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)}; + assign NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]}; + end + default: begin + if(`IEEE754) begin + assign XNaNResult = (`FLEN)'(0); + assign YNaNResult = (`FLEN)'(0); + assign ZNaNResult = (`FLEN)'(0); + assign InvalidResult = (`FLEN)'(0); + end else begin + assign XNaNResult = (`FLEN)'(0); + end + assign OverflowResult = (`FLEN)'(0); + assign KillProdResult = (`FLEN)'(0); + assign UnderflowResult = (`FLEN)'(0); + assign InfResult = (`FLEN)'(0); + assign NormResult = (`FLEN)'(0); + end + endcase + end + + end else begin + always_comb begin + case (FmtM) + 2'h3: begin + if(`IEEE754) begin + assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; + assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; + assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; + assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end else begin + assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end + + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; + assign KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + assign UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; + assign InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; + assign NormResult = {ResultSgn, ResultExp, ResultFrac}; + end + 2'h1: begin + if(`IEEE754) begin + assign XNaNResult = {{`FLEN-`D_LEN{1'b1}}, XSgnM, {`D_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`D_NF]}; + assign YNaNResult = {{`FLEN-`D_LEN{1'b1}}, YSgnM, {`D_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`D_NF]}; + assign ZNaNResult = {{`FLEN-`D_LEN{1'b1}}, ZSgnEffM, {`D_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`D_NF]}; + assign InvalidResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + end else begin + assign XNaNResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + end + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : + {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; + assign KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:0], ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; + assign UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; + assign NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]}; + end + 2'h0: begin + if(`IEEE754) begin + assign XNaNResult = {{`FLEN-`S_LEN{1'b1}}, XSgnM, {`S_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`S_NF]}; + assign YNaNResult = {{`FLEN-`S_LEN{1'b1}}, YSgnM, {`S_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`S_NF]}; + assign ZNaNResult = {{`FLEN-`S_LEN{1'b1}}, ZSgnEffM, {`S_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`S_NF]}; + assign InvalidResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + end else begin + assign XNaNResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + end + + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : + {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; + assign KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; + assign UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; + assign NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]}; + end + 2'h2: begin + if(`IEEE754) begin + assign XNaNResult = {{`FLEN-`H_LEN{1'b1}}, XSgnM, {`H_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`H_NF]}; + assign YNaNResult = {{`FLEN-`H_LEN{1'b1}}, YSgnM, {`H_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`H_NF]}; + assign ZNaNResult = {{`FLEN-`H_LEN{1'b1}}, ZSgnEffM, {`H_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`H_NF]}; + assign InvalidResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + end else begin + assign XNaNResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + end + + assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : + {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; + + assign KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:0], ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; + assign UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; + assign NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]}; + end + endcase + end - if(`IEEE754) begin - assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]}; - assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]}; - assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]}; - assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0}; - end else begin - assign XNaNResult = FmtM ? {1'b0, XExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpM[7:0], 1'b1, 22'b0}; - assign YNaNResult = FmtM ? {1'b0, YExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpM[7:0], 1'b1, 22'b0}; - assign ZNaNResult = FmtM ? {1'b0, ZExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, ZExpM[7:0], 1'b1, 22'b0}; - assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, 1'b0, 8'hff, 1'b1, 22'b0}; end - - assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : - {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} : - ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} : - {{32{1'b1}}, ResultSgn, 8'hff, 23'b0}; - assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} + (RoundAdd[59:29]&{31{AddendStickyM}})}; - assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {63'b0,(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - assign FMAResM = XNaNM ? XNaNResult : - YNaNM ? YNaNResult : - ZNaNM ? ZNaNResult : - Invalid ? InvalidResult : - XInfM ? FmtM ? {PSgnM, XExpM, XManM[`NF-1:0]} : {{32{1'b1}}, PSgnM, XExpM[7:0], XManM[51:29]} : - YInfM ? FmtM ? {PSgnM, YExpM, YManM[`NF-1:0]} : {{32{1'b1}}, PSgnM, YExpM[7:0], YManM[51:29]} : - ZInfM ? FmtM ? {ZSgnEffM, ZExpM, ZManM[`NF-1:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], ZManM[51:29]} : - KillProdM ? KillProdResult : - Overflow ? OverflowResult : - Underflow & ~ResultDenorm & (ResultExp!=1) ? UnderflowResult : - FmtM ? {ResultSgn, ResultExp, ResultFrac} : - {{32{1'b1}}, ResultSgn, ResultExp[7:0], ResultFrac[51:29]}; + if(`IEEE754) begin + assign FMAResM = XNaNM ? XNaNResult : + YNaNM ? YNaNResult : + ZNaNM ? ZNaNResult : + Invalid ? InvalidResult : + XInfM|YInfM|ZInfM ? InfResult : + KillProdM ? KillProdResult : + Overflow ? OverflowResult : + Underflow & ~ResultDenorm & (ResultExp!=1) ? UnderflowResult : + NormResult; + end else begin + assign FMAResM = XNaNM|YNaNM|ZNaNM|Invalid ? XNaNResult : + XInfM|YInfM|ZInfM ? InfResult : + KillProdM ? KillProdResult : + Overflow ? OverflowResult : + Underflow & ~ResultDenorm & (ResultExp!=1) ? UnderflowResult : + NormResult; + end endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 0dd6ea1b2..f9472c9b5 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -89,7 +89,6 @@ module fpu ( logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage - logic [10:0] BiasE; // bias based on precision (single=7f double=3ff) logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage logic XNaNQ, YNaNQ; // is the input a NaN - divide @@ -179,7 +178,7 @@ module fpu ( unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, - .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); + .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); // FMA // - two stage FMA @@ -231,7 +230,7 @@ module fpu ( .XSNaNE, .ClassResE); // Convert - fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, + fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE); // data to be stored in memory - to IEU diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv new file mode 100644 index 000000000..0db63fe91 --- /dev/null +++ b/pipelined/src/fpu/unpack.sv @@ -0,0 +1,361 @@ +`include "wally-config.vh" + +module unpack ( + input logic [`FLEN-1:0] X, Y, Z, + input logic [`FPSIZES/3:0] FmtE, + input logic [2:0] FOpCtrlE, + output logic XSgnE, YSgnE, ZSgnE, + output logic [`NE-1:0] XExpE, YExpE, ZExpE, + output logic [`NF:0] XManE, YManE, ZManE, + output logic XNormE, + output logic XNaNE, YNaNE, ZNaNE, + output logic XSNaNE, YSNaNE, ZSNaNE, + output logic XDenormE, YDenormE, ZDenormE, + output logic XZeroE, YZeroE, ZZeroE, + output logic XInfE, YInfE, ZInfE, + output logic XExpMaxE +); + + logic [`NF-1:0] XFracE, YFracE, ZFracE; + logic XExpNonzero, YExpNonzero, ZExpNonzero; + logic XFracZero, YFracZero, ZFracZero; // input fraction zero + logic XExpZero, YExpZero, ZExpZero; // input exponent zero + logic YExpMaxE, ZExpMaxE; // input exponent all 1s + + if (`FPSIZES == 1) begin + assign XSgnE = X[`FLEN-1]; + assign YSgnE = Y[`FLEN-1]; + assign ZSgnE = Z[`FLEN-1]; + + assign XExpE = X[`FLEN-2:`NF]; + assign YExpE = Y[`FLEN-2:`NF]; + assign ZExpE = Z[`FLEN-2:`NF]; + + assign XFracE = X[`NF-1:0]; + assign YFracE = Y[`NF-1:0]; + assign ZFracE = Z[`NF-1:0]; + + assign XExpNonzero = |XExpE; + assign YExpNonzero = |YExpE; + assign ZExpNonzero = |ZExpE; + + assign XExpMaxE = &XExpE; + assign YExpMaxE = &YExpE; + assign ZExpMaxE = &ZExpE; + + + end else if (`FPSIZES == 2) begin + + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Bottom half or NaN, if not properly NaN boxed + + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN + assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + assign YLen1 = &Y[`FLEN-1:`LEN1] ? Y[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + assign ZLen1 = &Z[`FLEN-1:`LEN1] ? Z[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + + assign XSgnE = FmtE ? X[`FLEN-1] : XLen1[`LEN1-1]; + assign YSgnE = FmtE ? Y[`FLEN-1] : YLen1[`LEN1-1]; + assign ZSgnE = FmtE ? Z[`FLEN-1] : ZLen1[`LEN1-1]; + + // example double to single conversion: + // 1023 = 0011 1111 1111 + // 127 = 0000 0111 1111 (subtract this) + // 896 = 0011 1000 0000 + // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b + // dexp = 0bdd dbbb bbbb + // also need to take into account possible zero/denorm/inf/NaN values + assign XExpE = FmtE ? X[`FLEN-2:`NF] : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; + assign YExpE = FmtE ? Y[`FLEN-2:`NF] : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; + assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + + assign XFracE = FmtE ? X[`NF-1:0] : {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + assign YFracE = FmtE ? Y[`NF-1:0] : {YLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + assign ZFracE = FmtE ? Z[`NF-1:0] : {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + + assign XExpNonzero = FmtE ? |X[`FLEN-2:`NF] : |XLen1[`LEN1-2:`NF1]; + assign YExpNonzero = FmtE ? |Y[`FLEN-2:`NF] : |YLen1[`LEN1-2:`NF1]; + assign ZExpNonzero = FmtE ? |Z[`FLEN-2:`NF] : |ZLen1[`LEN1-2:`NF1]; + + assign XExpMaxE = FmtE ? &X[`FLEN-2:`NF] : &XLen1[`LEN1-2:`NF1]; + assign YExpMaxE = FmtE ? &Y[`FLEN-2:`NF] : &YLen1[`LEN1-2:`NF1]; + assign ZExpMaxE = FmtE ? &Z[`FLEN-2:`NF] : &ZLen1[`LEN1-2:`NF1]; + + + end else if (`FPSIZES == 3) begin + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Bottom half or NaN, if not properly NaN boxed + logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Bottom half or NaN, if not properly NaN boxed + + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN + assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + assign YLen1 = &Y[`FLEN-1:`LEN1] ? Y[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + assign ZLen1 = &Z[`FLEN-1:`LEN1] ? Z[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + + assign XLen2 = &X[`FLEN-1:`LEN2] ? X[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; + assign YLen2 = &Y[`FLEN-1:`LEN2] ? Y[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; + assign ZLen2 = &Z[`FLEN-1:`LEN2] ? Z[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; + + always_comb begin + case (FmtE) + `FMT: begin + assign XSgnE = X[`FLEN-1]; + assign YSgnE = Y[`FLEN-1]; + assign ZSgnE = Z[`FLEN-1]; + + assign XExpE = X[`FLEN-2:`NF]; + assign YExpE = Y[`FLEN-2:`NF]; + assign ZExpE = Z[`FLEN-2:`NF]; + + assign XFracE = X[`NF-1:0]; + assign YFracE = Y[`NF-1:0]; + assign ZFracE = Z[`NF-1:0]; + + assign XExpNonzero = |X[`FLEN-2:`NF]; + assign YExpNonzero = |Y[`FLEN-2:`NF]; + assign ZExpNonzero = |Z[`FLEN-2:`NF]; + + assign XExpMaxE = &X[`FLEN-2:`NF]; + assign YExpMaxE = &Y[`FLEN-2:`NF]; + assign ZExpMaxE = &Z[`FLEN-2:`NF]; + end + `FMT1: begin + assign XSgnE = XLen1[`LEN1-1]; + assign YSgnE = YLen1[`LEN1-1]; + assign ZSgnE = ZLen1[`LEN1-1]; + + // example double to single conversion: + // 1023 = 0011 1111 1111 + // 127 = 0000 0111 1111 (subtract this) + // 896 = 0011 1000 0000 + // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b + // dexp = 0bdd dbbb bbbb + // also need to take into account possible zero/denorm/inf/NaN values + assign XExpE = {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; + assign YExpE = {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; + assign ZExpE = {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + + assign XFracE = {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + assign YFracE = {YLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + assign ZFracE = {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + + assign XExpNonzero = |XLen1[`LEN1-2:`NF1]; + assign YExpNonzero = |YLen1[`LEN1-2:`NF1]; + assign ZExpNonzero = |ZLen1[`LEN1-2:`NF1]; + + assign XExpMaxE = &XLen1[`LEN1-2:`NF1]; + assign YExpMaxE = &YLen1[`LEN1-2:`NF1]; + assign ZExpMaxE = &ZLen1[`LEN1-2:`NF1]; + end + `FMT2: begin + assign XSgnE = XLen2[`LEN2-1]; + assign YSgnE = YLen2[`LEN2-1]; + assign ZSgnE = ZLen2[`LEN2-1]; + + // example double to single conversion: + // 1023 = 0011 1111 1111 + // 127 = 0000 0111 1111 (subtract this) + // 896 = 0011 1000 0000 + // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b + // dexp = 0bdd dbbb bbbb + // also need to take into account possible zero/denorm/inf/NaN values + assign XExpE = {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; + assign YExpE = {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; + assign ZExpE = {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; + + assign XFracE = {XLen2[`NF2-1:0], (`NF-`NF2)'(0)}; + assign YFracE = {YLen2[`NF2-1:0], (`NF-`NF2)'(0)}; + assign ZFracE = {ZLen2[`NF2-1:0], (`NF-`NF2)'(0)}; + + assign XExpNonzero = |XLen2[`LEN2-2:`NF2]; + assign YExpNonzero = |YLen2[`LEN2-2:`NF2]; + assign ZExpNonzero = |ZLen2[`LEN2-2:`NF2]; + + assign XExpMaxE = &XLen2[`LEN2-2:`NF2]; + assign YExpMaxE = &YLen2[`LEN2-2:`NF2]; + assign ZExpMaxE = &ZLen2[`LEN2-2:`NF2]; + end + default: begin + assign XSgnE = 0; + assign YSgnE = 0; + assign ZSgnE = 0; + assign XExpE = 0; + assign YExpE = 0; + assign ZExpE = 0; + assign XFracE = 0; + assign YFracE = 0; + assign ZFracE = 0; + assign XExpNonzero = 0; + assign YExpNonzero = 0; + assign ZExpNonzero = 0; + assign XExpMaxE = 0; + assign YExpMaxE = 0; + assign ZExpMaxE = 0; + end + endcase + end + + end else begin + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Bottom half or NaN, if not properly NaN boxed + logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Bottom half or NaN, if not properly NaN boxed + logic [`LEN2-1:0] XLen3, YLen3, ZLen3; // Bottom half or NaN, if not properly NaN boxed + + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN + assign XLen1 = &X[`FLEN-1:`D_LEN] ? X[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; + assign YLen1 = &Y[`FLEN-1:`D_LEN] ? Y[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; + assign ZLen1 = &Z[`FLEN-1:`D_LEN] ? Z[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; + + assign XLen2 = &X[`FLEN-1:`S_LEN] ? X[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; + assign YLen2 = &Y[`FLEN-1:`S_LEN] ? Y[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; + assign ZLen2 = &Z[`FLEN-1:`S_LEN] ? Z[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; + + assign XLen3 = &X[`FLEN-1:`H_LEN] ? X[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + assign YLen3 = &Y[`FLEN-1:`H_LEN] ? Y[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + assign ZLen3 = &Z[`FLEN-1:`H_LEN] ? Z[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + + always_comb begin + case (FmtE) + 2'b11: begin + assign XSgnE = X[`FLEN-1]; + assign YSgnE = Y[`FLEN-1]; + assign ZSgnE = Z[`FLEN-1]; + + assign XExpE = X[`FLEN-2:`NF]; + assign YExpE = Y[`FLEN-2:`NF]; + assign ZExpE = Z[`FLEN-2:`NF]; + + assign XFracE = X[`NF-1:0]; + assign YFracE = Y[`NF-1:0]; + assign ZFracE = Z[`NF-1:0]; + + assign XExpNonzero = |X[`FLEN-2:`NF]; + assign YExpNonzero = |Y[`FLEN-2:`NF]; + assign ZExpNonzero = |Z[`FLEN-2:`NF]; + + assign XExpMaxE = &X[`FLEN-2:`NF]; + assign YExpMaxE = &Y[`FLEN-2:`NF]; + assign ZExpMaxE = &Z[`FLEN-2:`NF]; + end + 2'b01: begin + assign XSgnE = XLen1[`LEN1-1]; + assign YSgnE = YLen1[`LEN1-1]; + assign ZSgnE = ZLen1[`LEN1-1]; + + // example double to single conversion: + // 1023 = 0011 1111 1111 + // 127 = 0000 0111 1111 (subtract this) + // 896 = 0011 1000 0000 + // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b + // dexp = 0bdd dbbb bbbb + // also need to take into account possible zero/denorm/inf/NaN values + assign XExpE = {XLen1[`D_LEN-2], {`NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; + assign YExpE = {YLen1[`D_LEN-2], {`NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; + assign ZExpE = {ZLen1[`D_LEN-2], {`NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; + + assign XFracE = {XLen1[`D_NE-1:0], (`NF-`D_NE)'(0)}; + assign YFracE = {YLen1[`D_NE-1:0], (`NF-`D_NE)'(0)}; + assign ZFracE = {ZLen1[`D_NE-1:0], (`NF-`D_NE)'(0)}; + + assign XExpNonzero = |XLen1[`D_LEN-2:`D_NE]; + assign YExpNonzero = |YLen1[`D_LEN-2:`D_NE]; + assign ZExpNonzero = |ZLen1[`D_LEN-2:`D_NE]; + + assign XExpMaxE = &XLen1[`D_LEN-2:`D_NE]; + assign YExpMaxE = &YLen1[`D_LEN-2:`D_NE]; + assign ZExpMaxE = &ZLen1[`D_LEN-2:`D_NE]; + end + 2'b00: begin + assign XSgnE = XLen2[`S_LEN-1]; + assign YSgnE = YLen2[`S_LEN-1]; + assign ZSgnE = ZLen2[`S_LEN-1]; + + // example double to single conversion: + // 1023 = 0011 1111 1111 + // 127 = 0000 0111 1111 (subtract this) + // 896 = 0011 1000 0000 + // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b + // dexp = 0bdd dbbb bbbb + // also need to take into account possible zero/denorm/inf/NaN values + assign XExpE = {XLen2[`S_LEN-2], {`NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; + assign YExpE = {YLen2[`S_LEN-2], {`NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; + assign ZExpE = {ZLen2[`S_LEN-2], {`NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; + + assign XFracE = {XLen2[`S_NF-1:0], (`NF-`S_NF)'(0)}; + assign YFracE = {YLen2[`S_NF-1:0], (`NF-`S_NF)'(0)}; + assign ZFracE = {ZLen2[`S_NF-1:0], (`NF-`S_NF)'(0)}; + + assign XExpNonzero = |XLen2[`S_LEN-2:`S_NF]; + assign YExpNonzero = |YLen2[`S_LEN-2:`S_NF]; + assign ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF]; + + assign XExpMaxE = &XLen2[`S_LEN-2:`S_NF]; + assign YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; + assign ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; + end + 2'b10: begin + assign XSgnE = XLen3[`H_LEN-1]; + assign YSgnE = YLen3[`H_LEN-1]; + assign ZSgnE = ZLen3[`H_LEN-1]; + + // example double to single conversion: + // 1023 = 0011 1111 1111 + // 127 = 0000 0111 1111 (subtract this) + // 896 = 0011 1000 0000 + // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b + // dexp = 0bdd dbbb bbbb + // also need to take into account possible zero/denorm/inf/NaN values + assign XExpE = {XLen3[`H_LEN-2], {`NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; + assign YExpE = {YLen3[`H_LEN-2], {`NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; + assign ZExpE = {ZLen3[`H_LEN-2], {`NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; + + assign XFracE = {XLen3[`H_NF-1:0], (`NF-`H_NF)'(0)}; + assign YFracE = {YLen3[`H_NF-1:0], (`NF-`H_NF)'(0)}; + assign ZFracE = {ZLen3[`H_NF-1:0], (`NF-`H_NF)'(0)}; + + assign XExpNonzero = |XLen3[`H_LEN-2:`H_NF]; + assign YExpNonzero = |YLen3[`H_LEN-2:`H_NF]; + assign ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF]; + + assign XExpMaxE = &XLen3[`H_LEN-2:`H_NF]; + assign YExpMaxE = &YLen3[`H_LEN-2:`H_NF]; + assign ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF]; + end + endcase + end + + end + + assign XExpZero = ~XExpNonzero; + assign YExpZero = ~YExpNonzero; + assign ZExpZero = ~ZExpNonzero; + + assign XFracZero = ~|XFracE; + assign YFracZero = ~|YFracE; + assign ZFracZero = ~|ZFracE; + + assign XManE = {XExpNonzero, XFracE}; + assign YManE = {YExpNonzero, YFracE}; + assign ZManE = {ZExpNonzero, ZFracE}; + + assign XNormE = ~(XExpMaxE|XExpZero); + + // force single precision input to be a NaN if it isn't properly Nan Boxed + assign XNaNE = XExpMaxE & ~XFracZero; + assign YNaNE = YExpMaxE & ~YFracZero; + assign ZNaNE = ZExpMaxE & ~ZFracZero; + + assign XSNaNE = XNaNE&~XFracE[`NF-1]; + assign YSNaNE = YNaNE&~YFracE[`NF-1]; + assign ZSNaNE = ZNaNE&~ZFracE[`NF-1]; + + assign XDenormE = XExpZero & ~XFracZero; + assign YDenormE = YExpZero & ~YFracZero; + assign ZDenormE = ZExpZero & ~ZFracZero; + + assign XInfE = XExpMaxE & XFracZero; + assign YInfE = YExpMaxE & YFracZero; + assign ZInfE = ZExpMaxE & ZFracZero; + + assign XZeroE = XExpZero & XFracZero; + assign YZeroE = YExpZero & YFracZero; + assign ZZeroE = ZExpZero & ZFracZero; + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv deleted file mode 100644 index f503e47be..000000000 --- a/pipelined/src/fpu/unpacking.sv +++ /dev/null @@ -1,95 +0,0 @@ -`include "wally-config.vh" - -module unpack ( - input logic [63:0] X, Y, Z, - input logic FmtE, - input logic [2:0] FOpCtrlE, - output logic XSgnE, YSgnE, ZSgnE, - output logic [10:0] XExpE, YExpE, ZExpE, - output logic [52:0] XManE, YManE, ZManE, - output logic XNormE, - output logic XNaNE, YNaNE, ZNaNE, - output logic XSNaNE, YSNaNE, ZSNaNE, - output logic XDenormE, YDenormE, ZDenormE, - output logic XZeroE, YZeroE, ZZeroE, - output logic [10:0] BiasE, - output logic XInfE, YInfE, ZInfE, - output logic XExpMaxE -); - - logic [51:0] XFracE, YFracE, ZFracE; - logic XExpNonzero, YExpNonzero, ZExpNonzero; - logic XFracZero, YFracZero, ZFracZero; // input fraction zero - logic XExpZero, YExpZero, ZExpZero; // input exponent zero - logic YExpMaxE, ZExpMaxE; // input exponent all 1s - logic [31:0] XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed - - // Determine if number is NaN as double precision to check single precision NaN boxing - if (`F_SUPPORTED & ~`D_SUPPORTED) begin // eventually this should change to FLEN when FLEN isn't hardwared to 64 - assign XFloat = X[31:0]; - assign YFloat = Y[31:0]; - assign ZFloat = Z[31:0]; - end else begin - assign XFloat = &X[`FLEN-1:32] ? X[31:0] : 32'h7fc00000; - assign YFloat = &Y[`FLEN-1:32] ? Y[31:0] : 32'h7fc00000; - assign ZFloat = &Z[`FLEN-1:32] ? Z[31:0] : 32'h7fc00000; - end - - assign XSgnE = FmtE ? X[63] : XFloat[31]; - assign YSgnE = FmtE ? Y[63] : YFloat[31]; - assign ZSgnE = FmtE ? Z[63] : ZFloat[31]; - - assign XExpE = FmtE ? X[62:52] : {XFloat[30], {3{~XFloat[30]&~XExpZero|XExpMaxE}}, XFloat[29:23]}; - assign YExpE = FmtE ? Y[62:52] : {YFloat[30], {3{~YFloat[30]&~YExpZero|YExpMaxE}}, YFloat[29:23]}; - assign ZExpE = FmtE ? Z[62:52] : {ZFloat[30], {3{~ZFloat[30]&~ZExpZero|ZExpMaxE}}, ZFloat[29:23]}; - - assign XFracE = FmtE ? X[51:0] : {XFloat[22:0], 29'b0}; - assign YFracE = FmtE ? Y[51:0] : {YFloat[22:0], 29'b0}; - assign ZFracE = FmtE ? Z[51:0] : {ZFloat[22:0], 29'b0}; - - assign XExpNonzero = FmtE ? |X[62:52] : |XFloat[30:23]; - assign YExpNonzero = FmtE ? |Y[62:52] : |YFloat[30:23]; - assign ZExpNonzero = FmtE ? |Z[62:52] : |ZFloat[30:23]; - - assign XExpZero = ~XExpNonzero; - assign YExpZero = ~YExpNonzero; - assign ZExpZero = ~ZExpNonzero; - - assign XFracZero = ~|XFracE; - assign YFracZero = ~|YFracE; - assign ZFracZero = ~|ZFracE; - - assign XManE = {XExpNonzero, XFracE}; - assign YManE = {YExpNonzero, YFracE}; - assign ZManE = {ZExpNonzero, ZFracE}; - - assign XExpMaxE = FmtE ? &X[62:52] : &XFloat[30:23]; - assign YExpMaxE = FmtE ? &Y[62:52] : &YFloat[30:23]; - assign ZExpMaxE = FmtE ? &Z[62:52] : &ZFloat[30:23]; - - assign XNormE = ~(XExpMaxE|XExpZero); - - // force single precision input to be a NaN if it isn't properly Nan Boxed - assign XNaNE = XExpMaxE & ~XFracZero; - assign YNaNE = YExpMaxE & ~YFracZero; - assign ZNaNE = ZExpMaxE & ~ZFracZero; - - assign XSNaNE = XNaNE&~XFracE[51]; - assign YSNaNE = YNaNE&~YFracE[51]; - assign ZSNaNE = ZNaNE&~ZFracE[51]; - - assign XDenormE = XExpZero & ~XFracZero; - assign YDenormE = YExpZero & ~YFracZero; - assign ZDenormE = ZExpZero & ~ZFracZero; - - assign XInfE = XExpMaxE & XFracZero; - assign YInfE = YExpMaxE & YFracZero; - assign ZInfE = ZExpMaxE & ZFracZero; - - assign XZeroE = XExpZero & XFracZero; - assign YZeroE = YExpZero & YFracZero; - assign ZZeroE = ZExpZero & ZFracZero; - - assign BiasE = 11'h3ff; // always use 1023 because exponents are unpacked to double precision - -endmodule \ No newline at end of file diff --git a/pipelined/testbench/fp/tests/fma-testbench.sv b/pipelined/testbench/fp/tests/fma-testbench.sv new file mode 100644 index 000000000..6ce50387d --- /dev/null +++ b/pipelined/testbench/fp/tests/fma-testbench.sv @@ -0,0 +1,279 @@ + +`include "wally-config.vh" +`define PATH "../../../../tests/fp/vectors/" + +string tests[] = '{ + "f16_mulAdd_rne.tv", + "f16_mulAdd_rz.tv", + "f16_mulAdd_ru.tv", + "f16_mulAdd_rd.tv", + "f16_mulAdd_rnm.tv", + "f32_mulAdd_rne.tv", + "f32_mulAdd_rz.tv", + "f32_mulAdd_ru.tv", + "f32_mulAdd_rd.tv", + "f32_mulAdd_rnm.tv", + "f64_mulAdd_rne.tv", + "f64_mulAdd_rz.tv", + "f64_mulAdd_ru.tv", + "f64_mulAdd_rd.tv", + "f64_mulAdd_rnm.tv", + "f128_mulAdd_rne.tv", + "f128_mulAdd_rz.tv", + "f128_mulAdd_ru.tv", + "f128_mulAdd_rd.tv", + "f128_mulAdd_rnm.tv" +}; + +// steps to run FMA tests +// 1) create test vectors in riscv-wally/tests/fp with: ./run-all.sh +// 2) go to riscv-wally/pipelined/testbench/fp/tests +// 3) run ./sim-wally-batch + +module fmatestbench(); + + logic clk; + logic [31:0] errors=0; + logic [31:0] vectornum=0; + logic [`FLEN*4+7+4+4:0] testvectors[6133248:0]; + int i = `ZFH_SUPPORTED ? 0 : `F_SUPPORTED ? 5 : `D_SUPPORTED ? 10 : 15; // set i to the first test that is run + + logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [`FLEN-1:0] ans; // result from TestFloat + logic [7:0] flags; // flags read form testfloat + logic [2:0] FrmE; // rounding mode + logic [`FPSIZES/3:0] FmtE; // format - 10 = half, 00 = single, 01 = double, 11 = quad + logic [3:0] FrmRead; // rounding mode read from testfloat + logic [3:0] FmtRead; // format read from testfloat + logic [`FLEN-1:0] FMAResM; // FMA's outputed result + logic [4:0] FMAFlgM; // FMA's outputed flags + logic [2:0] FOpCtrlE; // which opperation + logic wnan; // is the outputed result NaN + logic ansnan; // is the correct answer NaN + + // signals needed to connect modules + logic [`NE+1:0] ProdExpE; + logic AddendStickyE; + logic KillProdE; + logic XSgnE, YSgnE, ZSgnE; + logic [`NE-1:0] XExpE, YExpE, ZExpE; + logic [`NF:0] XManE, YManE, ZManE; + logic XNormE; + logic XExpMaxE; + logic XNaNE, YNaNE, ZNaNE; + logic XSNaNE, YSNaNE, ZSNaNE; + logic XDenormE, YDenormE, ZDenormE; + logic XInfE, YInfE, ZInfE; + logic XZeroE, YZeroE, ZZeroE; + logic YExpMaxE, ZExpMaxE, Mult; + logic [3*`NF+5:0] SumE; + logic InvZE; + logic NegSumE; + logic ZSgnEffE; + logic PSgnE; + logic [$clog2(3*`NF+7)-1:0] NormCntE; + + + assign FOpCtrlE = 3'b0; // set to 0 because test float only tests fMADD + assign Mult = 1'b0; // set to zero because not testing multiplication + + // check if the calculated result or correct answer is NaN + always_comb begin + case (FmtRead) + 4'b11: begin // quad + assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]); + assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); + + end + 4'b01: begin // double + assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]); + assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); + + end + 4'b00: begin // single + assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]); + assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); + end + 4'b10: begin // half + assign ansnan = &ans[`H_LEN-2:`H_NF]&(|ans[`H_NF-1:0]); + assign wnan = &FMAResM[`H_LEN-2:`H_NF]&(|FMAResM[`H_NF-1:0]); + end + endcase + end + + // instantiate devices under test + unpack unpack(.X, .Y, .Z, .FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, + .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, + .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, + .XExpMaxE); + fma1 fma1(.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, + .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, + .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, + .ProdExpE, .AddendStickyE, .KillProdE); + fma2 fma2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM(XManE), .YManM(YManE), .ZManM(ZManE), + .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), + .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), + .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(FmtE), .FrmM(FrmE), + .FMAFlgM, .FMAResM, .Mult); + + + // produce clock + always begin + clk = 1; #5; clk = 0; #5; + end + + // Read first test + initial begin + $display("\n\nRunning %s vectors", tests[i]); + $readmemh({`PATH, tests[i]}, testvectors); + end + + // apply test vectors on rising edge of clk + always @(posedge clk) begin + #1; + flags = testvectors[vectornum][15:8]; + FrmRead = testvectors[vectornum][7:4]; + FmtRead = testvectors[vectornum][3:0]; + if (FmtRead==4'b11 & `Q_SUPPORTED) begin // quad + X = testvectors[vectornum][16+4*(`Q_LEN)-1:16+3*(`Q_LEN)]; + Y = testvectors[vectornum][16+3*(`Q_LEN)-1:16+2*(`Q_LEN)]; + Z = testvectors[vectornum][16+2*(`Q_LEN)-1:16+`Q_LEN]; + ans = testvectors[vectornum][16+(`Q_LEN-1):16]; + end + else if (FmtRead==4'b01 & `D_SUPPORTED) begin // double + X = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+4*(`D_LEN)-1:16+3*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+3*(`D_LEN)-1:16+2*(`D_LEN)]}; + Z = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+2*(`D_LEN)-1:16+`D_LEN]}; + ans = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+(`D_LEN-1):16]}; + end + else if (FmtRead==4'b00 & `F_SUPPORTED) begin // single + X = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+4*(`S_LEN)-1:16+3*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+3*(`S_LEN)-1:16+2*(`S_LEN)]}; + Z = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+2*(`S_LEN)-1:16+`S_LEN]}; + ans = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+(`S_LEN-1):16]}; + end + else if (FmtRead==4'b10 & `ZFH_SUPPORTED) begin // half + X = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+4*(`H_LEN)-1:16+3*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+3*(`H_LEN)-1:16+2*(`H_LEN)]}; + Z = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+2*(`H_LEN)-1:16+`H_LEN]}; + ans = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+(`H_LEN-1):16]}; + end + else begin + X = {`FLEN{1'bx}}; + Y = {`FLEN{1'bx}}; + Z = {`FLEN{1'bx}}; + ans = {`FLEN{1'bx}}; + end + + // trim format and rounding mode to appropriate size + if (`FPSIZES <= 2) FmtE = FmtRead === `FMT; // rewrite format if 2 or less floating formats are supported + else FmtE = FmtRead[1:0]; + FrmE = FrmRead[2:0]; + end + + // check results on falling edge of clk + always @(negedge clk) begin + // quad + if((FmtRead==4'b11) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0] | (XNaNE&(FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) | (YNaNE&(FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]})) | (ZNaNE&(FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})))))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(XDenormE) $display( "xdenorm "); + if(YDenormE) $display( "ydenorm "); + if(ZDenormE) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf "); + if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf "); + if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); + if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); + if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf "); + if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf "); + if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN "); + if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN "); + errors = errors + 1; + if (errors === 1) $stop; + end + // double + if((FmtRead==4'b01) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`D_LEN-2:0] === ans[`D_LEN-2:0] | (XNaNE&(FMAResM[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaNE&(FMAResM[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | (ZNaNE&(FMAResM[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]})))))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + errors = errors + 1; + if (errors === 1) $stop; + end + // single + if((FmtRead==4'b00) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`S_LEN-2:0] === ans[`S_LEN-2:0] | (XNaNE&(FMAResM[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaNE&(FMAResM[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | (ZNaNE&(FMAResM[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]})))))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + errors = errors + 1; + if (errors === 1) $stop; + end + // half + if((FmtRead==4'b01) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`H_LEN-2:0] === ans[`H_LEN-2:0] | (XNaNE&(FMAResM[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaNE&(FMAResM[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | (ZNaNE&(FMAResM[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]})))))) begin + $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); + if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(FMAFlgM[4] !== 0) $display( "invld "); + if(FMAFlgM[2] !== 0) $display( "ovrflw "); + if(FMAFlgM[1] !== 0) $display( "unflw "); + if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + errors = errors + 1; + if (errors === 1) $stop; + end + + // if ( vectornum === 3165862) $stop; // uncomment for specific test + vectornum = vectornum + 1; // increment test + if (testvectors[vectornum][0] === 1'bx) begin // if reached the end of file + if (errors) begin // if there were errors + $display("%s completed with %d tests and %d errors", tests[i], vectornum, errors); + $stop; + end + else begin // if no errors + if(tests[i] === "") begin // if no more tests + $display("\nAll tests completed with %d errors\n", errors); + $stop; + end + + $display("%s completed successfully with %d tests and %d errors (across all tests)\n", tests[i], vectornum, errors); + + // increment tests - skip some precisions if needed + if ((i === 4 & ~`F_SUPPORTED) | (i === 9 & ~`D_SUPPORTED) | (i === 14 & ~`Q_SUPPORTED)) i = i+5; + if ((i === 9 & ~`D_SUPPORTED) | (i === 14 & ~`Q_SUPPORTED)) i = i+5; + if ((i === 14 & ~`Q_SUPPORTED)) i = i+5; + i = i+1; + + // if no more tests - finish + if(tests[i] === "") begin + $display("\nAll tests completed with %d errors\n", errors); + $stop; + end + + // read next files + $display("Running %s vectors", tests[i]); + $readmemh({`PATH, tests[i]}, testvectors); + vectornum = 0; + end + end + end +endmodule diff --git a/pipelined/testbench/fp/tests/fma.do b/pipelined/testbench/fp/tests/fma.do new file mode 100644 index 000000000..6349be0ef --- /dev/null +++ b/pipelined/testbench/fp/tests/fma.do @@ -0,0 +1,50 @@ +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +# $num = the added words after the call +vlog +incdir+../../../config/$1 +incdir+../../../config/shared fma-testbench.sv ../../../src/fpu/fma.sv ../../../src/fpu/unpack.sv -suppress 2583 -suppress 7063 + +vsim -voptargs=+acc work.fmatestbench + +view wave +#-- display input and output signals as hexidecimal values +#do ./wave-dos/peripheral-waves.do +#add log -recursive /* +#do wave.do deal with when ready + +#-- Run the Simulation +#run 3600 +run -all +noview fma-testbench.sv +view wave + diff --git a/pipelined/testbench/fp/tests/sim-fma b/pipelined/testbench/fp/tests/sim-fma new file mode 100755 index 000000000..5027d43e4 --- /dev/null +++ b/pipelined/testbench/fp/tests/sim-fma @@ -0,0 +1 @@ +vsim -do "do fma.do rv64fp" diff --git a/pipelined/testbench/fp/tests/sim-fma-batch b/pipelined/testbench/fp/tests/sim-fma-batch new file mode 100755 index 000000000..321e0678d --- /dev/null +++ b/pipelined/testbench/fp/tests/sim-fma-batch @@ -0,0 +1 @@ +vsim -c -do "do fma.do rv64fp" \ No newline at end of file diff --git a/tests/fp/create_vectors128fma.sh b/tests/fp/create_vectors128fma.sh new file mode 100755 index 000000000..361a4add7 --- /dev/null +++ b/tests/fp/create_vectors128fma.sh @@ -0,0 +1,31 @@ +#!/bin/sh + +BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +OUTPUT="./vectors" + +$BUILD/testfloat_gen -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv + +# format: X_Y_Z_answer_flags_Frm_Fmt +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv +sed -ie 's/$/_0/' $OUTPUT/f128_mulAdd_rne.tv +sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rne.tv + +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv +sed -ie 's/$/_1/' $OUTPUT/f128_mulAdd_rz.tv +sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rz.tv + +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv +sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_ru.tv +sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_ru.tv + +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv +sed -ie 's/$/_2/' $OUTPUT/f128_mulAdd_rd.tv +sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rd.tv + +sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv +sed -ie 's/$/_4/' $OUTPUT/f128_mulAdd_rnm.tv +sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/create_vectors16fma.sh b/tests/fp/create_vectors16fma.sh new file mode 100755 index 000000000..d46e87680 --- /dev/null +++ b/tests/fp/create_vectors16fma.sh @@ -0,0 +1,31 @@ +#!/bin/sh + +BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +OUTPUT="./vectors" + +$BUILD/testfloat_gen -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv + +# format: X_Y_Z_answer_flags_Frm_Fmt +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv +sed -ie 's/$/_0/' $OUTPUT/f16_mulAdd_rne.tv +sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rne.tv + +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv +sed -ie 's/$/_1/' $OUTPUT/f16_mulAdd_rz.tv +sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rz.tv + +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv +sed -ie 's/$/_3/' $OUTPUT/f16_mulAdd_ru.tv +sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_ru.tv + +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv +sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rd.tv +sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rd.tv + +sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv +sed -ie 's/$/_4/' $OUTPUT/f16_mulAdd_rnm.tv +sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/create_vectors32fma.sh b/tests/fp/create_vectors32fma.sh new file mode 100755 index 000000000..7e48d1abe --- /dev/null +++ b/tests/fp/create_vectors32fma.sh @@ -0,0 +1,31 @@ +#!/bin/sh + +BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +OUTPUT="./vectors" + +$BUILD/testfloat_gen -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv + +# format: X_Y_Z_answer_flags_Frm_Fmt +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv +sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rne.tv +sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rne.tv + +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv +sed -ie 's/$/_1/' $OUTPUT/f32_mulAdd_rz.tv +sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rz.tv + +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv +sed -ie 's/$/_3/' $OUTPUT/f32_mulAdd_ru.tv +sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_ru.tv + +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv +sed -ie 's/$/_2/' $OUTPUT/f32_mulAdd_rd.tv +sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rd.tv + +sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv +sed -ie 's/$/_4/' $OUTPUT/f32_mulAdd_rnm.tv +sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/create_vectors64fma.sh b/tests/fp/create_vectors64fma.sh new file mode 100755 index 000000000..615245b30 --- /dev/null +++ b/tests/fp/create_vectors64fma.sh @@ -0,0 +1,31 @@ +#!/bin/sh + +BUILD="./TestFloat-3e/build/Linux-x86_64-GCC" +OUTPUT="./vectors" + +$BUILD/testfloat_gen -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv +$BUILD/testfloat_gen -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv +$BUILD/testfloat_gen -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv +$BUILD/testfloat_gen -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv +$BUILD/testfloat_gen -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv + +# format: X_Y_Z_answer_flags_Frm_Fmt +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv +sed -ie 's/$/_0/' $OUTPUT/f64_mulAdd_rne.tv +sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rne.tv + +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv +sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rz.tv +sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rz.tv + +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv +sed -ie 's/$/_3/' $OUTPUT/f64_mulAdd_ru.tv +sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_ru.tv + +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv +sed -ie 's/$/_2/' $OUTPUT/f64_mulAdd_rd.tv +sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rd.tv + +sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv +sed -ie 's/$/_4/' $OUTPUT/f64_mulAdd_rnm.tv +sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rnm.tv \ No newline at end of file diff --git a/tests/fp/run_all.sh b/tests/fp/run_all.sh index 8d2a17ceb..d34366b93 100755 --- a/tests/fp/run_all.sh +++ b/tests/fp/run_all.sh @@ -8,3 +8,7 @@ ./create_vectors64cmp.sh ./create_vectors64.sh ./create_vectorsi.sh +./create_vectors16fma.sh +./create_vectors32fma.sh +./create_vectors64fma.sh +./create_vectors128fma.sh From ca8fb45367b811cf9a4e31b7ffbde97c6cd30021 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Mar 2022 16:52:07 -0500 Subject: [PATCH 177/199] Added comment about needed fix to misaligned fault. --- pipelined/src/lsu/lsu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index ddf0f77dc..c9ceb455e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -161,7 +161,7 @@ module lsu ( .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM, .InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM, - .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, + .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw. .DAPageFault(DataDAPageFaultM), // *** should use LSURWM as this is includes the lr/sc squash. However this introduces a combo loop // from squash, depends on LSUPAdrM, depends on TLBHit, depends on these *AccessM inputs. From e6b42cb10f706765aeea11e00f17f055112056dd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Mar 2022 16:52:27 -0500 Subject: [PATCH 178/199] Added spoof of uart addresses +0x2 and +0x6. --- pipelined/testbench/testbench-linux.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 8723d6b9c..82742ff4b 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -475,7 +475,7 @@ module testbench; end \ if(`"STAGE`"=="M") begin \ // override on special conditions \ - if (dut.core.lsu.LSUPAdrM == 'h10000005) \ + if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) \ //$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \ force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ else \ From 23adb2dd03d385cd1d09d19ccec0b4aae0fe791f Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Wed, 23 Mar 2022 01:53:37 +0000 Subject: [PATCH 179/199] unpack.sv cleanup --- pipelined/src/fpu/fpu.sv | 2 +- pipelined/src/fpu/unpack.sv | 446 ++++++++++++++++++++++-------------- 2 files changed, 280 insertions(+), 168 deletions(-) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index f9472c9b5..2ffcb1264 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -175,7 +175,7 @@ module fpu ( // unpack unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, + unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 0db63fe91..1625b2fc2 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -1,58 +1,83 @@ `include "wally-config.vh" module unpack ( - input logic [`FLEN-1:0] X, Y, Z, - input logic [`FPSIZES/3:0] FmtE, - input logic [2:0] FOpCtrlE, - output logic XSgnE, YSgnE, ZSgnE, - output logic [`NE-1:0] XExpE, YExpE, ZExpE, - output logic [`NF:0] XManE, YManE, ZManE, - output logic XNormE, - output logic XNaNE, YNaNE, ZNaNE, - output logic XSNaNE, YSNaNE, ZSNaNE, - output logic XDenormE, YDenormE, ZDenormE, - output logic XZeroE, YZeroE, ZZeroE, - output logic XInfE, YInfE, ZInfE, - output logic XExpMaxE + input logic [`FLEN-1:0] X, Y, Z, // inputs from register file + input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 10 - double 11 - quad 10 - half + output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic XNormE, // is X a normalized number + output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN + output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN + output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero + output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic XExpMaxE // does X have the maximum exponent (NaN or Inf) ); - logic [`NF-1:0] XFracE, YFracE, ZFracE; - logic XExpNonzero, YExpNonzero, ZExpNonzero; - logic XFracZero, YFracZero, ZFracZero; // input fraction zero - logic XExpZero, YExpZero, ZExpZero; // input exponent zero - logic YExpMaxE, ZExpMaxE; // input exponent all 1s + logic [`NF-1:0] XFracE, YFracE, ZFracE; //Fraction of XYZ + logic XExpNonzero, YExpNonzero, ZExpNonzero; // is the exponent of XYZ non-zero + logic XFracZero, YFracZero, ZFracZero; // is the fraction zero + logic XExpZero, YExpZero, ZExpZero; // is the exponent zero + logic YExpMaxE, ZExpMaxE; // is the exponent all 1s - if (`FPSIZES == 1) begin + if (`FPSIZES == 1) begin // if there is only one floating point format supported + + // sign bit assign XSgnE = X[`FLEN-1]; assign YSgnE = Y[`FLEN-1]; assign ZSgnE = Z[`FLEN-1]; + // exponent assign XExpE = X[`FLEN-2:`NF]; assign YExpE = Y[`FLEN-2:`NF]; assign ZExpE = Z[`FLEN-2:`NF]; + // fraction (no assumed 1) assign XFracE = X[`NF-1:0]; assign YFracE = Y[`NF-1:0]; assign ZFracE = Z[`NF-1:0]; + // is the exponent non-zero assign XExpNonzero = |XExpE; assign YExpNonzero = |YExpE; assign ZExpNonzero = |ZExpE; + // is the exponent all 1's assign XExpMaxE = &XExpE; assign YExpMaxE = &YExpE; assign ZExpMaxE = &ZExpE; - end else if (`FPSIZES == 2) begin + end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Bottom half or NaN, if not properly NaN boxed + //***need better names for these constants + // largest format | smaller format + //---------------------------------- + // `FLEN | `LEN1 length of floating point number + // `NE | `NE1 length of exponent + // `NF | `NF1 length of fraction + // `BIAS | `BIAS1 exponent's bias value + // `FMT | `FMT1 precision's format value - Q=11 D=01 S=00 H=10 + + // Possible combinantions specified by spec: + // double and single + // single and half + + // Not needed but can also handle: + // quad and double + // quad and single + // quad and half + // double and half + + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; assign YLen1 = &Y[`FLEN-1:`LEN1] ? Y[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; assign ZLen1 = &Z[`FLEN-1:`LEN1] ? Z[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + // choose sign bit depending on format - 1=larger precsion 0=smaller precision assign XSgnE = FmtE ? X[`FLEN-1] : XLen1[`LEN1-1]; assign YSgnE = FmtE ? Y[`FLEN-1] : YLen1[`LEN1-1]; assign ZSgnE = FmtE ? Z[`FLEN-1] : ZLen1[`LEN1-1]; @@ -64,63 +89,94 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values + + // extract the exponent, converting the smaller exponent into the larger precision if nessisary assign XExpE = FmtE ? X[`FLEN-2:`NF] : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; assign YExpE = FmtE ? Y[`FLEN-2:`NF] : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + // extract the fraction, add trailing zeroes to the mantissa if nessisary assign XFracE = FmtE ? X[`NF-1:0] : {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; assign YFracE = FmtE ? Y[`NF-1:0] : {YLen1[`NF1-1:0], (`NF-`NF1)'(0)}; assign ZFracE = FmtE ? Z[`NF-1:0] : {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + // is the exponent non-zero assign XExpNonzero = FmtE ? |X[`FLEN-2:`NF] : |XLen1[`LEN1-2:`NF1]; assign YExpNonzero = FmtE ? |Y[`FLEN-2:`NF] : |YLen1[`LEN1-2:`NF1]; assign ZExpNonzero = FmtE ? |Z[`FLEN-2:`NF] : |ZLen1[`LEN1-2:`NF1]; + // is the exponent all 1's assign XExpMaxE = FmtE ? &X[`FLEN-2:`NF] : &XLen1[`LEN1-2:`NF1]; assign YExpMaxE = FmtE ? &Y[`FLEN-2:`NF] : &YLen1[`LEN1-2:`NF1]; assign ZExpMaxE = FmtE ? &Z[`FLEN-2:`NF] : &ZLen1[`LEN1-2:`NF1]; - end else if (`FPSIZES == 3) begin - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Bottom half or NaN, if not properly NaN boxed - logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Bottom half or NaN, if not properly NaN boxed + end else if (`FPSIZES == 3) begin // three floating point precsions supported + + //***need better names for these constants + // largest format | larger format | smallest format + //--------------------------------------------------- + // `FLEN | `LEN1 | `LEN2 length of floating point number + // `NE | `NE1 | `NE2 length of exponent + // `NF | `NF1 | `NF2 length of fraction + // `BIAS | `BIAS1 | `BIAS2 exponent's bias value + // `FMT | `FMT1 | `FMT2 precision's format value - Q=11 D=01 S=00 H=10 + + // Possible combinantions specified by spec: + // quad and double and single + // double and single and half + + // Not needed but can also handle: + // quad and double and half + // quad and single and half + + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision + logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for larger precision assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; assign YLen1 = &Y[`FLEN-1:`LEN1] ? Y[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; assign ZLen1 = &Z[`FLEN-1:`LEN1] ? Z[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for smaller precision assign XLen2 = &X[`FLEN-1:`LEN2] ? X[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; assign YLen2 = &Y[`FLEN-1:`LEN2] ? Y[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; assign ZLen2 = &Z[`FLEN-1:`LEN2] ? Z[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; always_comb begin case (FmtE) - `FMT: begin - assign XSgnE = X[`FLEN-1]; - assign YSgnE = Y[`FLEN-1]; - assign ZSgnE = Z[`FLEN-1]; + `FMT: begin // if input is largest precision (`FLEN - ie quad or double) + // extract the sign bit + XSgnE = X[`FLEN-1]; + YSgnE = Y[`FLEN-1]; + ZSgnE = Z[`FLEN-1]; - assign XExpE = X[`FLEN-2:`NF]; - assign YExpE = Y[`FLEN-2:`NF]; - assign ZExpE = Z[`FLEN-2:`NF]; + // extract the exponent + XExpE = X[`FLEN-2:`NF]; + YExpE = Y[`FLEN-2:`NF]; + ZExpE = Z[`FLEN-2:`NF]; - assign XFracE = X[`NF-1:0]; - assign YFracE = Y[`NF-1:0]; - assign ZFracE = Z[`NF-1:0]; + // extract the fraction + XFracE = X[`NF-1:0]; + YFracE = Y[`NF-1:0]; + ZFracE = Z[`NF-1:0]; - assign XExpNonzero = |X[`FLEN-2:`NF]; - assign YExpNonzero = |Y[`FLEN-2:`NF]; - assign ZExpNonzero = |Z[`FLEN-2:`NF]; + // is the exponent non-zero + XExpNonzero = |X[`FLEN-2:`NF]; + YExpNonzero = |Y[`FLEN-2:`NF]; + ZExpNonzero = |Z[`FLEN-2:`NF]; - assign XExpMaxE = &X[`FLEN-2:`NF]; - assign YExpMaxE = &Y[`FLEN-2:`NF]; - assign ZExpMaxE = &Z[`FLEN-2:`NF]; + // is the exponent all 1's + XExpMaxE = &X[`FLEN-2:`NF]; + YExpMaxE = &Y[`FLEN-2:`NF]; + ZExpMaxE = &Z[`FLEN-2:`NF]; end - `FMT1: begin - assign XSgnE = XLen1[`LEN1-1]; - assign YSgnE = YLen1[`LEN1-1]; - assign ZSgnE = ZLen1[`LEN1-1]; + `FMT1: begin // if input is larger precsion (`LEN1 - double or single) + + // extract the sign bit + XSgnE = XLen1[`LEN1-1]; + YSgnE = YLen1[`LEN1-1]; + ZSgnE = ZLen1[`LEN1-1]; // example double to single conversion: // 1023 = 0011 1111 1111 @@ -129,26 +185,33 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values - assign XExpE = {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; - assign YExpE = {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; - assign ZExpE = {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; - assign XFracE = {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; - assign YFracE = {YLen1[`NF1-1:0], (`NF-`NF1)'(0)}; - assign ZFracE = {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + // convert the larger precision's exponent to use the largest precision's bias + XExpE = {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; + YExpE = {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; + ZExpE = {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; - assign XExpNonzero = |XLen1[`LEN1-2:`NF1]; - assign YExpNonzero = |YLen1[`LEN1-2:`NF1]; - assign ZExpNonzero = |ZLen1[`LEN1-2:`NF1]; + // extract the fraction and add the nessesary trailing zeros + XFracE = {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + YFracE = {YLen1[`NF1-1:0], (`NF-`NF1)'(0)}; + ZFracE = {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)}; - assign XExpMaxE = &XLen1[`LEN1-2:`NF1]; - assign YExpMaxE = &YLen1[`LEN1-2:`NF1]; - assign ZExpMaxE = &ZLen1[`LEN1-2:`NF1]; + // is the exponent non-zero + XExpNonzero = |XLen1[`LEN1-2:`NF1]; + YExpNonzero = |YLen1[`LEN1-2:`NF1]; + ZExpNonzero = |ZLen1[`LEN1-2:`NF1]; + + // is the exponent all 1's + XExpMaxE = &XLen1[`LEN1-2:`NF1]; + YExpMaxE = &YLen1[`LEN1-2:`NF1]; + ZExpMaxE = &ZLen1[`LEN1-2:`NF1]; end - `FMT2: begin - assign XSgnE = XLen2[`LEN2-1]; - assign YSgnE = YLen2[`LEN2-1]; - assign ZSgnE = ZLen2[`LEN2-1]; + `FMT2: begin // if input is smallest precsion (`LEN2 - single or half) + + // exctract the sign bit + XSgnE = XLen2[`LEN2-1]; + YSgnE = YLen2[`LEN2-1]; + ZSgnE = ZLen2[`LEN2-1]; // example double to single conversion: // 1023 = 0011 1111 1111 @@ -157,87 +220,110 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values - assign XExpE = {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; - assign YExpE = {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; - assign ZExpE = {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; + + // convert the smallest precision's exponent to use the largest precision's bias + XExpE = {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; + YExpE = {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; + ZExpE = {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; - assign XFracE = {XLen2[`NF2-1:0], (`NF-`NF2)'(0)}; - assign YFracE = {YLen2[`NF2-1:0], (`NF-`NF2)'(0)}; - assign ZFracE = {ZLen2[`NF2-1:0], (`NF-`NF2)'(0)}; + // extract the fraction and add the nessesary trailing zeros + XFracE = {XLen2[`NF2-1:0], (`NF-`NF2)'(0)}; + YFracE = {YLen2[`NF2-1:0], (`NF-`NF2)'(0)}; + ZFracE = {ZLen2[`NF2-1:0], (`NF-`NF2)'(0)}; - assign XExpNonzero = |XLen2[`LEN2-2:`NF2]; - assign YExpNonzero = |YLen2[`LEN2-2:`NF2]; - assign ZExpNonzero = |ZLen2[`LEN2-2:`NF2]; + // is the exponent non-zero + XExpNonzero = |XLen2[`LEN2-2:`NF2]; + YExpNonzero = |YLen2[`LEN2-2:`NF2]; + ZExpNonzero = |ZLen2[`LEN2-2:`NF2]; - assign XExpMaxE = &XLen2[`LEN2-2:`NF2]; - assign YExpMaxE = &YLen2[`LEN2-2:`NF2]; - assign ZExpMaxE = &ZLen2[`LEN2-2:`NF2]; + // is the exponent all 1's + XExpMaxE = &XLen2[`LEN2-2:`NF2]; + YExpMaxE = &YLen2[`LEN2-2:`NF2]; + ZExpMaxE = &ZLen2[`LEN2-2:`NF2]; end default: begin - assign XSgnE = 0; - assign YSgnE = 0; - assign ZSgnE = 0; - assign XExpE = 0; - assign YExpE = 0; - assign ZExpE = 0; - assign XFracE = 0; - assign YFracE = 0; - assign ZFracE = 0; - assign XExpNonzero = 0; - assign YExpNonzero = 0; - assign ZExpNonzero = 0; - assign XExpMaxE = 0; - assign YExpMaxE = 0; - assign ZExpMaxE = 0; + XSgnE = 0; + YSgnE = 0; + ZSgnE = 0; + XExpE = 0; + YExpE = 0; + ZExpE = 0; + XFracE = 0; + YFracE = 0; + ZFracE = 0; + XExpNonzero = 0; + YExpNonzero = 0; + ZExpNonzero = 0; + XExpMaxE = 0; + YExpMaxE = 0; + ZExpMaxE = 0; end endcase end - end else begin - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Bottom half or NaN, if not properly NaN boxed - logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Bottom half or NaN, if not properly NaN boxed - logic [`LEN2-1:0] XLen3, YLen3, ZLen3; // Bottom half or NaN, if not properly NaN boxed + end else begin // if all precsisons are supported - quad, double, single, and half + + // quad | double | single | half + //------------------------------------------------------------------- + // `Q_LEN | `D_LEN | `S_LEN | `H_LEN length of floating point number + // `Q_NE | `D_NE | `S_NE | `H_NE length of exponent + // `Q_NF | `D_NF | `S_NF | `H_NF length of fraction + // `Q_BIAS | `D_BIAS | `S_BIAS | `H_BIAS exponent's bias value + // `Q_FMT | `D_FMT | `S_FMT | `H_FMT precision's format value - Q=11 D=01 S=00 H=10 + + + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision + logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision + logic [`LEN2-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision - // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - assign XLen1 = &X[`FLEN-1:`D_LEN] ? X[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; - assign YLen1 = &Y[`FLEN-1:`D_LEN] ? Y[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; - assign ZLen1 = &Z[`FLEN-1:`D_LEN] ? Z[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for double precision + assign XLen1 = &X[`Q_LEN-1:`D_LEN] ? X[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; + assign YLen1 = &Y[`Q_LEN-1:`D_LEN] ? Y[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; + assign ZLen1 = &Z[`Q_LEN-1:`D_LEN] ? Z[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; - assign XLen2 = &X[`FLEN-1:`S_LEN] ? X[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; - assign YLen2 = &Y[`FLEN-1:`S_LEN] ? Y[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; - assign ZLen2 = &Z[`FLEN-1:`S_LEN] ? Z[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for single precision + assign XLen2 = &X[`Q_LEN-1:`S_LEN] ? X[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; + assign YLen2 = &Y[`Q_LEN-1:`S_LEN] ? Y[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; + assign ZLen2 = &Z[`Q_LEN-1:`S_LEN] ? Z[`S_LEN-1:0] : {1'b0, {`S_NE+1{1'b1}}, (`S_NF-1)'(0)}; - assign XLen3 = &X[`FLEN-1:`H_LEN] ? X[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; - assign YLen3 = &Y[`FLEN-1:`H_LEN] ? Y[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; - assign ZLen3 = &Z[`FLEN-1:`H_LEN] ? Z[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for half precision + assign XLen3 = &X[`Q_LEN-1:`H_LEN] ? X[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + assign YLen3 = &Y[`Q_LEN-1:`H_LEN] ? Y[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + assign ZLen3 = &Z[`Q_LEN-1:`H_LEN] ? Z[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; always_comb begin case (FmtE) - 2'b11: begin - assign XSgnE = X[`FLEN-1]; - assign YSgnE = Y[`FLEN-1]; - assign ZSgnE = Z[`FLEN-1]; + `Q_BIAS: begin // if input is quad percision + // extract sign bit + XSgnE = X[`Q_LEN-1]; + YSgnE = Y[`Q_LEN-1]; + ZSgnE = Z[`Q_LEN-1]; - assign XExpE = X[`FLEN-2:`NF]; - assign YExpE = Y[`FLEN-2:`NF]; - assign ZExpE = Z[`FLEN-2:`NF]; + // extract the exponent + XExpE = X[`Q_LEN-2:`Q_NF]; + YExpE = Y[`Q_LEN-2:`Q_NF]; + ZExpE = Z[`Q_LEN-2:`Q_NF]; - assign XFracE = X[`NF-1:0]; - assign YFracE = Y[`NF-1:0]; - assign ZFracE = Z[`NF-1:0]; + // extract the fraction + XFracE = X[`Q_NF-1:0]; + YFracE = Y[`Q_NF-1:0]; + ZFracE = Z[`Q_NF-1:0]; - assign XExpNonzero = |X[`FLEN-2:`NF]; - assign YExpNonzero = |Y[`FLEN-2:`NF]; - assign ZExpNonzero = |Z[`FLEN-2:`NF]; + // is the exponent non-zero + XExpNonzero = |X[`Q_LEN-2:`Q_NF]; + YExpNonzero = |Y[`Q_LEN-2:`Q_NF]; + ZExpNonzero = |Z[`Q_LEN-2:`Q_NF]; - assign XExpMaxE = &X[`FLEN-2:`NF]; - assign YExpMaxE = &Y[`FLEN-2:`NF]; - assign ZExpMaxE = &Z[`FLEN-2:`NF]; + // is the exponent all 1's + XExpMaxE = &X[`Q_LEN-2:`Q_NF]; + YExpMaxE = &Y[`Q_LEN-2:`Q_NF]; + ZExpMaxE = &Z[`Q_LEN-2:`Q_NF]; end - 2'b01: begin - assign XSgnE = XLen1[`LEN1-1]; - assign YSgnE = YLen1[`LEN1-1]; - assign ZSgnE = ZLen1[`LEN1-1]; + `D_BIAS: begin // if input is double percision + // extract sign bit + XSgnE = XLen1[`D_LEN-1]; + YSgnE = YLen1[`D_LEN-1]; + ZSgnE = ZLen1[`D_LEN-1]; // example double to single conversion: // 1023 = 0011 1111 1111 @@ -246,26 +332,32 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values - assign XExpE = {XLen1[`D_LEN-2], {`NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; - assign YExpE = {YLen1[`D_LEN-2], {`NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; - assign ZExpE = {ZLen1[`D_LEN-2], {`NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; + + // convert the double precsion exponent into quad precsion + XExpE = {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; + YExpE = {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; + ZExpE = {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; - assign XFracE = {XLen1[`D_NE-1:0], (`NF-`D_NE)'(0)}; - assign YFracE = {YLen1[`D_NE-1:0], (`NF-`D_NE)'(0)}; - assign ZFracE = {ZLen1[`D_NE-1:0], (`NF-`D_NE)'(0)}; + // extract the fraction and add the nessesary trailing zeros + XFracE = {XLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; + YFracE = {YLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; + ZFracE = {ZLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; - assign XExpNonzero = |XLen1[`D_LEN-2:`D_NE]; - assign YExpNonzero = |YLen1[`D_LEN-2:`D_NE]; - assign ZExpNonzero = |ZLen1[`D_LEN-2:`D_NE]; + // is the exponent non-zero + XExpNonzero = |XLen1[`D_LEN-2:`D_NE]; + YExpNonzero = |YLen1[`D_LEN-2:`D_NE]; + ZExpNonzero = |ZLen1[`D_LEN-2:`D_NE]; - assign XExpMaxE = &XLen1[`D_LEN-2:`D_NE]; - assign YExpMaxE = &YLen1[`D_LEN-2:`D_NE]; - assign ZExpMaxE = &ZLen1[`D_LEN-2:`D_NE]; + // is the exponent all 1's + XExpMaxE = &XLen1[`D_LEN-2:`D_NE]; + YExpMaxE = &YLen1[`D_LEN-2:`D_NE]; + ZExpMaxE = &ZLen1[`D_LEN-2:`D_NE]; end - 2'b00: begin - assign XSgnE = XLen2[`S_LEN-1]; - assign YSgnE = YLen2[`S_LEN-1]; - assign ZSgnE = ZLen2[`S_LEN-1]; + `S_BIAS: begin // if input is single percision + // extract sign bit + XSgnE = XLen2[`S_LEN-1]; + YSgnE = YLen2[`S_LEN-1]; + ZSgnE = ZLen2[`S_LEN-1]; // example double to single conversion: // 1023 = 0011 1111 1111 @@ -274,26 +366,32 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values - assign XExpE = {XLen2[`S_LEN-2], {`NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; - assign YExpE = {YLen2[`S_LEN-2], {`NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; - assign ZExpE = {ZLen2[`S_LEN-2], {`NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; + + // convert the single precsion exponent into quad precsion + XExpE = {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; + YExpE = {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; + ZExpE = {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; - assign XFracE = {XLen2[`S_NF-1:0], (`NF-`S_NF)'(0)}; - assign YFracE = {YLen2[`S_NF-1:0], (`NF-`S_NF)'(0)}; - assign ZFracE = {ZLen2[`S_NF-1:0], (`NF-`S_NF)'(0)}; + // extract the fraction and add the nessesary trailing zeros + XFracE = {XLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; + YFracE = {YLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; + ZFracE = {ZLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; - assign XExpNonzero = |XLen2[`S_LEN-2:`S_NF]; - assign YExpNonzero = |YLen2[`S_LEN-2:`S_NF]; - assign ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF]; + // is the exponent non-zero + XExpNonzero = |XLen2[`S_LEN-2:`S_NF]; + YExpNonzero = |YLen2[`S_LEN-2:`S_NF]; + ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF]; - assign XExpMaxE = &XLen2[`S_LEN-2:`S_NF]; - assign YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; - assign ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; + // is the exponent all 1's + XExpMaxE = &XLen2[`S_LEN-2:`S_NF]; + YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; + ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; end - 2'b10: begin - assign XSgnE = XLen3[`H_LEN-1]; - assign YSgnE = YLen3[`H_LEN-1]; - assign ZSgnE = ZLen3[`H_LEN-1]; + `H_BIAS: begin // if input is half percision + // extract sign bit + XSgnE = XLen3[`H_LEN-1]; + YSgnE = YLen3[`H_LEN-1]; + ZSgnE = ZLen3[`H_LEN-1]; // example double to single conversion: // 1023 = 0011 1111 1111 @@ -302,58 +400,72 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values - assign XExpE = {XLen3[`H_LEN-2], {`NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; - assign YExpE = {YLen3[`H_LEN-2], {`NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; - assign ZExpE = {ZLen3[`H_LEN-2], {`NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; + + // convert the half precsion exponent into quad precsion + XExpE = {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; + YExpE = {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; + ZExpE = {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; - assign XFracE = {XLen3[`H_NF-1:0], (`NF-`H_NF)'(0)}; - assign YFracE = {YLen3[`H_NF-1:0], (`NF-`H_NF)'(0)}; - assign ZFracE = {ZLen3[`H_NF-1:0], (`NF-`H_NF)'(0)}; + // extract the fraction and add the nessesary trailing zeros + XFracE = {XLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; + YFracE = {YLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; + ZFracE = {ZLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; - assign XExpNonzero = |XLen3[`H_LEN-2:`H_NF]; - assign YExpNonzero = |YLen3[`H_LEN-2:`H_NF]; - assign ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF]; + // is the exponent non-zero + XExpNonzero = |XLen3[`H_LEN-2:`H_NF]; + YExpNonzero = |YLen3[`H_LEN-2:`H_NF]; + ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF]; - assign XExpMaxE = &XLen3[`H_LEN-2:`H_NF]; - assign YExpMaxE = &YLen3[`H_LEN-2:`H_NF]; - assign ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF]; + // is the exponent all 1's + XExpMaxE = &XLen3[`H_LEN-2:`H_NF]; + YExpMaxE = &YLen3[`H_LEN-2:`H_NF]; + ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF]; end endcase end end + // is the exponent all 0's assign XExpZero = ~XExpNonzero; assign YExpZero = ~YExpNonzero; assign ZExpZero = ~ZExpNonzero; + // is the fraction zero assign XFracZero = ~|XFracE; assign YFracZero = ~|YFracE; assign ZFracZero = ~|ZFracE; + // add the assumed one (or zero if denormal or zero) to create the mantissa assign XManE = {XExpNonzero, XFracE}; assign YManE = {YExpNonzero, YFracE}; assign ZManE = {ZExpNonzero, ZFracE}; + // is X normalized assign XNormE = ~(XExpMaxE|XExpZero); - // force single precision input to be a NaN if it isn't properly Nan Boxed + // is the input a NaN + // - force to be a NaN if it isn't properly Nan Boxed assign XNaNE = XExpMaxE & ~XFracZero; assign YNaNE = YExpMaxE & ~YFracZero; assign ZNaNE = ZExpMaxE & ~ZFracZero; + // is the input a singnaling NaN assign XSNaNE = XNaNE&~XFracE[`NF-1]; assign YSNaNE = YNaNE&~YFracE[`NF-1]; assign ZSNaNE = ZNaNE&~ZFracE[`NF-1]; + // is the input denormalized assign XDenormE = XExpZero & ~XFracZero; assign YDenormE = YExpZero & ~YFracZero; assign ZDenormE = ZExpZero & ~ZFracZero; + // is the input infinity assign XInfE = XExpMaxE & XFracZero; assign YInfE = YExpMaxE & YFracZero; assign ZInfE = ZExpMaxE & ZFracZero; + // is the input zero assign XZeroE = XExpZero & XFracZero; assign YZeroE = YExpZero & YFracZero; assign ZZeroE = ZExpZero & ZFracZero; From 4ca94585341cb714b3333007a59fe5c8b75af192 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Mar 2022 21:28:34 -0500 Subject: [PATCH 180/199] added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP. --- .../testvector-generation/parseGDBtoTrace.py | 4 +- linux/testvector-generation/parseState.py | 2 +- pipelined/testbench/testbench-linux.sv | 69 +++++++++++++++++-- 3 files changed, 68 insertions(+), 7 deletions(-) diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py index db444f696..412db5bb5 100755 --- a/linux/testvector-generation/parseGDBtoTrace.py +++ b/linux/testvector-generation/parseGDBtoTrace.py @@ -138,9 +138,9 @@ if len(sys.argv) != 2: sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n >') interruptFname = sys.argv[1] # reg number -RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45} +RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45, 'sstatus': 46, 'sip': 47, 'sie': 48} # initial state -CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None] +CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0, 'sstatus': 0, 'sip': 0, 'sie': 0}, {}, None, None, None] #with open (InputFile, 'r') as InputFileFP: #lines = InputFileFP.readlines() diff --git a/linux/testvector-generation/parseState.py b/linux/testvector-generation/parseState.py index abc36fb2f..1f7e93c09 100755 --- a/linux/testvector-generation/parseState.py +++ b/linux/testvector-generation/parseState.py @@ -34,7 +34,7 @@ stateGDBpath = outDir+'stateGDB.txt' if not os.path.exists(stateGDBpath): sys.exit('Error input file '+stateGDBpath+'not found') -singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv'] +singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv','sie','sip','sstatus'] # priv (current privilege mode) isn't technically a CSR but we can log it with the same machinery thirtyTwoBitCSRs = ['mcounteren','scounteren'] listCSRs = ['hpmcounter','pmpaddr'] diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 82742ff4b..a85c5672c 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -141,11 +141,11 @@ module testbench; logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; `DECLARE_TRACE_SCANNER_SIGNALS(E) `DECLARE_TRACE_SCANNER_SIGNALS(M) - integer NextMIPexpected; + integer NextMIPexpected, NextSIPexpected; integer NextMepcExpected; // Memory stage expected values from trace logic checkInstrM; - integer MIPexpected; + integer MIPexpected, SIPexpected; string name; logic [`AHBW-1:0] readDataExpected; // Write back stage expected values from trace @@ -168,11 +168,14 @@ module testbench; integer NumCSRPostWIndex; logic [`XLEN-1:0] InstrCountW; integer RequestDelayedMIP; + integer RequestDelayedSIP; integer ForceMIPFuture; integer CSRIndex; longint MepcExpected; integer CheckMIPFutureE; integer CheckMIPFutureM; + integer CheckSIPFutureE; + integer CheckSIPFutureM; // Useful Aliases `define RF dut.core.ieu.dp.regf.rf `define PC dut.core.ifu.pcreg.q @@ -185,6 +188,8 @@ module testbench; `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q `define MIE `CSR_BASE.csri.MIE_REGW `define MIP `CSR_BASE.csri.MIP_REGW + `define SIE `CSR_BASE.csri.SIE_REGW + `define SIP `CSR_BASE.csri.SIP_REGW `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q `define MEPC `CSR_BASE.csrm.MEPCreg.q @@ -197,6 +202,7 @@ module testbench; `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q `define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW + `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW `define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT `define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT `define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT @@ -297,6 +303,8 @@ module testbench; `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIE, [11:0]); `INIT_CHECKPOINT_VAL(MIP, [11:0]); + `INIT_CHECKPOINT_VAL(SIE, [11:0]); + `INIT_CHECKPOINT_VAL(SIP, [11:0]); `INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]); @@ -310,6 +318,7 @@ module testbench; `INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(PRIV, [1:0]); `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0); + `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0); // Many UART registers are difficult to initialize because under the hood // they are not simple registers. Instead some are generated by interesting // combinational blocks such that they depend upon a variety of different @@ -463,6 +472,10 @@ module testbench; CheckMIPFutureE = 1; \ NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ end \ + if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "sip") begin \ + CheckSIPFutureE = 1; \ + NextSIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ + end \ if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \ // $display("hello! we are here."); \ MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \ @@ -501,6 +514,7 @@ module testbench; if(CheckMIPFutureE) CheckMIPFutureE <= 0; CheckMIPFutureM <= CheckMIPFutureE; if(CheckMIPFutureM) begin + $display("DEBUG DEBUG DEBUG DEBUG"); // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); @@ -508,9 +522,12 @@ module testbench; RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately + $display("One One One One"); $display("%tns: Updating MIP to %x",$time,NextMIPexpected); MIPexpected = NextMIPexpected; - force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; + //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; + //force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected; + force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected; end // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); @@ -524,13 +541,54 @@ module testbench; if(RequestDelayedMIP & checkInstrM) begin $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW); $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + $display("Two Two Two Two"); MIPexpected = NextMIPexpected; - force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; + //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; + //force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected; + force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected; $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW); RequestDelayedMIP = 0; end end + // SIP spoofing +/* -----\/----- EXCLUDED -----\/----- + always @(posedge clk) begin + #1; + if(CheckSIPFutureE) CheckSIPFutureE <= 0; + CheckSIPFutureM <= CheckSIPFutureE; + if(CheckSIPFutureM) begin + // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); + // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); + // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); + if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin + RequestDelayedSIP <= 1; + $display("%tns: Requesting Delayed SIP. Current MEPC value is %x",$time,MepcExpected); + end else begin // update SIP immediately + $display("%tns: Updating SIP to %x",$time,NextSIPexpected); + SIPexpected = NextSIPexpected; + force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected; + end + // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); + // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); + // $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM); + // $display("%tn: MepcExpected = %x",$time,MepcExpected); + // $display("%tn: ExpectedPCE = %x",$time,ExpectedPCE); + // $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE)); + // $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]); + // $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]); + end + if(RequestDelayedSIP & checkInstrM) begin + $display("%tns: Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW); + $display("%tns: Updating SIP to %x",$time,NextSIPexpected); + SIPexpected = NextSIPexpected; + force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected; + $display("%tns: Finished Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW); + RequestDelayedSIP = 0; + end + end + -----/\----- EXCLUDED -----/\----- */ + // step 1: register expected state into the write back stage. always @(posedge clk) begin if (reset) begin @@ -634,9 +692,12 @@ module testbench; case(ExpectedCSRArrayW[NumCSRPostWIndex]) "mhartid": `checkCSR(dut.core.priv.priv.csr.csrm.MHARTID_REGW) "mstatus": `checkCSR(dut.core.priv.priv.csr.csrm.MSTATUS_REGW) + "sstatus": `checkCSR(dut.core.priv.priv.csr.csrs.SSTATUS_REGW) "mtvec": `checkCSR(dut.core.priv.priv.csr.csrm.MTVEC_REGW) "mip": `checkCSR(dut.core.priv.priv.csr.csrm.MIP_REGW) "mie": `checkCSR(dut.core.priv.priv.csr.csrm.MIE_REGW) + "sip": `checkCSR(dut.core.priv.priv.csr.csrs.SIP_REGW) + "sie": `checkCSR(dut.core.priv.priv.csr.csrs.SIE_REGW) "mideleg": `checkCSR(dut.core.priv.priv.csr.csrm.MIDELEG_REGW) "medeleg": `checkCSR(dut.core.priv.priv.csr.csrm.MEDELEG_REGW) "mepc": `checkCSR(dut.core.priv.priv.csr.csrm.MEPC_REGW) From c233ef97682aed5c635de9f08567aca215036819 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Mar 2022 21:44:08 -0500 Subject: [PATCH 181/199] Reverted change to configuration which caused issue with lint. --- pipelined/config/shared/wally-shared.vh | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 198a4ab2e..117d745f1 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -74,8 +74,10 @@ // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits `define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) +//`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) +`define NE 11//(`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) +//`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) +`define NF 52//(`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) `define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) `define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) From 849707f1614d85f80cbfc01b756e5b45d76fdbcc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Mar 2022 22:04:06 -0500 Subject: [PATCH 182/199] Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. --- pipelined/src/privileged/csri.sv | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 974b3616f..8a3f42fdf 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -95,21 +95,20 @@ module csri #(parameter // else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // restricted views of registers - always_comb begin:regs - // Add MEIP read-only signal - IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; + // Add MEIP read-only signal + assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; // Machine Mode - MIP_REGW = IP_REGW; - MIE_REGW = IE_REGW; + assign MIP_REGW = IP_REGW; + assign MIE_REGW = IE_REGW; - // Supervisor mode - if (`S_SUPPORTED) begin - SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible - SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; - end else begin - SIP_REGW = 12'b0; - SIE_REGW = 12'b0; - end + // Supervisor mode + if (`S_SUPPORTED) begin + assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible + assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; + end else begin + assign SIP_REGW = 12'b0; + assign SIE_REGW = 12'b0; end + endmodule From fcd23a006e1f59c729532926a341f111d8e03fc2 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Wed, 23 Mar 2022 03:24:41 +0000 Subject: [PATCH 183/199] fixed lint error in fpudivsqrtrecur.sv --- pipelined/src/fpu/fpudivsqrtrecur.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/fpu/fpudivsqrtrecur.sv b/pipelined/src/fpu/fpudivsqrtrecur.sv index fd47d2d87..62a441367 100644 --- a/pipelined/src/fpu/fpudivsqrtrecur.sv +++ b/pipelined/src/fpu/fpudivsqrtrecur.sv @@ -64,8 +64,8 @@ module fpudivsqrtrecur ( always_comb begin if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one - else if (FDivE & YZeroE | XInfE) FDivSqrtResM = {FDivSqrtResSgn, `NE'b1, `NF'b0}; // infinity - else if (FDivE & YInfE) FDivSqrtResM = {FDivSqrtResSgn, `NE'b0, `NF'b0}; // zero + else if (FDivE & YZeroE | XInfE) FDivSqrtResM = {FDivSqrtResSgn, (`NE)'(1), (`NF)'(0)}; // infinity + else if (FDivE & YInfE) FDivSqrtResM = {FDivSqrtResSgn, (`NE)'(0), (`NF)'(0)}; // zero else FDivSqrtResM = FDivSqrtRecurRes; end From 33b9b5423dd469c16ae2fcbff3b5ec4c9c3cb568 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Mar 2022 22:31:34 -0500 Subject: [PATCH 184/199] reverted temporary change to configs. --- pipelined/config/shared/wally-shared.vh | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 117d745f1..198a4ab2e 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -74,10 +74,8 @@ // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits `define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) -//`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -`define NE 11//(`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -//`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define NF 52//(`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) +`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) `define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) `define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) From aa60b57fb39cb6a89826638827b3987c34999f70 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Mar 2022 22:34:38 -0500 Subject: [PATCH 185/199] Cleanup in testbench-linux.sv. --- pipelined/testbench/testbench-linux.sv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index a85c5672c..62d13a1a3 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -514,15 +514,14 @@ module testbench; if(CheckMIPFutureE) CheckMIPFutureE <= 0; CheckMIPFutureM <= CheckMIPFutureE; if(CheckMIPFutureM) begin - $display("DEBUG DEBUG DEBUG DEBUG"); // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); + // *** this is probably not right anymore since either MIP or SIP can be forced. if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately - $display("One One One One"); $display("%tns: Updating MIP to %x",$time,NextMIPexpected); MIPexpected = NextMIPexpected; //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; @@ -541,7 +540,6 @@ module testbench; if(RequestDelayedMIP & checkInstrM) begin $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW); $display("%tns: Updating MIP to %x",$time,NextMIPexpected); - $display("Two Two Two Two"); MIPexpected = NextMIPexpected; //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; //force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected; From af435ab59192e6f3cd5a7a013e6d5fe3edb0b6c6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Mar 2022 10:26:17 -0500 Subject: [PATCH 186/199] Another change required for forcing to work correctly with MIE/MIP and SIE/SIP. --- pipelined/src/privileged/csri.sv | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 8a3f42fdf..b3f0f157b 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -95,20 +95,22 @@ module csri #(parameter // else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // restricted views of registers - // Add MEIP read-only signal - assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; + assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; + + always_comb begin:regs + // Add MEIP read-only signal // Machine Mode - assign MIP_REGW = IP_REGW; - assign MIE_REGW = IE_REGW; + MIP_REGW = IP_REGW; + MIE_REGW = IE_REGW; - // Supervisor mode - if (`S_SUPPORTED) begin - assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible - assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; - end else begin - assign SIP_REGW = 12'b0; - assign SIE_REGW = 12'b0; + // Supervisor mode + if (`S_SUPPORTED) begin + SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible + SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; + end else begin + SIP_REGW = 12'b0; + SIE_REGW = 12'b0; + end end - endmodule From 7cf994526ac4699374a16904312167aee9f20908 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Wed, 23 Mar 2022 18:26:59 +0000 Subject: [PATCH 187/199] fixed typo in unpack.sv --- pipelined/src/fpu/fma.sv | 352 ++++++++++++++++++------------------ pipelined/src/fpu/unpack.sv | 8 +- 2 files changed, 180 insertions(+), 180 deletions(-) diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 2b2a6b9ed..8d1ae344a 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -186,20 +186,20 @@ module expadd( end else if (`FPSIZES == 3) begin always_comb begin case (FmtE) - `FMT: assign Denorm = 1; - `FMT1: assign Denorm = `BIAS-`BIAS1+1; - `FMT2: assign Denorm = `BIAS-`BIAS2+1; - default: assign Denorm = 1'bx; + `FMT: Denorm = 1; + `FMT1: Denorm = `BIAS-`BIAS1+1; + `FMT2: Denorm = `BIAS-`BIAS2+1; + default: Denorm = 1'bx; endcase end end else begin always_comb begin case (FmtE) - 2'h3: assign Denorm = 1; - 2'h1: assign Denorm = `BIAS-`D_BIAS+1; - 2'h0: assign Denorm = `BIAS-`S_BIAS+1; - 2'h2: assign Denorm = `BIAS-`H_BIAS+1; + 2'h3: Denorm = 1; + 2'h1: Denorm = `BIAS-`D_BIAS+1; + 2'h0: Denorm = `BIAS-`S_BIAS+1; + 2'h2: Denorm = `BIAS-`H_BIAS+1; endcase end @@ -612,20 +612,20 @@ module normalize( end else if (`FPSIZES == 3) begin always_comb begin case (FmtM) - `FMT: assign SumExpTmp = SumExpTmpTmp; - `FMT1: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS1)&{`NE+2{|SumExpTmpTmp}}; - `FMT2: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS2)&{`NE+2{|SumExpTmpTmp}}; - default: assign SumExpTmp = `NE+2'bx; + `FMT: SumExpTmp = SumExpTmpTmp; + `FMT1: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS1)&{`NE+2{|SumExpTmpTmp}}; + `FMT2: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS2)&{`NE+2{|SumExpTmpTmp}}; + default: SumExpTmp = `NE+2'bx; endcase end end else begin always_comb begin case (FmtM) - 2'h3: assign SumExpTmp = SumExpTmpTmp; - 2'h1: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`D_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h0: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`S_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h2: assign SumExpTmp = (SumExpTmpTmp-`BIAS+`H_BIAS)&{`NE+2{|SumExpTmpTmp}}; + 2'h3: SumExpTmp = SumExpTmpTmp; + 2'h1: SumExpTmp = (SumExpTmpTmp-`BIAS+`D_BIAS)&{`NE+2{|SumExpTmpTmp}}; + 2'h0: SumExpTmp = (SumExpTmpTmp-`BIAS+`S_BIAS)&{`NE+2{|SumExpTmpTmp}}; + 2'h2: SumExpTmp = (SumExpTmpTmp-`BIAS+`H_BIAS)&{`NE+2{|SumExpTmpTmp}}; endcase end @@ -657,10 +657,10 @@ module normalize( assign Sum2GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF2+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`BIAS2)) | ~|SumExpTmpTmp; always_comb begin case (FmtM) - `FMT: assign PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; - `FMT1: assign PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; - `FMT2: assign PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; - default: assign PreResultDenorm = 1'bx; + `FMT: PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; + `FMT1: PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; + `FMT2: PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; + default: PreResultDenorm = 1'bx; endcase end @@ -676,10 +676,10 @@ module normalize( assign Sum3GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`H_NF+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`H_BIAS)) | ~|SumExpTmpTmp; always_comb begin case (FmtM) - 2'h3: assign PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; - 2'h1: assign PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; - 2'h0: assign PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; - 2'h2: assign PreResultDenorm = Sum3LEZ & Sum3GEFL & ~SumZero; + 2'h3: PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; + 2'h1: PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; + 2'h0: PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; + 2'h2: PreResultDenorm = Sum3LEZ & Sum3GEFL & ~SumZero; endcase end @@ -830,48 +830,48 @@ module fmaround( case (FmtM) `FMT: begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[2]; - assign Round = NormSum[1]; - assign LSBNormSum = NormSum[3]; + Guard = NormSum[2]; + Round = NormSum[1]; + LSBNormSum = NormSum[3]; // used to determine underflow flag - assign UfGuard = NormSum[1]; - assign UfRound = NormSum[0]; - assign UfLSBNormSum = NormSum[2]; + UfGuard = NormSum[1]; + UfRound = NormSum[0]; + UfLSBNormSum = NormSum[2]; // determine sticky - assign Sticky = UfSticky | NormSum[0]; + Sticky = UfSticky | NormSum[0]; end `FMT1: begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[`NF-`NF1+2]; - assign Round = NormSum[`NF-`NF1+1]; - assign LSBNormSum = NormSum[`NF-`NF1+3]; + Guard = NormSum[`NF-`NF1+2]; + Round = NormSum[`NF-`NF1+1]; + LSBNormSum = NormSum[`NF-`NF1+3]; // used to determine underflow flag - assign UfGuard = NormSum[`NF-`NF1+1]; - assign UfRound = NormSum[`NF-`NF1]; - assign UfLSBNormSum = NormSum[`NF-`NF1+2]; + UfGuard = NormSum[`NF-`NF1+1]; + UfRound = NormSum[`NF-`NF1]; + UfLSBNormSum = NormSum[`NF-`NF1+2]; // determine sticky - assign Sticky = UfSticky | NormSum[`NF-`NF1]; + Sticky = UfSticky | NormSum[`NF-`NF1]; end `FMT2: begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[`NF-`NF2+2]; - assign Round = NormSum[`NF-`NF2+1]; - assign LSBNormSum = NormSum[`NF-`NF2+3]; + Guard = NormSum[`NF-`NF2+2]; + Round = NormSum[`NF-`NF2+1]; + LSBNormSum = NormSum[`NF-`NF2+3]; // used to determine underflow flag - assign UfGuard = NormSum[`NF-`NF2+1]; - assign UfRound = NormSum[`NF-`NF2]; - assign UfLSBNormSum = NormSum[`NF-`NF2+2]; + UfGuard = NormSum[`NF-`NF2+1]; + UfRound = NormSum[`NF-`NF2]; + UfLSBNormSum = NormSum[`NF-`NF2+2]; // determine sticky - assign Sticky = UfSticky | NormSum[`NF-`NF2]; + Sticky = UfSticky | NormSum[`NF-`NF2]; end default: begin - assign Guard = 1'bx; - assign Round = 1'bx; - assign LSBNormSum = 1'bx; - assign UfGuard = 1'bx; - assign UfRound = 1'bx; - assign UfLSBNormSum = 1'bx; - assign Sticky = 1'bx; + Guard = 1'bx; + Round = 1'bx; + LSBNormSum = 1'bx; + UfGuard = 1'bx; + UfRound = 1'bx; + UfLSBNormSum = 1'bx; + Sticky = 1'bx; end endcase end @@ -881,51 +881,51 @@ module fmaround( case (FmtM) 2'h3: begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[2]; - assign Round = NormSum[1]; - assign LSBNormSum = NormSum[3]; + Guard = NormSum[2]; + Round = NormSum[1]; + LSBNormSum = NormSum[3]; // used to determine underflow flag - assign UfGuard = NormSum[1]; - assign UfRound = NormSum[0]; - assign UfLSBNormSum = NormSum[2]; + UfGuard = NormSum[1]; + UfRound = NormSum[0]; + UfLSBNormSum = NormSum[2]; // determine sticky - assign Sticky = UfSticky | NormSum[0]; + Sticky = UfSticky | NormSum[0]; end 2'h1: begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[`NF-`D_NF+2]; - assign Round = NormSum[`NF-`D_NF+1]; - assign LSBNormSum = NormSum[`NF-`D_NF+3]; + Guard = NormSum[`NF-`D_NF+2]; + Round = NormSum[`NF-`D_NF+1]; + LSBNormSum = NormSum[`NF-`D_NF+3]; // used to determine underflow flag - assign UfGuard = NormSum[`NF-`D_NF+1]; - assign UfRound = NormSum[`NF-`D_NF]; - assign UfLSBNormSum = NormSum[`NF-`D_NF+2]; + UfGuard = NormSum[`NF-`D_NF+1]; + UfRound = NormSum[`NF-`D_NF]; + UfLSBNormSum = NormSum[`NF-`D_NF+2]; // determine sticky - assign Sticky = UfSticky | NormSum[`NF-`D_NF]; + Sticky = UfSticky | NormSum[`NF-`D_NF]; end 2'h0: begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[`NF-`S_NF+2]; - assign Round = NormSum[`NF-`S_NF+1]; - assign LSBNormSum = NormSum[`NF-`S_NF+3]; + Guard = NormSum[`NF-`S_NF+2]; + Round = NormSum[`NF-`S_NF+1]; + LSBNormSum = NormSum[`NF-`S_NF+3]; // used to determine underflow flag - assign UfGuard = NormSum[`NF-`S_NF+1]; - assign UfRound = NormSum[`NF-`S_NF]; - assign UfLSBNormSum = NormSum[`NF-`S_NF+2]; + UfGuard = NormSum[`NF-`S_NF+1]; + UfRound = NormSum[`NF-`S_NF]; + UfLSBNormSum = NormSum[`NF-`S_NF+2]; // determine sticky - assign Sticky = UfSticky | NormSum[`NF-`S_NF]; + Sticky = UfSticky | NormSum[`NF-`S_NF]; end 2'h2: begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[`NF-`H_NF+2]; - assign Round = NormSum[`NF-`H_NF+1]; - assign LSBNormSum = NormSum[`NF-`H_NF+3]; + Guard = NormSum[`NF-`H_NF+2]; + Round = NormSum[`NF-`H_NF+1]; + LSBNormSum = NormSum[`NF-`H_NF+3]; // used to determine underflow flag - assign UfGuard = NormSum[`NF-`H_NF+1]; - assign UfRound = NormSum[`NF-`H_NF]; - assign UfLSBNormSum = NormSum[`NF-`H_NF+2]; + UfGuard = NormSum[`NF-`H_NF+1]; + UfRound = NormSum[`NF-`H_NF]; + UfLSBNormSum = NormSum[`NF-`H_NF+2]; // determine sticky - assign Sticky = UfSticky | NormSum[`NF-`H_NF]; + Sticky = UfSticky | NormSum[`NF-`H_NF]; end endcase end @@ -988,20 +988,20 @@ module fmaround( end else if (`FPSIZES == 3) begin always_comb begin case (FmtM) - `FMT: assign RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; - `FMT1: assign RoundAdd = Minus1 ? {{`NE+2+`NF1{1'b1}}, (`FLEN-1-`NE-`NF1)'(0)} : {(`NE+1+`NF1)'(0), Plus1, (`FLEN-1-`NE-`NF1)'(0)}; - `FMT2: assign RoundAdd = Minus1 ? {{`NE+2+`NF2{1'b1}}, (`FLEN-1-`NE-`NF2)'(0)} : {(`NE+1+`NF2)'(0), Plus1, (`FLEN-1-`NE-`NF2)'(0)}; - default: assign RoundAdd = (`FLEN+1)'(0); + `FMT: RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; + `FMT1: RoundAdd = Minus1 ? {{`NE+2+`NF1{1'b1}}, (`FLEN-1-`NE-`NF1)'(0)} : {(`NE+1+`NF1)'(0), Plus1, (`FLEN-1-`NE-`NF1)'(0)}; + `FMT2: RoundAdd = Minus1 ? {{`NE+2+`NF2{1'b1}}, (`FLEN-1-`NE-`NF2)'(0)} : {(`NE+1+`NF2)'(0), Plus1, (`FLEN-1-`NE-`NF2)'(0)}; + default: RoundAdd = (`FLEN+1)'(0); endcase end end else begin always_comb begin case (FmtM) - 2'h3: assign RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; - 2'h1: assign RoundAdd = Minus1 ? {{`NE+2+`D_NF{1'b1}}, (`FLEN-1-`NE-`D_NF)'(0)} : {(`NE+1+`D_NF)'(0), Plus1, (`FLEN-1-`NE-`D_NF)'(0)}; - 2'h0: assign RoundAdd = Minus1 ? {{`NE+2+`S_NF{1'b1}}, (`FLEN-1-`NE-`S_NF)'(0)} : {(`NE+1+`S_NF)'(0), Plus1, (`FLEN-1-`NE-`S_NF)'(0)}; - 2'h2: assign RoundAdd = Minus1 ? {{`NE+2+`H_NF{1'b1}}, (`FLEN-1-`NE-`H_NF)'(0)} : {(`NE+1+`H_NF)'(0), Plus1, (`FLEN-1-`NE-`H_NF)'(0)}; + 2'h3: RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; + 2'h1: RoundAdd = Minus1 ? {{`NE+2+`D_NF{1'b1}}, (`FLEN-1-`NE-`D_NF)'(0)} : {(`NE+1+`D_NF)'(0), Plus1, (`FLEN-1-`NE-`D_NF)'(0)}; + 2'h0: RoundAdd = Minus1 ? {{`NE+2+`S_NF{1'b1}}, (`FLEN-1-`NE-`S_NF)'(0)} : {(`NE+1+`S_NF)'(0), Plus1, (`FLEN-1-`NE-`S_NF)'(0)}; + 2'h2: RoundAdd = Minus1 ? {{`NE+2+`H_NF{1'b1}}, (`FLEN-1-`NE-`H_NF)'(0)} : {(`NE+1+`H_NF)'(0), Plus1, (`FLEN-1-`NE-`H_NF)'(0)}; endcase end @@ -1056,20 +1056,20 @@ module fmaflags( end else if (`FPSIZES == 3) begin always_comb begin case (FmtM) - `FMT: assign GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; - `FMT1: assign GtMaxExp = &FullResultExp[`NE1-1:0] | FullResultExp[`NE1]; - `FMT2: assign GtMaxExp = &FullResultExp[`NE2-1:0] | FullResultExp[`NE2]; - default: assign GtMaxExp = 1'bx; + `FMT: GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; + `FMT1: GtMaxExp = &FullResultExp[`NE1-1:0] | FullResultExp[`NE1]; + `FMT2: GtMaxExp = &FullResultExp[`NE2-1:0] | FullResultExp[`NE2]; + default: GtMaxExp = 1'bx; endcase end end else begin always_comb begin case (FmtM) - 2'h3: assign GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; - 2'h1: assign GtMaxExp = &FullResultExp[`D_NE-1:0] | FullResultExp[`D_NE]; - 2'h0: assign GtMaxExp = &FullResultExp[`S_NE-1:0] | FullResultExp[`S_NE]; - 2'h2: assign GtMaxExp = &FullResultExp[`H_NE-1:0] | FullResultExp[`H_NE]; + 2'h3: GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; + 2'h1: GtMaxExp = &FullResultExp[`D_NE-1:0] | FullResultExp[`D_NE]; + 2'h0: GtMaxExp = &FullResultExp[`S_NE-1:0] | FullResultExp[`S_NE]; + 2'h2: GtMaxExp = &FullResultExp[`H_NE-1:0] | FullResultExp[`H_NE]; endcase end @@ -1157,68 +1157,68 @@ module resultselect( case (FmtM) `FMT: begin if(`IEEE754) begin - assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; - assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; - assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; + YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; + ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; + InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin - assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - assign KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; - assign UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; - assign InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; - assign NormResult = {ResultSgn, ResultExp, ResultFrac}; + KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; + InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; + NormResult = {ResultSgn, ResultExp, ResultFrac}; end `FMT1: begin if(`IEEE754) begin - assign XNaNResult = {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; - assign YNaNResult = {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; - assign ZNaNResult = {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; - assign InvalidResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + XNaNResult = {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; + YNaNResult = {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; + ZNaNResult = {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; + InvalidResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end else begin - assign XNaNResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + XNaNResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : + OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - assign KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; - assign UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - assign InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - assign NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; + KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; + NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; end `FMT2: begin if(`IEEE754) begin - assign XNaNResult = {{`FLEN-`LEN2{1'b1}}, XSgnM, {`NE2{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF2]}; - assign YNaNResult = {{`FLEN-`LEN2{1'b1}}, YSgnM, {`NE2{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF2]}; - assign ZNaNResult = {{`FLEN-`LEN2{1'b1}}, ZSgnEffM, {`NE2{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF2]}; - assign InvalidResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + XNaNResult = {{`FLEN-`LEN2{1'b1}}, XSgnM, {`NE2{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF2]}; + YNaNResult = {{`FLEN-`LEN2{1'b1}}, YSgnM, {`NE2{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF2]}; + ZNaNResult = {{`FLEN-`LEN2{1'b1}}, ZSgnEffM, {`NE2{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF2]}; + InvalidResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; end else begin - assign XNaNResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + XNaNResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : + OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, (`NF2)'(0)}; - assign KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; - assign UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - assign InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)}; - assign NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]}; + KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; + UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)}; + NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]}; end default: begin if(`IEEE754) begin - assign XNaNResult = (`FLEN)'(0); - assign YNaNResult = (`FLEN)'(0); - assign ZNaNResult = (`FLEN)'(0); - assign InvalidResult = (`FLEN)'(0); + XNaNResult = (`FLEN)'(0); + YNaNResult = (`FLEN)'(0); + ZNaNResult = (`FLEN)'(0); + InvalidResult = (`FLEN)'(0); end else begin - assign XNaNResult = (`FLEN)'(0); + XNaNResult = (`FLEN)'(0); end - assign OverflowResult = (`FLEN)'(0); - assign KillProdResult = (`FLEN)'(0); - assign UnderflowResult = (`FLEN)'(0); - assign InfResult = (`FLEN)'(0); - assign NormResult = (`FLEN)'(0); + OverflowResult = (`FLEN)'(0); + KillProdResult = (`FLEN)'(0); + UnderflowResult = (`FLEN)'(0); + InfResult = (`FLEN)'(0); + NormResult = (`FLEN)'(0); end endcase end @@ -1228,71 +1228,71 @@ module resultselect( case (FmtM) 2'h3: begin if(`IEEE754) begin - assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; - assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; - assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; + YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; + ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; + InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin - assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - assign KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; - assign UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; - assign InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; - assign NormResult = {ResultSgn, ResultExp, ResultFrac}; + KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; + UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; + InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; + NormResult = {ResultSgn, ResultExp, ResultFrac}; end 2'h1: begin if(`IEEE754) begin - assign XNaNResult = {{`FLEN-`D_LEN{1'b1}}, XSgnM, {`D_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`D_NF]}; - assign YNaNResult = {{`FLEN-`D_LEN{1'b1}}, YSgnM, {`D_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`D_NF]}; - assign ZNaNResult = {{`FLEN-`D_LEN{1'b1}}, ZSgnEffM, {`D_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`D_NF]}; - assign InvalidResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + XNaNResult = {{`FLEN-`D_LEN{1'b1}}, XSgnM, {`D_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`D_NF]}; + YNaNResult = {{`FLEN-`D_LEN{1'b1}}, YSgnM, {`D_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`D_NF]}; + ZNaNResult = {{`FLEN-`D_LEN{1'b1}}, ZSgnEffM, {`D_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`D_NF]}; + InvalidResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; end else begin - assign XNaNResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + XNaNResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : + OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; - assign KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:0], ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; - assign UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - assign InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; - assign NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]}; + KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:0], ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; + UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; + NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]}; end 2'h0: begin if(`IEEE754) begin - assign XNaNResult = {{`FLEN-`S_LEN{1'b1}}, XSgnM, {`S_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`S_NF]}; - assign YNaNResult = {{`FLEN-`S_LEN{1'b1}}, YSgnM, {`S_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`S_NF]}; - assign ZNaNResult = {{`FLEN-`S_LEN{1'b1}}, ZSgnEffM, {`S_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`S_NF]}; - assign InvalidResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + XNaNResult = {{`FLEN-`S_LEN{1'b1}}, XSgnM, {`S_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`S_NF]}; + YNaNResult = {{`FLEN-`S_LEN{1'b1}}, YSgnM, {`S_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`S_NF]}; + ZNaNResult = {{`FLEN-`S_LEN{1'b1}}, ZSgnEffM, {`S_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`S_NF]}; + InvalidResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; end else begin - assign XNaNResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + XNaNResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : + OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; - assign KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; - assign UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - assign InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; - assign NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]}; + KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; + UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; + NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]}; end 2'h2: begin if(`IEEE754) begin - assign XNaNResult = {{`FLEN-`H_LEN{1'b1}}, XSgnM, {`H_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`H_NF]}; - assign YNaNResult = {{`FLEN-`H_LEN{1'b1}}, YSgnM, {`H_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`H_NF]}; - assign ZNaNResult = {{`FLEN-`H_LEN{1'b1}}, ZSgnEffM, {`H_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`H_NF]}; - assign InvalidResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + XNaNResult = {{`FLEN-`H_LEN{1'b1}}, XSgnM, {`H_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`H_NF]}; + YNaNResult = {{`FLEN-`H_LEN{1'b1}}, YSgnM, {`H_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`H_NF]}; + ZNaNResult = {{`FLEN-`H_LEN{1'b1}}, ZSgnEffM, {`H_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`H_NF]}; + InvalidResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; end else begin - assign XNaNResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + XNaNResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : + OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; - assign KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:0], ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; - assign UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - assign InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; - assign NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]}; + KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:0], ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; + UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; + NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]}; end endcase end diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 1625b2fc2..3041cd72f 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -293,7 +293,7 @@ module unpack ( always_comb begin case (FmtE) - `Q_BIAS: begin // if input is quad percision + 2'b11: begin // if input is quad percision // extract sign bit XSgnE = X[`Q_LEN-1]; YSgnE = Y[`Q_LEN-1]; @@ -319,7 +319,7 @@ module unpack ( YExpMaxE = &Y[`Q_LEN-2:`Q_NF]; ZExpMaxE = &Z[`Q_LEN-2:`Q_NF]; end - `D_BIAS: begin // if input is double percision + 2'b01: begin // if input is double percision // extract sign bit XSgnE = XLen1[`D_LEN-1]; YSgnE = YLen1[`D_LEN-1]; @@ -353,7 +353,7 @@ module unpack ( YExpMaxE = &YLen1[`D_LEN-2:`D_NE]; ZExpMaxE = &ZLen1[`D_LEN-2:`D_NE]; end - `S_BIAS: begin // if input is single percision + 2'b00: begin // if input is single percision // extract sign bit XSgnE = XLen2[`S_LEN-1]; YSgnE = YLen2[`S_LEN-1]; @@ -387,7 +387,7 @@ module unpack ( YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; end - `H_BIAS: begin // if input is half percision + 2'b10: begin // if input is half percision // extract sign bit XSgnE = XLen3[`H_LEN-1]; YSgnE = YLen3[`H_LEN-1]; From 71aad2d213437bf213f2982297094eceed552994 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Mar 2022 14:17:59 -0500 Subject: [PATCH 188/199] Moved WriteDataM register into LSU. --- pipelined/src/ieu/datapath.sv | 4 +--- pipelined/src/ieu/ieu.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 4 +++- pipelined/src/wally/wallypipelinedcore.sv | 6 +++--- pipelined/testbench/testbench-linux.sv | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 52c0dc208..8178f1656 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -55,7 +55,7 @@ module datapath ( input logic FWriteIntM, input logic [`XLEN-1:0] FIntResM, output logic [`XLEN-1:0] SrcAM, - output logic [`XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] WriteDataE, // Writeback stage signals input logic StallW, FlushW, (* mark_debug = "true" *) input logic RegWriteW, @@ -83,7 +83,6 @@ module datapath ( logic [`XLEN-1:0] SrcAE2, SrcBE2; logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; - logic [`XLEN-1:0] WriteDataE; // Memory stage signals logic [`XLEN-1:0] IEUResultM; logic [`XLEN-1:0] IFResultM; @@ -119,7 +118,6 @@ module datapath ( // Memory stage pipeline register flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM); - flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); // Writeback stage pipeline register and logic diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 8f85f7596..a10d1f92f 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -52,7 +52,7 @@ module ieu ( output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU - output logic [`XLEN-1:0] WriteDataM, // Address and write data to LSU + output logic [`XLEN-1:0] WriteDataE, // Address and write data to LSU output logic [2:0] Funct3M, // size and signedness to LSU output logic [`XLEN-1:0] SrcAM, // to privilege and fpu @@ -106,7 +106,7 @@ module ieu ( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE, .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, - .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, + .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE, .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, .CSRReadValW, .ReadDataM, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 5f1c31ea9..7442aea70 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -50,7 +50,7 @@ module lsu ( // address and write data input logic [`XLEN-1:0] IEUAdrE, (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM, - input logic [`XLEN-1:0] WriteDataM, + input logic [`XLEN-1:0] WriteDataE, output logic [`XLEN-1:0] ReadDataM, // cpu privilege input logic [1:0] PrivilegeModeW, @@ -105,10 +105,12 @@ module lsu ( logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; logic [(`XLEN-1)/8:0] ByteMaskM; + logic [`XLEN-1:0] WriteDataM; // *** TO DO: Burst mode flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); + flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); assign IEUAdrExtM = {2'b00, IEUAdrM}; assign LSUStallM = DCacheStallM | InterlockStall | BusStall; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index c8be1116b..336e73f44 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -127,7 +127,7 @@ module wallypipelinedcore ( // cpu lsu interface logic [2:0] Funct3M; logic [`XLEN-1:0] IEUAdrE; - (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM; + (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataE; (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; logic [`XLEN-1:0] ReadDataW; @@ -223,7 +223,7 @@ module wallypipelinedcore ( .MemRWM, // read/write control goes to LSU .AtomicE, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU - .WriteDataM, // Write data to LSU + .WriteDataE, // Write data to LSU .Funct3M, // size and signedness to LSU .SrcAM, // to privilege and fpu .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, @@ -252,7 +252,7 @@ module wallypipelinedcore ( .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, //.DataMisalignedM(DataMisalignedM), - .IEUAdrE, .IEUAdrM, .WriteDataM, + .IEUAdrE, .IEUAdrM, .WriteDataE, .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 62d13a1a3..6044d124d 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -101,7 +101,7 @@ module testbench; flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW); flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); - flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.WriteDataM, WriteDataW); + flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); /////////////////////////////////////////////////////////////////////////////// From 4b376e2834008b21c32afca1a27f39075dd8380b Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 24 Mar 2022 17:08:10 -0700 Subject: [PATCH 189/199] 1st attempt at multiple channel PLIC --- linux/testvector-generation/genCheckpoint.sh | 6 +- linux/testvector-generation/parsePlicState.py | 24 +- pipelined/src/privileged/csr.sv | 14 +- pipelined/src/privileged/csri.sv | 30 +- pipelined/src/privileged/privileged.sv | 4 +- pipelined/src/uncore/plic.sv | 229 +++++++++------ pipelined/src/uncore/uncore.sv | 5 +- pipelined/src/wally/wallypipelinedcore.sv | 268 +++++++++--------- pipelined/src/wally/wallypipelinedsoc.sv | 6 +- pipelined/testbench/testbench-linux.sv | 4 +- 10 files changed, 325 insertions(+), 265 deletions(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 8f4d0a111..dea4d5551 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -101,10 +101,12 @@ then set logging on # Priority Levels for sources 1 thru 63 x/63xw 0x0C000004 - # Interrupt Enables + # Interrupt Enables for sources 1 thru 63 for contexts 0 and 1 x/2xw 0x0C020000 - # Global Priority Threshold + x/2xw 0x0C020080 + # Global Priority Threshold for contexts 0 and 1 x/1xw 0x0C200000 + x/1xw 0x0C201000 set logging off shell echo \"GDB storing RAM to $rawRamFile\" dump binary memory $rawRamFile 0x80000000 0xffffffff diff --git a/linux/testvector-generation/parsePlicState.py b/linux/testvector-generation/parsePlicState.py index a3c3787c8..35ef00b1d 100755 --- a/linux/testvector-generation/parsePlicState.py +++ b/linux/testvector-generation/parsePlicState.py @@ -1,5 +1,6 @@ #! /usr/bin/python3 import sys, os +from functools import reduce ################ # Helper Funcs # @@ -21,6 +22,9 @@ def tokenize(string): token = token + char return tokens +def strip0x(num): + return num[2:] + def stripZeroes(num): num = num.strip('0') if num=='': @@ -42,7 +46,7 @@ if not os.path.exists(rawPlicStateFile): sys.exit('Error input file '+rawPlicStateFile+'not found') with open(rawPlicStateFile, 'r') as rawPlicStateFile: - plicIntPriorityArray=[] + plicIntPriorityArray = [] # iterates over number of different sources # 0x0C000004 thru 0x0C000010 plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] # 0x0C000014 thru 0x0C000020 @@ -76,20 +80,30 @@ with open(rawPlicStateFile, 'r') as rawPlicStateFile: # 0x0C0000f4 thru 0x0C0000fc plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + plicIntEnableArray = [] # iterates over number of different contexts # 0x0C020000 thru 0x0C020004 plicIntEnable = tokenize(rawPlicStateFile.readline())[1:] + plicIntEnable = map(strip0x,plicIntEnable) + plicIntEnableArray.append(reduce(lambda x,y: x+y,plicIntEnable)) + # 0x0C020080 thru 0x0C020084 + plicIntEnable = tokenize(rawPlicStateFile.readline())[1:] + plicIntEnable = map(strip0x,plicIntEnable) + plicIntEnableArray.append(reduce(lambda x,y: x+y,plicIntEnable)) + plicIntPriorityThresholdArray = [] # iterates over number of different contexts # 0x0C200000 - plicIntPriorityThreshold = tokenize(rawPlicStateFile.readline())[1:] + plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C201000 + plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:] with open(outDir+'checkpoint-PLIC_INT_PRIORITY', 'w') as outFile: for word in plicIntPriorityArray: outFile.write(stripZeroes(word[2:])+'\n') with open(outDir+'checkpoint-PLIC_INT_ENABLE', 'w') as outFile: - for word in plicIntEnable: - outFile.write(stripZeroes(word[2:])) + for word in plicIntEnableArray: + outFile.write(word+'\n') with open(outDir+'checkpoint-PLIC_THRESHOLD', 'w') as outFile: - for word in plicIntPriorityThreshold: + for word in plicIntPriorityThresholdArray: outFile.write(stripZeroes(word[2:])+'\n') print("Finished parsing PLIC state!") diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index cac7aa670..ecdcbe50d 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -43,13 +43,13 @@ module csr #(parameter input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, - input logic TimerIntM, ExtIntM, SwIntM, + input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, - input logic BPPredDirWrongM, - input logic BTBPredPCWrongM, - input logic RASPredPCWrongM, - input logic BPPredClassNonCFIWrongM, + input logic BPPredDirWrongM, + input logic BTBPredPCWrongM, + input logic RASPredPCWrongM, + input logic BPPredClassNonCFIWrongM, input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, @@ -123,7 +123,7 @@ module csr #(parameter assign CSRUWriteM = CSRWriteM; csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, - .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM, + .CSRAdrM, .ExtIntM, .ExtIntS, .TimerIntM, .SwIntM, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM); csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteSSTATUSM, @@ -167,7 +167,7 @@ module csr #(parameter // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) | - (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE); + (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE); assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & IllegalCSRSAccessM & IllegalCSRUAccessM | InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM; diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 8a3f42fdf..7eff94962 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -41,7 +41,7 @@ module csri #(parameter input logic InstrValidNotFlushedM, StallW, input logic CSRMWriteM, CSRSWriteM, input logic [11:0] CSRAdrM, - input logic ExtIntM, TimerIntM, SwIntM, + input logic ExtIntM, ExtIntS, TimerIntM, SwIntM, input logic [`XLEN-1:0] MIDELEG_REGW, output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, input logic [`XLEN-1:0] CSRWriteValM @@ -57,12 +57,12 @@ module csri #(parameter always_comb begin IntInM = 0; - IntInM[11] = ExtIntM;; // MEIP - IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP - IntInM[7] = TimerIntM; // MTIP - IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP - IntInM[3] = SwIntM; // MSIP - IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP + IntInM[11] = ExtIntM; // MEIP + IntInM[9] = ExtIntS | (ExtIntM & MIDELEG_REGW[9]); // SEIP + IntInM[7] = TimerIntM; // MTIP + IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP + IntInM[3] = SwIntM; // MSIP + IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP end // Interrupt Write Enables @@ -82,21 +82,19 @@ module csri #(parameter assign MIP_WRITE_MASK = 12'h000; assign SIP_WRITE_MASK = 12'h000; end - always @(posedge clk) //, posedge reset) begin // *** I strongly feel that IntInM should go directly to IP_REGW -- Ben 9/7/21 + always @(posedge clk) if (reset) IP_REGW_writeable <= 10'b0; - else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable - else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable -// else if (WriteUIPM) IP_REGW = (CSRWriteValM & 12'hBBB) | (NextIPM & 12'h080); // MTIP unclearable - else IP_REGW_writeable <= IP_REGW_writeable | IntInM[9:0]; // *** check this turns off interrupts properly even when MIDELEG changes - always @(posedge clk) //, posedge reset) begin + else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable + else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable + else IP_REGW_writeable <= IP_REGW_writeable | {1'b0, IntInM[8:0]}; // *** check this turns off interrupts properly even when MIDELEG changes + always @(posedge clk) if (reset) IE_REGW <= 12'b0; else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields -// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // restricted views of registers - // Add MEIP read-only signal - assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; + // Add ExtIntM read-only signal + assign IP_REGW = {ExtIntM,1'b0,ExtIntS,9'b0} | {2'b0,IP_REGW_writeable}; // Machine Mode assign MIP_REGW = IP_REGW; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 8493a15bd..9a8fb9f8a 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -55,7 +55,7 @@ module privileged ( input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, input logic LoadMisalignedFaultM, input logic StoreAmoMisalignedFaultM, - input logic TimerIntM, ExtIntM, SwIntM, + input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, input logic [63:0] MTIME_CLINT, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [4:0] SetFflagsM, @@ -150,7 +150,7 @@ module privileged ( .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, - .TimerIntM, .ExtIntM, .SwIntM, + .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv index 2d5459989..cccbe75cf 100644 --- a/pipelined/src/uncore/plic.sv +++ b/pipelined/src/uncore/plic.sv @@ -37,6 +37,15 @@ `include "wally-config.vh" +`define N `PLIC_NUM_SRC +// number of interrupt sources +// does not include source 0, which does not connect to anything according to spec +// up to 63 sources supported; *** in the future, allow up to 1023 sources + +`define C 2 +// number of conexts +// hardcoded to 2 contexts for now; *** later upgrade to arbitrary (up to 15872) contexts + module plic ( input logic HCLK, HRESETn, input logic HSELPLIC, @@ -48,25 +57,26 @@ module plic ( input logic UARTIntr,GPIOIntr, output logic [`XLEN-1:0] HREADPLIC, output logic HRESPPLIC, HREADYPLIC, - output logic ExtIntM); - - localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec + output logic ExtIntM, ExtIntS); logic memwrite, memread, initTrans; logic [23:0] entry, entryd; logic [31:0] Din, Dout; - logic [N:1] requests; - logic [2:0] intPriority[N:1]; - logic [2:0] intThreshold; - logic [N:1] intPending, nextIntPending, intEn, intInProgress; - logic [5:0] intClaim; // ID's are 6 bits if we stay within 63 sources - - logic [N:1] pendingArray[7:1]; - logic [7:1] pendingPGrouped; - logic [7:1] pendingMaxP; - logic [N:1] pendingRequestsAtMaxP; - logic [7:1] threshMask; + // context-independent signals + logic [`N:1] requests; + logic [`N:1][2:0] intPriority; + logic [`N:1] intInProgress, intPending, nextIntPending; + + // context-dependent signals + logic [`C-1:0][2:0] intThreshold; + logic [`C-1:0][`N:1] intEn; + logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources + logic [`C-1:0][7:1][`N:1] irqMatrix; + logic [`C-1:0][7:1] priorities_with_irqs; + logic [`C-1:0][7:1] max_priority_with_irqs; + logic [`C-1:0][`N:1] irqs_at_max_priority; + logic [`C-1:0][7:1] threshMask; // ======= // AHB I/O @@ -82,12 +92,12 @@ module plic ( // account for subword read/write circuitry // -- Note PLIC registers are 32 bits no matter what; access them with LW SW. - if (`XLEN == 64) begin + if (`XLEN == 64) begin assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0]; assign HREADPLIC = entryd[2] ? {Dout,32'b0} : {32'b0,Dout}; end else begin // 32-bit - assign Din = HWDATA[31:0]; assign HREADPLIC = Dout; + assign Din = HWDATA[31:0]; end // ================== @@ -96,43 +106,56 @@ module plic ( always @(posedge HCLK,negedge HRESETn) begin // resetting if (~HRESETn) begin - intPriority <= #1 '{default:3'b0}; - intEn <= #1 {N{1'b0}}; - intThreshold <= #1 3'b0; - intInProgress <= #1 {N{1'b0}}; + intPriority <= #1 {`N{3'b0}}; + intEn <= #1 {2{`N'b0}}; + intThreshold <= #1 {2{3'b0}}; + intInProgress <= #1 `N'b0; // writing end else begin if (memwrite) casez(entryd) 24'h0000??: intPriority[entryd[7:2]] <= #1 Din[2:0]; - `ifdef PLIC_NUM_SRC_LT_32 - 24'h002000: intEn[N:1] <= #1 Din[N:1]; + `ifdef PLIC_NUM_SRC_LT_32 // *** switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources + 24'h002000: intEn[0][`N:1] <= #1 Din[`N:1]; + 24'h002080: intEn[1][`N:1] <= #1 Din[`N:1]; `endif `ifndef PLIC_NUM_SRC_LT_32 - 24'h002000: intEn[31:1] <= #1 Din[31:1]; - 24'h002004: intEn[N:32] <= #1 Din[31:0]; + 24'h002000: intEn[0][31:1] <= #1 Din[31:1]; + 24'h002004: intEn[0][`N:32] <= #1 Din[31:0]; + 24'h002080: intEn[1][31:1] <= #1 Din[31:1]; + 24'h002084: intEn[1][`N:32] <= #1 Din[31:0]; `endif - 24'h200000: intThreshold[2:0] <= #1 Din[2:0]; - 24'h200004: intInProgress <= #1 intInProgress & ~(`PLIC_NUM_SRC'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h200000: intThreshold[0] <= #1 Din[2:0]; + 24'h200004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h201000: intThreshold[1] <= #1 Din[2:0]; + 24'h201004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase // reading if (memread) casez(entry) 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; `ifdef PLIC_NUM_SRC_LT_32 - 24'h001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0}; - 24'h002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0}; + 24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0}; + 24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0}; + 24'h002080: Dout <= #1 {{(31-`N){1'b0}},intEn[1],1'b0}; `endif `ifndef PLIC_NUM_SRC_LT_32 24'h001000: Dout <= #1 {intPending[31:1],1'b0}; - 24'h001004: Dout <= #1 {{(63-N){1'b0}},intPending[N:32]}; - 24'h002000: Dout <= #1 {intEn[31:1],1'b0}; - 24'h002004: Dout <= #1 {{(63-N){1'b0}},intEn[N:32]}; + 24'h001004: Dout <= #1 {{(63-`N){1'b0}},intPending[`N:32]}; + 24'h002000: Dout <= #1 {intEn[0][31:1],1'b0}; + 24'h002004: Dout <= #1 {{(63-`N){1'b0}},intEn[0][`N:32]}; + 24'h002080: Dout <= #1 {intEn[0][31:1],1'b0}; + 24'h002084: Dout <= #1 {{(63-`N){1'b0}},intEn[1][`N:32]}; `endif - 24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]}; + 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; 24'h200004: begin - Dout <= #1 {26'b0,intClaim}; - intInProgress <= #1 intInProgress | (`PLIC_NUM_SRC'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed + Dout <= #1 {26'b0,intClaim[0]}; + intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed + end + 24'h201000: Dout <= #1 {29'b0,intThreshold[1]}; + 24'h201004: begin + Dout <= #1 {26'b0,intClaim[1]}; + intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed end default: Dout <= #1 32'h0; // invalid access endcase @@ -143,7 +166,7 @@ module plic ( // connect sources to requests always_comb begin - requests = {N{1'b0}}; + requests = `N'b0; `ifdef PLIC_GPIO_ID requests[`PLIC_GPIO_ID] = GPIOIntr; `endif @@ -152,66 +175,88 @@ module plic ( `endif end - // pending updates - // *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered) - assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress - ~({N{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read - flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); + // pending interrupt requests + assign nextIntPending = + (intPending | // existing pending requests + (requests & ~intInProgress)) & // assert new requests (if they aren't already being serviced) + ~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed + ~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1)); + flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); - // pending array - indexed by priority_lvl x source_ID - genvar i, j; - for (j=1; j<=7; j++) begin: pending - for (i=1; i<=N; i=i+1) begin: pendingbit - assign pendingArray[j][i] = (intPriority[i]==j) & intEn[i] & intPending[i]; + // context-dependent signals + genvar ctx; + for (ctx=0; ctx<`C; ctx++) begin + // request matrix + // priority level (rows) X source ID (columns) + // + // irqMatrix[ctx][pri][src] is high if source + // has priority level and has an "active" interrupt request + // ("active" meaning it is enabled in context and is pending) + genvar src, pri; + for (pri=1; pri<=7; pri++) begin + for (src=1; src<=`N; src++) begin + assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src]; + end end - end - // pending array, except grouped by priority - assign pendingPGrouped[7:1] = {|pendingArray[7], - |pendingArray[6], - |pendingArray[5], - |pendingArray[4], - |pendingArray[3], - |pendingArray[2], - |pendingArray[1]}; - //assign pendingPGrouped = pendingArray.or; - // pendingPGrouped, except only topmost priority is active - assign pendingMaxP[7:1] = {pendingPGrouped[7], - pendingPGrouped[6] & ~|pendingPGrouped[7], - pendingPGrouped[5] & ~|pendingPGrouped[7:6], - pendingPGrouped[4] & ~|pendingPGrouped[7:5], - pendingPGrouped[3] & ~|pendingPGrouped[7:4], - pendingPGrouped[2] & ~|pendingPGrouped[7:3], - pendingPGrouped[1] & ~|pendingPGrouped[7:2]}; - // select the pending requests at that priority - assign pendingRequestsAtMaxP[N:1] = ({N{pendingMaxP[7]}} & pendingArray[7]) - | ({N{pendingMaxP[6]}} & pendingArray[6]) - | ({N{pendingMaxP[5]}} & pendingArray[5]) - | ({N{pendingMaxP[4]}} & pendingArray[4]) - | ({N{pendingMaxP[3]}} & pendingArray[3]) - | ({N{pendingMaxP[2]}} & pendingArray[2]) - | ({N{pendingMaxP[1]}} & pendingArray[1]); - // find the lowest ID amongst active interrupts at the highest priority - logic [5:0] k; - always_comb begin - intClaim = 6'b0; - for (k=N; k>0; k=k-1) begin - if (pendingRequestsAtMaxP[k]) intClaim = k; + // which prority levels have one or more active requests? + assign priorities_with_irqs[ctx][7:1] = { + |irqMatrix[ctx][7], + |irqMatrix[ctx][6], + |irqMatrix[ctx][5], + |irqMatrix[ctx][4], + |irqMatrix[ctx][3], + |irqMatrix[ctx][2], + |irqMatrix[ctx][1] + }; + + // get the highest priority level that has active requests + assign max_priority_with_irqs[ctx][7:1] = { + priorities_with_irqs[ctx][7], + priorities_with_irqs[ctx][6] & ~|priorities_with_irqs[ctx][7], + priorities_with_irqs[ctx][5] & ~|priorities_with_irqs[ctx][7:6], + priorities_with_irqs[ctx][4] & ~|priorities_with_irqs[ctx][7:5], + priorities_with_irqs[ctx][3] & ~|priorities_with_irqs[ctx][7:4], + priorities_with_irqs[ctx][2] & ~|priorities_with_irqs[ctx][7:3], + priorities_with_irqs[ctx][1] & ~|priorities_with_irqs[ctx][7:2] + }; + + // of the sources at the highest priority level that has active requests, + // which sources have active requests? + assign irqs_at_max_priority[ctx][`N:1] = + ({`N{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) | + ({`N{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) | + ({`N{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) | + ({`N{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) | + ({`N{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) | + ({`N{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) | + ({`N{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]); + + // of the sources at the highest priority level that has active requests, + // choose the source with the lowest source ID to be the most urgent + // and set intClaim to the source ID of the most urgent active request + integer k; + always_comb begin + intClaim[ctx] = 6'b0; + for (k=`N; k>0; k--) begin + if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0]; + end end - end - - // create threshold mask - always_comb begin - threshMask[7] = (intThreshold != 7); - threshMask[6] = (intThreshold != 6) & threshMask[7]; - threshMask[5] = (intThreshold != 5) & threshMask[6]; - threshMask[4] = (intThreshold != 4) & threshMask[5]; - threshMask[3] = (intThreshold != 3) & threshMask[4]; - threshMask[2] = (intThreshold != 2) & threshMask[3]; - threshMask[1] = (intThreshold != 1) & threshMask[2]; - end - // is the max priority > threshold? - // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? - assign ExtIntM = |(threshMask & pendingPGrouped); + + // create threshold mask + always_comb begin + threshMask[ctx][7] = (intThreshold[ctx] != 7); + threshMask[ctx][6] = (intThreshold[ctx] != 6) & threshMask[ctx][7]; + threshMask[ctx][5] = (intThreshold[ctx] != 5) & threshMask[ctx][6]; + threshMask[ctx][4] = (intThreshold[ctx] != 4) & threshMask[ctx][5]; + threshMask[ctx][3] = (intThreshold[ctx] != 3) & threshMask[ctx][4]; + threshMask[ctx][2] = (intThreshold[ctx] != 2) & threshMask[ctx][3]; + threshMask[ctx][1] = (intThreshold[ctx] != 1) & threshMask[ctx][2]; + end + // is the max priority > threshold? + // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? + end + assign ExtIntM = |(threshMask[0] & priorities_with_irqs[0]); + assign ExtIntS = |(threshMask[1] & priorities_with_irqs[1]); endmodule diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index d90a30d7c..f48b96963 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -55,7 +55,7 @@ module uncore ( input logic [3:0] HSIZED, input logic HWRITED, // peripheral pins - output logic TimerIntM, SwIntM, ExtIntM, + output logic TimerIntM, SwIntM, ExtIntM, ExtIntS, input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, @@ -133,9 +133,10 @@ module uncore ( .HWRITE, .HREADY, .HTRANS, .HWDATA, .UARTIntr, .GPIOIntr, .HREADPLIC, .HRESPPLIC, .HREADYPLIC, - .ExtIntM); + .ExtIntM, .ExtIntS); end else begin : plic assign ExtIntM = 0; + assign ExtIntS = 0; end if (`GPIO_SUPPORTED == 1) begin : gpio gpio gpio( diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index c8be1116b..366ae2170 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -32,137 +32,137 @@ /* verilator lint_on UNUSED */ module wallypipelinedcore ( - input logic clk, reset, + input logic clk, reset, // Privileged - input logic TimerIntM, ExtIntM, SwIntM, - input logic [63:0] MTIME_CLINT, + input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, + input logic [63:0] MTIME_CLINT, // Bus Interface input logic [`AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [31:0] HADDR, + input logic HREADY, HRESP, + output logic HCLK, HRESETn, + output logic [31:0] HADDR, output logic [`AHBW-1:0] HWDATA, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, // Delayed signals for subword write - output logic [2:0] HADDRD, - output logic [3:0] HSIZED, - output logic HWRITED + output logic [2:0] HADDRD, + output logic [3:0] HSIZED, + output logic HWRITED ); // logic [1:0] ForwardAE, ForwardBE; - logic StallF, StallD, StallE, StallM, StallW; - logic FlushF, FlushD, FlushE, FlushM, FlushW; - logic RetM; + logic StallF, StallD, StallE, StallM, StallW; + logic FlushF, FlushD, FlushE, FlushM, FlushW; + logic RetM; (* mark_debug = "true" *) logic TrapM; // new signals that must connect through DP - logic MDUE, W64E; - logic CSRReadM, CSRWriteM, PrivilegedM; - logic [1:0] AtomicE; - logic [1:0] AtomicM; - logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; - logic [`XLEN-1:0] SrcAM; - logic [2:0] Funct3E; + logic MDUE, W64E; + logic CSRReadM, CSRWriteM, PrivilegedM; + logic [1:0] AtomicE; + logic [1:0] AtomicM; + logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; + logic [`XLEN-1:0] SrcAM; + logic [2:0] Funct3E; // logic [31:0] InstrF; - logic [31:0] InstrD, InstrW; - (* mark_debug = "true" *) logic [31:0] InstrM; - logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; - (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] PrivilegedNextPCM; - (* mark_debug = "true" *) logic [1:0] MemRWM; - (* mark_debug = "true" *) logic InstrValidM; - logic InstrMisalignedFaultM; - logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; - logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; - logic LoadMisalignedFaultM, LoadAccessFaultM; - logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; - logic [`XLEN-1:0] InstrMisalignedAdrM; + logic [31:0] InstrD, InstrW; + (* mark_debug = "true" *) logic [31:0] InstrM; + logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; + (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; + logic [`XLEN-1:0] CSRReadValW, MDUResultW; + logic [`XLEN-1:0] PrivilegedNextPCM; + (* mark_debug = "true" *) logic [1:0] MemRWM; + (* mark_debug = "true" *) logic InstrValidM; + logic InstrMisalignedFaultM; + logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; + logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; + logic LoadMisalignedFaultM, LoadAccessFaultM; + logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; + logic [`XLEN-1:0] InstrMisalignedAdrM; logic InvalidateICacheM, FlushDCacheM; - logic PCSrcE; - logic CSRWritePendingDEM; - logic DivBusyE; + logic PCSrcE; + logic CSRWritePendingDEM; + logic DivBusyE; logic DivE; - logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; - logic SquashSCW; + logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; + logic SquashSCW; // floating point unit signals - logic [2:0] FRM_REGW; + logic [2:0] FRM_REGW; logic [4:0] RdM, RdW; - logic FStallD; - logic FWriteIntE; - logic [`XLEN-1:0] FWriteDataE; - logic [`XLEN-1:0] FIntResM; - logic FDivBusyE; - logic IllegalFPUInstrD, IllegalFPUInstrE; - logic FRegWriteM; - logic FPUStallD; - logic [4:0] SetFflagsM; + logic FStallD; + logic FWriteIntE; + logic [`XLEN-1:0] FWriteDataE; + logic [`XLEN-1:0] FIntResM; + logic FDivBusyE; + logic IllegalFPUInstrD, IllegalFPUInstrE; + logic FRegWriteM; + logic FPUStallD; + logic [4:0] SetFflagsM; // memory management unit signals - logic ITLBWriteF; - logic ITLBFlushF, DTLBFlushM; - logic ITLBMissF; - logic [`XLEN-1:0] SATP_REGW; + logic ITLBWriteF; + logic ITLBFlushF, DTLBFlushM; + logic ITLBMissF; + logic [`XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP; - logic [1:0] PrivilegeModeW; - logic [`XLEN-1:0] PTE; - logic [1:0] PageType; + logic [1:0] PrivilegeModeW; + logic [`XLEN-1:0] PTE; + logic [1:0] PageType; // PMA checker signals var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; // IMem stalls - logic IFUStallF; - logic LSUStallM; + logic IFUStallF; + logic LSUStallM; // cpu lsu interface - logic [2:0] Funct3M; - logic [`XLEN-1:0] IEUAdrE; + logic [2:0] Funct3M; + logic [`XLEN-1:0] IEUAdrE; (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM; - (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; - (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; - logic [`XLEN-1:0] ReadDataW; - logic CommittedM; + (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; + (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; + logic [`XLEN-1:0] ReadDataW; + logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] IFUBusAdr; - logic [`XLEN-1:0] IFUBusHRDATA; - logic IFUBusRead; - logic IFUBusAck; + logic [`PA_BITS-1:0] IFUBusAdr; + logic [`XLEN-1:0] IFUBusHRDATA; + logic IFUBusRead; + logic IFUBusAck; // AHB LSU interface - logic [`PA_BITS-1:0] LSUBusAdr; - logic LSUBusRead; - logic LSUBusWrite; - logic LSUBusAck; - logic [`XLEN-1:0] LSUBusHRDATA; - logic [`XLEN-1:0] LSUBusHWDATA; + logic [`PA_BITS-1:0] LSUBusAdr; + logic LSUBusRead; + logic LSUBusWrite; + logic LSUBusAck; + logic [`XLEN-1:0] LSUBusHRDATA; + logic [`XLEN-1:0] LSUBusHWDATA; - logic BPPredWrongE; - logic BPPredDirWrongM; - logic BTBPredPCWrongM; - logic RASPredPCWrongM; - logic BPPredClassNonCFIWrongM; - logic [4:0] InstrClassM; - logic InstrAccessFaultF; - logic [2:0] LSUBusSize; + logic BPPredWrongE; + logic BPPredDirWrongM; + logic BTBPredPCWrongM; + logic RASPredPCWrongM; + logic BPPredClassNonCFIWrongM; + logic [4:0] InstrClassM; + logic InstrAccessFaultF; + logic [2:0] LSUBusSize; - logic ExceptionM; - logic PendingInterruptM; - logic DCacheMiss; - logic DCacheAccess; - logic ICacheMiss; - logic ICacheAccess; - logic BreakpointFaultM, EcallFaultM; + logic ExceptionM; + logic PendingInterruptM; + logic DCacheMiss; + logic DCacheAccess; + logic ICacheMiss; + logic ICacheAccess; + logic BreakpointFaultM, EcallFaultM; logic InstrDAPageFaultF; ifu ifu( @@ -203,8 +203,8 @@ module wallypipelinedcore ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF - - ); // instruction fetch unit: PC, branch prediction, instruction cache + + ); // instruction fetch unit: PC, branch prediction, instruction cache ieu ieu( .clk, .reset, @@ -221,7 +221,7 @@ module wallypipelinedcore ( // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU - .AtomicE, // atomic control goes to LSU + .AtomicE, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU .WriteDataM, // Write data to LSU .Funct3M, // size and signedness to LSU @@ -245,41 +245,41 @@ module wallypipelinedcore ( lsu lsu( .clk, .reset, .StallM, .FlushM, .StallW, - .FlushW, - // CPU interface - .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), - .AtomicM, .TrapM, - .CommittedM, .DCacheMiss, .DCacheAccess, - .SquashSCW, - //.DataMisalignedM(DataMisalignedM), - .IEUAdrE, .IEUAdrM, .WriteDataM, - .ReadDataM, .FlushDCacheM, - // connected to ahb (all stay the same) - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, + .FlushW, + // CPU interface + .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), + .AtomicM, .TrapM, + .CommittedM, .DCacheMiss, .DCacheAccess, + .SquashSCW, + //.DataMisalignedM(DataMisalignedM), + .IEUAdrE, .IEUAdrM, .WriteDataM, + .ReadDataM, .FlushDCacheM, + // connected to ahb (all stay the same) + .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, - // connect to csr or privilege and stay the same. - .PrivilegeModeW, // connects to csr - .PMPCFG_ARRAY_REGW, // connects to csr - .PMPADDR_ARRAY_REGW, // connects to csr - // hptw keep i/o - .SATP_REGW, // from csr - .STATUS_MXR, // from csr - .STATUS_SUM, // from csr - .STATUS_MPRV, // from csr - .STATUS_MPP, // from csr + // connect to csr or privilege and stay the same. + .PrivilegeModeW, // connects to csr + .PMPCFG_ARRAY_REGW, // connects to csr + .PMPADDR_ARRAY_REGW, // connects to csr + // hptw keep i/o + .SATP_REGW, // from csr + .STATUS_MXR, // from csr + .STATUS_SUM, // from csr + .STATUS_MPRV, // from csr + .STATUS_MPP, // from csr - .DTLBFlushM, // connects to privilege - .LoadPageFaultM, // connects to privilege - .StoreAmoPageFaultM, // connects to privilege - .LoadMisalignedFaultM, // connects to privilege - .LoadAccessFaultM, // connects to privilege - .StoreAmoMisalignedFaultM, // connects to privilege - .StoreAmoAccessFaultM, // connects to privilege + .DTLBFlushM, // connects to privilege + .LoadPageFaultM, // connects to privilege + .StoreAmoPageFaultM, // connects to privilege + .LoadMisalignedFaultM, // connects to privilege + .LoadAccessFaultM, // connects to privilege + .StoreAmoMisalignedFaultM, // connects to privilege + .StoreAmoAccessFaultM, // connects to privilege .InstrDAPageFaultF, - .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, - .LSUStallM); // change to LSUStallM + .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, + .LSUStallM); // change to LSUStallM // *** Ross: please make EBU conditional when only supporting internal memories @@ -306,13 +306,13 @@ module wallypipelinedcore ( .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, .LSUStallM, .IFUStallF, .FPUStallD, .FStallD, - .DivBusyE, .FDivBusyE, - .EcallFaultM, .BreakpointFaultM, + .DivBusyE, .FDivBusyE, + .EcallFaultM, .BreakpointFaultM, .InvalidateICacheM, // Stall & flush outputs - .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW - ); // global stall and flush control + .StallF, .StallD, .StallE, .StallM, .StallW, + .FlushF, .FlushD, .FlushE, .FlushM, .FlushW + ); // global stall and flush control if (`ZICSR_SUPPORTED) begin:priv privileged priv( @@ -331,7 +331,7 @@ module wallypipelinedcore ( .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, - .TimerIntM, .ExtIntM, .SwIntM, + .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, .MTIME_CLINT, .InstrMisalignedAdrM, .IEUAdrM, .SetFflagsM, diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 1b7f38311..0d844d3cf 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -74,7 +74,7 @@ module wallypipelinedsoc ( logic HRESP; logic TimerIntM, SwIntM; // from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs - logic ExtIntM; // from PLIC + logic ExtIntM,ExtIntS; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; @@ -84,7 +84,7 @@ module wallypipelinedsoc ( // instantiate processor and memories wallypipelinedcore core(.clk, .reset, - .TimerIntM, .ExtIntM, .SwIntM, + .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, .MTIME_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, @@ -94,7 +94,7 @@ module wallypipelinedsoc ( uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, - .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, + .TimerIntM, .SwIntM, .ExtIntM, .ExtIntS, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .HSELEXT, .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 62d13a1a3..8b37bcbc5 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -334,8 +334,8 @@ module testbench; //`INIT_CHECKPOINT_VAL(UART_MSR, [7:0]); `INIT_CHECKPOINT_VAL(UART_SCR, [7:0]); `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); - `INIT_CHECKPOINT_VAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1]); - `INIT_CHECKPOINT_VAL(PLIC_THRESHOLD, [2:0]); + `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0); + `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_THRESHOLD, [2:0],1,0); integer memFile; integer readResult; From 6f6663cd67263ccdbe3fb4a2783fc8c6d355517f Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 25 Mar 2022 01:02:22 +0000 Subject: [PATCH 190/199] fix multiple-context PLIC checkpoint generation --- linux/testvector-generation/parsePlicState.py | 2 +- pipelined/testbench/testbench-linux.sv | 20 ++++++++++++++++--- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/linux/testvector-generation/parsePlicState.py b/linux/testvector-generation/parsePlicState.py index 35ef00b1d..b917bfdc3 100755 --- a/linux/testvector-generation/parsePlicState.py +++ b/linux/testvector-generation/parsePlicState.py @@ -101,7 +101,7 @@ with open(outDir+'checkpoint-PLIC_INT_PRIORITY', 'w') as outFile: outFile.write(stripZeroes(word[2:])+'\n') with open(outDir+'checkpoint-PLIC_INT_ENABLE', 'w') as outFile: for word in plicIntEnableArray: - outFile.write(word+'\n') + outFile.write(stripZeroes(word)+'\n') with open(outDir+'checkpoint-PLIC_THRESHOLD', 'w') as outFile: for word in plicIntPriorityThresholdArray: outFile.write(stripZeroes(word[2:])+'\n') diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 36153d737..12950b637 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -266,6 +266,19 @@ module testbench; end \ end + `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + for (i=ARRAY_MIN; i" in the signal name `define INIT_CHECKPOINT_GENBLK_ARRAY(SIGNAL_BASE,SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ @@ -296,6 +309,7 @@ module testbench; end \ end + genvar i; `INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1); `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0); `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); @@ -333,9 +347,9 @@ module testbench; //`INIT_CHECKPOINT_VAL(UART_LSR, [7:0]); //`INIT_CHECKPOINT_VAL(UART_MSR, [7:0]); `INIT_CHECKPOINT_VAL(UART_SCR, [7:0]); - `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); - `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0); - `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_THRESHOLD, [2:0],1,0); + `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); + `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0); + `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0); integer memFile; integer readResult; From 61c714ebe6e65885f728da5e3f22be5b085d8ac0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 25 Mar 2022 13:10:31 -0500 Subject: [PATCH 191/199] I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. --- pipelined/src/privileged/csri.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 7eff94962..b9a302d2a 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -58,7 +58,7 @@ module csri #(parameter always_comb begin IntInM = 0; IntInM[11] = ExtIntM; // MEIP - IntInM[9] = ExtIntS | (ExtIntM & MIDELEG_REGW[9]); // SEIP + IntInM[9] = (ExtIntM & MIDELEG_REGW[9]); // SEIP IntInM[7] = TimerIntM; // MTIP IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP IntInM[3] = SwIntM; // MSIP From 7ae1d141911386b9d4fecd8c1e2ca3c5c8c609ee Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 25 Mar 2022 22:57:03 +0000 Subject: [PATCH 192/199] added basic trap tests that do not pass regression yet. updated signature adresses --- pipelined/testbench/tests.vh | 24 +- .../rv64i_m/privilege/Makefrag | 3 +- .../references/WALLY-trap-01.reference_output | 244 +++++++++--------- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 231 ++++++++++++----- .../rv64i_m/privilege/src/WALLY-trap-01.S | 52 ++-- 5 files changed, 321 insertions(+), 233 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 8ae9bc196..687878bc2 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1450,29 +1450,31 @@ string imperas32f[] = '{ string wally64priv[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-CSR-permission-s-01", "004080", + "rv64i_m/privilege/WALLY-CSR-permission-s-01", "0050a0", //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "005070", //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "003070", - "rv64i_m/privilege/WALLY-CSR-permission-u-01", "005080", + "rv64i_m/privilege/WALLY-CSR-permission-u-01", "0050a0", // "rv64i_m/privilege/WALLY-MARCHID", "003070", /* "rv64i_m/privilege/WALLY-MCAUSE", "003070", "rv64i_m/privilege/WALLY-MEDELEG", "003070", "rv64i_m/privilege/WALLY-MHARTID", "003070", "rv64i_m/privilege/WALLY-MIMPID", "003070",*/ - "rv64i_m/privilege/WALLY-minfo-01", "004080", - "rv64i_m/privilege/WALLY-misa-01", "004080", - "rv64i_m/privilege/WALLY-MMU-SV39", "004080", - "rv64i_m/privilege/WALLY-MMU-SV48", "004080", + "rv64i_m/privilege/WALLY-minfo-01", "0040a0", + "rv64i_m/privilege/WALLY-misa-01", "0040a0", + "rv64i_m/privilege/WALLY-MMU-SV39", "0040a0", + "rv64i_m/privilege/WALLY-MMU-SV48", "0040a0", /* "rv64i_m/privilege/WALLY-MSTATUS", "002070", "rv64i_m/privilege/WALLY-MTVEC", "002070", "rv64i_m/privilege/WALLY-MVENDORID", "003070", */ - "rv64i_m/privilege/WALLY-PMA", "004080", - "rv64i_m/privilege/WALLY-PMP", "004080", + "rv64i_m/privilege/WALLY-PMA", "0040a0", + "rv64i_m/privilege/WALLY-PMP", "0040a0", // "rv64i_m/privilege/WALLY-SCAUSE", "002070", - "rv64i_m/privilege/WALLY-scratch-01", "004080", - "rv64i_m/privilege/WALLY-sscratch-s-01", "004080" + "rv64i_m/privilege/WALLY-scratch-01", "0040a0", + "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0" +// "rv64i_m/privilege/WALLY-trap-01", "0040a0" // "rv64i_m/privilege/WALLY-STVEC", "002070", -// "rv64i_m/privilege/WALLY-UCAUSE", "002070" +// "rv64i_m/privilege/WALLY-UCAUSE", "002070", + }; string wally64periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index adf328390..73ef3c203 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -56,7 +56,8 @@ target_tests_nosim = \ WALLY-MIMPID \ WALLY-MVENDORID \ WALLY-CSR-PERMISSIONS-M \ - WALLY-CSR-PERMISSIONS-S + WALLY-CSR-PERMISSIONS-S \ + WALLY-trap-01 \ # Have all 0's in references! #WALLY-MEPC \ #WALLY-SEPC \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 6fbd0f382..eef583deb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -1,3 +1,93 @@ +00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts +00000000 +00000001 # mcause from an instruction access fault +00000000 +00000000 # mtval of faulting instruction address (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000002 # mcause from an Illegal instruction +00000000 +00000000 # mtval of faulting instruction (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000003 # mcause from Breakpoint +00000000 +800003ec # mtval of breakpoint instruction adress (0x800003ec) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000004 # mcause from load address misaligned +00000000 +800003f5 # mtval of misaligned address (0x800003f5) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000005 # mcause from load access +00000000 +00000000 # mtval of accessed adress (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000006 # mcause from store misaligned +00000000 +80000411 # mtval of address with misaligned store instr (0x80000410) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000007 # mcause from store access +00000000 +00000000 # mtval of accessed address (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0000000b # mcause from M mode ecall +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000008 # mcause from U mode ecall +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00000080 # masked out mstatus.MPP = 00 (from U mode), mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000009 # mcause from S mode ecall +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +000007ec # value to indicate a vectored interrupts +00000000 +00000007 # mcause value from m time interrupt +80000000 +00000000 # mtval for mtime interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +000007ec # value to indicate a vectored interrupts +00000000 +00000001 # mcause value from m soft interrupt +80000000 +00000000 # mtval for msoft interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +000007ec # value to indicate a vectored interrupts +00000000 +0000000b # mcause value from m ext interrupt +80000000 +00000000 # mtval for mext interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0000b309 # medeleg after attempted write of all 1's (only some bits are writeable) +00000000 +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) +00000000 00000001 # Test 5.3.1.4: mcause from an instruction access fault 00000000 00000000 # mtval of faulting instruction address (0x0) @@ -12,49 +102,67 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -00000000 # mtval of breakpoint instruction adress (*** Determined from make) +800003ec # mtval of breakpoint instruction adress (0x800003ec) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -00000000 # mtval of misaligned address (*** Determined from make) +800003f5 # mtval of misaligned address (0x800003f5) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000005 # mcause from load access 00000000 -00000000 # mtval of address with access faulting instr (*** Determined from make) +00000000 # mtval of accessed adress (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000006 # mcause from store misaligned 00000000 -00000000 # mtval of address with misaligned store instr (*** Determined from make) +80000411 # mtval of address with misaligned store instr (0x80000410) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000007 # mcause from store access 00000000 -00000000 # mtval of address with faulting store instr (*** Determined from make) +00000000 # mtval of accessed address (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 0000000b # mcause from M mode ecall 00000000 -00000000 # mtval of +00000000 # mtval of ecall (*** defined to be zero for now) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -00000008 # mcause from U mode ecall +000007ec # value to indicate a vectored interrupts 00000000 -00000000 # mtval of +00000007 # mcause value from time interrupt +80000000 +00000000 # mtval for mtime interrupt (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -00000009 # mcause from S mode ecall +000007ec # value to indicate a vectored interrupts 00000000 -00000000 # mtval of address with faulting store instr (*** Determined from make) +00000001 # mcause value from m soft interrupt +80000000 +00000000 # mtval for msoft interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +000007ec # value to indicate a vectored interrupts +00000000 +0000000b # mcause value from m ext interrupt +80000000 +00000000 # mtval for mext interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0000000b # mcause from M mode ecall from test termination +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -964,119 +1072,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 99e000fad..534fd433f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -55,6 +55,99 @@ RVTEST_CODE_BEGIN .endm +// Code to trigger traps goes here so we have consistent mtvals for instruction adresses +// Even if more tests are added. +.macro CAUSE_TRAP_TRIGGERS +j end_trap_triggers + +// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines +// This effectively includes everything that isn't to do with page faults (virtual memory) + +cause_instr_addr_misaligned: + // cause a misaligned address trap + auipc x28, 0 // get current PC, which is aligned + addi x28, x28, 0x3 // add 1 to pc to create misaligned address + jr x28 // cause instruction address midaligned trap + ret + +cause_instr_access: + la x28, 0x0 // address zero is an address with no memory + sd x1, -8(sp) // push the return adress ontot the stack + addi sp, sp, -8 + jalr x28 // cause instruction access trap + ld x1, 0(sp) // pop return adress back from the stack + addi sp, sp, 8 + ret + +cause_illegal_instr: + .word 0x00000000 // a 32 bit zros is an illegal instruction + ret + +cause_breakpnt: // **** + ebreak + ret + +cause_load_addr_misaligned: + auipc x28, 0 // get current PC, which is aligned + addi x28, x28, 1 + lw x29, 0(x28) // load from a misaligned address + ret + +cause_load_acc: + la x28, 0 // 0 is an address with no memory + lw x29, 0(x28) // load from unimplemented address + ret + +cause_store_addr_misaligned: + auipc x28, 0 // get current PC, which is aligned + addi x28, x28, 1 + sw x29, 0(x28) // store to a misaligned address + ret + +cause_store_acc: + la x28, 0 // 0 is an address with no memory + sw x29, 0(x28) // store to unimplemented address + ret + +cause_ecall: + // *** ASSUMES you have already gone to the mode you need to call this from. + ecall + ret + +cause_time_interrupt: + // The following code works for both RV32 and RV64. + // RV64 alone would be easier using double-word adds and stores + li x28, 0x100 // Desired offset from the present time + la x29, 0x02004000 // MTIMECMP register in CLINT + la x30, 0x0200BFF8 // MTIME register in CLINT + lw x7, 0(x30) // low word of MTIME + lw x31, 4(x30) // high word of MTIME + add x28, x7, x28 // add desired offset to the current time + bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) + addi x31, x31, 1 // if wrap, increment most significant word + sw x31,4(x29) // store into most significant word of MTIMECMP +nowrap: + sw x28, 0(x29) // store into least significant word of MTIMECMP + loop: j loop // wait until interrupt occurs + ret + +cause_soft_interrupt: + la x28, 0x02000000 // MSIP register in CLINT + li x29, 1 // 1 in the lsb + sw x29, 0(x28) // Write MSIP bit + ret + +cause_ext_interrupt: + li x28, 0x10060000 // load base GPIO memory location + li x29, 0x1 + sw x29, 8(x28) // enable the first pin as an output + sw x29, 28(x28) // set first pin to high interrupt enable + sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt) + ret + +end_trap_triggers: +.endm + .macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0 // MODE decides which mode this trap handler will be taken in (M or S mode) // Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1) @@ -577,7 +670,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // The previous CSR value before write attempt // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access li x30, 0xbad // load bad value to be overwritten by csrr - li x29, \VAL + li x29, \VAL\() csrw \CSR\(), x29 csrr x30, \CSR sd x30, 0(x6) @@ -627,86 +720,86 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a addi x16, x16, 8 .endm -// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines -// This effectively includes everything that isn't to do with page faults (virtual memory) +// // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines +// // This effectively includes everything that isn't to do with page faults (virtual memory) -.macro CAUSE_INSTR_ADDR_MISALIGNED - // cause a misaligned address trap - auipc x28, 0 // get current PC, which is aligned - addi x28, x28, 0x1 // add 1 to pc to create misaligned address - jalr x28 // cause instruction address midaligned trap -.endm +// .macro CAUSE_INSTR_ADDR_MISALIGNED +// // cause a misaligned address trap +// auipc x28, 0 // get current PC, which is aligned +// addi x28, x28, 0x1 // add 1 to pc to create misaligned address +// jalr x28 // cause instruction address midaligned trap +// .endm -.macro CAUSE_INSTR_ACCESS - la x28, 0x0 // address zero is an address with no memory - jalr x28 // cause instruction access trap -.endm +// .macro CAUSE_INSTR_ACCESS +// la x28, 0x0 // address zero is an address with no memory +// jalr x28 // cause instruction access trap +// .endm -.macro CAUSE_ILLEGAL_INSTR - .word 0x00000000 // a 32 bit zros is an illegal instruction -.endm +// .macro CAUSE_ILLEGAL_INSTR +// .word 0x00000000 // a 32 bit zros is an illegal instruction +// .endm -.macro CAUSE_BREAKPNT // **** - ebreak -.endm +// .macro CAUSE_BREAKPNT // **** +// ebreak +// .endm -.macro CAUSE_LOAD_ADDR_MISALIGNED - auipc x28, 0 // get current PC, which is aligned - addi x28, x28, 1 - lw x29, 0(x28) // load from a misaligned address -.endm +// .macro CAUSE_LOAD_ADDR_MISALIGNED +// auipc x28, 0 // get current PC, which is aligned +// addi x28, x28, 1 +// lw x29, 0(x28) // load from a misaligned address +// .endm -.macro CAUSE_LOAD_ACC - la x28, 0 // 0 is an address with no memory - lw x29, 0(x28) // load from unimplemented address -.endm +// .macro CAUSE_LOAD_ACC +// la x28, 0 // 0 is an address with no memory +// lw x29, 0(x28) // load from unimplemented address +// .endm -.macro CAUSE_STORE_ADDR_MISALIGNED - auipc x28, 0 // get current PC, which is aligned - addi x28, x28, 1 - sw x29, 0(x28) // store to a misaligned address -.endm +// .macro CAUSE_STORE_ADDR_MISALIGNED +// auipc x28, 0 // get current PC, which is aligned +// addi x28, x28, 1 +// sw x29, 0(x28) // store to a misaligned address +// .endm -.macro CAUSE_STORE_ACC - la x28, 0 // 0 is an address with no memory - sw x29, 0(x28) // store to unimplemented address -.endm +// .macro CAUSE_STORE_ACC +// la x28, 0 // 0 is an address with no memory +// sw x29, 0(x28) // store to unimplemented address +// .endm -.macro CAUSE_ECALL - // *** ASSUMES you have already gone to the mode you need to call this from. - ecall -.endm +// .macro CAUSE_ECALL +// // *** ASSUMES you have already gone to the mode you need to call this from. +// ecall +// .endm -.macro CAUSE_TIME_INTERRUPT - // The following code works for both RV32 and RV64. - // RV64 alone would be easier using double-word adds and stores - li x28, 0x100 // Desired offset from the present time - la x29, 0x02004000 // MTIMECMP register in CLINT - la x30, 0x0200BFF8 // MTIME register in CLINT - lw x7, 0(x30) // low word of MTIME - lw x31, 4(x30) // high word of MTIME - add x28, x7, x28 // add desired offset to the current time - bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) - addi x31, x31, 1 // if wrap, increment most significant word - sw x31,4(x29) // store into most significant word of MTIMECMP -nowrap: - sw x28, 0(x29) // store into least significant word of MTIMECMP - loop: j loop // wait until interrupt occurs -.endm +// .macro CAUSE_TIME_INTERRUPT +// // The following code works for both RV32 and RV64. +// // RV64 alone would be easier using double-word adds and stores +// li x28, 0x100 // Desired offset from the present time +// la x29, 0x02004000 // MTIMECMP register in CLINT +// la x30, 0x0200BFF8 // MTIME register in CLINT +// lw x7, 0(x30) // low word of MTIME +// lw x31, 4(x30) // high word of MTIME +// add x28, x7, x28 // add desired offset to the current time +// bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) +// addi x31, x31, 1 // if wrap, increment most significant word +// sw x31,4(x29) // store into most significant word of MTIMECMP +// nowrap: +// sw x28, 0(x29) // store into least significant word of MTIMECMP +// loop: j loop // wait until interrupt occurs +// .endm -.macro CAUSE_SOFT_INTERRUPT - la x28, 0x02000000 // MSIP register in CLINT - li x29, 1 // 1 in the lsb - sw x29, 0(x28) // Write MSIP bit -.endm +// .macro CAUSE_SOFT_INTERRUPT +// la x28, 0x02000000 // MSIP register in CLINT +// li x29, 1 // 1 in the lsb +// sw x29, 0(x28) // Write MSIP bit +// .endm -.macro CAUSE_EXT_INTERRUPT - li x28, 0x10060000 // load base GPIO memory location - li x29, 0x1 - sw x29, 8(x28) // enable the first pin as an output - sw x29, 28(x28) // set first pin to high interrupt enable - sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt) -.endm +// .macro CAUSE_EXT_INTERRUPT +// li x28, 0x10060000 // load base GPIO memory location +// li x29, 0x1 +// sw x29, 8(x28) // enable the first pin as an output +// sw x29, 28(x28) // set first pin to high interrupt enable +// sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt) +// .endm .macro END_TESTS // invokes one final ecall to return to machine mode then terminates this program, so the output is diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index be1ca6509..45d34c344 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -25,50 +25,50 @@ INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1 -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts +WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts // test 5.3.1.4 Basic trap tests -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC +// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc GOTO_U_MODE // Causes M mode ecall GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken +jal cause_ext_interrupt // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL // M mode ecall -// GOTO_U_MODE // leave these untested since we only need to ensure that from M mode are not delegated -// GOTO_S_MODE +// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +jal cause_ecall // M mode ecall -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. +jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken +jal cause_ext_interrupt END_TESTS From 62a330c290a907054d65abfb2dff45d08602125e Mon Sep 17 00:00:00 2001 From: Skylar Litz Date: Sat, 26 Mar 2022 21:28:32 +0000 Subject: [PATCH 193/199] update to match new filesystem organization --- pipelined/regression/buildrootBugFinder.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/regression/buildrootBugFinder.py b/pipelined/regression/buildrootBugFinder.py index b6639e714..89a838d2f 100755 --- a/pipelined/regression/buildrootBugFinder.py +++ b/pipelined/regression/buildrootBugFinder.py @@ -4,7 +4,7 @@ import sys, os, subprocess def main(): maxGoodCount = 400e6 # num instrs that execute sucessfully starting from 0 currInstrCount = maxGoodCount - linuxTestvectors = "../../tests/linux-testgen/linux-testvectors" + linuxTestvectors = "/opt/riscv/linux-testvectors" if not os.path.exists(linuxTestvectors): sys.stderr.write("Error: Linux testvectors not found at "+linuxTestvectors+"\n") exit(1) @@ -22,7 +22,7 @@ def main(): break checkpoint = checkpointList[0] logFile = logDir+"checkpoint"+str(checkpoint)+".log" - runCommand="{\nvsim -c < Date: Sat, 26 Mar 2022 21:28:57 +0000 Subject: [PATCH 194/199] add AtemptedInstructionCount signal --- pipelined/regression/linux-wave.do | 4 +--- pipelined/testbench/testbench-linux.sv | 6 ++++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index 1d59dcbf0..770b3d340 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -4,6 +4,7 @@ add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate -radix unsigned /testbench/InstrCountW +add wave -noupdate -radix unsigned /testbench/AttemptedInstructionCount add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/IllegalFPUInstrD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE @@ -388,7 +389,6 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/cor add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState @@ -526,9 +526,7 @@ add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/TakeSpillF add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/IFUCacheBusStallF add wave -noupdate -color Yellow /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DAPageFault -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/OtherPageFault add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/Accessed add wave -noupdate /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/WriteAccess add wave -noupdate /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/TLBPageFault TreeUpdate [SetDefaultTree] diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 12950b637..da6233150 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -176,6 +176,7 @@ module testbench; integer CheckMIPFutureM; integer CheckSIPFutureE; integer CheckSIPFutureM; + logic [`XLEN-1:0] AttemptedInstructionCount; // Useful Aliases `define RF dut.core.ieu.dp.regf.rf `define PC dut.core.ifu.pcreg.q @@ -380,11 +381,13 @@ module testbench; traceFileM = $fopen({testvectorDir,"all.txt"}, "r"); traceFileE = $fopen({testvectorDir,"all.txt"}, "r"); InstrCountW = '0; + AttemptedInstructionCount = '0; end else begin // checkpoint //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM); traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); InstrCountW = CHECKPOINT; + AttemptedInstructionCount = CHECKPOINT; // manual checkpoint initializations that don't neatly fit into MACRO force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17]; force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11]; @@ -440,6 +443,9 @@ module testbench; for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \ //$display("char = %s", line``STAGE[index]); \ if (line``STAGE[index``STAGE] == " " | line``STAGE[index``STAGE] == "\n") begin \ + if (line``STAGE[index``STAGE] == "\n" & `"STAGE`"=="M") begin \ + AttemptedInstructionCount += 1; \ + end \ EndIndex``STAGE = index``STAGE; \ ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \ //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \ From 8d5c231a13ff385ffca6ebde22ed136cafc29092 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 27 Mar 2022 15:11:36 -0700 Subject: [PATCH 195/199] change devicetree to expect only 128MB of RAM --- linux/devicetree/wally-virt.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/devicetree/wally-virt.dts b/linux/devicetree/wally-virt.dts index f35848c59..6d7955855 100644 --- a/linux/devicetree/wally-virt.dts +++ b/linux/devicetree/wally-virt.dts @@ -15,7 +15,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x00 0x80000000 0x00 0x8000000>; + reg = <0x00 0x80000000 0x00 0x08000000>; }; cpus { From 800bc855194096dc02b952378e9bd5ecff94d226 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 27 Mar 2022 15:13:03 -0700 Subject: [PATCH 196/199] refactored buildroot configuration --- .../{ => wally}/busybox.config | 0 .../{ => wally}/linux.config | 0 .../{ => wally}/main.config | 12 +++--- .../wally/rootfs_overlay/.profile | 37 +++++++++++++++++ .../wally/rootfs_overlay/etc/inittab | 41 +++++++++++++++++++ 5 files changed, 84 insertions(+), 6 deletions(-) rename linux/buildroot-config-src/{ => wally}/busybox.config (100%) rename linux/buildroot-config-src/{ => wally}/linux.config (100%) rename linux/buildroot-config-src/{ => wally}/main.config (99%) create mode 100644 linux/buildroot-config-src/wally/rootfs_overlay/.profile create mode 100644 linux/buildroot-config-src/wally/rootfs_overlay/etc/inittab diff --git a/linux/buildroot-config-src/busybox.config b/linux/buildroot-config-src/wally/busybox.config similarity index 100% rename from linux/buildroot-config-src/busybox.config rename to linux/buildroot-config-src/wally/busybox.config diff --git a/linux/buildroot-config-src/linux.config b/linux/buildroot-config-src/wally/linux.config similarity index 100% rename from linux/buildroot-config-src/linux.config rename to linux/buildroot-config-src/wally/linux.config diff --git a/linux/buildroot-config-src/main.config b/linux/buildroot-config-src/wally/main.config similarity index 99% rename from linux/buildroot-config-src/main.config rename to linux/buildroot-config-src/wally/main.config index bcdd727ff..7e5f68df7 100644 --- a/linux/buildroot-config-src/main.config +++ b/linux/buildroot-config-src/wally/main.config @@ -8,6 +8,7 @@ BR2_HOST_GCC_AT_LEAST_5=y BR2_HOST_GCC_AT_LEAST_6=y BR2_HOST_GCC_AT_LEAST_7=y BR2_HOST_GCC_AT_LEAST_8=y +BR2_HOST_GCC_AT_LEAST_9=y # # Target options @@ -87,7 +88,7 @@ BR2_BZCAT="bzcat" BR2_XZCAT="xzcat" BR2_LZCAT="lzip -d -c" BR2_TAR_OPTIONS="" -BR2_DEFCONFIG="./configs/wally-qemu_riscv64_virt_defconfig" +BR2_DEFCONFIG="./board/wally/main.config" BR2_DL_DIR="$(TOPDIR)/dl" BR2_HOST_DIR="$(BASE_DIR)/host" @@ -406,11 +407,10 @@ BR2_GENERATE_LOCALE="" # BR2_SYSTEM_ENABLE_NLS is not set # BR2_TARGET_TZ_INFO is not set BR2_ROOTFS_USERS_TABLES="" -BR2_ROOTFS_OVERLAY="" +BR2_ROOTFS_OVERLAY="./board/wally/rootfs_overlay" BR2_ROOTFS_POST_BUILD_SCRIPT="" BR2_ROOTFS_POST_FAKEROOT_SCRIPT="" -BR2_ROOTFS_POST_IMAGE_SCRIPT="board/qemu/post-image.sh" -BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_DEFCONFIG)" +BR2_ROOTFS_POST_IMAGE_SCRIPT="" # # Kernel @@ -430,7 +430,7 @@ BR2_LINUX_KERNEL_PATCH="" # BR2_LINUX_KERNEL_USE_DEFCONFIG is not set # BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="./linux.config" +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="./board/wally/linux.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="" BR2_LINUX_KERNEL_CUSTOM_LOGO_PATH="" BR2_LINUX_KERNEL_IMAGE=y @@ -473,7 +473,7 @@ BR2_LINUX_KERNEL_GZIP=y # Target packages # BR2_PACKAGE_BUSYBOX=y -BR2_PACKAGE_BUSYBOX_CONFIG="./busybox.config" +BR2_PACKAGE_BUSYBOX_CONFIG="./board/wally/busybox.config" BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="" # BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set # BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set diff --git a/linux/buildroot-config-src/wally/rootfs_overlay/.profile b/linux/buildroot-config-src/wally/rootfs_overlay/.profile new file mode 100644 index 000000000..65dccfef0 --- /dev/null +++ b/linux/buildroot-config-src/wally/rootfs_overlay/.profile @@ -0,0 +1,37 @@ +echo "Hello this ~/.profile is meant to demonstrate running some basic commands on Wally." +echo "I am $(whoami)" +echo "And I am on $(hostname)" +touch myFile.txt +echo "This is a line of text." > myFile.txt +echo "A second line of text." >> myFile.txt +mkdir myDir +mv myFile.txt myDir +echo "Created myFile.txt and moved it to myDir. It contains:" +cat myDir/myFile.txt +touch myScript.sh +echo "echo \"Hello this is another example script\"" > myScript.sh +chmod +x myScript.sh +echo "Created myScript.sh. Running it yields:" +./myScript.sh +cd myDir +ln -s ../myScript.sh symLinkToMyScript.sh +echo "Created symLinkToMyScript.sh. Running it yields:" +./symLinkToMyScript.sh +ln ../myScript.sh hardLinkToMyScript.sh +echo "Created hardLinkToMyScript.sh. Running it yields:" +./hardLinkToMyScript.sh +echo "Now let\'s remove all these example files and scripts" +cd / +rm -r myDir +rm myScript.sh +echo "Here is disk usage:" +df -h +echo "And here are the current processes:" +ps +echo "We can create a user." +cd / +mkdir home +echo "password\npassword\n" | adduser myUser +su -c "cd ~; echo \"I am $(whoami) (a new user) and my home directory is $(pwd)\"" +echo "And finally a login prompt." +login diff --git a/linux/buildroot-config-src/wally/rootfs_overlay/etc/inittab b/linux/buildroot-config-src/wally/rootfs_overlay/etc/inittab new file mode 100644 index 000000000..7ae8de339 --- /dev/null +++ b/linux/buildroot-config-src/wally/rootfs_overlay/etc/inittab @@ -0,0 +1,41 @@ +# /etc/inittab +# +# Copyright (C) 2001 Erik Andersen +# +# Note: BusyBox init doesn't support runlevels. The runlevels field is +# completely ignored by BusyBox init. If you want runlevels, use +# sysvinit. +# +# Format for each entry: ::: +# +# id == tty to run on, or empty for /dev/console +# runlevels == ignored +# action == one of sysinit, respawn, askfirst, wait, and once +# process == program to run + +# Startup the system +::sysinit:/bin/mount -t proc proc /proc +::sysinit:/bin/mount -o remount,rw / +::sysinit:/bin/mkdir -p /dev/pts /dev/shm +::sysinit:/bin/mount -a +::sysinit:/sbin/swapon -a +null::sysinit:/bin/ln -sf /proc/self/fd /dev/fd +null::sysinit:/bin/ln -sf /proc/self/fd/0 /dev/stdin +null::sysinit:/bin/ln -sf /proc/self/fd/1 /dev/stdout +null::sysinit:/bin/ln -sf /proc/self/fd/2 /dev/stderr +::sysinit:/bin/hostname -F /etc/hostname +# now run any rc scripts +::sysinit:/etc/init.d/rcS + +# (commented out) Put a getty on the serial port +#console::respawn:/sbin/getty -L console 0 vt100 # GENERIC_SERIAL +# Actually no, let's automatically login +console::respawn:-/bin/sh + +# Stuff to do for the 3-finger salute +#::ctrlaltdel:/sbin/reboot + +# Stuff to do before rebooting +::shutdown:/etc/init.d/rcK +::shutdown:/sbin/swapoff -a +::shutdown:/bin/umount -a -r From 4e1b50e50c73869869f9633534cc7fbb7e0081ae Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 27 Mar 2022 19:05:44 -0700 Subject: [PATCH 197/199] fix parseGDBtoTrace.py to expect the CSRs that QEMU actually prints out --- linux/testvector-generation/parseGDBtoTrace.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py index 412db5bb5..97145a358 100755 --- a/linux/testvector-generation/parseGDBtoTrace.py +++ b/linux/testvector-generation/parseGDBtoTrace.py @@ -138,9 +138,9 @@ if len(sys.argv) != 2: sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n >') interruptFname = sys.argv[1] # reg number -RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45, 'sstatus': 46, 'sip': 47, 'sie': 48} +RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45, 'mscratch': 46, 'sscratch': 47, 'satp': 48} # initial state -CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0, 'sstatus': 0, 'sip': 0, 'sie': 0}, {}, None, None, None] +CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0, 'mscratch': 0, 'sscratch': 0, 'satp': 0}, {}, None, None, None] #with open (InputFile, 'r') as InputFileFP: #lines = InputFileFP.readlines() From 9b5bbd29b4f3f0a25c76fd64050493bee9dc5308 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 27 Mar 2022 19:16:39 -0700 Subject: [PATCH 198/199] change genCheckpoint.sh to only log 128MB of RAM --- linux/testvector-generation/genCheckpoint.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index dea4d5551..4ac478825 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -109,7 +109,7 @@ then x/1xw 0x0C201000 set logging off shell echo \"GDB storing RAM to $rawRamFile\" - dump binary memory $rawRamFile 0x80000000 0xffffffff + dump binary memory $rawRamFile 0x80000000 0x07ffffff kill q end_of_script From 501dc7cd68acee7625909a7c65afbf4a2d0bdc96 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 27 Mar 2022 20:54:59 -0700 Subject: [PATCH 199/199] fix genCheckpoint.sh binary memory dump --- linux/testvector-generation/genCheckpoint.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 4ac478825..447377b33 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -109,7 +109,7 @@ then x/1xw 0x0C201000 set logging off shell echo \"GDB storing RAM to $rawRamFile\" - dump binary memory $rawRamFile 0x80000000 0x07ffffff + dump binary memory $rawRamFile 0x80000000 0x87ffffff kill q end_of_script