From 27f65523151d369a373ce9c93634c5a8b3c0552d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 16 Feb 2023 11:05:24 -0600
Subject: [PATCH 01/47] keep this commit off of cvw.

---
 src/generic/mem/ram1p1rwbe.sv          |   2 +-
 src/generic/mem/ram1p1rwbe_64x128.sv   |   3 +-
 src/generic/mem/ram1p1rwbe_64x44.sv    |   9 ++-
 src/generic/mem/ram2p1r1wbe.sv         | 105 ++++++++++++++++++++++++-
 src/generic/mem/ram2p1r1wbe_1024x68.sv |   4 +-
 src/generic/mem/ram2p1r1wbe_128x64.sv  |  50 ++++++++++++
 src/generic/mem/ram2p1r1wbe_512x64.sv  |  50 ++++++++++++
 src/generic/mem/ram2p1r1wbe_64x32.sv   |   4 +-
 src/generic/mem/rom1p1r_128x64.sv      |   3 +-
 9 files changed, 218 insertions(+), 12 deletions(-)
 create mode 100644 src/generic/mem/ram2p1r1wbe_128x64.sv
 create mode 100644 src/generic/mem/ram2p1r1wbe_512x64.sv

diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index e33e708a3..a77a0eee9 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -69,7 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));
 
-  end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
+  end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
      genvar index;
      // 64 x 128-bit SRAM
      logic [WIDTH-1:0] BitWriteMask;
diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv
index fa8e32f0b..095f77c0d 100755
--- a/src/generic/mem/ram1p1rwbe_64x128.sv
+++ b/src/generic/mem/ram1p1rwbe_64x128.sv
@@ -35,6 +35,7 @@ module ram1p1rwbe_64x128(
 );
 
    // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor
-   generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+  ts1n28hpcpsvtb64x128m4sw sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+//  generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
 
 endmodule
diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv
index 7fa71f312..77ba09510 100644
--- a/src/generic/mem/ram1p1rwbe_64x44.sv
+++ b/src/generic/mem/ram1p1rwbe_64x44.sv
@@ -29,12 +29,13 @@ module ram1p1rwbe_64x44(
   input  logic 	        CEB, 
   input  logic          WEB,
   input  logic [5:0]    A, 
-  input  logic [127:0]  D,
-  input  logic [127:0]  BWEB, 
-  output logic [127:0]  Q
+  input  logic [43:0]  D,
+  input  logic [43:0]  BWEB, 
+  output logic [43:0]  Q
 );
 
    // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor
-   generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+  TS1N28HPCPSVTB64X44M4SW sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+  //generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
 
 endmodule
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index 08c232bba..0daac6ff8 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -45,8 +45,6 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 );
 
    logic [WIDTH-1:0] 		   mem[DEPTH-1:0];
-   localparam                      SRAMWIDTH = 32;
-   localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
 
   // ***************************************************************************
   // TRUE Smem macro
@@ -64,7 +62,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 				  .QA(rd1),
 				  .QB());
 
-   end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
+   end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
    
       ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
 				  .CEBA(~ce1), .CEBB(~ce2),
@@ -78,6 +76,9 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 
    end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
 
+     localparam                      SRAMWIDTH = 32;
+     localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
+
       logic [SRAMWIDTH-1:0]     SRAMReadData;      
       logic [SRAMWIDTH-1:0]     SRAMWriteData;      
       logic [SRAMWIDTH-1:0]     RD1Sets[SRAMNUMSETS-1:0];
@@ -106,6 +107,104 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 				.QA(SRAMReadData),
 				.QB());
 
+   end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 4096) begin
+
+     localparam                      SRAMWIDTH = 64;
+     localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
+
+     logic [SRAMWIDTH-1:0]           SRAMReadData;      
+     logic [SRAMWIDTH-1:0]           SRAMWriteData;      
+     logic [SRAMWIDTH-1:0]           RD1Sets[SRAMNUMSETS-1:0];
+     logic [SRAMNUMSETS-1:0]         SRAMBitMaskPre;      
+     logic [SRAMWIDTH-1:0]           SRAMBitMask;      
+     logic [$clog2(DEPTH)-1:0]       RA1Q;
+     
+     
+     onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);      
+     genvar                          index;
+     for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
+	   assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];	 
+	   assign SRAMWriteData[index*2+1:index*2] = wd2;
+	   assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};      
+     end
+     flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);      
+     assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];      
+     ram2p1r1wbe_128x64 memory2(.CLKA(clk), .CLKB(clk), 
+				                .CEBA(~ce1), .CEBB(~ce2),
+				                .WEBA('0), .WEBB(~we2),			      
+				                .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), 
+				                .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
+				                .DA('0),
+				                .DB(SRAMWriteData),
+				                .BWEBA('0), .BWEBB(SRAMBitMask),
+				                .QA(SRAMReadData),
+				                .QB());
+
+   end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 16384) begin
+
+     localparam                      SRAMWIDTH = 64;
+     localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
+
+     logic [SRAMWIDTH-1:0]           SRAMReadData;      
+     logic [SRAMWIDTH-1:0]           SRAMWriteData;      
+     logic [SRAMWIDTH-1:0]           RD1Sets[SRAMNUMSETS-1:0];
+     logic [SRAMNUMSETS-1:0]         SRAMBitMaskPre;      
+     logic [SRAMWIDTH-1:0]           SRAMBitMask;      
+     logic [$clog2(DEPTH)-1:0]       RA1Q;
+     
+     
+     onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);      
+     genvar                          index;
+     for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
+	   assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];	 
+	   assign SRAMWriteData[index*2+1:index*2] = wd2;
+	   assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};      
+     end
+     flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);      
+     assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];      
+     ram2p1r1wbe_512x64 memory2(.CLKA(clk), .CLKB(clk), 
+				                .CEBA(~ce1), .CEBB(~ce2),
+				                .WEBA('0), .WEBB(~we2),			      
+				                .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), 
+				                .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
+				                .DA('0),
+				                .DB(SRAMWriteData),
+				                .BWEBA('0), .BWEBB(SRAMBitMask),
+				                .QA(SRAMReadData),
+				                .QB());
+
+   end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 65536) begin
+
+     localparam                      SRAMWIDTH = 64;
+     localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
+
+     logic [SRAMWIDTH-1:0]           SRAMReadData;      
+     logic [SRAMWIDTH-1:0]           SRAMWriteData;      
+     logic [SRAMWIDTH-1:0]           RD1Sets[SRAMNUMSETS-1:0];
+     logic [SRAMNUMSETS-1:0]         SRAMBitMaskPre;      
+     logic [SRAMWIDTH-1:0]           SRAMBitMask;      
+     logic [$clog2(DEPTH)-1:0]       RA1Q;
+     
+     
+     onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);      
+     genvar                          index;
+     for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
+	   assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];	 
+	   assign SRAMWriteData[index*2+1:index*2] = wd2;
+	   assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};      
+     end
+     flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);      
+     assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];      
+     ram2p1r1wbe_2048x64 memory2(.CLKA(clk), .CLKB(clk), 
+				                .CEBA(~ce1), .CEBB(~ce2),
+				                .WEBA('0), .WEBB(~we2),			      
+				                .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), 
+				                .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
+				                .DA('0),
+				                .DB(SRAMWriteData),
+				                .BWEBA('0), .BWEBB(SRAMBitMask),
+				                .QA(SRAMReadData),
+				                .QB());
    end else begin
       
       // ***************************************************************************
diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv
index e6a6b6257..6dbc23b3c 100755
--- a/src/generic/mem/ram2p1r1wbe_1024x68.sv
+++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv
@@ -42,7 +42,9 @@ module ram2p1r1wbe_1024x68(
 );
 
    // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor
-   generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+  TSDN28HPCPA1024X68M4MW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
 			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+//   generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+//			     .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
 
 endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv
new file mode 100644
index 000000000..49d2631ee
--- /dev/null
+++ b/src/generic/mem/ram2p1r1wbe_128x64.sv
@@ -0,0 +1,50 @@
+///////////////////////////////////////////
+// ram2p1rwbe_128x64.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram2p1r1wbe_128x64( 
+  input  logic          CLKA, 
+  input  logic          CLKB, 
+  input  logic 	        CEBA, 
+  input  logic 	        CEBB, 
+  input  logic          WEBA,
+  input  logic          WEBB,
+  input  logic [6:0]    AA, 
+  input  logic [6:0]    AB, 
+  input  logic [63:0]   DA,
+  input  logic [63:0]   DB,
+  input  logic [63:0]   BWEBA, 
+  input  logic [63:0]   BWEBB, 
+  output logic [63:0]   QA,
+  output logic [63:0]   QB
+);
+
+   // replace "generic128x64RAM" with "TSDN..128X64.." module from your memory vendor
+  TSDN28HPCPA128X64M4FW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+			   .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+  // generic128x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+//			   .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+
+endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv
new file mode 100644
index 000000000..14fbea75c
--- /dev/null
+++ b/src/generic/mem/ram2p1r1wbe_512x64.sv
@@ -0,0 +1,50 @@
+///////////////////////////////////////////
+// ram2p1rwbe_2048x64.sv
+//
+// Written: james.stine@okstate.edu 28 January 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram2p1r1wbe_2048x64( 
+  input  logic          CLKA, 
+  input  logic          CLKB, 
+  input  logic 	        CEBA, 
+  input  logic 	        CEBB, 
+  input  logic          WEBA,
+  input  logic          WEBB,
+  input  logic [8:0]    AA, 
+  input  logic [8:0]    AB, 
+  input  logic [63:0]   DA,
+  input  logic [63:0]   DB,
+  input  logic [63:0]   BWEBA, 
+  input  logic [63:0]   BWEBB, 
+  output logic [63:0]   QA,
+  output logic [63:0]   QB
+);
+
+   // replace "generic2048x64RAM" with "TSDN..2048X64.." module from your memory vendor
+  TSDN28HPCPA2048X64MMFW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+			   .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+  // generic2048x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+//			   .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+
+endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv
index 8bc19637d..713aa84f5 100755
--- a/src/generic/mem/ram2p1r1wbe_64x32.sv
+++ b/src/generic/mem/ram2p1r1wbe_64x32.sv
@@ -42,7 +42,9 @@ module ram2p1r1wbe_64x32(
 );
 
    // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
-   generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+  TSDN28HPCPA64X32M4MW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
 			   .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
+  // generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
+//			   .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
 
 endmodule
diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv
index 14e83f5f5..3c7ea4842 100755
--- a/src/generic/mem/rom1p1r_128x64.sv
+++ b/src/generic/mem/rom1p1r_128x64.sv
@@ -32,6 +32,7 @@ module rom1p1r_128x64(
 );
 
    // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
-   generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
+ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q);
+//   generic64x128ROM romIP (.CLK, .CEB, .A, .Q); 
 
 endmodule

From c8324b055bcac8c10b03a360126028b13bcc7edb Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 16 Feb 2023 11:06:53 -0600
Subject: [PATCH 02/47] dc shell setup.

---
 synthDC/.synopsys_dc.setup | 51 ++++++++++++++------------------------
 1 file changed, 18 insertions(+), 33 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 2fdc11c27..f058bd820 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -3,39 +3,30 @@
 set CURRENT_DIR  [exec pwd]
 set search_path [list "./" ]
 
-set tech $::env(TECH)
-
-if { [info exists ::env(RISCV)] } {
-  set timing_lib $::env(RISCV)/cad/lib
-} else {
-  set timing_lib ../addins   
-}
-
-if {$tech == "sky130"} {
-    set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
-    lappend search_path $s8lib
-} elseif {$tech == "sky90"} {
-    set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
-    lappend search_path $s9lib
-} elseif {$tech == "tsmc28"} {
-    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
-    lappend search_path $s10lib
-}
+set memory ../memory
+set pdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/7-track/tcbn28hpcplusbwp7t30p140-set/
+set tsmc28nlib $pdk/tcbn28hpcplusbwp7t30p140_190a_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp7t30p140_180a
+set iolib1p8 /import/yukari1/pdk/TSMC/28/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a/
+lappend search_path $tsmc28nlib
+lappend search_path $iolib1p8
+lappend search_path $memory
 
 # Synthetic libraries
 set synthetic_library   [list dw_foundation.sldb]
 
-# Set standard cell libraries
+# Set OKSTATE standard cell libraries
 set target_library [list]
 
-#lappend target_library scc9gena_tt_1.2v_25C.db
-if {$tech == "sky130"} {
-    lappend target_library $s8lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
-} elseif {$tech == "sky90"} {
-    lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
-} elseif {$tech == "tsmc28"} {
-    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
-}
+lappend target_library $iolib1p8/tphn28hpcpgv18tt0p9v1p8v25c.db
+lappend target_library $tsmc28nlib/tcbn28hpcplusbwp7t30p140tt0p9v25c.db
+lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
+lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
+lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
+lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db
+lappend target_library $memory/dbs/tsdn28hpcpa128x64m4fw_tt0p9v25c.db
+lappend target_library $memory/dbs/tsdn28hpcpa512x64m4fw_tt0p9v25c.db
+lappend target_library $memory/dbs/tsdn28hpcpa2048x64m4mw_tt0p9v25c.db
 
 # Set Link Library
 set link_library "$target_library $synthetic_library"
@@ -48,12 +39,6 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-if {$tech == "tsmc28"} {
-    set memory /home/jstine/WallyMem/rv64gc/
-    lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
-    lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
-    lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
-}
 
 # Set up User Information
 set company "Oklahoma State University"

From a325adf1be97e4ac96a1fff380be9343b6b798ed Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Feb 2023 10:57:50 -0600
Subject: [PATCH 03/47] Fixed bug with branch predictor.

---
 src/ifu/bpred/bpred.sv | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index f50232527..3240a29c9 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -222,8 +222,7 @@ module bpred (
   assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
   
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
-  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
-  //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark
+  assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
 
   // Output the predicted PC or corrected PC on miss-predict.
   // Selects the BP or PC+2/4.

From 0d271130b9679c7ae707d4c144c674aa2179e229 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Feb 2023 15:37:03 -0600
Subject: [PATCH 04/47] Fixed a branch predictor performance issue.

---
 src/ifu/bpred/bpred.sv             |  6 ++++++
 src/ifu/bpred/speculativegshare.sv | 12 +++++++++---
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 3240a29c9..f11ae37f9 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -222,8 +222,14 @@ module bpred (
   assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
   
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
+  //assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
   assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
 
+  logic BPPredWrongEAlt;
+  logic NotMatch;
+  assign BPPredWrongEAlt = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark
+  assign NotMatch = BPPredWrongE != BPPredWrongEAlt;
+
   // Output the predicted PC or corrected PC on miss-predict.
   // Selects the BP or PC+2/4.
   mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv
index 1dd7d4cdb..48601021a 100644
--- a/src/ifu/bpred/speculativegshare.sv
+++ b/src/ifu/bpred/speculativegshare.sv
@@ -101,9 +101,16 @@ module speculativegshare #(parameter int k = 10 ) (
   // If the front end is flushed or the direction prediction is wrong, reset to
   // most recent valid GHR.  For a BP wrong this is GHRD with the correct prediction shifted in.
   // For FlushE this is GHRE.  GHRNextE is both.
+  logic [k-1:0] 		   GHRClassWrongAndPredF;
+  logic [k-1:0] 		   GHRClassWrong;
+  mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF);
+
   assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
-  mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
-					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
+//  mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
+//					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
+
+  mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0], 
+					{FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF);  
 
   // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
   flopenr  #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);	
@@ -112,7 +119,6 @@ module speculativegshare #(parameter int k = 10 ) (
   // With instruction class prediction, the class could be wrong and is checked in Decode.
   // If it is wrong and branch does exist then shift right and insert the prediction.
   // If the branch does not exist then shift left and use GHRLastF to restore the LSB.
-  logic [k-1:0] 		   GHRClassWrong;
   mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
   // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
   mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);

From df4a27a2e318cb922e242d2dd33f431391f5df72 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Feb 2023 15:53:15 -0600
Subject: [PATCH 05/47] Updated global history predictor.

---
 src/ifu/bpred/speculativeglobalhistory.sv | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
index 8ebda61c5..76ee5a47c 100644
--- a/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/src/ifu/bpred/speculativeglobalhistory.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-module speculativeglobalhistory #(parameter int k = 10 ) (
+module speculativegshare #(parameter int k = 10 ) (
   input logic 			  clk,
   input logic 			  reset,
   input logic 			  StallF, StallD, StallE, StallM, StallW, 
@@ -57,9 +57,9 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   logic 				   FlushDOrDirWrong;
   
   assign IndexNextF = GHRNextF;
-  assign IndexF = GHRF;
-  assign IndexD = GHRD;
-  assign IndexE = GHRE;
+  assign IndexF = GHRF        ;
+  assign IndexD = GHRD[k-1:0] ;
+  assign IndexE = GHRE[k-1:0] ;
       
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
@@ -100,9 +100,16 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   // If the front end is flushed or the direction prediction is wrong, reset to
   // most recent valid GHR.  For a BP wrong this is GHRD with the correct prediction shifted in.
   // For FlushE this is GHRE.  GHRNextE is both.
+  logic [k-1:0] 		   GHRClassWrongAndPredF;
+  logic [k-1:0] 		   GHRClassWrong;
+  mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF);
+
   assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
-  mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
-					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
+//  mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
+//					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
+
+  mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0], 
+					{FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF);  
 
   // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
   flopenr  #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);	
@@ -111,7 +118,6 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   // With instruction class prediction, the class could be wrong and is checked in Decode.
   // If it is wrong and branch does exist then shift right and insert the prediction.
   // If the branch does not exist then shift left and use GHRLastF to restore the LSB.
-  logic [k-1:0] 		   GHRClassWrong;
   mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
   // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
   mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);

From a95be0b56744a7e19e6c13aa2272fe499ae677ec Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Feb 2023 15:53:49 -0600
Subject: [PATCH 06/47] More updates.

---
 src/ifu/bpred/speculativeglobalhistory.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
index 76ee5a47c..ca36a19f1 100644
--- a/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/src/ifu/bpred/speculativeglobalhistory.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// gsharePredictor.sv
+// speculativeglobalhistory.sv
 //
 // Written: Shreya Sanghai
 // Email: ssanghai@hmc.edu
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-module speculativegshare #(parameter int k = 10 ) (
+module speculativeglobalhistory #(parameter int k = 10 ) (
   input logic 			  clk,
   input logic 			  reset,
   input logic 			  StallF, StallD, StallE, StallM, StallW, 

From 2f1bebfd5755bae5645d367e302016caf4fcc6c2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Feb 2023 16:05:48 -0600
Subject: [PATCH 07/47] Fixed global history predictor.

---
 src/ifu/bpred/bpred.sv         |  2 +-
 src/ifu/bpred/globalhistory.sv | 25 +++++++++++++------------
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index f11ae37f9..af7591524 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -101,7 +101,7 @@ module bpred (
 
   end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
     globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
diff --git a/src/ifu/bpred/globalhistory.sv b/src/ifu/bpred/globalhistory.sv
index e951a0151..18ad695b1 100644
--- a/src/ifu/bpred/globalhistory.sv
+++ b/src/ifu/bpred/globalhistory.sv
@@ -28,34 +28,35 @@
 
 `include "wally-config.vh"
 
-module globalhistory #(parameter k = 10) (
+module global #(parameter k = 10) (
   input logic             clk,
   input logic             reset,
-  input logic             StallF, StallD, StallE, StallM,
-  input logic             FlushD, FlushE, FlushM,
-  //   input logic [`XLEN-1:0] LookUpPC,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCM,
   input logic             BranchInstrE, BranchInstrM, PCSrcE
 );
 
+  logic [k-1:0]            IndexNextF, IndexE;
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
+
+  assign IndexNextF = GHR;
+  assign IndexE = GHRM;
   
-      
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
-    .ra1(GHR),
+    .ra1(IndexNextF),
     .rd1(DirPredictionF),
-    .wa2(GHRE),
-    .wd2(NewDirPredictionE),
-    .we2(BranchInstrE & ~StallM & ~FlushM),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallW & ~FlushW),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -66,7 +67,6 @@ module globalhistory #(parameter k = 10) (
 
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-
   assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
   flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
@@ -74,6 +74,7 @@ module globalhistory #(parameter k = 10) (
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
 
 
 endmodule

From 0cacfbd322769044ba890b4375595832c7475fd1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Feb 2023 16:08:34 -0600
Subject: [PATCH 08/47] Renamed globalhistory predictor.

---
 src/ifu/bpred/globalhistory.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ifu/bpred/globalhistory.sv b/src/ifu/bpred/globalhistory.sv
index 18ad695b1..a88804773 100644
--- a/src/ifu/bpred/globalhistory.sv
+++ b/src/ifu/bpred/globalhistory.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-module global #(parameter k = 10) (
+module globalhistory #(parameter k = 10) (
   input logic             clk,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,

From d44cb1febb28430e78bc9bfb46871b8998b10199 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 18 Feb 2023 23:55:46 -0600
Subject: [PATCH 09/47] Minor fix.

---
 src/ifu/bpred/bpred.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index af7591524..115db895c 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -100,7 +100,7 @@ module bpred (
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
-    globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+    globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 

From 9ee48637dc933dffc2c26d41c3f43c5f5a0e4acf Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Feb 2023 00:17:37 -0600
Subject: [PATCH 10/47] Possibly much better branch predictor implemention. The
 complexity is significantly reduced.

---
 config/rv32gc/wally-config.vh  |   4 +-
 config/rv64gc/wally-config.vh  |   2 +-
 src/ifu/bpred/bpred.sv         |   6 ++
 src/ifu/bpred/gshareForward.sv | 108 +++++++++++++++++++++++++++++++++
 testbench/testbench.sv         |   4 +-
 testbench/tests.vh             |   2 +-
 6 files changed, 120 insertions(+), 6 deletions(-)
 create mode 100644 src/ifu/bpred/gshareForward.sv

diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
index 089a9ada4..c40aadbc1 100644
--- a/config/rv32gc/wally-config.vh
+++ b/config/rv32gc/wally-config.vh
@@ -132,8 +132,8 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
-`define BPRED_SIZE 10
+`define BPRED_TYPE "GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_SIZE 16
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
index c3dd87295..e02f683c7 100644
--- a/config/rv64gc/wally-config.vh
+++ b/config/rv64gc/wally-config.vh
@@ -135,7 +135,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPRED_TYPE "GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 115db895c..c7a8d196e 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -119,6 +119,12 @@ module bpred (
       .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
       .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
 
+  end else if (`BPRED_TYPE == "GSHARE_FORWARD") begin:Predictor
+    gshareForward #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
+      .PCSrcE);
+	
   end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
     // *** Fix me
 /* -----\/----- EXCLUDED -----\/-----
diff --git a/src/ifu/bpred/gshareForward.sv b/src/ifu/bpred/gshareForward.sv
new file mode 100644
index 000000000..77ab90fba
--- /dev/null
+++ b/src/ifu/bpred/gshareForward.sv
@@ -0,0 +1,108 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module gshareForward #(parameter k = 10) (
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      DirPredictionF, 
+  output logic            DirPredictionWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE
+);
+
+  logic                    MatchF, MatchD, MatchE, MatchM;
+  logic                    MatchNextX, MatchXF;
+
+  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPrediction, ForwardDirPredictionF;
+  logic [1:0]              NewDirPredictionE, NewDirPredictionM;
+
+
+  logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE, IndexM;
+
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]            GHRNext, GHRNextF;
+  logic                    PCSrcM;
+
+  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+
+  assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
+  assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
+  assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
+
+  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
+
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
+                                   MatchD ? {2{DirPredictionD[1]}} :
+                                   MatchE ? {NewDirPredictionE} :
+                                   NewDirPredictionM ;
+  
+  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
+
+  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
+
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallM & ~FlushM),
+    .ra1(IndexNextF),
+    .rd1(TableDirPredictionF),
+    .wa2(IndexM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallW & ~FlushW),
+    .bwe2(1'b1));
+
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, DirPredictionD, DirPredictionE);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
+
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+  assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
+  assign GHRF = BranchInstrD  ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
+  assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
+  assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
+
+  assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
+  assign GHRM = GHR;
+
+  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+endmodule
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 329d4c605..a85ffd65b 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -28,8 +28,8 @@
 `include "wally-config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 0
-`define BPRED_LOGGER 0
+`define PrintHPMCounters 1
+`define BPRED_LOGGER 1
 
 module testbench;
   parameter DEBUG=0;
diff --git a/testbench/tests.vh b/testbench/tests.vh
index ec6f04f43..6ab4533fa 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -51,6 +51,7 @@ string tvpaths[] = '{
   string embench[] = '{
     `EMBENCH,
     "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
+    "bd_speedopt_speed/src/nsichneu/nsichneu",
     "bd_speedopt_speed/src/aha-mont64/aha-mont64",
     "bd_speedopt_speed/src/crc32/crc32",
     "bd_speedopt_speed/src/edn/edn",
@@ -61,7 +62,6 @@ string tvpaths[] = '{
     "bd_speedopt_speed/src/nettle-aes/nettle-aes",
     "bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
     "bd_speedopt_speed/src/nbody/nbody",
-    "bd_speedopt_speed/src/nsichneu/nsichneu",
     "bd_speedopt_speed/src/picojpeg/picojpeg",
     // "bd_speedopt_speed/src/primecount/primecount",
     "bd_speedopt_speed/src/qrduino/qrduino",

From 7d031fcae067f00eb46b5d41876f425ab2f00806 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 07:03:31 -0800
Subject: [PATCH 11/47] Disabled W64M register for RV32

---
 src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 5d490df28..0a96e1b1a 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -129,7 +129,6 @@ module fdivsqrtpreproc (
 
     // pipeline registers
     flopen #(1)        mdureg(clk, IFDivStartE, IntDivE,     IntDivM);
-    flopen #(1)        w64reg(clk, IFDivStartE, W64E,     W64M);
     flopen #(1)       altbreg(clk, IFDivStartE, ALTBE,    ALTBM);
     flopen #(1)    negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
     flopen #(1)      bzeroreg(clk, IFDivStartE, BZeroE,   BZeroM);
@@ -137,6 +136,8 @@ module fdivsqrtpreproc (
     flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE,       nM);
     flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE,       mM);
     flopen #(`XLEN)   srcareg(clk, IFDivStartE, AE,       AM);
+    if (`XLEN==64) 
+      flopen #(1)      w64reg(clk, IFDivStartE, W64E,     W64M);
 
   end else begin // Int not supported
     assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};

From 53875a9bbdc671ee070b56ea1950acfb331ff83a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 15:29:41 -0800
Subject: [PATCH 12/47] New extractArea script to generate area tables

---
 synthDC/extractArea.pl | 118 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)
 create mode 100755 synthDC/extractArea.pl

diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl
new file mode 100755
index 000000000..d16c74df5
--- /dev/null
+++ b/synthDC/extractArea.pl
@@ -0,0 +1,118 @@
+#!/bin/perl -W
+
+###########################################
+## extractArea.pl
+##
+## Written: David_Harris@hmc.edu 
+## Created: 19 Feb 2023
+## Modified: 
+##
+## Purpose: Pull area statistics from run directory
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+
+use strict;
+use warnings;
+import os;
+
+my %configResults;
+my $dir = "runs";
+my $macro = "Macro/Black Box area:";
+my $seq = "Noncombinational area:";
+my $buf = "Buf/Inv area:";
+my $comb = "Combinational area:";
+my $macroC = "Number of macros/black boxes:";
+my $seqC = "Number of sequential cells:";
+my $bufC = "Number of buf/inv:";
+my $combC = "Number of combinational cells:";
+my @keywords = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", $macro, $seq, $buf, $comb, $macroC, $seqC, $bufC, $combC);
+my @keywordsp = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", 
+                 "RAMs", "Flip-flops", "Inv/Buf", "Logic", "RAMs Cnt", "Flip-flops Cnt", "Inv/Buf Cnt", "Logic Cnt", "Total Cnt");
+my @configs = ("rv32e", "rv32i", "rv32imc", "rv32gc", "rv64i", "rv64gc");
+
+opendir(DIR, $dir) or die "Could not open $dir";
+
+while (my $filename = readdir(DIR)) {
+    if ($filename =~ /orig_tsmc28psyn/) {
+#        print "$filename\n";
+        &processRun("$dir/$filename");
+    }
+}
+closedir(DIR);
+
+# print table of results
+printf("%20s\t", "");
+foreach my $config (@configs) {
+    printf("%s\t", $config);
+}
+print ("\n");
+foreach my $kw (@keywordsp) {
+    my $kws = substr($kw, 0, 3);
+    printf("%20s\t", $kw);
+    foreach my $config (@configs) {
+        my $r = $configResults{$config};
+        if (exists ${$r}{$kw}) {
+            my $area = ${$r}{$kw};
+            while ($area =~ s/(\d+)(\d\d\d)/$1\,$2/){};
+            #print "${$r}{$kw}\t";
+            print "$area\t";
+        } else {
+            print("\t");
+        }        
+    }
+    print("\n");
+}
+
+sub processRun {
+    my $fname = shift;
+    my $ffname = "$fname/reports/wallypipelinedcore_area.rep";
+    open(FILE, "$ffname") or die ("Could not read $ffname");
+
+    # Extract configuration from fname;
+    $fname =~ /_([^_]*)_orig/; 
+    my $config = $1;
+    #print("Reading $config from $ffname\n");
+
+    # Search for results
+    my %results;
+    while (my $line = <FILE>) {
+        foreach my $kw (@keywords) {
+           # print "$kw $line\n";
+            if ($line =~ /^${kw}\s+(\S*)/) {
+                #print "$line $kw $1\n";
+                $results{$kw} = int($1);
+            }
+        }
+    }
+    foreach my $kw (@keywords) {
+        #print "$kw\t$results{$kw}\n";
+    }
+    $results{"Logic"} = $results{$comb} - $results{$buf};
+    $results{"Inv/Buf"} = $results{$buf};
+    $results{"Flip-flops"} = $results{$seq};
+    $results{"RAMs"} = $results{$macro};
+    $results{"Logic Cnt"} = $results{$combC} - $results{$bufC};
+    $results{"Inv/Buf Cnt"} = $results{$bufC};
+    $results{"Flip-flops Cnt"} = $results{$seqC};
+    $results{"RAMs Cnt"} = $results{$macroC};
+    $results{"Total Cnt"} = $results{$macroC} + $results{$seqC} +  $results{$combC};
+    close(FILE);
+    $configResults{$config} = \%results;
+}
\ No newline at end of file

From ac21bed64d6cda7cb4944919d60bde1b361fc4c6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 15:31:00 -0800
Subject: [PATCH 13/47] Moved conditional instantiation outside pmpchecker

---
 src/mmu/mmu.sv        | 18 +++++++++++------
 src/mmu/pmpchecker.sv | 46 +++++++++++++++++++------------------------
 2 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index 8a440c39d..5b5248161 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -107,15 +107,21 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
     .Cacheable, .Idempotent, .SelTIM,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
-  pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
-    .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-    .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
-    .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
+  if (`PMP_ENTRIES > 0) 
+    pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
+      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
+      .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
+      .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
+  else begin
+    assign PMPInstrAccessFaultF     = 0;
+    assign PMPStoreAmoAccessFaultM  = 0;
+    assign PMPLoadAccessFaultM      = 0;
+  end
 
   // Access faults
   // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
-  assign InstrAccessFaultF    = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
-  assign LoadAccessFaultM     = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
+  assign InstrAccessFaultF    = (PMAInstrAccessFaultF    | PMPInstrAccessFaultF)    & ~(Translate & ~TLBHit);
+  assign LoadAccessFaultM     = (PMALoadAccessFaultM     | PMPLoadAccessFaultM)     & ~(Translate & ~TLBHit);
   assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
 
   // Misaligned faults
diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
index a57961365..de8ce7b31 100644
--- a/src/mmu/pmpchecker.sv
+++ b/src/mmu/pmpchecker.sv
@@ -49,34 +49,28 @@ module pmpchecker (
   output logic                     PMPStoreAmoAccessFaultM
 );
 
-  if (`PMP_ENTRIES > 0) begin
-    // Bit i is high when the address falls in PMP region i
-    logic                    EnforcePMP;
-    logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
-    logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
-    logic [`PMP_ENTRIES-1:0] Active;     // PMP register i is non-null
-    logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
-    logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
+  // Bit i is high when the address falls in PMP region i
+  logic                    EnforcePMP;
+  logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
+  logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
+  logic [`PMP_ENTRIES-1:0] Active;     // PMP register i is non-null
+  logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
+  logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
 
-    pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
-      .PhysicalAddress, 
-      .PMPCfg(PMPCFG_ARRAY_REGW),
-      .PMPAdr(PMPADDR_ARRAY_REGW),
-      .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
-      .PAgePMPAdrOut(PAgePMPAdr),
-      .Match, .Active, .L, .X, .W, .R);
+  pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
+    .PhysicalAddress, 
+    .PMPCfg(PMPCFG_ARRAY_REGW),
+    .PMPAdr(PMPADDR_ARRAY_REGW),
+    .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
+    .PAgePMPAdrOut(PAgePMPAdr),
+    .Match, .Active, .L, .X, .W, .R);
 
-    priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
+  priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 
-    // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
-    assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
+  // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
+  assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
 
-    assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
-    assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
-    assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
-  end else begin
-    assign PMPInstrAccessFaultF     = 0;
-    assign PMPStoreAmoAccessFaultM  = 0;
-    assign PMPLoadAccessFaultM      = 0;
-  end
+  assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
+  assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
+  assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
  endmodule

From 636b096026dafc75f6e3ef1b63a9c8e14cd9b0c7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 15:31:33 -0800
Subject: [PATCH 14/47] Run extractArea at end of extractSummary

---
 synthDC/extractSummary.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py
index 85bc6f0aa..94902f9c9 100755
--- a/synthDC/extractSummary.py
+++ b/synthDC/extractSummary.py
@@ -263,3 +263,4 @@ if __name__ == '__main__':
     plotConfigs('sky90', mod='orig')
     plotConfigs('tsmc28psyn', mod='orig')
     normAreaDelay(mod='orig')
+    os.system("./extractArea.pl");

From ce97aa7e63a9867dfd9afea38369e36c609b0aec Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 15:32:32 -0800
Subject: [PATCH 15/47] Removed orig feature  from featuresweep to avoid
 redundancy with configsweep

---
 synthDC/wallySynth.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 73bb58698..831ffca2e 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -56,7 +56,7 @@ if __name__ == '__main__':
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: 
+        for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0']: 
             runSynth(config, mod, tech, freq, maxopt, usesram)
     else:
         defaultfreq = 500 if tech == 'sky90' else 1500

From 5b8d1e4134c31b2d1bfd4da746654d6c14041319 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 16:08:23 -0800
Subject: [PATCH 16/47] PMP checker size check to avoid spurious warnings

---
 src/mmu/pmpchecker.sv | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
index de8ce7b31..9c9c745bb 100644
--- a/src/mmu/pmpchecker.sv
+++ b/src/mmu/pmpchecker.sv
@@ -57,13 +57,14 @@ module pmpchecker (
   logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
   logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
 
-  pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
-    .PhysicalAddress, 
-    .PMPCfg(PMPCFG_ARRAY_REGW),
-    .PMPAdr(PMPADDR_ARRAY_REGW),
-    .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
-    .PAgePMPAdrOut(PAgePMPAdr),
-    .Match, .Active, .L, .X, .W, .R);
+  if (`PMP_ENTRIES > 0) 
+    pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
+      .PhysicalAddress, 
+      .PMPCfg(PMPCFG_ARRAY_REGW),
+      .PMPAdr(PMPADDR_ARRAY_REGW),
+      .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
+      .PAgePMPAdrOut(PAgePMPAdr),
+      .Match, .Active, .L, .X, .W, .R);
 
   priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 

From 06872e382297f463d1b82174b6286e8f9ffc151f Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 16:14:38 -0800
Subject: [PATCH 17/47] Adjusted DTIM to always be 512B independent of XLEN

---
 src/lsu/dtim.sv | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv
index 4a5cba1f2..9383b7760 100644
--- a/src/lsu/dtim.sv
+++ b/src/lsu/dtim.sv
@@ -42,12 +42,16 @@ module dtim(
 
   logic                      we;
  
-  localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8);
-  localparam OFFSET     = $clog2(`LLEN/8);
+  localparam LLENBYTES  = `LLEN/8;
+  // verilator  lint_off WIDTH 
+  localparam DEPTH      = `DTIM_RANGE/LLENBYTES;
+  // verilator  lint_on WIDTH 
+  localparam ADDR_WDITH = $clog2(DEPTH);
+  localparam OFFSET     = $clog2(LLENBYTES);
 
   assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
 
-  ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) 
+  ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(`LLEN)) 
     ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
   

From 5b197f4f9daf6a4aeb1c68d2fa0badefc6b481cf Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 19:59:07 -0800
Subject: [PATCH 18/47] Parameterized btb to depend on BPRED_SIZE

---
 src/ifu/bpred/bpred.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index a65633c92..aacf3b69f 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -137,7 +137,8 @@ module bpred (
   // Part 2 Branch target address prediction
   // BTB contains target address for all CFI
 
-  btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
+  btb #(`BPRED_SIZE) 
+    TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
           .PCNextF, .PCF, .PCD, .PCE,
           .PredPCF,
           .BTBPredInstrClassF,

From bf5f776501d043e141c588a00988a7083a3e8064 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 19:59:30 -0800
Subject: [PATCH 19/47] Reduced rv32imc int divider to 2 copies to avoid it
 being on the critical path

---
 config/rv32imc/wally-config.vh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
index 010b6599f..52dfef069 100644
--- a/config/rv32imc/wally-config.vh
+++ b/config/rv32imc/wally-config.vh
@@ -68,7 +68,7 @@
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
+`define IDIV_BITSPERCYCLE 2
 `define IDIV_ON_FPU 0
 
 // Legal number of PMP entries are 0, 16, or 64

From c5090cd8673977c53041d2c0e073554aec9ca156 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 20:05:39 -0800
Subject: [PATCH 20/47] Added noAtomic feature to swweep

---
 synthDC/Makefile      | 5 +++++
 synthDC/wallySynth.py | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 034b2f86e..5ea9677c5 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -89,6 +89,7 @@ endif
 # when mod = noPriv, the privileged unit and PMP are disabled
 # when mod = noFPU, the FPU, privileged unit, and PMP are disabled
 # when mod = noMulDiv, the MDU, FPU, privileged unit, and PMP are disabled.
+# when mod = noAtomic, the Atomic, MDU, FPU, privileged unit, and PMP are disabled
 
 ifneq ($(MOD), orig)
 	# PMP 0
@@ -103,6 +104,10 @@ ifneq ($(MOD), noPriv)
 ifneq ($(MOD), noFPU)
 	# no muldiv
 	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh
+ifneq ($(MOD), noMulDiv)
+	# no atomic
+	sed -i 's/1 *<< *0/0 << 0/' $(CONFIGDIR)/wally-config.vh
+endif
 endif
 endif
 endif
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 831ffca2e..139bcdd60 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -56,7 +56,7 @@ if __name__ == '__main__':
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0']: 
+        for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'PMP0']: 
             runSynth(config, mod, tech, freq, maxopt, usesram)
     else:
         defaultfreq = 500 if tech == 'sky90' else 1500

From 0ac9c9e62a5b3101232c94b41d45c02cd2e54e94 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Feb 2023 20:13:50 -0800
Subject: [PATCH 21/47] Added BTB_SIZE parameter independent of BPRED_SIIZE

---
 config/buildroot/wally-config.vh  | 1 +
 config/fpga/wally-config.vh       | 1 +
 config/rv32e/wally-config.vh      | 1 +
 config/rv32gc/wally-config.vh     | 1 +
 config/rv32i/wally-config.vh      | 1 +
 config/rv32imc/wally-config.vh    | 1 +
 config/rv64fpquad/wally-config.vh | 1 +
 config/rv64gc/wally-config.vh     | 1 +
 config/rv64i/wally-config.vh      | 1 +
 src/ifu/bpred/bpred.sv            | 2 +-
 10 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
index f10e11f99..656bfbe4c 100644
--- a/config/buildroot/wally-config.vh
+++ b/config/buildroot/wally-config.vh
@@ -132,6 +132,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 
 `define HPTW_WRITES_SUPPORTED 1
diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
index d0299c4e3..a4c97a86e 100644
--- a/config/fpga/wally-config.vh
+++ b/config/fpga/wally-config.vh
@@ -141,6 +141,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 
 `define HPTW_WRITES_SUPPORTED 1
diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
index 8cd9ca3f4..8a0dd5f4b 100644
--- a/config/rv32e/wally-config.vh
+++ b/config/rv32e/wally-config.vh
@@ -136,6 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
index e45c2b093..07b4668ec 100644
--- a/config/rv32gc/wally-config.vh
+++ b/config/rv32gc/wally-config.vh
@@ -135,6 +135,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
index d400cebe9..4ef0b60e7 100644
--- a/config/rv32i/wally-config.vh
+++ b/config/rv32i/wally-config.vh
@@ -136,6 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
index 52dfef069..19da7c42f 100644
--- a/config/rv32imc/wally-config.vh
+++ b/config/rv32imc/wally-config.vh
@@ -135,6 +135,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
index 23a9aa05e..7f0c2a048 100644
--- a/config/rv64fpquad/wally-config.vh
+++ b/config/rv64fpquad/wally-config.vh
@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
index 0b8a932d6..d163dc34b 100644
--- a/config/rv64gc/wally-config.vh
+++ b/config/rv64gc/wally-config.vh
@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
index 627cac8f7..24a171a75 100644
--- a/config/rv64i/wally-config.vh
+++ b/config/rv64i/wally-config.vh
@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index aacf3b69f..1903ed984 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -137,7 +137,7 @@ module bpred (
   // Part 2 Branch target address prediction
   // BTB contains target address for all CFI
 
-  btb #(`BPRED_SIZE) 
+  btb #(`BTB_SIZE) 
     TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
           .PCNextF, .PCF, .PCD, .PCE,
           .PredPCF,

From b32093b33bfe20b27ef249c7cc3a8b51332b6428 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Feb 2023 22:49:48 -0600
Subject: [PATCH 22/47] Simplified branch predictor.

---
 bin/parseHPMC.py                  |  11 +-
 config/buildroot/wally-config.vh  |   2 +-
 config/fpga/wally-config.vh       |   2 +-
 config/rv32e/wally-config.vh      |   2 +-
 config/rv32gc/wally-config.vh     |   4 +-
 config/rv32i/wally-config.vh      |   2 +-
 config/rv32imc/wally-config.vh    |   2 +-
 config/rv64fpquad/wally-config.vh |   2 +-
 config/rv64gc/wally-config.vh     |   2 +-
 sim/wave.do                       | 492 ++++++++++++++----------------
 src/ifu/bpred/bpred.sv            |   2 +-
 11 files changed, 249 insertions(+), 274 deletions(-)

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 5b5ce522d..0cc75e108 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -150,7 +150,6 @@ if(sys.argv[1] == '-b'):
     if(sys.argv[2] == '-s'):
         summery = 1
         sys.argv = sys.argv[1::]
-    print('summery = %d' % summery)
     for config in sys.argv[2::]:
         benchmarks = ProcessFile(config)
         ComputeAverage(benchmarks)
@@ -163,7 +162,16 @@ if(sys.argv[1] == '-b'):
         print(config)
         for benchmark in benchmarks:
             (nameString, opt, dataDict) = benchmark
+            print("BENCHMARK")
+            print(nameString)
+            print(opt)
+            print(dataDict)
             benchmarkAll.append((nameString, opt, config, dataDict))
+    print('ALL!!!!!!!!!!')
+    #for bench in benchmarkAll:
+    #    print('BENCHMARK')
+    #    print(bench)
+    #print('ALL!!!!!!!!!!')
 
     # now extract all branch prediction direction miss rates for each
     # namestring + opt, config
@@ -177,7 +185,6 @@ if(sys.argv[1] == '-b'):
 
     size = len(benchmarkDict)
     index = 1
-    print('summery = %d' % summery)
     if(summery == 0):
         print('Number of plots', size)
         for benchmarkName in benchmarkDict:
diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
index 783b9d91b..4c84bd1df 100644
--- a/config/buildroot/wally-config.vh
+++ b/config/buildroot/wally-config.vh
@@ -129,7 +129,7 @@
 `define PLIC_GPIO_ID 3
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
 
 
diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
index c4d9cf629..f86b2e2ac 100644
--- a/config/fpga/wally-config.vh
+++ b/config/fpga/wally-config.vh
@@ -138,7 +138,7 @@
 `define PLIC_GPIO_ID 3
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
 
 
diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
index 24242b384..b028da8f5 100644
--- a/config/rv32e/wally-config.vh
+++ b/config/rv32e/wally-config.vh
@@ -133,7 +133,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
index c40aadbc1..a62e2b79d 100644
--- a/config/rv32gc/wally-config.vh
+++ b/config/rv32gc/wally-config.vh
@@ -132,8 +132,8 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
-`define BPRED_SIZE 16
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
index 0a081b415..56c086bed 100644
--- a/config/rv32i/wally-config.vh
+++ b/config/rv32i/wally-config.vh
@@ -133,7 +133,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
index b4293dcc6..309cfef15 100644
--- a/config/rv32imc/wally-config.vh
+++ b/config/rv32imc/wally-config.vh
@@ -132,7 +132,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
index 3757175a3..3f46c5656 100644
--- a/config/rv64fpquad/wally-config.vh
+++ b/config/rv64fpquad/wally-config.vh
@@ -135,7 +135,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
index e02f683c7..017bd9cba 100644
--- a/config/rv64gc/wally-config.vh
+++ b/config/rv64gc/wally-config.vh
@@ -135,7 +135,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/sim/wave.do b/sim/wave.do
index 5faf74f35..fcb6484dc 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -91,12 +91,8 @@ add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
 add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
 add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
@@ -181,210 +177,210 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
-add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
-add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
-add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
+add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
+add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -608,62 +604,34 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
-add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
-add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
-add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
-add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
-add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
-add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
-add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
+add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
+add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
-add wave -noupdate /testbench/dut/core/ifu/CSRWriteFenceM
-add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/NextFFLAGSM
-add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/WriteFFLAGSM
-add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/InstrValidNotFlushedM
-add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRUWriteM
-add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
-add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRAdrM
-add wave -noupdate /testbench/dut/core/ifu/PCLinkE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {497341 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {161886 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -679,4 +647,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {497212 ns} {497470 ns}
+WaveRestoreZoom {161823 ns} {161929 ns}
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index c7a8d196e..e1a1ab8f3 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -119,7 +119,7 @@ module bpred (
       .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
       .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
 
-  end else if (`BPRED_TYPE == "GSHARE_FORWARD") begin:Predictor
+  end else if (`BPRED_TYPE == "BP_GSHARE_FORWARD") begin:Predictor
     gshareForward #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),

From 100e100835628bdfdf16fc05750954b06a097999 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Feb 2023 23:48:16 -0600
Subject: [PATCH 23/47] reset branch predictor after each test.

---
 sim/wally-batch.do     |  8 ++++----
 sim/wally.do           | 10 +++++-----
 sim/wave.do            | 25 +++++++++++--------------
 testbench/testbench.sv | 34 +++++++++++++++++++++++++++++-----
 4 files changed, 49 insertions(+), 28 deletions(-)

diff --git a/sim/wally-batch.do b/sim/wally-batch.do
index 064f503b2..3168b4520 100644
--- a/sim/wally-batch.do
+++ b/sim/wally-batch.do
@@ -43,7 +43,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
-    vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691  -fatal 7
+    vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
 
     run -all
     run -all
@@ -52,7 +52,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=1 -o testbenchopt 
-    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829  -fatal 7
+    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
 
     #-- Run the Simulation
     echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@@ -63,7 +63,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     exec ./slack-notifier/slack-notifier.py
 
 } elseif {$2 eq "ahb"} {
-    vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596  +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+    vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286  +define+RAM_LATENCY=$3 +define+BURST_EN=$4
     # start and run simulation
     # remove +acc flag for faster sim during regressions if there is no need to access internal signals
     vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
@@ -77,7 +77,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     run -all
     # power off -r /dut/core/*
 } else {
-    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
+    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
     # start and run simulation
     # remove +acc flag for faster sim during regressions if there is no need to access internal signals
     vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
diff --git a/sim/wally.do b/sim/wally.do
index 895b10b95..9b9fc30fc 100644
--- a/sim/wally.do
+++ b/sim/wally.do
@@ -36,7 +36,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt 
-    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829  -fatal 7
+    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
 
     #-- Run the Simulation
     #run -all
@@ -50,7 +50,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt 
-    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829  -fatal 7
+    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
 
     #-- Run the Simulation
     echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@@ -68,7 +68,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } elseif {$2 eq "fpga"} {
     echo "hello"
-    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063
+    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt     
     vsim workopt +nowarn3829  -fatal 7
     
@@ -78,10 +78,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } else {
     if {$2 eq "ahb"} {
-        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
     } else {
         # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
-        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 
+        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
     }
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
 
diff --git a/sim/wave.do b/sim/wave.do
index fcb6484dc..6564e6549 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -95,13 +95,15 @@ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
 add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
@@ -355,11 +357,6 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmach
 add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
 add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
 add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
@@ -631,7 +628,7 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Di
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {161886 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {394986 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -647,4 +644,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {161823 ns} {161929 ns}
+WaveRestoreZoom {394883 ns} {395051 ns}
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index baf8980da..e811ea4b9 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -461,13 +461,36 @@ logic [3:0] dummy;
 	    		.start(DCacheFlushStart),
 		    	.done(DCacheFlushDone));
 
+
   // initialize the branch predictor
-  if (`BPRED_SUPPORTED == 1)
-    begin
-      genvar adrindex;
-      
+  if (`BPRED_SUPPORTED == 1) begin
+    integer adrindex;
+
+	always @(*) begin
+	  if(reset) begin
+		for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
+		  force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+		end
+		for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
+		  force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+		end
+        #1;
+		for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
+		  release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
+		end 
+		for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
+		  release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+		end
+	  end
+	end
+  end
+
+  
+  if (`BPRED_SUPPORTED == 1) begin
+/* -----\/----- EXCLUDED -----\/-----
+    genvar adrindex;
       // Initializing all zeroes into the branch predictor memory.
-      for(adrindex = 0; adrindex < 2**10; adrindex++) begin
+      for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
         initial begin 
         force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
         #1;
@@ -481,6 +504,7 @@ logic [3:0] dummy;
         release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
         end
       end
+ -----/\----- EXCLUDED -----/\----- */
 
       if (`BPRED_LOGGER) begin
         string direction;

From 2d417c33a498085b874cc6d31143d11f80c4b694 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Feb 2023 23:53:10 -0600
Subject: [PATCH 24/47] Simplified BTB by removing the valid bit.  the
 instruction class provides the equivalent information.

---
 src/ifu/bpred/bpred.sv |  6 ++----
 src/ifu/bpred/btb.sv   | 26 +++++++-------------------
 2 files changed, 9 insertions(+), 23 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 798ec44c7..2b4156cfb 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -69,7 +69,6 @@ module bpred (
   output logic             PredictionInstrClassWrongM // Class prediction is wrong
   );
 
-  logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
   logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
@@ -148,7 +147,6 @@ module bpred (
           .PCNextF, .PCF, .PCD, .PCE,
           .PredPCF,
           .BTBPredInstrClassF,
-          .PredValidF,
           .AnyWrongPredInstrClassE,
           .IEUAdrE,
           .InstrClassD,
@@ -186,8 +184,8 @@ module bpred (
 						PredInstrClassF[1];
   end else begin
 	assign PredInstrClassF = BTBPredInstrClassF;
-	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
-						PredInstrClassF[1] & PredValidF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
+						PredInstrClassF[1];
   end
   
   // Part 3 RAS
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 7893ace5f..41dc6befa 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -37,7 +37,6 @@ module btb #(parameter int Depth = 10 ) (
   input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,                 // PC at various stages
   output logic [`XLEN-1:0] PredPCF,                                // BTB's guess at PC
   output logic [3:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
-  output logic             PredValidF,                             // BTB's guess is valid
   // update
   input  logic             AnyWrongPredInstrClassE,             // BTB's instruction class guess was wrong
   input  logic [`XLEN-1:0] IEUAdrE,                                // Branch/jump target address to insert into btb
@@ -45,16 +44,13 @@ module btb #(parameter int Depth = 10 ) (
   input  logic [3:0]       InstrClassE                             // Instruction class to insert into btb
 );
 
-  localparam TotalDepth = 2 ** Depth;
-  logic [TotalDepth-1:0]    ValidBits;
   logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
   logic [`XLEN-1:0] 		ResetPC;
   logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
-  logic [`XLEN+4:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
+  logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
   logic [`XLEN+3:0] 		TableBTBPredictionF;
   logic [`XLEN-1:0] 		PredPCD;  
   logic 					UpdateEn;
-  logic 					TablePredValidF, PredValidD;
     
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
@@ -78,22 +74,14 @@ module btb #(parameter int Depth = 10 ) (
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
-  assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} :
-                                MatchD ? {PredValidD, InstrClassD, PredPCD} :
-                                {1'b1, InstrClassE, IEUAdrE} ;
+  assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
+                                MatchD ? {InstrClassD, PredPCD} :
+                                {InstrClassE, IEUAdrE} ;
 
-  flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
+  flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
-  assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF};
+  assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
 
-  always_ff @ (posedge clk) begin
-    if (reset) begin
-      ValidBits <= #1 {TotalDepth{1'b0}};
-    end else if ((UpdateEn) & ~StallM & ~FlushM) begin
-      ValidBits[PCEIndex] <= #1 |InstrClassE;
-    end
-	if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
-  end
 
   assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
 
@@ -102,6 +90,6 @@ module btb #(parameter int Depth = 10 ) (
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
      .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
 
-  flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD});
+  flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, {PredPCF}, {PredPCD});
 
 endmodule

From f896367946edb4c8a6d20e625568b92d790ca49e Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Sun, 19 Feb 2023 23:53:50 -0600
Subject: [PATCH 25/47] Add setup.csh for C shell users at OSU

---
 setup.csh | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100755 setup.csh

diff --git a/setup.csh b/setup.csh
new file mode 100755
index 000000000..d715634ec
--- /dev/null
+++ b/setup.csh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# setup.csh
+# james.stine@okstate.edu 18 February 2023
+
+echo "Executing Wally setup.sh"
+
+# Path to Wally repository
+set WALLY = $PWD
+echo '$WALLY set to ' ${WALLY}
+
+# Extend alias which makes extending PATH much easier.
+alias extend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 ${\!:1}:\!:2;echo Added \!:2 to \!:1'
+alias prepend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 "\!:2":${\!:1};echo Added \!:2 to \!:1'
+
+# License servers and commercial CAD tool paths
+# Must edit these based on your local environment.  Ask your sysadmin.
+setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu                 # Change this to your Siemens license server
+setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu              # Change this to your Synopsys license server
+setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin   # Change this for your path to Questa
+setenv SNPSPATH /cad/synopsys/SYN/bin                             # Change this for your path to Design Compiler
+
+# Path to RISC-V Tools
+setenv RISCV /opt/riscv   # change this if you installed the tools in a different location
+
+# Tools
+# Questa and Synopsys
+extend PATH $QUESTAPATH
+extend PATH $SNPSPATH 
+# GCC
+prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/lib
+prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
+extend PATH $RISCV/riscv-gnu-toolchain/bin # GCC tools
+extend PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
+# Spike
+extend LD_LIBRARY_PATH $RISCV/lib
+extend PATH $RISCV/bin
+# utility functions in Wally repository
+extend PATH $WALLY/bin
+# Verilator
+extend PATH /usr/local/bin/verilator # Change this for your path to Verilator
+# ModelSim/Questa (vsim)
+# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks.  Ues 2021.2 for now
+
+# Imperas; put this in if you are using it
+#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
+#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
+
+echo "setup done"

From bd8497a665c4a78b3fa37ce9600690e8381ed993 Mon Sep 17 00:00:00 2001
From: David Harris <74973295+davidharrishmc@users.noreply.github.com>
Date: Mon, 20 Feb 2023 03:30:08 -0800
Subject: [PATCH 26/47] Update setup.csh

---
 setup.csh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/setup.csh b/setup.csh
index d715634ec..58b0918dd 100755
--- a/setup.csh
+++ b/setup.csh
@@ -3,7 +3,7 @@
 # setup.csh
 # james.stine@okstate.edu 18 February 2023
 
-echo "Executing Wally setup.sh"
+echo "Executing Wally setup.csh"
 
 # Path to Wally repository
 set WALLY = $PWD

From 1d3b41e0fbc9ed8a85b81c0038a67962ac5902ac Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 04:02:00 -0800
Subject: [PATCH 27/47] New expression for BTB_SIZE to avoid error during sky90
 synthesis

---
 config/buildroot/wally-config.vh  | 2 +-
 config/fpga/wally-config.vh       | 2 +-
 config/rv32e/wally-config.vh      | 2 +-
 config/rv32gc/wally-config.vh     | 2 +-
 config/rv32i/wally-config.vh      | 2 +-
 config/rv32imc/wally-config.vh    | 2 +-
 config/rv64fpquad/wally-config.vh | 2 +-
 config/rv64gc/wally-config.vh     | 2 +-
 config/rv64i/wally-config.vh      | 2 +-
 src/ifu/bpred/btb.sv              | 2 +-
 synthDC/Makefile                  | 1 +
 11 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
index 656bfbe4c..a42587d96 100644
--- a/config/buildroot/wally-config.vh
+++ b/config/buildroot/wally-config.vh
@@ -132,7 +132,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 
 `define HPTW_WRITES_SUPPORTED 1
diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
index a4c97a86e..6f52e3e9a 100644
--- a/config/fpga/wally-config.vh
+++ b/config/fpga/wally-config.vh
@@ -141,7 +141,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 
 `define HPTW_WRITES_SUPPORTED 1
diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
index 8a0dd5f4b..296bcbea8 100644
--- a/config/rv32e/wally-config.vh
+++ b/config/rv32e/wally-config.vh
@@ -136,7 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
index 07b4668ec..28d91e58b 100644
--- a/config/rv32gc/wally-config.vh
+++ b/config/rv32gc/wally-config.vh
@@ -135,7 +135,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
index 4ef0b60e7..60cba64a3 100644
--- a/config/rv32i/wally-config.vh
+++ b/config/rv32i/wally-config.vh
@@ -136,7 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
index 19da7c42f..9d263ae39 100644
--- a/config/rv32imc/wally-config.vh
+++ b/config/rv32imc/wally-config.vh
@@ -135,7 +135,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
index 7f0c2a048..00b193029 100644
--- a/config/rv64fpquad/wally-config.vh
+++ b/config/rv64fpquad/wally-config.vh
@@ -138,7 +138,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
index d163dc34b..d61d66c67 100644
--- a/config/rv64gc/wally-config.vh
+++ b/config/rv64gc/wally-config.vh
@@ -138,7 +138,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
index 24a171a75..7cc8d887e 100644
--- a/config/rv64i/wally-config.vh
+++ b/config/rv64i/wally-config.vh
@@ -138,7 +138,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
-`define BTB_SIZE (`BPRED_SIZE)
+`define BTB_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
 
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 7893ace5f..bf64ccbe8 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -30,7 +30,7 @@
 
 `include "wally-config.vh"
 
-module btb #(parameter int Depth = 10 ) (
+module btb #(parameter Depth = 10 ) (
   input  logic             clk,
   input  logic             reset,
   input  logic             StallF, StallD, StallM, FlushD, FlushM,
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 5ea9677c5..136e610d2 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -72,6 +72,7 @@ else
 	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
+	sed -i 's/BTB_SIZE.*/BTB_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
 ifneq ($(filter $(CONFIG), $(DIRS32)),)
 	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
 	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh

From a59526fc8eba2878917e2feebb03c727e93f873b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 05:32:43 -0800
Subject: [PATCH 28/47] Fixed IROM size parameters

---
 src/ifu/irom.sv | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv
index ba23cf23b..f47f315f6 100644
--- a/src/ifu/irom.sv
+++ b/src/ifu/irom.sv
@@ -33,8 +33,9 @@ module irom(
   output logic [31:0] 	  IROMInstrF // Instruction read data
 );
 
-  localparam ADDR_WDITH = $clog2(`IROM_RANGE/8); 
-  localparam OFFSET = $clog2(`XLEN/8);
+  localparam XLENBYTES = `XLEN/8;
+  localparam ADDR_WDITH = $clog2(`IROM_RANGE/XLENBYTES); 
+  localparam OFFSET = $clog2(XLENBYTES);
 
   logic [`XLEN-1:0] IROMInstrFFull;
   logic [31:0] 		RawIROMInstrF;

From da6064e07f5613747eaa5b141846d86f45573365 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 05:33:33 -0800
Subject: [PATCH 29/47] Fixed critical range to 50 ps and improved reporting in
 synthesis

---
 synthDC/scripts/synth.tcl | 159 +++++++++++++++++++-------------------
 1 file changed, 78 insertions(+), 81 deletions(-)

diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index c4579e5c5..aea0d6f17 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -116,7 +116,7 @@ if {  $find_clock != [list] } {
 }
 
 # Optimize paths that are close to critical
-set_critical_range [expr $my_period*0.05] $current_design
+set_critical_range 0.05 $current_design
 
 # Partitioning - flatten or hierarchically synthesize
 if { $maxopt == 1 } {
@@ -227,7 +227,7 @@ set write_cst  1        ;# generate report of constraints
 set write_hier 1        ;# generate hierarchy report
 
 # Report Constraint Violators
-set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint_all_violators.rpt"]
+set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"]
 redirect $filename {report_constraint -all_violators}
 
 # Check design
@@ -247,23 +247,23 @@ set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
 write_sdf $filename
 
 # QoR
-set filename [format "%s%s%s%s"  $outputDir "/reports/" $my_toplevel "_qor.rep"]
+set filename [format "%s%s"  $outputDir "/reports/qor.rep"]
 redirect $filename { report_qor }
 
 # Report Timing
-set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"]
+set filename [format "%s%s" $outputDir "/reports/reportpath.rep"]
 #redirect $filename { report_path_group }
 
-set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"]
+set filename [format "%s%s" $outputDir "/reports/report_clock.rep"]
 # redirect $filename { report_clock }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_timing.rep"]
+set filename [format "%s%s" $outputDir  "/reports/timing.rep"]
 redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mindelay.rep"]
+set filename [format "%s%s" $outputDir  "/reports/mindelay.rep"]
 redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_per_module_timing.rep"]
+set filename [format "%s%s" $outputDir  "/reports/per_module_timing.rep"]
 redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
@@ -281,7 +281,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
 redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mdu_timing.rep"]
+set filename [format "%s%s" $outputDir  "/reports/mdu_timing.rep"]
 redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" }
@@ -305,7 +305,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
 redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_fpu_timing.rep"]
+# set filename [format "%s%s%s%s" $outputDir  "/reports/fpu_timing.rep"]
 # redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
 # redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
 # redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
@@ -313,90 +313,87 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
 # redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
 # redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_ifu_timing.rep"]
-redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
+# set filename [format "%s%s%s%s" $outputDir  "/reports/ifu_timing.rep"]
+# redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_stall_flush_timing.rep"]
-redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
+# set filename [format "%s%s%s%s" $outputDir  "/reports/stall_flush_timing.rep"]
+# redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_ieu_timing.rep"]
-redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
+# set filename [format "%s%s%s%s" $outputDir  "/reports/ieu_timing.rep"]
+# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_fpu_timing.rep"]
-redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
+# set filename [format "%s%s%s%s" $outputDir  "/reports/fpu_timing.rep"]
+# redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mmu_timing.rep"]
-redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
+# set filename [format "%s%s%s%s" $outputDir  "/reports/mmu_timing.rep"]
+# redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_priv_timing.rep"]
-redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
-redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
+# set filename [format "%s%s%s%s" $outputDir  "/reports/priv_timing.rep"]
+# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_min_timing.rep"]
-redirect $filename { report_timing -delay min }
-
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_area.rep"]
+set filename [format "%s%s" $outputDir  "/reports/area.rep"]
 redirect $filename { report_area -hierarchy -nosplit -physical -designware}
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_cell.rep"]
-# redirect $filename { report_cell [get_cells -hier *] }
+set filename [format "%s%s" $outputDir  "/reports/cell.rep"]
+#redirect $filename { report_cell [get_cells -hier *] }  # not too useful
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_power.rep"]
+set filename [format "%s%s" $outputDir  "/reports/power.rep"]
 redirect $filename { report_power -hierarchy -levels 1 }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_constraint.rep"]
+set filename [format "%s%s" $outputDir  "/reports/constraint.rep"]
 redirect $filename { report_constraint }
 
-set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_hier.rep"]
+set filename [format "%s%s" $outputDir  "/reports/hier.rep"]
 # redirect $filename { report_hierarchy }
 
 # end run clock and echo run time in minutes

From df9950483e460bcfb8e5a6489b313e3080a92fac Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 05:59:57 -0800
Subject: [PATCH 30/47] Removed unused and incomplete ROM macro instantations

---
 src/generic/mem/rom1p1r.sv | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
index c5c1f8b0a..6930bc0db 100644
--- a/src/generic/mem/rom1p1r.sv
+++ b/src/generic/mem/rom1p1r.sv
@@ -38,19 +38,19 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
 
    // Core Memory
    logic [DATA_WIDTH-1:0] 	 ROM [(2**ADDR_WIDTH)-1:0];
-   if ((`USE_SRAM == 1) & (DATA_WIDTH == 64)) begin
+/*   if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 64)) begin
       rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
 
-   end if ((`USE_SRAM == 1) & (DATA_WIDTH == 32)) begin
+   end if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 32)) begin
       rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));      
 
-   end else begin
-      always @ (posedge clk) begin
+   end else begin */
+   always @ (posedge clk) begin
 	 if(ce) dout <= ROM[addr];    
-      end
+   end
    
    // for FPGA, initialize with zero-stage bootloader
-   if(PRELOAD_ENABLED) begin
+   if(PRELOAD_ENABLED) 
       initial begin
 	 ROM[0] =  64'h9581819300002197; 
 	 ROM[1] =  64'h4281420141014081; 
@@ -96,7 +96,5 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
 	 ROM[41] = 64'h40a7853b4015551b;   
 	 ROM[42] = 64'h808210a7a02367c9;
       end 
-    end 
-  end 
 
 endmodule 

From e02f31ec04c8f456d93be6036f7666a47e205049 Mon Sep 17 00:00:00 2001
From: Mike Thompson <mike@openhwgroup.org>
Date: Mon, 20 Feb 2023 12:05:00 -0500
Subject: [PATCH 31/47] Initial Contributing doc

---
 CONTRIBUTING.md | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 CONTRIBUTING.md

diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
new file mode 100644
index 000000000..b80fb2251
--- /dev/null
+++ b/CONTRIBUTING.md
@@ -0,0 +1,21 @@
+# Contributing
+New Contributors are always welcome.
+
+## Contributor Agreement
+Most Contributors are [members](https://www.openhwgroup.org/membership/) of the
+OpenHW Group and participate in one or more [Technical Task Groups](https://www.openhwgroup.org/working-groups/).
+Membership is strongly encouraged, but not required.  Contributors must be
+covered by the terms of the [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php)
+(for individuals) **or** the [Eclipse Member Committer and Contributor Agreement](https://www.eclipse.org/legal/committer_process/EclipseMemberCommitterAgreement.pdf)
+(for employees of Member companies). The ECA/MCCA provides a legal
+framework for a Contributor's technical contributions to the OpenHW Group,
+including provisions for grant of copyright license and a Developer
+Certificate of Origin on contributions merged into OpenHW Group repositories.
+
+## The Mechanics
+1. [Fork](https://help.github.com/articles/fork-a-repo/) the [cvw](https://github.com/openhwgroup/cvw) repository
+2. Clone repository: `git clone https://github.com/[your_github_username]/cvw`
+3. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name.  See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) for a useful nominclature.
+5. Commit your changes: `git commit -m 'Add some feature'`
+6. Push feature branch: `git push origin <my_branch>`
+7. Submit a [pull request](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/creating-a-pull-request-from-a-fork).

From 403473b79d2da31c09faebd2306110a6a27bbe3e Mon Sep 17 00:00:00 2001
From: Mike Thompson <mike@openhwgroup.org>
Date: Mon, 20 Feb 2023 12:11:40 -0500
Subject: [PATCH 32/47] Add SPDX header to CONTRIBUTING

---
 CONTRIBUTING.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index b80fb2251..d9919d464 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -1,3 +1,6 @@
+<!---
+SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+--->
 # Contributing
 New Contributors are always welcome.
 

From 023ba680882a66de86301af5a4d88fe4fdcbd4f7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 10:16:45 -0800
Subject: [PATCH 33/47] Extraction script updates to match new reports names

---
 config/shared/wally-shared.vh | 2 +-
 src/lsu/lsu.sv                | 6 ++++--
 synthDC/extractArea.pl        | 4 ++--
 synthDC/extractSummary.py     | 6 +++++-
 4 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/config/shared/wally-shared.vh b/config/shared/wally-shared.vh
index 507388f7f..3da14abd5 100644
--- a/config/shared/wally-shared.vh
+++ b/config/shared/wally-shared.vh
@@ -117,7 +117,7 @@
 
 // largest length in IEU/FPU
 `define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
-`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
+`define LLEN (($unsigned(`FLEN)<$unsigned(`XLEN)) ? ($unsigned(`XLEN)) : ($unsigned(`FLEN)))
 `define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
 `define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
 `define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index e01de3128..040691080 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -357,8 +357,10 @@ module lsu (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if (`BIGENDIAN_SUPPORTED) begin:endian
-    endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
-    endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
+//    endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
+//    endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
+    endianswap #(64) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
+    endianswap #(64) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
   end else begin
     assign LSUWriteDataM = LittleEndianWriteDataM;
     assign LittleEndianReadDataWordM = ReadDataWordMuxM;
diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl
index d16c74df5..a2a89d7d6 100755
--- a/synthDC/extractArea.pl
+++ b/synthDC/extractArea.pl
@@ -51,7 +51,7 @@ opendir(DIR, $dir) or die "Could not open $dir";
 
 while (my $filename = readdir(DIR)) {
     if ($filename =~ /orig_tsmc28psyn/) {
-#        print "$filename\n";
+#    if ($filename =~ /orig_sky90/) {
         &processRun("$dir/$filename");
     }
 }
@@ -82,7 +82,7 @@ foreach my $kw (@keywordsp) {
 
 sub processRun {
     my $fname = shift;
-    my $ffname = "$fname/reports/wallypipelinedcore_area.rep";
+    my $ffname = "$fname/reports/area.rep";
     open(FILE, "$ffname") or die ("Could not read $ffname");
 
     # Extract configuration from fname;
diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py
index 94902f9c9..65b7d1842 100755
--- a/synthDC/extractSummary.py
+++ b/synthDC/extractSummary.py
@@ -141,7 +141,7 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
     if norm:
         delays = [d/fo4 for d in delays]
         areas = [a/add32area for a in areas]
-    
+   
     plt.scatter(delays, areas, marker=marker, color=color)
     plt.xlabel('Cycle time (ns)')
     plt.ylabel('Area (sq microns)')
@@ -165,6 +165,9 @@ def plotFeatures(tech, width, config):
                 areas += [oneSynth.area]
                 labels += [oneSynth.mod]
 
+    if (delays == []):
+        print("No delays found for freq ", freq, ". Did you set --skyfreq and --tsmcfreq?\n")
+
     fig, (ax) = plt.subplots(1, 1)
 
     fig = areaDelay(tech, delays, areas, labels, fig, ax)
@@ -185,6 +188,7 @@ def plotConfigs(tech, mod=''):
 
     fig, (ax) = plt.subplots(1, 1)
 
+
     fig = areaDelay(tech, delays, areas, labels, fig, ax)
 
     titleStr = tech+'_'+mod

From 00daa8aca01acba051e78072fb96ba30b5f0b61e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 10:37:10 -0800
Subject: [PATCH 34/47] Turned off SSTC_SUPPORTED in buildroot and fpga

---
 config/buildroot/wally-config.vh | 2 +-
 config/fpga/wally-config.vh      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
index a42587d96..f8fdb61d2 100644
--- a/config/buildroot/wally-config.vh
+++ b/config/buildroot/wally-config.vh
@@ -42,7 +42,7 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define COUNTERS 32
 `define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 1
+`define SSTC_SUPPORTED 0
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1
diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
index 6f52e3e9a..ec3b268bd 100644
--- a/config/fpga/wally-config.vh
+++ b/config/fpga/wally-config.vh
@@ -43,7 +43,7 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define ZFH_SUPPORTED 0
 `define COUNTERS 32
-`define SSTC_SUPPORTED 1
+`define SSTC_SUPPORTED 0
 
 // LSU microarchitectural Features
 `define BUS_SUPPORTED 1

From 535c7e156f698fc20e9b193f13f489e26fd678fa Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 11:04:33 -0800
Subject: [PATCH 35/47] touched extractArea to test commit issue

---
 synthDC/extractArea.pl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl
index a2a89d7d6..09c64d9de 100755
--- a/synthDC/extractArea.pl
+++ b/synthDC/extractArea.pl
@@ -50,7 +50,7 @@ my @configs = ("rv32e", "rv32i", "rv32imc", "rv32gc", "rv64i", "rv64gc");
 opendir(DIR, $dir) or die "Could not open $dir";
 
 while (my $filename = readdir(DIR)) {
-    if ($filename =~ /orig_tsmc28psyn/) {
+    if ($filename =~ /orig_tsmc28psyn/) { 
 #    if ($filename =~ /orig_sky90/) {
         &processRun("$dir/$filename");
     }

From fc87425f670f9f95e77706b51d2cdce364fe1abc Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 11:18:31 -0800
Subject: [PATCH 36/47] touched extractArea.pl

---
 synthDC/extractArea.pl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl
index 09c64d9de..50cecbf9a 100755
--- a/synthDC/extractArea.pl
+++ b/synthDC/extractArea.pl
@@ -57,7 +57,7 @@ while (my $filename = readdir(DIR)) {
 }
 closedir(DIR);
 
-# print table of results
+# print table of results 
 printf("%20s\t", "");
 foreach my $config (@configs) {
     printf("%s\t", $config);

From bdcd867c118b6634fd5479314f6af96925f5e5b1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Feb 2023 12:42:46 -0800
Subject: [PATCH 37/47] Removed test code that broke LSU

---
 src/lsu/lsu.sv | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 040691080..e01de3128 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -357,10 +357,8 @@ module lsu (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if (`BIGENDIAN_SUPPORTED) begin:endian
-//    endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
-//    endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
-    endianswap #(64) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
-    endianswap #(64) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
+    endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
+    endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
   end else begin
     assign LSUWriteDataM = LittleEndianWriteDataM;
     assign LittleEndianReadDataWordM = ReadDataWordMuxM;

From 1982c66b72591c42b7495832e810256ad314af1d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 15:39:42 -0600
Subject: [PATCH 38/47] Simiplified BTB.

---
 src/ifu/bpred/bpred.sv          | 10 +++++-----
 src/ifu/bpred/btb.sv            | 33 +++++++++++++++++++--------------
 src/ifu/ifu.sv                  |  3 ++-
 src/wally/wallypipelinedcore.sv |  2 +-
 4 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 2b4156cfb..e7bf1be13 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -56,6 +56,7 @@ module bpred (
   input  logic             JumpD, JumpE,
   input logic              PCSrcE,                    // Executation stage branch is taken
   input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
+  input logic [`XLEN-1:0]  IEUAdrM,                   // The branch/jump target address
   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
   output logic             JumpOrTakenBranchM,        // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
@@ -143,14 +144,13 @@ module bpred (
   // BTB contains target address for all CFI
 
   btb #(`BTB_SIZE) 
-    TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
-          .PCNextF, .PCF, .PCD, .PCE,
+    TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+          .PCNextF, .PCF, .PCD, .PCE, .PCM,
           .PredPCF,
           .BTBPredInstrClassF,
           .AnyWrongPredInstrClassE,
-          .IEUAdrE,
-          .InstrClassD,
-          .InstrClassE);
+          .IEUAdrE, .IEUAdrM,
+          .InstrClassD, .InstrClassE, .InstrClassM);
 
   // the branch predictor needs a compact decoding of the instruction class.
   if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 8f7b3a2b8..1dae8c890 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -31,22 +31,24 @@
 `include "wally-config.vh"
 
 module btb #(parameter Depth = 10 ) (
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallF, StallD, StallM, FlushD, FlushM,
-  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,                 // PC at various stages
-  output logic [`XLEN-1:0] PredPCF,                                // BTB's guess at PC
-  output logic [3:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
+  input logic 			   clk,
+  input logic 			   reset,
+  input logic 			   StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
+  input logic [`XLEN-1:0]  PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
+  output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
+  output logic [3:0] 	   BTBPredInstrClassF, // BTB's guess at instruction class
   // update
-  input  logic             AnyWrongPredInstrClassE,             // BTB's instruction class guess was wrong
-  input  logic [`XLEN-1:0] IEUAdrE,                                // Branch/jump target address to insert into btb
-  input  logic [3:0]       InstrClassD,                            // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassE                             // Instruction class to insert into btb
+  input logic 			   AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong
+  input logic [`XLEN-1:0]  IEUAdrE, // Branch/jump target address to insert into btb
+  input logic [`XLEN-1:0]  IEUAdrM, // Branch/jump target address to insert into btb
+  input logic [3:0] 	   InstrClassD, // Instruction class to insert into btb
+  input logic [3:0] 	   InstrClassE, // Instruction class to insert into btb
+  input logic [3:0] 	   InstrClassM                            // Instruction class to insert into btb
 );
 
-  logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
+  logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex;
   logic [`XLEN-1:0] 		ResetPC;
-  logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
+  logic 					MatchF, MatchD, MatchE, MatchM, MatchNextX, MatchXF;
   logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
   logic [`XLEN+3:0] 		TableBTBPredictionF;
   logic [`XLEN-1:0] 		PredPCD;  
@@ -59,6 +61,7 @@ module btb #(parameter Depth = 10 ) (
   assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]};
   assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
   assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
+  assign PCMIndex = {PCM[Depth+1] ^ PCM[1], PCM[Depth:2]};
 
   // must output a valid PC and valid bit during reset.  Because only PCF, not PCNextF is reset, PCNextF is invalid
   // during reset.  The BTB must produce a non X PC1NextF to allow the simulation to run.
@@ -70,13 +73,15 @@ module btb #(parameter Depth = 10 ) (
   assign MatchF = PCNextFIndex == PCFIndex;
   assign MatchD = PCNextFIndex == PCDIndex;
   assign MatchE = PCNextFIndex == PCEIndex;
+  assign MatchM = PCNextFIndex == PCMIndex;
   assign MatchNextX = MatchF | MatchD | MatchE;
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
   assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
                                 MatchD ? {InstrClassD, PredPCD} :
-                                {InstrClassE, IEUAdrE} ;
+                                MatchE ? {InstrClassE, IEUAdrE} :
+                                {InstrClassM, IEUAdrM} ;
 
   flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
@@ -90,6 +95,6 @@ module btb #(parameter Depth = 10 ) (
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
      .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
 
-  flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, {PredPCF}, {PredPCD});
+  flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
 
 endmodule
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 51317e0b0..3c6cd9414 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -52,6 +52,7 @@ module ifu (
   output logic [`XLEN-1:0] 	PCLinkE,                                  // The address following the branch instruction. (AKA Fall through address)
   input  logic 				PCSrcE,                                   // Executation stage branch is taken
   input  logic [`XLEN-1:0] 	IEUAdrE,                                  // The branch/jump target address
+  input  logic [`XLEN-1:0] 	IEUAdrM,                                  // The branch/jump target address
   output logic [`XLEN-1:0] 	PCE,                                      // Execution stage instruction address
   output logic 				BPPredWrongE,                             // Prediction is wrong
   output logic 				BPPredWrongM,                             // Prediction is wrong
@@ -327,7 +328,7 @@ module ifu (
                 .StallF, .StallD, .StallE, .StallM, .StallW,
                 .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, 
                 .BranchD, .BranchE, .JumpD, .JumpE,
-                .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
+                .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
                 .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
 
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index a03caea15..c26ffb3a4 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -174,7 +174,7 @@ module wallypipelinedcore (
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
     .ICacheAccess, .ICacheMiss,
     // Execute
-    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE,  .BPPredWrongM, 
+    .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPPredWrongE,  .BPPredWrongM, 
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
     .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,

From d887124837e4105ae050fbae2fc315b2b4a60362 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 16:00:29 -0600
Subject: [PATCH 39/47] Found a bug where the d and i cache misses were not
 recorded in the performance counters.

---
 src/privileged/csrc.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
index ad9475d32..d61835826 100644
--- a/src/privileged/csrc.sv
+++ b/src/privileged/csrc.sv
@@ -94,9 +94,9 @@ module csrc #(parameter
     assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
     assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
     assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM;                     // data cache access
-    assign CounterEvent[12] = DCacheMiss & InstrValidNotFlushedM;                       // data cache miss
+    assign CounterEvent[12] = DCacheMiss;                                               // data cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[13] = ICacheAccess & InstrValidNotFlushedM;                     // instruction cache access
-    assign CounterEvent[14] = ICacheMiss & InstrValidNotFlushedM;                       // instruction cache miss
+    assign CounterEvent[14] = ICacheMiss;                                               // instruction cache miss. Miss asserted 1 cycle at start of cache miss
 	assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM;                     // branch predictor wrong
     assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end

From 5187c781844344195138f2ca4ffe51237f5fc262 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 16:18:04 -0600
Subject: [PATCH 40/47] Fixed forwarding bug in the BTB.

---
 src/ifu/bpred/bpred.sv | 2 +-
 src/ifu/bpred/btb.sv   | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index e7bf1be13..97101a3ea 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -148,7 +148,7 @@ module bpred (
           .PCNextF, .PCF, .PCD, .PCE, .PCM,
           .PredPCF,
           .BTBPredInstrClassF,
-          .AnyWrongPredInstrClassE,
+          .PredictionInstrClassWrongM,
           .IEUAdrE, .IEUAdrM,
           .InstrClassD, .InstrClassE, .InstrClassM);
 
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 1dae8c890..a8f67efeb 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -38,7 +38,7 @@ module btb #(parameter Depth = 10 ) (
   output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
   output logic [3:0] 	   BTBPredInstrClassF, // BTB's guess at instruction class
   // update
-  input logic 			   AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong
+  input logic 			   PredictionInstrClassWrongM, // BTB's instruction class guess was wrong
   input logic [`XLEN-1:0]  IEUAdrE, // Branch/jump target address to insert into btb
   input logic [`XLEN-1:0]  IEUAdrM, // Branch/jump target address to insert into btb
   input logic [3:0] 	   InstrClassD, // Instruction class to insert into btb
@@ -74,7 +74,7 @@ module btb #(parameter Depth = 10 ) (
   assign MatchD = PCNextFIndex == PCDIndex;
   assign MatchE = PCNextFIndex == PCEIndex;
   assign MatchM = PCNextFIndex == PCMIndex;
-  assign MatchNextX = MatchF | MatchD | MatchE;
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
@@ -88,12 +88,12 @@ module btb #(parameter Depth = 10 ) (
   assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
 
 
-  assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
+  assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
 
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
-     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
+     .ce2(~StallM & ~FlushM), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
 
   flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
 

From 68e39eeb6675f3475bc79f1eb9ec1db4018de5ab Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 17:54:22 -0600
Subject: [PATCH 41/47] Fixed another bug in the btb.

---
 src/ifu/bpred/bpred.sv         | 2 +-
 src/ifu/bpred/btb.sv           | 4 ++--
 src/ifu/bpred/gshareForward.sv | 4 ++--
 testbench/tests.vh             | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 97101a3ea..b0ea2683b 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -144,7 +144,7 @@ module bpred (
   // BTB contains target address for all CFI
 
   btb #(`BTB_SIZE) 
-    TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+    TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
           .PCNextF, .PCF, .PCD, .PCE, .PCM,
           .PredPCF,
           .BTBPredInstrClassF,
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index a8f67efeb..8e2d0e259 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -33,7 +33,7 @@
 module btb #(parameter Depth = 10 ) (
   input logic 			   clk,
   input logic 			   reset,
-  input logic 			   StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
+  input logic 			   StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
   input logic [`XLEN-1:0]  PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
   output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
   output logic [3:0] 	   BTBPredInstrClassF, // BTB's guess at instruction class
@@ -93,7 +93,7 @@ module btb #(parameter Depth = 10 ) (
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
-     .ce2(~StallM & ~FlushM), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
+     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
 
   flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
 
diff --git a/src/ifu/bpred/gshareForward.sv b/src/ifu/bpred/gshareForward.sv
index 77ab90fba..57bcd4bee 100644
--- a/src/ifu/bpred/gshareForward.sv
+++ b/src/ifu/bpred/gshareForward.sv
@@ -83,7 +83,7 @@ module gshareForward #(parameter k = 10) (
     .rd1(TableDirPredictionF),
     .wa2(IndexM),
     .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallW & ~FlushW),
+    .we2(BranchInstrM),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -102,7 +102,7 @@ module gshareForward #(parameter k = 10) (
   assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
   assign GHRM = GHR;
 
-  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
+  flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNext, GHR);
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
     
 endmodule
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 6ab4533fa..2ec4e43fc 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -50,8 +50,8 @@ string tvpaths[] = '{
 
   string embench[] = '{
     `EMBENCH,
-    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/nsichneu/nsichneu",
+    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/aha-mont64/aha-mont64",
     "bd_speedopt_speed/src/crc32/crc32",
     "bd_speedopt_speed/src/edn/edn",

From a14c71bd9597dfa4e1a41f61d974197349e14abf Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 18:36:33 -0600
Subject: [PATCH 42/47] Renamed branch predictors and consolidated global and
 gshare predictors.

---
 config/buildroot/wally-config.vh              |   2 +-
 config/fpga/wally-config.vh                   |   4 +-
 config/rv32e/wally-config.vh                  |   2 +-
 config/rv32gc/wally-config.vh                 |   2 +-
 config/rv32i/wally-config.vh                  |   2 +-
 config/rv32imc/wally-config.vh                |   2 +-
 config/rv64fpquad/wally-config.vh             |   2 +-
 config/rv64gc/wally-config.vh                 |   2 +-
 config/rv64i/wally-config.vh                  |   2 +-
 sim/wave.do                                   | 117 ++++++++++--------
 src/ifu/bpred/bpred.sv                        |  40 +++---
 src/ifu/bpred/gshare.sv                       |  73 ++++++++---
 .../{gshareForward.sv => gsharebasic.sv}      |  69 ++++-------
 13 files changed, 167 insertions(+), 152 deletions(-)
 rename src/ifu/bpred/{gshareForward.sv => gsharebasic.sv} (53%)

diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
index 813566a20..12c7db2d0 100644
--- a/config/buildroot/wally-config.vh
+++ b/config/buildroot/wally-config.vh
@@ -130,7 +130,7 @@
 `define PLIC_GPIO_ID 3
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
index 00b84f23f..a2488c060 100644
--- a/config/fpga/wally-config.vh
+++ b/config/fpga/wally-config.vh
@@ -139,8 +139,8 @@
 `define PLIC_GPIO_ID 3
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
-`define BPRED_SIZE 10
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+`define BPRED_SIZE 12
 `define BTB_SIZE 10
 
 
diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
index bda7b4492..6e0de3347 100644
--- a/config/rv32e/wally-config.vh
+++ b/config/rv32e/wally-config.vh
@@ -134,7 +134,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
index 88fc70ade..57857f3be 100644
--- a/config/rv32gc/wally-config.vh
+++ b/config/rv32gc/wally-config.vh
@@ -133,7 +133,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
index 86bad6f91..efbf6e7c0 100644
--- a/config/rv32i/wally-config.vh
+++ b/config/rv32i/wally-config.vh
@@ -134,7 +134,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
index eb9ce6528..8fb29a678 100644
--- a/config/rv32imc/wally-config.vh
+++ b/config/rv32imc/wally-config.vh
@@ -133,7 +133,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
index ea36327d3..dd8058c28 100644
--- a/config/rv64fpquad/wally-config.vh
+++ b/config/rv64fpquad/wally-config.vh
@@ -136,7 +136,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
index c323a9f0e..4100f4c08 100644
--- a/config/rv64gc/wally-config.vh
+++ b/config/rv64gc/wally-config.vh
@@ -136,7 +136,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
index 7cc8d887e..a3702c3fd 100644
--- a/config/rv64i/wally-config.vh
+++ b/config/rv64i/wally-config.vh
@@ -136,7 +136,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
diff --git a/sim/wave.do b/sim/wave.do
index 6564e6549..23413957d 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -37,17 +37,17 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
-add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
-add wave -noupdate -expand -group PCS /testbench/PCW
+add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
+add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
@@ -95,15 +95,15 @@ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
 add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
 add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
@@ -556,21 +556,21 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
-add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
-add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
-add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
-add wave -noupdate -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
-add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
-add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
-add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
-add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
+add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
 add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
@@ -602,23 +602,23 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
-add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
-add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
-add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
-add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
-add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
-add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
+add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
+add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
+add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
+add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
+add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
+add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
+add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
@@ -627,9 +627,16 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/In
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
+add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheAccess
+add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheMiss
+add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAccess
+add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss
+add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {394986 ns} 0}
-quietly wave cursor active 5
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {368581 ns} 0} {{Cursor 5} {394987 ns} 1}
+quietly wave cursor active 4
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
 configure wave -justifyvalue left
@@ -644,4 +651,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {394883 ns} {395051 ns}
+WaveRestoreZoom {368125 ns} {368797 ns}
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index b0ea2683b..da4070e14 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -94,36 +94,32 @@ module bpred (
 
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
-  if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
+  if (`BPRED_TYPE == "BP_TWOBIT") begin:Predictor
     twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
-  end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
-    globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
-
-  end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
-    speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .DirPredictionF, .DirPredictionWrongE,
-      .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
-	    
-  end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
+  end else if (`BPRED_TYPE == "BP_GSHARE") begin:Predictor
     gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
-
-  end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
-    speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
-      .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
-
-  end else if (`BPRED_TYPE == "BP_GSHARE_FORWARD") begin:Predictor
-    gshareForward #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
       .PCSrcE);
+
+  end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor
+    gshare #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
+      .PCSrcE);
+
+  end else if (`BPRED_TYPE == "BP_GSHARE_BASIC") begin:Predictor
+    gsharebasic #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
+
+  end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
+    gsharebasic #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 	
   end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
     // *** Fix me
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index 35a73fb04..bb9d25f49 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -28,7 +28,8 @@
 
 `include "wally-config.vh"
 
-module gshare #(parameter k = 10) (
+module gshare #(parameter k = 10,
+                parameter string TYPE = "gshare") (
   input logic             clk,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
@@ -36,28 +37,60 @@ module gshare #(parameter k = 10) (
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCM,
-  input logic             BranchInstrE, BranchInstrM, PCSrcE
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE
 );
 
-  logic [k-1:0]            IndexNextF, IndexE;
-  logic [1:0]              DirPredictionD, DirPredictionE;
+  logic                    MatchF, MatchD, MatchE, MatchM;
+  logic                    MatchNextX, MatchXF;
+
+  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPrediction, ForwardDirPredictionF;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
-  logic [k-1:0]            GHRNext;
+  logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE, IndexM;
+
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM;
+  logic [k-1:0]            GHRNextM, GHRNextF;
   logic                    PCSrcM;
 
-  assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  if(TYPE == "gshare") begin
+	assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+	assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
+	assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
+	assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
+	assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  end else if(TYPE == "global") begin
+	assign IndexNextF = {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+	assign IndexF = {PCF[k+1] ^ PCF[1], PCF[k:2]};
+	assign IndexD = {PCD[k+1] ^ PCD[1], PCD[k:2]};
+	assign IndexE = {PCE[k+1] ^ PCE[1], PCE[k:2]};
+	assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  end
+
+  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
+
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
+                                   MatchD ? {2{DirPredictionD[1]}} :
+                                   MatchE ? {NewDirPredictionE} :
+                                   NewDirPredictionM ;
   
+  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
+
+  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
+
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
-    .rd1(DirPredictionF),
-    .wa2(IndexE),
+    .rd1(TableDirPredictionF),
+    .wa2(IndexM),
     .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallW & ~FlushW),
+    .we2(BranchInstrM),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -68,14 +101,14 @@ module gshare #(parameter k = 10) (
 
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-  assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
-  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
+  assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
+  assign GHRF = BranchInstrD  ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
+  assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
+  assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
+
+  assign GHRNextM = {PCSrcM, GHRM[k-1:1]};
+
+  flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNextM, GHRM);
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
     
-  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
-  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
-  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
-
-
 endmodule
diff --git a/src/ifu/bpred/gshareForward.sv b/src/ifu/bpred/gsharebasic.sv
similarity index 53%
rename from src/ifu/bpred/gshareForward.sv
rename to src/ifu/bpred/gsharebasic.sv
index 57bcd4bee..45438b856 100644
--- a/src/ifu/bpred/gshareForward.sv
+++ b/src/ifu/bpred/gsharebasic.sv
@@ -28,7 +28,8 @@
 
 `include "wally-config.vh"
 
-module gshareForward #(parameter k = 10) (
+module gsharebasic #(parameter k = 10,
+                     parameter string TYPE = "global") (
   input logic             clk,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
@@ -36,54 +37,33 @@ module gshareForward #(parameter k = 10) (
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE
+  input logic [`XLEN-1:0] PCNextF, PCM,
+  input logic             BranchInstrE, BranchInstrM, PCSrcE
 );
 
-  logic                    MatchF, MatchD, MatchE, MatchM;
-  logic                    MatchNextX, MatchXF;
-
-  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPrediction, ForwardDirPredictionF;
+  logic [k-1:0]            IndexNextF, IndexE;
+  logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-
-  logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE, IndexM;
-
   logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
-  logic [k-1:0]            GHRNext, GHRNextF;
+  logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
-  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-
-  assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
-  assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
-  assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
-  assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
-
-  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
-  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
-  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
-  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
-  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
-
-  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
-
-  assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
-                                   MatchD ? {2{DirPredictionD[1]}} :
-                                   MatchE ? {NewDirPredictionE} :
-                                   NewDirPredictionM ;
+  if(TYPE == "gshare") begin
+	assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+	assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  end else if(TYPE == "global") begin
+	assign IndexNextF = {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+	assign IndexE = {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  end
   
-  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
-
-  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
-
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
-    .rd1(TableDirPredictionF),
-    .wa2(IndexM),
+    .rd1(DirPredictionF),
+    .wa2(IndexE),
     .wd2(NewDirPredictionM),
-    .we2(BranchInstrM),
+    .we2(BranchInstrM & ~StallW & ~FlushW),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -94,15 +74,14 @@ module gshareForward #(parameter k = 10) (
 
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-  assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
-  assign GHRF = BranchInstrD  ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
-  assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
-  assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
-
   assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
-  assign GHRM = GHR;
-
-  flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNext, GHR);
+  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
     
+  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
+  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
+  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
+
+
 endmodule

From d2e06d9ef0aef9b52a11a4ff4751114761c68ddc Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 18:45:45 -0600
Subject: [PATCH 43/47] Cleanup branch predictor files.

---
 src/ifu/bpred/foldedgshare.sv             | 146 ---------------
 src/ifu/bpred/globalhistory.sv            |  80 --------
 src/ifu/bpred/gshare.sv                   |  13 +-
 src/ifu/bpred/gsharebasic.sv              |  11 +-
 src/ifu/bpred/optgshare.sv                | 219 ----------------------
 src/ifu/bpred/speculativeglobalhistory.sv | 136 --------------
 src/ifu/bpred/speculativegshare.sv        | 137 --------------
 7 files changed, 13 insertions(+), 729 deletions(-)
 delete mode 100644 src/ifu/bpred/foldedgshare.sv
 delete mode 100644 src/ifu/bpred/globalhistory.sv
 delete mode 100644 src/ifu/bpred/optgshare.sv
 delete mode 100644 src/ifu/bpred/speculativeglobalhistory.sv
 delete mode 100644 src/ifu/bpred/speculativegshare.sv

diff --git a/src/ifu/bpred/foldedgshare.sv b/src/ifu/bpred/foldedgshare.sv
deleted file mode 100644
index 85b7db383..000000000
--- a/src/ifu/bpred/foldedgshare.sv
+++ /dev/null
@@ -1,146 +0,0 @@
-///////////////////////////////////////////
-// gsharePredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module foldedgshare #(parameter k = 16, depth = 10) (
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW, 
-  input logic             FlushD, FlushE, FlushM, FlushW,
-//   input logic [`XLEN-1:0] LookUpPC,
-  output logic [1:0]      DirPredictionF, 
-  output logic            DirPredictionWrongE,
-  // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
-  input logic             PCSrcE
-);
-
-  logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
-  logic                    MatchNextX, MatchXF;
-
-  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
-
-  logic [k-1:0]            GHRF;
-  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
-  logic [k-1:0]            GHRNextF;
-  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
-  logic [k-1:0]            IndexNextF, IndexF;
-  logic [k-1:0]            IndexD, IndexE, IndexM, IndexW;
-  logic [depth-1:0] 	     FinalIndexNextF, FinalIndexW;
-  
-  logic                    PCSrcM, PCSrcW;
-  logic [`XLEN-1:0]        PCW;
-
-  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
-  localparam        		   delta = 2 * depth - k;
-  
-  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
-  assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
-  assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
-  assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
-  assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
-
-  // just be dumb for now.
-  //localparam int kToDepthRatio = (k+depth) / depth;
-  assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]};
-  assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]};
-        
-  ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
-    .ra1(FinalIndexNextF),
-    .rd1(TableDirPredictionF),
-    .wa2(FinalIndexW),
-    .wd2(NewDirPredictionW),
-    .we2(BranchInstrW & ~StallW & ~FlushW),
-    .bwe2(1'b1));
-
-  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
-  //  and then register for use in the Fetch stage.
-  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
-  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
-  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
-  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
-  assign MatchW = BranchInstrW & (IndexNextF == IndexW);
-  assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
-
-  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
-
-  assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
-                                   MatchD ? NewDirPredictionD :
-                                   MatchE ? NewDirPredictionE :
-                                   MatchM ? NewDirPredictionM :
-                                   NewDirPredictionW;
-
-  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
-
-  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
-
-  // DirPrediction pipeline
-  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
-  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
-
-  // New prediction pipeline
-  satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
-  flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
-  flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
-
-  // PCSrc pipeline
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
-  
-  // GHR pipeline
-  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
-                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
-                    GHRF;
-
-  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
-  
-  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
-  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
-
-  assign GHRNextE = FlushE ? GHRNextM : GHRD;
-  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
-  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
-
-  assign GHRNextM = FlushM ? GHRNextW : GHRE;
-  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
-
-  assign GHRNextW = FlushW ? GHRW : GHRM;
-  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
-  
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
-
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
-endmodule
diff --git a/src/ifu/bpred/globalhistory.sv b/src/ifu/bpred/globalhistory.sv
deleted file mode 100644
index a88804773..000000000
--- a/src/ifu/bpred/globalhistory.sv
+++ /dev/null
@@ -1,80 +0,0 @@
-///////////////////////////////////////////
-// globalHistoryPredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module globalhistory #(parameter k = 10) (
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW,
-  input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      DirPredictionF, 
-  output logic            DirPredictionWrongE,
-  // update
-  input logic             BranchInstrE, BranchInstrM, PCSrcE
-);
-
-  logic [k-1:0]            IndexNextF, IndexE;
-  logic [1:0]              DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionE, NewDirPredictionM;
-
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
-  logic [k-1:0]            GHRNext;
-  logic                    PCSrcM;
-
-  assign IndexNextF = GHR;
-  assign IndexE = GHRM;
-  
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallM & ~FlushM),
-    .ra1(IndexNextF),
-    .rd1(DirPredictionF),
-    .wa2(IndexE),
-    .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallW & ~FlushW),
-    .bwe2(1'b1));
-
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, DirPredictionD, DirPredictionE);
-
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
-
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
-
-  assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
-  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-    
-  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
-  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
-  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
-
-
-endmodule
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index bb9d25f49..c13bce943 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -1,12 +1,13 @@
 ///////////////////////////////////////////
-// globalHistoryPredictor.sv
+// gshare.sv
 //
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 16 March 2021
+// Adapted from ssanghai@hmc.edu (Shreya Sanghai)
+// Modified: 20 February 2023
 //
-// Purpose: Global History Branch predictor with parameterized global history register
+// Purpose: gshare and Global History Branch predictors
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv
index 45438b856..d73797275 100644
--- a/src/ifu/bpred/gsharebasic.sv
+++ b/src/ifu/bpred/gsharebasic.sv
@@ -1,10 +1,11 @@
 ///////////////////////////////////////////
-// globalHistoryPredictor.sv
+// gsharebasic.sv
 //
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 16 March 2021
+// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
+// Modified: 20 February 2023 
 //
 // Purpose: Global History Branch predictor with parameterized global history register
 // 
diff --git a/src/ifu/bpred/optgshare.sv b/src/ifu/bpred/optgshare.sv
deleted file mode 100644
index 78c98c5e6..000000000
--- a/src/ifu/bpred/optgshare.sv
+++ /dev/null
@@ -1,219 +0,0 @@
-///////////////////////////////////////////
-// gsharePredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module optgshare #(parameter k = 10) (
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallF, StallD, StallE, StallM, StallW, 
-  input  logic             FlushD, FlushE, FlushM, FlushW,
-//   input logic [`XLEN-1:0] LookUpPC,
-  output logic [1:0]       DirPredictionF, 
-  output logic             DirPredictionWrongE,
-  // update
-  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-  input  logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
-  input  logic             PCSrcE
-);
-
-  logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
-  logic                    MatchNextX, MatchXF;
-
-  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
-
-  logic [k-1:0]            GHRF;
-  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
-  logic [k-1:0]            GHRNextF;
-  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
-  logic [k-1:0]            IndexNextF, IndexF;
-  logic [k-1:0]            IndexD, IndexE, IndexM, IndexW;
-  
-  logic                    PCSrcM, PCSrcW;
-  logic [`XLEN-1:0]        PCW;
-
-  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
-
-  logic [k+4:0]            GHRNext, GHR;
-  logic                    GHRUpdateEn;
-  
-  assign GHRUpdateEn = BranchInstrF | (DirPredictionWrongE & BranchInstrE) |
-                       FlushD | FlushE | FlushM | FlushW;
-
-  // it doesn't work this way.  Instead we need to see how many branch instructions are flushed.
-  // then shift over by that amount.
-  logic                    RemoveBrW, RemoveBrM, RemoveBrE, RemoveBrD, RemoveBrF, RemoveBrNextF;
-  
-  assign RemoveBrW = '0;
-  assign RemoveBrM = BranchInstrM & FlushW;
-  assign RemoveBrE = BranchInstrE & FlushM;
-  assign RemoveBrD = BranchInstrD & FlushE;
-  assign RemoveBrF = BranchInstrF & FlushD;
-  assign RemoveBrNextF = BranchInstrF & FlushD;
-  
-  always_comb begin
-    casez ({BranchInstrF, DirPredictionWrongE, RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM}) 
-      6'b00_0000: GHRNext = GHR;  // no change
-      6'b00_0001: GHRNext = {GHR[k+4:k+1], GHR[k-1:0], 1'b0}; // RemoveBrM
-      6'b0?_0010: GHRNext = {GHR[k+4:k+2], GHR[k:0], 1'b0};   // RemoveBrE
-      6'b0?_0011: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0};   // RemoveBrE, RemoveBrM
-
-      6'b00_0100: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrD
-      6'b00_0101: GHRNext = {GHR[k+4:k+3], GHR[k+1:0], 1'b0}; // RemoveBrD, RemoveBrM
-      6'b0?_0110: GHRNext = {GHR[k+4:k+3], GHR[k+1], GHR[k-1:0], 2'b0}; // RemoveBrD, RemoveBrE
-      6'b0?_0111: GHRNext = {GHR[k+4:k+3], GHR[k-1:0], 3'b0}; // RemoveBrD, RemoveBrE, RemoveBrM
-
-      6'b?0_1000: GHRNext = {GHR[k+2:0],   2'b0}; // RemoveBrF, 
-      6'b?0_1001: GHRNext = {GHR[k+2:k+1], GHR[k-1:0],  3'b0}; // RemoveBrF, RemoveBrM
-      6'b??_1010: GHRNext = {GHR[k+2], GHR[k:0],  3'b0}; // RemoveBrF, RemoveBrE
-      6'b??_1011: GHRNext = {GHR[k+2], GHR[k-1:0],  4'b0}; // RemoveBrF, RemoveBrE, RemoveBrM
-
-      6'b?0_1100: GHRNext = {GHR[k+1:0],  3'b0}; // RemoveBrF, RemoveBrD
-      6'b?0_1101: GHRNext = {GHR[k+1], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrM
-      6'b??_1110: GHRNext = {GHR[k:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrE
-      6'b??_1111: GHRNext = {GHR[k-1:0], 5'b0}; // RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM
-
-      6'b?1_0000: GHRNext = {PCSrcE, GHR[k+3:0]}; // Miss prediction, no branches to flushes
-      6'b?1_0001: GHRNext = {PCSrcE, GHR[k+3:k], GHR[k-1:1], 1'b0}; // Miss prediction, branch in Memory stage dropped
-
-      6'b?1_1100: GHRNext = {PCSrcE, GHR[k+1:0], 2'b00}; // Miss prediction, cannot have RemoveBrE
-      6'b?1_1101: GHRNext = {PCSrcE, GHR[k+1], GHR[k-1:0], 3'b0}; // Miss prediction, cannot have RemoveBrE
-      6'b10_0000: GHRNext = {DirPredictionF[1], GHR[k+4:1]};
-      6'b10_0001: GHRNext = {DirPredictionF[1], GHR[k+4:k+1], GHR[k-1:1], 1'b0};
-      6'b10_0010: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k:1], 1'b0};
-      6'b10_0011: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k-1:1], 2'b0};
-      6'b10_0100: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1:1], 1'b0};
-      6'b10_0101: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1], GHR[k-1:1], 2'b0};
-      6'b10_0110: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k], GHR[k-1:1], 2'b0};
-      6'b10_0111: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k-1:1], 3'b0};
-      
-      default: GHRNext = GHR;
-    endcase
-  end
-
-  flopenr  #(k+5) GHRReg(clk, reset, GHRUpdateEn,  GHRNext, GHR);
-  logic [k-1:0] GHRNextF_temp, GHRF_temp;
-  logic [k:0]   GHRD_temp, GHRE_temp, GHRM_temp, GHRW_temp;
-  logic         GHRFExtra_temp;
-
-  // these are also in the ieu controller.  should create inputs.
-  logic         InstrValidF, InstrValidD, InstrValidE, InstrValidM, InstrValidW;
-  flopenrc #(1)  InstrValidFReg(clk, reset, FlushD, ~StallF, 1'b1, InstrValidF);
-  flopenrc #(1)  InstrValidDReg(clk, reset, FlushD, ~StallD, InstrValidF, InstrValidD);
-  flopenrc #(1)  InstrValidEReg(clk, reset, FlushE, ~StallE, InstrValidD, InstrValidE);
-  flopenrc #(1)  InstrValidMReg(clk, reset, FlushM, ~StallM, InstrValidE, InstrValidM);
-  flopenrc #(1)  InstrValidWReg(clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
-
-  
-  assign GHRNextF_temp = GHRNext[k+4:5];
-  assign GHRF_temp = InstrValidF ? GHR[k+3:4] : GHRNextF_temp;
-  assign GHRFExtra_temp = InstrValidF ? 1'b0 : GHR[k+4];
-  assign GHRD_temp = InstrValidD ? GHR[k+3:3] : {GHRFExtra_temp, GHRF_temp};
-  assign GHRE_temp = InstrValidE ?  GHR[k+2:2] : GHRD_temp;
-  assign GHRM_temp = InstrValidM ? GHR[k+1:1] : GHRE_temp;
-  assign GHRW_temp = InstrValidW ? GHR[k:0] : GHRM_temp;
-  
-  
-  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
-  assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
-  assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
-  assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
-  assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
-      
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
-    .ra1(IndexNextF),
-    .rd1(TableDirPredictionF),
-    .wa2(IndexW),
-    .wd2(NewDirPredictionW),
-    .we2(BranchInstrW & ~StallW & ~FlushW),
-    .bwe2(1'b1));
-
-  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
-  //  and then register for use in the Fetch stage.
-  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
-  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
-  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
-  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
-  assign MatchW = BranchInstrW & (IndexNextF == IndexW);
-  assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
-
-  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
-
-  assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
-                                   MatchD ? NewDirPredictionD :
-                                   MatchE ? NewDirPredictionE :
-                                   MatchM ? NewDirPredictionM :
-                                   NewDirPredictionW;
-
-  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
-
-  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
-
-  // DirPrediction pipeline
-  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
-  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
-
-  // New prediction pipeline
-  satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
-  flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
-  flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
-
-  // PCSrc pipeline
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
-  
-  // GHR pipeline
-  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
-                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
-                    GHRF;
-
-  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
-  
-  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
-  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
-
-  assign GHRNextE = FlushE ? GHRNextM : GHRD;
-  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
-  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
-
-  assign GHRNextM = FlushM ? GHRNextW : GHRE;
-  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
-
-  assign GHRNextW = FlushW ? GHRW : GHRM;
-  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
-  
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
-
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
-endmodule
diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
deleted file mode 100644
index ca36a19f1..000000000
--- a/src/ifu/bpred/speculativeglobalhistory.sv
+++ /dev/null
@@ -1,136 +0,0 @@
-///////////////////////////////////////////
-// speculativeglobalhistory.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module speculativeglobalhistory #(parameter int k = 10 ) (
-  input logic 			  clk,
-  input logic 			  reset,
-  input logic 			  StallF, StallD, StallE, StallM, StallW, 
-  input logic 			  FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0] 	  DirPredictionF, 
-  output logic 			  DirPredictionWrongE,
-  // update
-  input logic [3:0] 	  PredInstrClassF,
-  input logic [3:0]       InstrClassD, InstrClassE, InstrClassM,
-  input logic [3:0] 	  WrongPredInstrClassD, 
-  input logic 			  PCSrcE
-);
-
-  logic                    MatchF, MatchD, MatchE;
-  logic                    MatchNextX, MatchXF;
-
-  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionE;
-
-  logic [k-1:0] 		   GHRF, GHRD, GHRE, GHRM;
-  logic 				   GHRLastF;
-  logic [k-1:0] 		   GHRNextF, GHRNextD, GHRNextE, GHRNextM;
-  logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE;
-  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
-
-  logic 				   FlushDOrDirWrong;
-  
-  assign IndexNextF = GHRNextF;
-  assign IndexF = GHRF        ;
-  assign IndexD = GHRD[k-1:0] ;
-  assign IndexE = GHRE[k-1:0] ;
-      
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
-    .ra1(IndexNextF),
-    .rd1(TableDirPredictionF),
-    .wa2(IndexE),
-    .wd2(NewDirPredictionE),
-    .we2(InstrClassE[0]),
-    .bwe2(1'b1));
-
-  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
-  // and then register for use in the Fetch stage.
-  assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
-  assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
-  assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
-  assign MatchNextX = MatchF | MatchD | MatchE;
-
-  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
-
-  assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
-                                   MatchD ? {2{DirPredictionD[1]}} :
-                                   NewDirPredictionE ;
-  
-  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
-
-  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
-
-  // DirPrediction pipeline
-  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
-  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
-
-  
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-
-  // GHR pipeline
-
-  // If Fetch has a branch, speculatively insert prediction into the GHR
-  // If the front end is flushed or the direction prediction is wrong, reset to
-  // most recent valid GHR.  For a BP wrong this is GHRD with the correct prediction shifted in.
-  // For FlushE this is GHRE.  GHRNextE is both.
-  logic [k-1:0] 		   GHRClassWrongAndPredF;
-  logic [k-1:0] 		   GHRClassWrong;
-  mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF);
-
-  assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
-//  mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
-//					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
-
-  mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0], 
-					{FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF);  
-
-  // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
-  flopenr  #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);	
-  flopenr  #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF);
-
-  // With instruction class prediction, the class could be wrong and is checked in Decode.
-  // If it is wrong and branch does exist then shift right and insert the prediction.
-  // If the branch does not exist then shift left and use GHRLastF to restore the LSB.
-  mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
-  // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
-  mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
-
-  flopenr  #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
-
-  mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
-
-  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
-
-  assign GHRNextM = FlushM ? GHRM : GHRE;
-  flopenr  #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM);
-  
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
-
-endmodule
diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv
deleted file mode 100644
index 48601021a..000000000
--- a/src/ifu/bpred/speculativegshare.sv
+++ /dev/null
@@ -1,137 +0,0 @@
-///////////////////////////////////////////
-// gsharePredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module speculativegshare #(parameter int k = 10 ) (
-  input logic 			  clk,
-  input logic 			  reset,
-  input logic 			  StallF, StallD, StallE, StallM, StallW, 
-  input logic 			  FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0] 	  DirPredictionF, 
-  output logic 			  DirPredictionWrongE,
-  // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
-  input logic [3:0] 	  PredInstrClassF,
-  input logic [3:0]       InstrClassD, InstrClassE, InstrClassM,
-  input logic [3:0] 	  WrongPredInstrClassD, 
-  input logic 			  PCSrcE
-);
-
-  logic                    MatchF, MatchD, MatchE;
-  logic                    MatchNextX, MatchXF;
-
-  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionE;
-
-  logic [k-1:0] 		   GHRF, GHRD, GHRE, GHRM;
-  logic 				   GHRLastF;
-  logic [k-1:0] 		   GHRNextF, GHRNextD, GHRNextE, GHRNextM;
-  logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE;
-  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
-
-  logic 				   FlushDOrDirWrong;
-  
-  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
-  assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
-  assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
-      
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
-    .ra1(IndexNextF),
-    .rd1(TableDirPredictionF),
-    .wa2(IndexE),
-    .wd2(NewDirPredictionE),
-    .we2(InstrClassE[0]),
-    .bwe2(1'b1));
-
-  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
-  // and then register for use in the Fetch stage.
-  assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
-  assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
-  assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
-  assign MatchNextX = MatchF | MatchD | MatchE;
-
-  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
-
-  assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
-                                   MatchD ? {2{DirPredictionD[1]}} :
-                                   NewDirPredictionE ;
-  
-  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
-
-  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
-
-  // DirPrediction pipeline
-  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
-  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
-
-  
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-
-  // GHR pipeline
-
-  // If Fetch has a branch, speculatively insert prediction into the GHR
-  // If the front end is flushed or the direction prediction is wrong, reset to
-  // most recent valid GHR.  For a BP wrong this is GHRD with the correct prediction shifted in.
-  // For FlushE this is GHRE.  GHRNextE is both.
-  logic [k-1:0] 		   GHRClassWrongAndPredF;
-  logic [k-1:0] 		   GHRClassWrong;
-  mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF);
-
-  assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
-//  mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
-//					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
-
-  mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0], 
-					{FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF);  
-
-  // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
-  flopenr  #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);	
-  flopenr  #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF);
-
-  // With instruction class prediction, the class could be wrong and is checked in Decode.
-  // If it is wrong and branch does exist then shift right and insert the prediction.
-  // If the branch does not exist then shift left and use GHRLastF to restore the LSB.
-  mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
-  // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
-  mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
-
-  flopenr  #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
-
-  mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
-
-  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
-
-  assign GHRNextM = FlushM ? GHRM : GHRE;
-  flopenr  #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM);
-  
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
-
-endmodule

From fd5c12431e31f9255695e716f2cb92d591ae789f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Feb 2023 18:48:02 -0600
Subject: [PATCH 44/47] Fixed typo in the global branch predictor.

---
 src/ifu/bpred/gshare.sv      | 10 +++++-----
 src/ifu/bpred/gsharebasic.sv |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index c13bce943..d996b5b62 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -61,11 +61,11 @@ module gshare #(parameter k = 10,
 	assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
 	assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
   end else if(TYPE == "global") begin
-	assign IndexNextF = {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-	assign IndexF = {PCF[k+1] ^ PCF[1], PCF[k:2]};
-	assign IndexD = {PCD[k+1] ^ PCD[1], PCD[k:2]};
-	assign IndexE = {PCE[k+1] ^ PCE[1], PCE[k:2]};
-	assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};
+	assign IndexNextF = GHRNextF;
+	assign IndexF = GHRF;
+	assign IndexD = GHRD;
+	assign IndexE = GHRE;
+	assign IndexM = GHRM;
   end
 
   assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv
index d73797275..6446ecbc3 100644
--- a/src/ifu/bpred/gsharebasic.sv
+++ b/src/ifu/bpred/gsharebasic.sv
@@ -54,8 +54,8 @@ module gsharebasic #(parameter k = 10,
 	assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
 	assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
   end else if(TYPE == "global") begin
-	assign IndexNextF = {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-	assign IndexE = {PCM[k+1] ^ PCM[1], PCM[k:2]};
+	assign IndexNextF = GHRNext;
+	assign IndexE = GHRE;
   end
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),

From 0b9fd8a4b310554b4744a2178e2eafe4dd4c572d Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 21 Feb 2023 09:32:17 -0800
Subject: [PATCH 45/47] Fixed Issue #106: fld rasies load access fault instead
 of illegal instruction.  The IEU controller had considered all fp loads and
 stores to be legal regardless of whether the FPU is enabled or the type is
 supported.  Merged illegal instruction detection from both units into the
 Decode stage, saving two bits of pipeline register as well.

---
 src/fpu/fctrl.sv                | 15 +++++++--------
 src/fpu/fpu.sv                  |  4 ++--
 src/ieu/controller.sv           | 12 ++++++------
 src/ieu/ieu.sv                  |  6 +++---
 src/ifu/ifu.sv                  | 11 +++++++----
 src/privileged/privdec.sv       |  7 +++----
 src/privileged/privileged.sv    | 10 +++++-----
 src/privileged/privpiperegs.sv  | 14 +++++++-------
 src/wally/wallypipelinedcore.sv | 15 +++++++--------
 9 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index 563206134..e787d10b4 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -60,14 +60,13 @@ module fctrl (
   output logic [4:0] 	        Adr1D, Adr2D, Adr3D,                // adresses of each input
   output logic [4:0] 	        Adr1E, Adr2E, Adr3E,                // adresses of each input
   // other control signals
-  output logic                IllegalFPUInstrM,                   // Is the instruction an illegal fpu instruction
+  output logic                IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction
   output logic 		            FDivStartE, IDivStartE              // Start division or squareroot
   );
 
   `define FCTRLW 12
 
   logic [`FCTRLW-1:0]   ControlsD;    // control signals
-  logic                 IllegalFPUInstrD, IllegalFPUInstrE; // is the intruction an illegal fpu instruction
   logic 		            FRegWriteD;   // FP register write enable
   logic 		            FDivStartD;   // start division/sqrt
   logic 		            FWriteIntD;   // integer register write enable
@@ -280,9 +279,9 @@ module fctrl (
   assign Adr3D = InstrD[31:27];
  
   // D/E pipleine register
-  flopenrc #(14+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
-              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, IllegalFPUInstrD, FCvtIntD},
-              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE});
+  flopenrc #(13+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
+              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD},
+              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE});
   flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
   flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
   flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
@@ -292,9 +291,9 @@ module fctrl (
   else                             assign IDivStartE = 0; 
 
   // E/M pipleine register
-  flopenrc #(14+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
-              {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE},
-              {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, IllegalFPUInstrM, FCvtIntM});
+  flopenrc #(13+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
+              {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE},
+              {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, FCvtIntM});
   
   // renameing for readability
   assign FpLoadStoreM = FResSelM[1];
diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
index 73bf1971e..eabc57b32 100755
--- a/src/fpu/fpu.sv
+++ b/src/fpu/fpu.sv
@@ -55,7 +55,7 @@ module fpu (
   output logic 		          FpLoadStoreM,  // Fp load instruction? (to LSU)
   output logic [`FLEN-1:0]  FWriteDataM,   // Data to be written to memory (to LSU) 
   output logic [`XLEN-1:0]  FIntResM,      // data to be written to integer register (to IEU)
-  output logic 		          IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit)
+  output logic 		          IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU)
   output logic [4:0] 	      SetFflagsM,    // FPU flags (to privileged unit)
   // Writeback stage 
   input  logic [4:0] 	      RdW,           // which FP register to write to (from IEU)
@@ -171,7 +171,7 @@ module fpu (
               .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
               .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
               .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
-              .IllegalFPUInstrM, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
+              .IllegalFPUInstrD, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
               .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, 
               .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
 
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index d66425343..0b1852cb0 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -36,8 +36,8 @@ module controller(
   input  logic        StallD, FlushD,          // Stall, flush Decode stage
   input  logic [31:0] InstrD,                  // Instruction in Decode stage
   output logic [2:0]  ImmSrcD,                 // Type of immediate extension
-  input  logic        IllegalIEUInstrFaultD,   // Illegal IEU instruction
-  output logic        IllegalBaseInstrFaultD,  // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
+  input  logic        IllegalIEUFPUInstrD,     // Illegal IEU and FPU instruction
+  output logic        IllegalBaseInstrD,       // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
   // Execute stage control signals             
   input  logic 	      StallE, FlushE,          // Stall, flush Execute stage
   input  logic [1:0]  FlagsE,                  // Comparison flags ({eq, lt})
@@ -126,7 +126,7 @@ module controller(
     // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
       7'b0000000:     ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction
       7'b0000011:     ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
-      7'b0000111:     ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // flw - only legal if FP supported
+      7'b0000111:     ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported
       7'b0001111: if (`ZIFENCEI_SUPPORTED)
                       ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
               	  else
@@ -138,7 +138,7 @@ module controller(
                   else
                       ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
       7'b0100011:     ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // sw
-      7'b0100111:     ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // fsw - only legal if FP supported
+      7'b0100111:     ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported
       7'b0101111: if (`A_SUPPORTED) begin
                     if (InstrD[31:27] == 5'b00010)
                       ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
@@ -178,10 +178,10 @@ module controller(
   // Squash control signals if coming from an illegal compressed instruction
   // On RV32E, can't write to upper 16 registers.  Checking reads to upper 16 is more costly so disregard them.
   assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; 
-  assign IllegalBaseInstrFaultD = ControlsD[0] | IllegalERegAdrD;
+  assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD;
   assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
           ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, 
-          PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
+          PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
   
 
   assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv
index 9d3a833e9..346594eba 100644
--- a/src/ieu/ieu.sv
+++ b/src/ieu/ieu.sv
@@ -32,8 +32,8 @@ module ieu (
   input  logic 		          clk, reset,
   // Decode stage signals
   input  logic [31:0] 	    InstrD,                          // Instruction
-  input  logic 		          IllegalIEUInstrFaultD,           // Illegal instruction
-  output logic 		          IllegalBaseInstrFaultD,          // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
+  input  logic 		          IllegalIEUFPUInstrD,             // Illegal instruction
+  output logic 		          IllegalBaseInstrD,               // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
   // Execute stage signals
   input  logic [`XLEN-1:0]  PCE,                             // PC
   input  logic [`XLEN-1:0]  PCLinkE,                         // PC + 4
@@ -94,7 +94,7 @@ module ieu (
            
   controller c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
-    .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
+    .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
     .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
     .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 51317e0b0..1a63bfca8 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -70,9 +70,10 @@ module ifu (
   output logic 				RASPredPCWrongM,                          // RAS prediction is wrong
   output logic 				PredictionInstrClassWrongM,               // Class prediction is wrong
   // Faults
-  input logic 				IllegalBaseInstrFaultD,                   // Illegal non-compressed instruction
+  input logic 				IllegalBaseInstrD,                   // Illegal non-compressed instruction
+  input logic         IllegalFPUInstrD,                    // Illegal FP instruction
   output logic 				InstrPageFaultF,                          // Instruction page fault 
-  output logic 				IllegalIEUInstrFaultD,                    // Illegal instruction including compressed
+  output logic 				IllegalIEUFPUInstrD,                      // Illegal instruction including compressed & FP
   output logic 				InstrMisalignedFaultM,                    // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
   // mmu management
   input logic [1:0] 		PrivilegeModeW,                           // Priviledge mode in Writeback stage
@@ -116,6 +117,7 @@ module ifu (
   logic                        CompressedE;                           // The execution instruction is compressed
   logic [31:0] 				   PostSpillInstrRawF;                    // Fetch instruction after merge two halves of spill
   logic [31:0] 				   InstrRawD;                             // Non-decompressed instruction in the Decode stage
+  logic                  IllegalIEUInstrD;                 // IEU Instruction (regular or compressed) is not good
   
   logic [1:0]                  IFURWF;                                // IFU alreays read IFURWF = 10
   logic [31:0]                 InstrE;                                // Instruction in the Execution stage
@@ -349,11 +351,12 @@ module ifu (
   if (`C_SUPPORTED) begin
     logic IllegalCompInstrD;
     decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
-    assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
+    assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
   end else begin  
     assign InstrD = InstrRawD;
-    assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD;
+    assign IllegalIEUInstrD = IllegalBaseInstrD;
   end
+  assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
 
   // Misaligned PC logic
   // Instruction address misalignement only from br/jal(r) instructions.
diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv
index fe73ebbf7..21239dc95 100644
--- a/src/privileged/privdec.sv
+++ b/src/privileged/privdec.sv
@@ -34,8 +34,7 @@ module privdec (
   input  logic         StallM,
   input  logic [31:20] InstrM,                              // privileged instruction function field
   input  logic         PrivilegedM,                         // is this a privileged instruction (from IEU controller)
-  input  logic         IllegalIEUInstrFaultM,               // Not a legal IEU instruction
-  input  logic         IllegalFPUInstrM,                    // Not a legal FPU instruction
+  input  logic         IllegalIEUFPUInstrM,                 // Not a legal IEU instruction
   input  logic         IllegalCSRAccessM,                   // Not a legal CSR access
   input  logic [1:0]   PrivilegeModeW,                      // current privilege level
   input  logic         STATUS_TSR, STATUS_TVM, STATUS_TW,   // status bits
@@ -85,6 +84,6 @@ module privdec (
   ///////////////////////////////////////////
   
   assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
-  assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | 
-                               WFITimeoutM; 
+  assign IllegalInstrFaultM = IllegalIEUFPUInstrM | IllegalPrivilegedInstrM | IllegalCSRAccessM | 
+                              WFITimeoutM; 
 endmodule
diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv
index 29d65f131..300da8a65 100644
--- a/src/privileged/privileged.sv
+++ b/src/privileged/privileged.sv
@@ -65,7 +65,7 @@ module privileged (
   input  logic             LoadPageFaultM, StoreAmoPageFaultM,        // page faults
   input  logic             InstrMisalignedFaultM,                     // misaligned instruction fault
   input  logic             LoadMisalignedFaultM, StoreAmoMisalignedFaultM,  // misaligned data fault
-  input  logic             IllegalIEUInstrFaultD, IllegalFPUInstrM,   // illegal instruction faults
+  input  logic             IllegalIEUFPUInstrD,                       // illegal instruction from IEU or FPU
   input  logic             MTimerInt, MExtInt, SExtInt, MSwInt,       // interrupt sources
   input  logic [63:0]      MTIME_CLINT,                               // timer value from CLINT
   input  logic [4:0]       SetFflagsM,                                // set FCSR flags from FPU
@@ -95,7 +95,7 @@ module privileged (
   logic [11:0]             MIDELEG_REGW;                              // interrupt delegation CSR
   logic                    sretM, mretM;                              // supervisor / machine return instruction
   logic                    IllegalCSRAccessM;                         // Illegal access to CSR
-  logic                    IllegalIEUInstrFaultM;                     // Illegal IEU instruction, delayed to Mem stage
+  logic                    IllegalIEUFPUInstrM;                       // Illegal IEU or FPU instruction, delayed to Mem stage
   logic                    InstrPageFaultM;                           // Instruction page fault, delayed to Mem stage
   logic                    InstrAccessFaultM;                         // Instruction access fault, delayed to Mem stages
   logic                    IllegalInstrFaultM;                        // Illegal instruction fault
@@ -115,7 +115,7 @@ module privileged (
 
   // decode privileged instructions
   privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), 
-    .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, 
+    .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, 
     .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
     .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
 
@@ -137,8 +137,8 @@ module privileged (
 
   // pipeline early-arriving trap sources
   privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-    .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, 
-    .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM);
+    .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUFPUInstrD, 
+    .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUFPUInstrM);
 
   // trap logic
   trap trap(.reset,
diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv
index 03e1d6213..c3d308c11 100644
--- a/src/privileged/privpiperegs.sv
+++ b/src/privileged/privpiperegs.sv
@@ -33,24 +33,24 @@ module privpiperegs (
   input  logic         StallD, StallE, StallM,
   input  logic         FlushD, FlushE, FlushM,
   input  logic         InstrPageFaultF, InstrAccessFaultF,  // instruction faults
-  input  logic         IllegalIEUInstrFaultD,               // illegal IEU instruction decoded
+  input  logic         IllegalIEUFPUInstrD,                 // illegal IEU instruction decoded
   output logic         InstrPageFaultM, InstrAccessFaultM,  // delayed instruction faults
-  output logic         IllegalIEUInstrFaultM                // delayed illegal IEU instruction
+  output logic         IllegalIEUFPUInstrM                  // delayed illegal IEU instruction
 );
 
   // Delayed fault signals
   logic                InstrPageFaultD, InstrAccessFaultD;
   logic                InstrPageFaultE, InstrAccessFaultE;
-  logic                IllegalIEUInstrFaultE; 
+  logic                IllegalIEUFPUInstrE; 
 
   // pipeline fault signals
   flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
                   {InstrPageFaultF, InstrAccessFaultF},
                   {InstrPageFaultD, InstrAccessFaultD});
   flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE,
-                  {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD}, 
-                  {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE});
+                  {IllegalIEUFPUInstrD, InstrPageFaultD, InstrAccessFaultD}, 
+                  {IllegalIEUFPUInstrE, InstrPageFaultE, InstrAccessFaultE});
   flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM,
-                  {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE},
-                  {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM});
+                  {IllegalIEUFPUInstrE, InstrPageFaultE, InstrAccessFaultE},
+                  {IllegalIEUFPUInstrM, InstrPageFaultM, InstrAccessFaultM});
 endmodule
\ No newline at end of file
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index a03caea15..7ac53117d 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -70,7 +70,7 @@ module wallypipelinedcore (
   logic [1:0] 					 MemRWM;
   logic 						 InstrValidD, InstrValidE, InstrValidM;
   logic                          InstrMisalignedFaultM;
-  logic                          IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
+  logic                          IllegalBaseInstrD, IllegalFPUInstrD, IllegalIEUFPUInstrD;
   logic                          InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
   logic                          LoadMisalignedFaultM, LoadAccessFaultM;
   logic                          StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
@@ -91,7 +91,6 @@ module wallypipelinedcore (
   logic [`XLEN-1:0]              FCvtIntResW; 
   logic                          FCvtIntW; 
   logic                          FDivBusyE;
-  logic                          IllegalFPUInstrM;
   logic                          FRegWriteM;
   logic                          FCvtIntStallD;
   logic                          FpLoadStoreM;
@@ -180,7 +179,7 @@ module wallypipelinedcore (
     .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
     .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
     // Faults out
-    .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
+    .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
     // mmu management
     .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
     .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
@@ -190,7 +189,7 @@ module wallypipelinedcore (
   // integer execution unit: integer register file, datapath and controller
   ieu ieu(.clk, .reset,
      // Decode Stage interface
-     .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
+     .InstrD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
      // Execute Stage interface
      .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
      .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, 
@@ -294,12 +293,12 @@ module wallypipelinedcore (
       .RASPredPCWrongM, .PredictionInstrClassWrongM,
       .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
-      .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, 
+      .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, 
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
       .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
       .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
       .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
-      .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW,
+      .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
       .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
@@ -347,7 +346,7 @@ module wallypipelinedcore (
       .FCvtIntResW, // fp -> int conversion result to be stored in int register
       .FCvtIntW,   // fpu result selection
       .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
-      .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
+      .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
       .SetFflagsM,        // FPU flags (to privileged unit)
       .FIntDivResultW); 
   end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
@@ -357,7 +356,7 @@ module wallypipelinedcore (
     assign FIntResM = 0;
     assign FCvtIntW = 0;
     assign FDivBusyE = 0;
-    assign IllegalFPUInstrM = 1;
+    assign IllegalFPUInstrD = 1;
     assign SetFflagsM = 0;
     assign FpLoadStoreM = 0;
   end

From 5ce476241bf0be4aafc8edb56594ab06e717bc55 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 21 Feb 2023 09:33:36 -0800
Subject: [PATCH 46/47] Debug test case updates

---
 tests/custom/debug/Makefile |  1 +
 tests/custom/debug/debug.S  | 14 ++++++++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile
index ddabe4e31..7f3fd926e 100644
--- a/tests/custom/debug/Makefile
+++ b/tests/custom/debug/Makefile
@@ -4,6 +4,7 @@ TARGET = debug
 
 $(TARGET).signature.output: $(TARGET).elf.memfile $(TARGET).elf
 	spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=4 $(TARGET).elf
+	riscv_sim_RV64 debug.elf -T debug.sig
 #	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
 #	echo "Signature matches! Success!"
 	mkdir -p ../work 
diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S
index e6e00e865..d91229dac 100644
--- a/tests/custom/debug/debug.S
+++ b/tests/custom/debug/debug.S
@@ -18,24 +18,29 @@ rvtest_entry_point:
     fsd f12, 0(a6)
 
     # openhwgroup/cvw Issue #56
-    fld f4, 16(a7)
+    fld f4, 16(a7) # cfa695b1047553b1
     fld f14, 24(a7)
     fsgnjx.s f10,f4,f14  # expected f 0xffffffff7fc00000, hdl has been giving 0xcfa695b1047553b1
-    fsd f19, 8(a6)
+    fsd f19, 16(a6)
 
     # openhwgroup/cvw Issue #57
     fld f0, 32(a7)
     fld f15, 40(a7)
     fsgnjx.s f30,f0,f15  # expected f 0xfffffffffb3754ef, hdl has been giving 0xffffffff7b3754ef
-    fsd f30, 16(a6)
+    fsd f30, 24(a6)
 
     # openhwgroup/cvw Issue #58
     fld f14, 48(a7)
     fclass.s x2, f14 # expected 0x0000000000000200, hdl had been giving 0x0000000000000220
-    sd x2, 24(a6)
+    sd x2, 32(a6)
 
     # fsgnjx.s, fclass.s, fsgnjn.s, fsgnj.s, fneg.s, fabs.s, fmv.s all treat inputs as dp rather than sp
 
+    #openhwgroup/cvw Issue #65 #expected 0xffffffffffffffff, hdl had been giving 0x00000000ffffffff
+    fld f17, 56(a7)
+    fmv.x.s x30, f17
+    sd x30, 40(a6)
+
 
 #########################
 # HTIF and signature
@@ -66,6 +71,7 @@ rvtest_data:
 .dword 0xffffffff7fc00000
 .dword 0xfffffffffb3754ef
 .dword 0x7fefffffffffffff
+.dword 0x00000000ffffffff
 
 .EQU XLEN,64
 begin_signature:

From 8df7768d3250c7712614d98bf9614fbd94b2a8b5 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 21 Feb 2023 09:57:57 -0800
Subject: [PATCH 47/47] Fixed Issue #65 fmv sign selection.  Sign needs to come
 from most significant bit of raw X source without doing NaN Box fixes first.

---
 src/fpu/fpu.sv | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
index eabc57b32..8ff36fbfc 100755
--- a/src/fpu/fpu.sv
+++ b/src/fpu/fpu.sv
@@ -160,6 +160,7 @@ module fpu (
   logic [`FLEN-1:0] BoxedOneE;                            // One value for Z for multiplication, with NaN boxing if needed
   logic             StallUnpackedM;                       // Stall unpacker outputs during multicycle fdivsqrt
   logic [`FLEN-1:0] SgnExtXE;                             // Sign-extended X input for move to integer
+  logic             mvsgn;                                // sign bit for extending move
 
   //////////////////////////////////////////////////////////////////////////////////////////
   // Decode Stage: fctrl decoder, read register file
@@ -278,21 +279,25 @@ module fpu (
   mux3  #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
   assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
 
-  // select the result that may be written to the integer register - to IEU
-  if(`FPSIZES == 1)
+  // select the result that may be written to the integer register with fmv - to IEU
+  if(`FPSIZES == 1) begin
+    assign mvsgn = XE[`FLEN-1];
     assign SgnExtXE = XE;
-  else if(`FPSIZES == 2) 
-    mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{XsE}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
-  else if(`FPSIZES == 3 | `FPSIZES == 4)
-    mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]}, 
-                                {{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]}, 
-                                {{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]}, 
+  end else if(`FPSIZES == 2) begin
+    mux2 #(1)     sgnmux (XE[`LEN1-1], XE[`FLEN-1],FmtE, mvsgn);
+    mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{mvsgn}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
+  end else if(`FPSIZES == 3 | `FPSIZES == 4) begin
+    mux4 #(1)     sgnmux (XE[`H_LEN-1], XE[`S_LEN-1], XE[`D_LEN-1], XE[`LLEN-1], FmtE, mvsgn);
+    mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{mvsgn}}, XE[`H_LEN-1:0]}, 
+                                {{`FLEN-`S_LEN{mvsgn}}, XE[`S_LEN-1:0]}, 
+                                {{`FLEN-`D_LEN{mvsgn}}, XE[`D_LEN-1:0]}, 
                                 XE, FmtE, SgnExtXE); 
+  end
 
   if (`FLEN>`XLEN)
     assign IntSrcXE = SgnExtXE[`XLEN-1:0];
   else 
-    assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE};
+    assign IntSrcXE = {{`XLEN-`FLEN{mvsgn}}, SgnExtXE};
   mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
 
   // E/M pipe registers