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Added more signals to debugger in hopes I can figure out why the mig is not responding.

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This commit is contained in:
Ross Thompson 2023-04-18 15:51:52 -05:00
parent 2df6c6cb0f
commit 667524efcb
2 changed files with 75 additions and 10 deletions
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65
fpga/constraints/small-debug.xdc
View File

@ -63,6 +63,71 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {m_axi_arvalid}]] connect_debug_port u_ila_0/probe8 [get_nets [list {m_axi_arvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {c0_init_calib_complete}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {ui_clk_sync_rst}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {mmcm_locked}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {m_axi_awvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {m_axi_awready}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {BUS_axi_arvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {BUS_axi_awready}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {BUS_axi_arvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {BUS_axi_arready}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {BUS_axi_rvalid}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {BUS_axi_rready}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {BUS_axi_wready}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]

20
fpga/src/fpgaTopArtyA7.v
View File

@ -136,14 +136,14 @@ module fpgaTop
wire [3:0] BUS_axi_awcache; wire [3:0] BUS_axi_awcache;
wire [30:0] BUS_axi_awaddr; wire [30:0] BUS_axi_awaddr;
wire [2:0] BUS_axi_awprot; wire [2:0] BUS_axi_awprot;
wire BUS_axi_awvalid; (* mark_debug = "true" *) wire BUS_axi_awvalid;
wire BUS_axi_awready; (* mark_debug = "true" *) wire BUS_axi_awready;
wire BUS_axi_awlock; wire BUS_axi_awlock;
wire [63:0] BUS_axi_wdata; wire [63:0] BUS_axi_wdata;
wire [7:0] BUS_axi_wstrb; wire [7:0] BUS_axi_wstrb;
wire BUS_axi_wlast; wire BUS_axi_wlast;
wire BUS_axi_wvalid; (* mark_debug = "true" *) wire BUS_axi_wvalid;
wire BUS_axi_wready; (* mark_debug = "true" *) wire BUS_axi_wready;
wire [3:0] BUS_axi_bid; wire [3:0] BUS_axi_bid;
wire [1:0] BUS_axi_bresp; wire [1:0] BUS_axi_bresp;
wire BUS_axi_bvalid; wire BUS_axi_bvalid;
@ -154,16 +154,16 @@ module fpgaTop
wire [1:0] BUS_axi_arburst; wire [1:0] BUS_axi_arburst;
wire [2:0] BUS_axi_arprot; wire [2:0] BUS_axi_arprot;
wire [3:0] BUS_axi_arcache; wire [3:0] BUS_axi_arcache;
wire BUS_axi_arvalid; (* mark_debug = "true" *) wire BUS_axi_arvalid;
wire [30:0] BUS_axi_araddr; wire [30:0] BUS_axi_araddr;
wire BUS_axi_arlock; wire BUS_axi_arlock;
wire BUS_axi_arready; (* mark_debug = "true" *) wire BUS_axi_arready;
wire [3:0] BUS_axi_rid; wire [3:0] BUS_axi_rid;
wire [63:0] BUS_axi_rdata; wire [63:0] BUS_axi_rdata;
wire [1:0] BUS_axi_rresp; (* mark_debug = "true" *) wire [1:0] BUS_axi_rresp;
wire BUS_axi_rvalid; (* mark_debug = "true" *) wire BUS_axi_rvalid;
wire BUS_axi_rlast; wire BUS_axi_rlast;
wire BUS_axi_rready; (* mark_debug = "true" *) wire BUS_axi_rready;
wire BUSCLK; wire BUSCLK;
@ -171,7 +171,7 @@ module fpgaTop
(* mark_debug = "true" *) wire c0_init_calib_complete; (* mark_debug = "true" *) wire c0_init_calib_complete;
wire dbg_clk; wire dbg_clk;
wire [511 : 0] dbg_bus; wire [511 : 0] dbg_bus;
wire ui_clk_sync_rst; (* mark_debug = "true" *) wire ui_clk_sync_rst;
wire CLK208; wire CLK208;
wire clk167; wire clk167;