From 5e9157244b841b912fd01999b350a32b3acd29a9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 14 Nov 2023 15:18:16 -0800 Subject: [PATCH 1/5] Restored Zfh to 0 for rv64gc because it breaks floating-point tests --- config/rv64gc/config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 564b32f5d..8decf60d5 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -42,7 +42,7 @@ localparam ZIFENCEI_SUPPORTED = 1; localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; -localparam ZFH_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; localparam SSTC_SUPPORTED = 1; localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 1; From 98176665de32e50407470d1ef5e8944781270e9c Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Nov 2023 08:05:41 -0800 Subject: [PATCH 2/5] Fixed messed-up hazard.sv --- src/hazard/hazard.sv | 38 +++++++++----------------------------- 1 file changed, 9 insertions(+), 29 deletions(-) diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 028dbf61d..12bd83bc5 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -26,8 +26,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module hazard import cvw::*; #(parameter cvw_t P) ( - // Detect hazards +module hazard import cvw::*; #(parameter cvw_t P) ( input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, input logic LSUStallM, IFUStallF, @@ -46,28 +45,9 @@ module hazard import cvw::*; #(parameter cvw_t P) ( logic WFIStallM, WFIInterruptedM; - logic ValidWfiM, ValidTrapM, ValidRetM, ValidCSRWriteFenceM, ValidCSRRdStallD; - logic ValidFPUStallD, ValidFCvtIntStallD, ValidFDivBusyE, ValidMDUStallD, ValidDivBusyE; - - // Gate Stall/Flush sources with supported features - // This is not logically necessary because the original signals are already 0 when the feature is unsupported - // However, synthesis does not propagate the constant 0 across modules - // By gating these signals, synthesis eliminates unnecessary stall/flush logic, saving about 10% cycle time for rv32e - // These lines of code gating with a compile-time constant generate no hardware. - assign ValidWfiM = wfiM & P.ZICSR_SUPPORTED; - assign ValidTrapM = TrapM & P.ZICSR_SUPPORTED; - assign ValidRetM = RetM & P.ZICSR_SUPPORTED; - assign ValidCSRWriteFenceM = CSRWriteFenceM & P.ZICSR_SUPPORTED; - assign ValidCSRRdStallD = CSRRdStallD & P.ZICSR_SUPPORTED; - assign ValidFPUStallD = RetM & P.F_SUPPORTED; - assign ValidFCvtIntStallD = RetM & P.F_SUPPORTED; - assign ValidFDivBusyE = FDivBusyE & P.F_SUPPORTED; - assign ValidMDUStallD = MDUStallD & P.M_SUPPORTED; - assign ValidDivBusyE = DivBusyE & P.M_SUPPORTED; - // WFI logic - assign WFIStallM = ValidWfiM & ~IntPendingM; // WFI waiting for an interrupt or timeout - assign WFIInterruptedM = ValidWfiM & IntPendingM; // WFI detects a pending interrupt. Retire WFI; trap if interrupt is enabled. + assign WFIStallM = wfiM & ~IntPendingM; // WFI waiting for an interrupt or timeout + assign WFIInterruptedM = wfiM & IntPendingM; // WFI detects a pending interrupt. Retire WFI; trap if interrupt is enabled. // stalls and flushes // loads: stall for one cycle if the subsequent instruction depends on the load @@ -89,10 +69,10 @@ module hazard import cvw::*; #(parameter cvw_t P) ( // Branch misprediction is found in the Execute stage and must flush the next two instructions. // However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete // When a WFI is interrupted and causes a trap, it flushes the rest of the pipeline but not the W stage, because the WFI needs to commit - assign FlushDCause = ValidTrapM | ValidRetM | ValidCSRWriteFenceM | BPWrongE; - assign FlushECause = ValidTrapM | ValidRetM | ValidCSRWriteFenceM |(BPWrongE & ~(ValidDivBusyE | ValidFDivBusyE)); - assign FlushMCause = ValidTrapM | ValidRetM | ValidCSRWriteFenceM; - assign FlushWCause = ValidTrapM & ~WFIInterruptedM; + assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE; + assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE)); + assign FlushMCause = TrapM | RetM | CSRWriteFenceM; + assign FlushWCause = TrapM & ~WFIInterruptedM; // Stall causes // Most data depenency stalls are identified in the decode stage @@ -103,8 +83,8 @@ module hazard import cvw::*; #(parameter cvw_t P) ( // The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions // A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation assign StallFCause = '0; - assign StallDCause = (LoadStallD | StoreStallD | ValidMDUStallD | ValidCSRRdStallD | ValidFCvtIntStallD | ValidFPUStallD) & ~FlushDCause; - assign StallECause = (ValidDivBusyE | ValidFDivBusyE) & ~FlushECause; + assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause; + assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; assign StallMCause = WFIStallM & ~FlushMCause; // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1. // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; From cfaeeae25a44dfd2c95f4fbdb0b06abb1622c5ba Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Nov 2023 08:15:01 -0800 Subject: [PATCH 3/5] Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter --- sim/imperas.ic | 5 ++++- testbench/testbench-imperas.sv | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index adb10dcad..8d20cdd8f 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -22,6 +22,9 @@ --override cpu/Zicbom=T --override cpu/Zicbop=T --override cpu/Zicboz=T +--override cmomp_bytes=64 # Zic64b +--override cmoz_bytes=64 # Zic64b +--override lr_sc_grain=64 # Za64rs # 64 KiB continuous huge pages supported --override cpu/Svpbmt=T @@ -40,7 +43,7 @@ --override cpu/reset_address=0x80000000 ---override cpu/unaligned=F +--override cpu/unaligned=T # Zicclsm (should be true) --override cpu/ignore_non_leaf_DAU=1 --override cpu/wfi_is_nop=T --override cpu/misa_Extensions_mask=0x0 diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv index b503372d4..c27722f9f 100644 --- a/testbench/testbench-imperas.sv +++ b/testbench/testbench-imperas.sv @@ -237,7 +237,7 @@ module testbench; assign HRDATAEXT = 0; end - if(P.FPGA) begin : sdcard + if(P.SDC_SUPPORTED) begin : sdcard // *** fix later /* -----\/----- EXCLUDED -----\/----- sdModel sdcard From 817ddbc7c5cef82f1987eac1c9e3847d47e205cb Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Nov 2023 08:19:50 -0800 Subject: [PATCH 4/5] Adjusted LSU misaligned buffer to fix synthesis warning --- src/lsu/lsu.sv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index ba7d8e119..d872e0114 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -92,7 +92,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit ); - localparam MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED; + localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED; + localparam MLEN = MISALIGN_SUPPROT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer @@ -118,9 +119,9 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic [P.LLEN-1:0] DTIMReadDataWordM; // DTIM read data /* verilator lint_off WIDTHEXPAND */ - logic [(MISALIGN_SUPPORT+1)*P.LLEN-1:0] DCacheReadDataWordM; // D$ read data - logic [(MISALIGN_SUPPORT+1)*P.LLEN-1:0] LSUWriteDataSpillM; // Final write data - logic [((MISALIGN_SUPPORT+1)*P.LLEN-1)/8:0] ByteMaskSpillM; // Selects which bytes within a word to write + logic [MLEN-1:0] DCacheReadDataWordM; // D$ read data + logic [MLEN-1:0] LSUWriteDataSpillM; // Final write data + logic [MLEN/8-1:0] ByteMaskSpillM; // Selects which bytes within a word to write /* verilator lint_on WIDTHEXPAND */ logic [P.LLEN-1:0] DCacheReadDataWordSpillM; // D$ read data logic [P.LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data From eef39bd49546ed66de44cfec32acc1ea18264463 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Nov 2023 08:30:48 -0800 Subject: [PATCH 5/5] Fixed typo in lsu parameter --- src/lsu/lsu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index d872e0114..f01dc609b 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -93,7 +93,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit ); localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED; - localparam MLEN = MISALIGN_SUPPROT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess + localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess logic [P.XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer logic [P.XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer