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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2021-09-08 12:47:03 -05:00
commit 6606eea27e
15 changed files with 661 additions and 1173 deletions
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2
wally-pipelined/config/rv64icfd/wally-config.vh
View File

@ -26,7 +26,7 @@
// include shared configuration // include shared configuration
`include "wally-shared.vh" `include "wally-shared.vh"
// `include "../shared/wally-shared.vh" // `include "../shared/wally-shared.vh"
`define QEMU 0 `define QEMU 0
`define BUILDROOT 0 `define BUILDROOT 0

2
wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
View File

@ -142,7 +142,7 @@ assign ansnan = FmtE ? &ans[`FLEN-2:`NF] && |ans[`NF-1:0] : &ans[30:23] && |ans[
.BiasE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
.FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE,
.ProdExpE, .AddendStickyE, .KillProdE); .ProdExpE, .AddendStickyE, .KillProdE);
fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .ZSgnM(ZSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM({XAssumed1E,XFracE}), .YManM({YAssumed1E,YFracE}), .ZManM({ZAssumed1E,ZFracE}), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE), fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM({XAssumed1E,XFracE}), .YManM({YAssumed1E,YFracE}), .ZManM({ZAssumed1E,ZFracE}), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE),
// .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM, // .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM,
.FOpCtrlM(FOpCtrlE[2:0]), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FOpCtrlM(FOpCtrlE[2:0]), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE),
.FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM); .FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM);

9
wally-pipelined/linux-testgen/testvector-generation/CreateTrace.sh
View File

@ -15,4 +15,11 @@ outDir="../linux-testvectors"
# - Logs info needed by buildroot testbench # - Logs info needed by buildroot testbench
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > all.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog read -p "Warning: running this script will overwrite the contents of $outDir/all.txt.
Would you like to proceed? (y/n) " -n 1 -r
echo
if [[ $REPLY =~ ^[Yy]$ ]]
then
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > $outDir/all.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog
fi

6
wally-pipelined/linux-testgen/testvector-generation/debugBuildroot.sh
View File

@ -14,16 +14,16 @@ outDir="../linux-testvectors"
# Uncomment this version for QEMU debugging of kernel # Uncomment this version for QEMU debugging of kernel
# - good for poking around VM if it boots up # - good for poking around VM if it boots up
# - good for running QEMU commands (press "Ctrl-A" then "c" to open QEMU command prompt) # - good for running QEMU commands (press "Ctrl-A" then "c" to open QEMU command prompt)
#$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio #$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1
# Uncomment this version for GDB debugging of kernel # Uncomment this version for GDB debugging of kernel
# - attempts to load in symbols from "vmlinux" # - attempts to load in symbols from "vmlinux"
# - good for looking at backtraces when Linux gets stuck for some reason # - good for looking at backtraces when Linux gets stuck for some reason
#$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -gdb tcp::1237 -S & riscv64-unknown-elf-gdb -x gdbinit_debug $customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -gdb tcp::1237 -S & riscv64-unknown-elf-gdb -x gdbinit_debug
# Uncomment this version to generate qemu_output.txt # Uncomment this version to generate qemu_output.txt
# - Uses GDB script # - Uses GDB script
# - Logs raw QEMU output to qemu_output.txt # - Logs raw QEMU output to qemu_output.txt
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug #($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
# Uncomment this version for parse_qemu.py debugging # Uncomment this version for parse_qemu.py debugging
# - Uses qemu_output.txt # - Uses qemu_output.txt

4
wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog
View File

@ -3,9 +3,9 @@ target extended-remote :1236
file ../buildroot-image-output/vmlinux file ../buildroot-image-output/vmlinux
stepi 1000 stepi 1000
b do_idle b do_idle
ignore 1 2
c c
c # using 3 continues didn't work because the first breakpoint hit causes a pipe break error
c
set confirm off set confirm off
kill kill
q q

24
wally-pipelined/linux-testgen/testvector-generation/logBuildrootMem.sh
View File

@ -8,14 +8,20 @@ customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qe
imageDir="../buildroot-image-output" imageDir="../buildroot-image-output"
testVecDir="../linux-testvectors" testVecDir="../linux-testvectors"
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1235 -S 2>/dev/null >/dev/null) & read -p "Warning: running this script will overwrite the contents of memory dumps needed for simulation.
riscv64-unknown-elf-gdb -x gdbinit_mem Would you like to proceed? (y/n) " -n 1 -r
echo "Translating Mem from GDB to Questa format" echo
./fix_mem.py if [[ $REPLY =~ ^[Yy]$ ]]
echo "Done" then
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1235 -S 2>/dev/null >/dev/null) &
riscv64-unknown-elf-gdb -x gdbinit_mem
echo "Translating Mem from GDB to Questa format"
./fix_mem.py
echo "Done"
echo "Creating debugging objdump of linux image" echo "Creating debugging objdump of linux image"
riscv64-unknown-elf-objdump -D $imageDir/vmlinux > $testVecDir/vmlinux.objdump riscv64-unknown-elf-objdump -D $imageDir/vmlinux > $testVecDir/vmlinux.objdump
extractFunctionRadix.sh $testVecDir/vmlinux.objdump extractFunctionRadix.sh $testVecDir/vmlinux.objdump
echo "Done" echo "Done"
fi

15
wally-pipelined/regression/wally-buildroot.do
View File

@ -34,19 +34,10 @@ vopt +acc work.testbench -o workopt
vsim workopt -suppress 8852,12070 vsim workopt -suppress 8852,12070
run 150 ms
add log -r /*
do linux-wave.do
run 150 ms
#run 180 us
#-- Run the Simulation #-- Run the Simulation
#run -all run -all
#do ./wave-dos/linux-waves.do do ./wave-dos/linux-waves.do
#run 60 ms run -all
#run -all
exec ./slack-notifier/slack-notifier.py exec ./slack-notifier/slack-notifier.py
##quit ##quit

328
wally-pipelined/regression/wave-dos/linux-waves.do
View File

@ -3,7 +3,8 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate -divider <NULL> add wave -noupdate -divider <NULL>
add wave -noupdate /testbench/clk add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset
add wave -noupdate -radix decimal /testbench/instrs add wave -noupdate -radix decimal /testbench/errorCount
add wave -noupdate -radix decimal /testbench/InstrCountW
add wave -noupdate -divider Stalls_and_Flushes add wave -noupdate -divider Stalls_and_Flushes
add wave -noupdate /testbench/dut/hart/StallF add wave -noupdate /testbench/dut/hart/StallF
add wave -noupdate /testbench/dut/hart/StallD add wave -noupdate /testbench/dut/hart/StallD
@ -14,33 +15,15 @@ add wave -noupdate /testbench/dut/hart/FlushD
add wave -noupdate /testbench/dut/hart/FlushE add wave -noupdate /testbench/dut/hart/FlushE
add wave -noupdate /testbench/dut/hart/FlushM add wave -noupdate /testbench/dut/hart/FlushM
add wave -noupdate /testbench/dut/hart/FlushW add wave -noupdate /testbench/dut/hart/FlushW
add wave -noupdate -divider InstrTranslator
add wave -noupdate -group InstrTranslator /testbench/SvMode
add wave -noupdate -group InstrTranslator /testbench/PTE_R
add wave -noupdate -group InstrTranslator /testbench/PTE_X
add wave -noupdate -group InstrTranslator /testbench/SATP
add wave -noupdate -group InstrTranslator /testbench/PTE
add wave -noupdate -group InstrTranslator /testbench/BaseAdr
add wave -noupdate -group InstrTranslator /testbench/PAdr
add wave -noupdate -group InstrTranslator /testbench/VPN
add wave -noupdate -group InstrTranslator /testbench/Offset
add wave -noupdate -group InstrTranslator /testbench/readAdrExpected
add wave -noupdate -group InstrTranslator /testbench/readAdrTranslated
add wave -noupdate -group InstrTranslator /testbench/writeAdrExpected
add wave -noupdate -group InstrTranslator /testbench/writeAdrTranslated
add wave -noupdate -divider F add wave -noupdate -divider F
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCF add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCF
add wave -noupdate -divider D add wave -noupdate -divider D
add wave -noupdate -radix hexadecimal /testbench/PCDexpected
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD
add wave -noupdate -radix hexadecimal /testbench/PCtextD
add wave -noupdate /testbench/InstrDName add wave -noupdate /testbench/InstrDName
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidD
add wave -noupdate -radix hexadecimal /testbench/PCDwrong
add wave -noupdate -divider E add wave -noupdate -divider E
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCE
add wave -noupdate -radix hexadecimal /testbench/PCtextE
add wave -noupdate /testbench/InstrEName add wave -noupdate /testbench/InstrEName
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrE
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidE
@ -49,8 +32,8 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcBE
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
add wave -noupdate -divider M add wave -noupdate -divider M
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM
add wave -noupdate -radix hexadecimal /testbench/PCtextM
add wave -noupdate /testbench/InstrMName add wave -noupdate /testbench/InstrMName
add wave -noupdate /testbench/textM
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu/dcache/MemPAdrM add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu/dcache/MemPAdrM
@ -80,168 +63,8 @@ add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/Translatio
add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/WalkerState add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/NextWalkerState add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/NextWalkerState
add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/InitialWalkerState add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/InitialWalkerState
add wave -noupdate -group LSU /testbench/dut/hart/lsu/clk add wave -noupdate -group LSU -r /testbench/dut/hart/lsu/*
add wave -noupdate -group LSU /testbench/dut/hart/lsu/reset add wave -noupdate -group DCache -r /testbench/dut/hart/lsu/dcache/*
add wave -noupdate -group LSU /testbench/dut/hart/lsu/StallM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/FlushM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/StallW
add wave -noupdate -group LSU /testbench/dut/hart/lsu/FlushW
add wave -noupdate -group LSU /testbench/dut/hart/lsu/LSUStall
add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemRWM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/Funct3M
add wave -noupdate -group LSU /testbench/dut/hart/lsu/Funct7M
add wave -noupdate -group LSU /testbench/dut/hart/lsu/AtomicM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/ExceptionM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/PendingInterruptM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/CommittedM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/SquashSCW
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DataMisalignedM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAdrM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAdrE
add wave -noupdate -group LSU /testbench/dut/hart/lsu/WriteDataM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/ReadDataW
add wave -noupdate -group LSU /testbench/dut/hart/lsu/PrivilegeModeW
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBFlushM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBLoadPageFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBStorePageFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/LoadMisalignedFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/LoadAccessFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/StoreMisalignedFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/StoreAccessFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/CommitM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBPAdrM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBReadM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBWriteM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCfromAHBAck
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCfromAHBReadData
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBWriteData
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBSizeM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/SATP_REGW
add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_MXR
add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_SUM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_MPRV
add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_MPP
add wave -noupdate -group LSU /testbench/dut/hart/lsu/PCF
add wave -noupdate -group LSU /testbench/dut/hart/lsu/ITLBMissF
add wave -noupdate -group LSU /testbench/dut/hart/lsu/PageType
add wave -noupdate -group LSU /testbench/dut/hart/lsu/ITLBWriteF
add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerInstrPageFaultF
add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerLoadPageFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerStorePageFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBHitM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/SquashSCM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBPageFaultM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAccessM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/CurrState
add wave -noupdate -group LSU /testbench/dut/hart/lsu/NextState
add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemPAdrM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBMissM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBWriteM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWReadPTE
add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWStall
add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWPAdrE
add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWRead
add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemRWMtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/Funct3MtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/AtomicMtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAdrEtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/ReadDataWfromDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/StallWtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DataMisalignedMfromDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWReady
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DisableTranslation
add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCacheStall
add wave -noupdate -group LSU /testbench/dut/hart/lsu/CacheableM
add wave -noupdate -group LSU /testbench/dut/hart/lsu/CacheableMtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/SelPTW
add wave -noupdate -group LSU /testbench/dut/hart/lsu/CommittedMfromDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/PendingInterruptMtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/FlushWtoDCache
add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerPageFaultM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/clk
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/reset
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/StallM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/StallW
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FlushM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FlushW
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemRWM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct3M
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct7M
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AtomicM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemAdrE
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemPAdrM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataW
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DCacheStall
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CommittedM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ExceptionM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/PendingInterruptM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DTLBMissM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CacheableM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DTLBWriteM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ITLBWriteF
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelPTW
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBPAdr
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBRead
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBWrite
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBAck
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/HRDATA
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/HWDATA
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelAdrM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMAdr
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWriteData
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SetValidM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ClearValidM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SetDirtyM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ClearDirtyM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Valid
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Dirty
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/WayHit
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CacheHit
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/NewReplacement
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataWordM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FinalWriteDataM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FinalAMOWriteDataM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FinalWriteDataWordsM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FetchCount
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/NextFetchCount
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelMemWriteDataM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct3W
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWriteEnable
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SaveSRAMRead
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AtomicW
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimWay
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimDirtyWay
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimDirty
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelAMOWrite
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelUncached
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct7W
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemPAdrDecodedW
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/BasePAdrM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimTag
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AnyCPUReqM
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FetchCountFlag
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/PreCntEn
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CntEn
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CntReset
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CPUBusy
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/PreviousCPUBusy
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelEvict
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CurrState
add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/NextState
add wave -noupdate -group EBU /testbench/dut/hart/ebu/clk add wave -noupdate -group EBU /testbench/dut/hart/ebu/clk
add wave -noupdate -group EBU /testbench/dut/hart/ebu/reset add wave -noupdate -group EBU /testbench/dut/hart/ebu/reset
add wave -noupdate -group EBU /testbench/dut/hart/ebu/StallW add wave -noupdate -group EBU /testbench/dut/hart/ebu/StallW
@ -275,7 +98,6 @@ add wave -noupdate -group EBU /testbench/dut/hart/ebu/HMASTLOCK
add wave -noupdate -group EBU /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group EBU /testbench/dut/hart/ebu/HADDRD
add wave -noupdate -group EBU /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group EBU /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -group EBU /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group EBU /testbench/dut/hart/ebu/HWRITED
add wave -noupdate -group EBU /testbench/dut/hart/ebu/CommitM
add wave -noupdate -group EBU /testbench/dut/hart/ebu/GrantData add wave -noupdate -group EBU /testbench/dut/hart/ebu/GrantData
add wave -noupdate -group EBU /testbench/dut/hart/ebu/AccessAddress add wave -noupdate -group EBU /testbench/dut/hart/ebu/AccessAddress
add wave -noupdate -group EBU /testbench/dut/hart/ebu/ISize add wave -noupdate -group EBU /testbench/dut/hart/ebu/ISize
@ -292,81 +114,77 @@ add wave -noupdate -group EBU /testbench/dut/hart/ebu/BusState
add wave -noupdate -group EBU /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group EBU /testbench/dut/hart/ebu/NextBusState
add wave -noupdate -divider W add wave -noupdate -divider W
add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate -radix hexadecimal /testbench/PCW
add wave -noupdate -radix hexadecimal /testbench/PCtextW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
add wave -noupdate /testbench/textM
add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -divider RegFile add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/RegWriteW
add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW add wave -noupdate -group RF -radix unsigned /testbench/dut/hart/ieu/dp/RdW
add wave -noupdate -radix unsigned /testbench/regNumExpected add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -radix unsigned /testbench/dut/hart/ieu/dp/RdW add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]}
add wave -noupdate -radix hexadecimal /testbench/regExpected add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]}
add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3 add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[5]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[6]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[7]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[5]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[8]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[6]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[9]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[7]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[10]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[8]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[11]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[9]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[12]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[10]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[13]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[11]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[14]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[12]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[15]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[13]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[16]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[14]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[17]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[15]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[18]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[16]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[19]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[17]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[20]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[18]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[21]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[19]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[22]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[20]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[23]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[21]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[24]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[22]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[25]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[23]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[26]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[24]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[27]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[25]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[28]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[26]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[29]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[27]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[30]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[28]} add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[31]}
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[29]} add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[30]} add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW
add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[31]} add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW
add wave -noupdate -divider CSRs add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
add wave -noupdate -divider <NULL> add wave -noupdate -divider <NULL>
add wave -hex -r /testbench/* add wave -hex -r /testbench/*
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]

13
wally-pipelined/regression/wave-dos/peripheral-waves.do
View File

@ -112,16 +112,3 @@ add wave -hex /testbench/dut/uncore/gpio/gpio/*
# everything else # everything else
add wave -hex -r /testbench/* add wave -hex -r /testbench/*
# appearance
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 250
configure wave -valuecolwidth 150
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal

760
wally-pipelined/src/fpu/fma.sv
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File diff suppressed because it is too large Load Diff

16
wally-pipelined/src/fpu/fpu.sv
View File

@ -225,7 +225,7 @@ module fpu (
.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, .XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
.XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM,
.XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
.FOpCtrlE, .FOpCtrlM, .FOpCtrlE,
.FmtE, .FmtM, .FrmM, .FmtE, .FmtM, .FrmM,
// outputs: // outputs:
.FMAFlgM, .FMAResM); .FMAFlgM, .FMAResM);
@ -257,19 +257,7 @@ module fpu (
// outputs: // outputs:
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
// convert from signle to double and vice versa
// add/FP <-> FP convert
// - computation is done in two stages
// - contains some E/M pipleine registers
//*** remove uneeded logic
//*** change to use the unpacking unit if possible
// faddcvt faddcvt (.clk, .reset, .FlushM, .StallM, .FrmM, .FOpCtrlM, .FmtE, .FmtM, .FSrcXE, .FSrcYE, .FOpCtrlE,
// .XSgnM, .YSgnM, .XManM, .YManM, .XExpM, .YExpM,
// .XSgnE, .YSgnE, .XManE, .YManE, .XExpE, .YExpE, .XDenormE, .YDenormE, .XNormE, .XNormM, .YNormM, .XZeroE, .YZeroE, .XInfE, .YInfE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE,
// // outputs:
// .CvtFpResM, .CvtFpFlgM);
cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
// compare unit // compare unit

1
wally-pipelined/src/mmu/hptw.sv
View File

@ -146,6 +146,7 @@ module hptw
if (`XLEN == 32) begin if (`XLEN == 32) begin
assign InitialWalkerState = L1_ADR; assign InitialWalkerState = L1_ADR;
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
// *** Possible bug - should be L1_ADR?
assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
end else begin end else begin
logic GigapageMisaligned, TerapageMisaligned; logic GigapageMisaligned, TerapageMisaligned;

2
wally-pipelined/src/privileged/csri.sv
View File

@ -78,7 +78,7 @@ module csri #(parameter
assign MIP_WRITE_MASK = 12'h000; assign MIP_WRITE_MASK = 12'h000;
assign SIP_WRITE_MASK = 12'h000; assign SIP_WRITE_MASK = 12'h000;
end end
always @(posedge clk, posedge reset) begin always @(posedge clk, posedge reset) begin // *** I strongly feel that IntInM should go directly to IP_REGW -- Ben 9/7/21
if (reset) IP_REGW_writeable <= 10'b0; if (reset) IP_REGW_writeable <= 10'b0;
else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable

2
wally-pipelined/src/privileged/trap.sv
View File

@ -63,7 +63,7 @@ module trap (
// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
assign PendingInterruptM = (|PendingIntsM) & InstrValidM; assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
assign InterruptM = PendingInterruptM & ~CommittedM; assign InterruptM = PendingInterruptM & ~CommittedM;

650
wally-pipelined/testbench/testbench-linux.sv
View File

@ -30,8 +30,7 @@
module testbench(); module testbench();
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*6779000; // # of instructions at which to turn on waves in graphical sim
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
string ProgramAddrMapFile, ProgramLabelMapFile; string ProgramAddrMapFile, ProgramLabelMapFile;
@ -72,9 +71,9 @@ module testbench();
// Signal Declarations // Signal Declarations
// ------------------- // -------------------
// Testbench Core // Testbench Core
integer instrs;
integer warningCount = 0; integer warningCount = 0;
// PC, Instr Checking integer errorCount = 0;
// P, Instr Checking
logic [`XLEN-1:0] PCW; logic [`XLEN-1:0] PCW;
integer data_file_all; integer data_file_all;
@ -85,64 +84,69 @@ module testbench();
// Write Back trace signals // Write Back trace signals
logic checkInstrW; logic checkInstrW;
//integer RegAdr; //integer RegAdr;
integer fault; integer fault;
logic TrapW; logic TrapW;
// Signals used to parse the trace file. // Signals used to parse the trace file.
logic checkInstrM; logic checkInstrM;
integer matchCount; integer matchCount;
string line; string line;
logic [`XLEN-1:0] ExpectedPCM; logic [`XLEN-1:0] ExpectedPCM;
logic [31:0] ExpectedInstrM; logic [31:0] ExpectedInstrM;
string textM; string textM;
string token; string token;
string ExpectedTokens [31:0]; string ExpectedTokens [31:0];
integer index; integer index;
integer StartIndex, EndIndex; integer StartIndex, EndIndex;
integer TokenIndex; integer TokenIndex;
integer MarkerIndex; integer MarkerIndex;
integer NumCSRM; integer NumCSRM;
// Memory stage expected values from trace // Memory stage expected values from trace
string RegWriteM; string RegWriteM;
integer ExpectedRegAdrM; integer ExpectedRegAdrM;
logic [`XLEN-1:0] ExpectedRegValueM; logic [`XLEN-1:0] ExpectedRegValueM;
string MemOpM; string MemOpM;
logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM; logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM;
string ExpectedCSRArrayM[10:0]; string ExpectedCSRArrayM[10:0];
logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0]; logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0];
// Write back stage expected values from trace // Write back stage expected values from trace
logic [`XLEN-1:0] ExpectedPCW; logic [`XLEN-1:0] ExpectedPCW;
logic [31:0] ExpectedInstrW; logic [31:0] ExpectedInstrW;
string textW; string textW;
string RegWriteW; string RegWriteW;
integer ExpectedRegAdrW; integer ExpectedRegAdrW;
logic [`XLEN-1:0] ExpectedRegValueW; logic [`XLEN-1:0] ExpectedRegValueW;
string MemOpW; string MemOpW;
logic [`XLEN-1:0] ExpectedMemAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; logic [`XLEN-1:0] ExpectedMemAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
integer NumCSRW; integer NumCSRW;
string ExpectedCSRArrayW[10:0]; string ExpectedCSRArrayW[10:0];
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0]; logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
logic [`XLEN-1:0] ExpectedIntType; logic [`XLEN-1:0] ExpectedIntType;
integer NumCSRMIndex; logic forcedInterrupt;
integer NumCSRWIndex; integer NumCSRMIndex;
integer NumCSRPostWIndex; integer NumCSRWIndex;
// logic CurrentInterruptForce; integer NumCSRPostWIndex;
// logic CurrentInterruptForce;
logic [`XLEN-1:0] InstrCountW; logic [`XLEN-1:0] InstrCountW;
// ----------- // -----------
// Error Macro // Error Macro
// ----------- // -----------
`define ERROR \ `define ERROR \
$display("processed %0d instructions with %0d warnings", instrs, warningCount); \ errorCount +=1; \
$display("processed %0d instructions with %0d warnings", InstrCountW, warningCount); \
$stop; $stop;
initial begin initial begin
data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
InstrCountW = '0; InstrCountW = '0;
force dut.hart.priv.SwIntM = 0;
force dut.hart.priv.TimerIntM = 0;
force dut.hart.priv.ExtIntM = 0;
end end
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
@ -160,7 +164,7 @@ module testbench();
flopenrc #(`XLEN) PCWReg(clk, reset, dut.hart.FlushW, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); flopenrc #(`XLEN) PCWReg(clk, reset, dut.hart.FlushW, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
flopenr #(1) TrapWReg(clk, reset, ~dut.hart.StallW, dut.hart.hzu.TrapM, TrapW); flopenr #(1) TrapWReg(clk, reset, ~dut.hart.StallW, dut.hart.hzu.TrapM, TrapW);
// because qemu does not match exactly to wally it is necessary to read the the // Because qemu does not match exactly to wally it is necessary to read the the
// trace in the memory stage and detect if anything in wally must be overwritten. // trace in the memory stage and detect if anything in wally must be overwritten.
// This includes mtimer, interrupts, and various bits in mstatus and xtval. // This includes mtimer, interrupts, and various bits in mstatus and xtval.
@ -186,14 +190,14 @@ module testbench();
TokenIndex = 0; TokenIndex = 0;
//$display("len = %d", line.len()); //$display("len = %d", line.len());
for(index = 0; index < line.len(); index++) begin for(index = 0; index < line.len(); index++) begin
//$display("char = %s", line[index]); //$display("char = %s", line[index]);
if (line[index] == " " || line[index] == "\n") begin if (line[index] == " " || line[index] == "\n") begin
EndIndex = index; EndIndex = index;
ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1); ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1);
//$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1)); //$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1));
StartIndex = EndIndex + 1; StartIndex = EndIndex + 1;
TokenIndex++; TokenIndex++;
end end
end end
MarkerIndex = 3; MarkerIndex = 3;
@ -204,71 +208,69 @@ module testbench();
#2; #2;
while(TokenIndex > MarkerIndex) begin while(TokenIndex > MarkerIndex) begin
// parse the GPR // parse the GPR
if (ExpectedTokens[MarkerIndex] == "GPR") begin if (ExpectedTokens[MarkerIndex] == "GPR") begin
RegWriteM = ExpectedTokens[MarkerIndex]; RegWriteM = ExpectedTokens[MarkerIndex];
matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM); matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM);
matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM); matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM);
MarkerIndex += 3; MarkerIndex += 3;
// parse memory address, read data, and/or write data // parse memory address, read data, and/or write data
end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin
MemOpM = ExpectedTokens[MarkerIndex]; MemOpM = ExpectedTokens[MarkerIndex];
matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM); matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM);
matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM); matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM);
matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM); matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM);
MarkerIndex += 4; MarkerIndex += 4;
// parse CSRs, because there are 1 or more CSRs after the CSR token // parse CSRs, because there are 1 or more CSRs after the CSR token
// we check if the CSR token or the number of CSRs is greater than 0. // we check if the CSR token or the number of CSRs is greater than 0.
// if so then we want to parse for a CSR. // if so then we want to parse for a CSR.
end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin
if(ExpectedTokens[MarkerIndex] == "CSR") begin if(ExpectedTokens[MarkerIndex] == "CSR") begin
// all additional CSR's won't have this token. // all additional CSR's won't have this token.
MarkerIndex++; MarkerIndex++;
end end
matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]); matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]);
matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]); matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]);
MarkerIndex += 2; MarkerIndex += 2;
// if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts // if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts
// are imprecise. Forcing the trap at this time will allow wally to track what qemu does. // are imprecise. Forcing the trap at this time will allow wally to track what qemu does.
// the msb of xcause will be set. // the msb of xcause will be set.
// bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine // bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine
// bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external // bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external
if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin
//what type? //what type?
ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C; ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
$display("%t: CSR = %s. Forcing interrupt of cause = %x", $time, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]); $display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
forcedInterrupt = 1;
if(ExpectedIntType == 0) begin if(ExpectedIntType == 0) begin
force dut.hart.priv.SwIntM = 1'b1; force dut.hart.priv.SwIntM = 1'b1;
$display("Force SwIntM"); $display("Activate spoofed SwIntM");
end end else if(ExpectedIntType == 4) begin
else if(ExpectedIntType == 4) begin force dut.hart.priv.TimerIntM = 1'b1;
force dut.hart.priv.TimerIntM = 1'b1; $display("Activate spoofed TimeIntM");
$display("Force TimeIntM"); end else if(ExpectedIntType == 8) begin
end force dut.hart.priv.ExtIntM = 1'b1;
else if(ExpectedIntType == 8) begin $display("Activate spoofed ExtIntM");
force dut.hart.priv.ExtIntM = 1'b1; end else forcedInterrupt = 0;
$display("Force ExtIntM"); end
end NumCSRM++;
end end
NumCSRM++;
end
end end
// override on special conditions // override on special conditions
if (ExpectedMemAdrM == 'h10000005) begin if (ExpectedMemAdrM == 'h10000005) begin
//$display("%t: Overwriting read data from CLINT.", $time); //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW);
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
end end
if(textM.substr(0,5) == "rdtime") begin if(textM.substr(0,5) == "rdtime") begin
$display("%t: Overwrite read value of CSR on read of MTIME in memory stage.", $time); $display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW);
force dut.hart.priv.csr.CSRReadValM = ExpectedRegValueM; force dut.uncore.clint.clint.MTIME = ExpectedRegValueM;
//dut.hart.ieu.dp.regf.wd3 //dut.hart.ieu.dp.regf.wd3
end end
end // if (checkInstrM) end // if (checkInstrM)
@ -288,64 +290,68 @@ module testbench();
ExpectedMemWriteDataW <= '0; ExpectedMemWriteDataW <= '0;
ExpectedMemReadDataW <= '0; ExpectedMemReadDataW <= '0;
NumCSRW <= '0; NumCSRW <= '0;
end end else if(~dut.hart.StallW) begin
else if(~dut.hart.StallW) begin
if(dut.hart.FlushW) begin if(dut.hart.FlushW) begin
ExpectedPCW <= '0; ExpectedPCW <= '0;
ExpectedInstrW <= '0; ExpectedInstrW <= '0;
textW <= ""; textW <= "";
RegWriteW <= ""; RegWriteW <= "";
ExpectedRegAdrW <= '0; ExpectedRegAdrW <= '0;
ExpectedRegValueW <= '0; ExpectedRegValueW <= '0;
ExpectedMemAdrW <= '0; ExpectedMemAdrW <= '0;
MemOpW <= ""; MemOpW <= "";
ExpectedMemWriteDataW <= '0; ExpectedMemWriteDataW <= '0;
ExpectedMemReadDataW <= '0; ExpectedMemReadDataW <= '0;
NumCSRW <= '0; NumCSRW <= '0;
end else begin end else begin
ExpectedPCW <= ExpectedPCM; ExpectedPCW <= ExpectedPCM;
ExpectedInstrW <= ExpectedInstrM; ExpectedInstrW <= ExpectedInstrM;
textW <= textM; textW <= textM;
RegWriteW <= RegWriteM; RegWriteW <= RegWriteM;
ExpectedRegAdrW <= ExpectedRegAdrM; ExpectedRegAdrW <= ExpectedRegAdrM;
ExpectedRegValueW <= ExpectedRegValueM; ExpectedRegValueW <= ExpectedRegValueM;
ExpectedMemAdrW <= ExpectedMemAdrM; ExpectedMemAdrW <= ExpectedMemAdrM;
MemOpW <= MemOpM; MemOpW <= MemOpM;
ExpectedMemWriteDataW <= ExpectedMemWriteDataM; ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
ExpectedMemReadDataW <= ExpectedMemReadDataM; ExpectedMemReadDataW <= ExpectedMemReadDataM;
NumCSRW <= NumCSRM; NumCSRW <= NumCSRM;
for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin
ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex];
ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex];
end end
end end
// override on special conditions // override on special conditions
#1; #1;
if(~dut.hart.StallW) begin if(~dut.hart.StallW) begin
if(textM.substr(0,5) == "rdtime") begin if(textW.substr(0,5) == "rdtime") begin
$display("%t:Releasing force of CSRReadValM.", $time); $display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
release dut.hart.priv.csr.CSRReadValM; release dut.uncore.clint.clint.MTIME;
//release dut.hart.ieu.dp.regf.wd3; //release dut.hart.ieu.dp.regf.wd3;
end end
if (ExpectedMemAdrM == 'h10000005) begin if (ExpectedMemAdrM == 'h10000005) begin
//$display("%t: releasing force of ReadDataM.", $time); //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
release dut.hart.ieu.dp.ReadDataM; release dut.hart.ieu.dp.ReadDataM;
end end
// remove forces on interrupts // force interrupts to 0
for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin if (forcedInterrupt) begin
if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin forcedInterrupt = 0;
//what type? if(ExpectedIntType == 0) begin
$display("%t: Releasing all forces on interrupts", $time); force dut.hart.priv.SwIntM = 1'b0;
$display("Deactivate spoofed SwIntM");
release dut.hart.priv.SwIntM; end
release dut.hart.priv.TimerIntM; else if(ExpectedIntType == 4) begin
release dut.hart.priv.ExtIntM; force dut.hart.priv.TimerIntM = 1'b0;
end $display("Deactivate spoofed TimeIntM");
end end
else if(ExpectedIntType == 8) begin
force dut.hart.priv.ExtIntM = 1'b0;
$display("Deactivate spoofed ExtIntM");
end
end
end end
end end
end end
@ -355,229 +361,214 @@ module testbench();
// always check PC, instruction bits // always check PC, instruction bits
if (checkInstrW) begin if (checkInstrW) begin
InstrCountW += 1; InstrCountW += 1;
// turn on waves at certain point
if (InstrCountW == waveOnICount) $stop;
// check PCW // check PCW
fault = 0; fault = 0;
if(PCW != ExpectedPCW) begin if(PCW != ExpectedPCW) begin
$display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW); $display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
fault = 1; fault = 1;
end end
// check instruction value // check instruction value
if(dut.hart.ifu.InstrW != ExpectedInstrW) begin if(dut.hart.ifu.InstrW != ExpectedInstrW) begin
$display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW); $display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
fault = 1; fault = 1;
end end
// check the number of instructions // check the number of instructions
if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin
$display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW); $display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
#2; // delay 2 ns. #2; // delay 2 ns.
if(`DEBUG_TRACE > 2) begin if(`DEBUG_TRACE > 2) begin
$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW); $display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
$display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); $display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
end end
if (RegWriteW == "GPR") begin if (RegWriteW == "GPR") begin
if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
$display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW); $display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
fault = 1; fault = 1;
end end
if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin
$display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); $display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
fault = 1; fault = 1;
end end
end end
if (MemOpW.substr(0,2) == "Mem") begin if (MemOpW.substr(0,2) == "Mem") begin
if(`DEBUG_TRACE > 3) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW); if(`DEBUG_TRACE > 3) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW);
// always check address // always check address
if (MemAdrW != ExpectedMemAdrW) begin if (MemAdrW != ExpectedMemAdrW) begin
$display("MemAdrW: %016x does not equal expected value: %016x", MemAdrW, ExpectedMemAdrW); $display("MemAdrW: %016x does not equal expected value: %016x", MemAdrW, ExpectedMemAdrW);
fault = 1; fault = 1;
end end
// check read data // check read data
if(MemOpW == "MemR" || MemOpW == "MemRW") begin if(MemOpW == "MemR" || MemOpW == "MemRW") begin
if(`DEBUG_TRACE > 3) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW); if(`DEBUG_TRACE > 3) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
if (dut.hart.ieu.dp.ReadDataW != ExpectedMemReadDataW) begin if (dut.hart.ieu.dp.ReadDataW != ExpectedMemReadDataW) begin
$display("ReadDataW: %016x does not equal expected value: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW); $display("ReadDataW: %016x does not equal expected value: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
fault = 1; fault = 1;
end end
end end
// check write data // check write data
else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin
if(`DEBUG_TRACE > 3) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); if(`DEBUG_TRACE > 3) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
if (WriteDataW != ExpectedMemWriteDataW) begin if (WriteDataW != ExpectedMemWriteDataW) begin
$display("WriteDataW: %016x does not equal expected value: %016x", WriteDataW, ExpectedMemWriteDataW); $display("WriteDataW: %016x does not equal expected value: %016x", WriteDataW, ExpectedMemWriteDataW);
fault = 1; fault = 1;
end end
end end
end end
// check csr // check csr
//$display("%t, about to check csr, NumCSRW = %d", $time, NumCSRW); //$display("%t, about to check csr, NumCSRW = %d", $time, NumCSRW);
for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("%t, NumCSRPostWIndex = %d, Expected CSR: %s = %016x", $time, NumCSRPostWIndex, ExpectedCSRArrayW[NumCSRPostWIndex], ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, NumCSRPostWIndex = %d, Expected CSR: %s = %016x", $time, NumCSRPostWIndex, ExpectedCSRArrayW[NumCSRPostWIndex], ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
case(ExpectedCSRArrayW[NumCSRPostWIndex]) case(ExpectedCSRArrayW[NumCSRPostWIndex])
"mhartid": begin "mhartid": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mstatus": begin "mstatus": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if ((dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW) != (ExpectedCSRArrayValueW[NumCSRPostWIndex])) begin if ((dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW) != (ExpectedCSRArrayValueW[NumCSRPostWIndex])) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mtvec": begin "mtvec": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mip": begin "mip": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MIP_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MIP_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mie": begin "mie": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MIE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MIE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mideleg": begin "mideleg": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"medeleg": begin "medeleg": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mepc": begin "mepc": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mtval": begin
"mtval": begin if(`DEBUG_TRACE > 0) begin
if(`DEBUG_TRACE > 0) begin $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); end
end if (dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
if (dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); if(!`DontHaltOnCSRMisMatch) fault = 1;
if(!`DontHaltOnCSRMisMatch) fault = 1; end
end end
end "sepc": begin
if(`DEBUG_TRACE > 0) begin
"sepc": begin $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(`DEBUG_TRACE > 0) begin end
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); if (dut.hart.priv.csr.genblk1.csrs.SEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
end $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if (dut.hart.priv.csr.genblk1.csrs.SEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if(!`DontHaltOnCSRMisMatch) fault = 1;
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); end
if(!`DontHaltOnCSRMisMatch) fault = 1; end
end "scause": begin
end if(`DEBUG_TRACE > 0) begin
"scause": begin $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(`DEBUG_TRACE > 0) begin end
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); if (dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
end $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if (dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if(!`DontHaltOnCSRMisMatch) fault = 1;
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); end
if(!`DontHaltOnCSRMisMatch) fault = 1; end
end "stvec": begin
end if(`DEBUG_TRACE > 0) begin
"stvec": begin $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(`DEBUG_TRACE > 0) begin end
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); if (dut.hart.priv.csr.genblk1.csrs.STVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
end $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if (dut.hart.priv.csr.genblk1.csrs.STVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if(!`DontHaltOnCSRMisMatch) fault = 1;
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); end
if(!`DontHaltOnCSRMisMatch) fault = 1; end
end "stval": begin
end if(`DEBUG_TRACE > 0) begin
"stval": begin $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(`DEBUG_TRACE > 0) begin end
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); if (dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
end $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if (dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if(!`DontHaltOnCSRMisMatch) fault = 1;
$display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); end
if(!`DontHaltOnCSRMisMatch) fault = 1; end
end endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex])
end
endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex])
/* -----\/----- EXCLUDED -----\/-----
if(CurrentInterruptForce) begin
CurrentInterruptForce = 1'b0;
// remove forces on interrupts
$display("%t: Releasing all forces on interrupts", $time);
release dut.hart.priv.SwIntM;
release dut.hart.priv.TimerIntM;
release dut.hart.priv.ExtIntM;
end
-----/\----- EXCLUDED -----/\----- */
end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++)
if (fault == 1) begin if (fault == 1) begin `ERROR end
`ERROR
end
end // if (checkInstrW) end // if (checkInstrW)
end // always @ (negedge clk) end // always @ (negedge clk)
// track the current function // track the current function
FunctionName FunctionName(.reset(reset), FunctionName FunctionName(.reset(reset),
.clk(clk), .clk(clk),
.ProgramAddrMapFile(ProgramAddrMapFile), .ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile)); .ProgramLabelMapFile(ProgramLabelMapFile));
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
@ -589,7 +580,6 @@ module testbench();
// -------------- // --------------
initial initial
begin begin
instrs = 0;
reset <= 1; # 22; reset <= 0; reset <= 1; # 22; reset <= 0;
end end
// initial loading of memories // initial loading of memories