From b2dace02a68597a00b36612d0401751f522bee22 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 19 Mar 2024 10:53:35 -0700 Subject: [PATCH 01/11] Changed linux boot to clone into new directory linuximg. There's probably a better location for this, but this is for preliminary testing --- linux/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/Makefile b/linux/Makefile index 46a193090..5f57e73a3 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -1,4 +1,4 @@ -RISCV := /opt/riscv +RISCV := $(WALLY)/linuximg # Changed to test linux build #BUILDROOT := ${RISCV}/buildroot-test BUILDROOT := buildroot IMAGES := ${BUILDROOT}/output/images From ad0cb798bc45d5d3808c92655de4e0ca0bd725da Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 19 Mar 2024 14:38:58 -0700 Subject: [PATCH 02/11] Added new buildroot in root directory to gitignore --- .gitignore | 3 +++ linux/Makefile | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 2acbd1f2a..8e52bfbd2 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,9 @@ __pycache__/ .vscode/ +#buildrootignore +/buildroot/ + #External repos addins/riscv-arch-test/Makefile.include addins/riscv-tests/target diff --git a/linux/Makefile b/linux/Makefile index 5f57e73a3..aadb3e087 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -1,4 +1,4 @@ -RISCV := $(WALLY)/linuximg # Changed to test linux build +RISCV := $(WALLY)# Changed to test linux build #BUILDROOT := ${RISCV}/buildroot-test BUILDROOT := buildroot IMAGES := ${BUILDROOT}/output/images @@ -37,8 +37,8 @@ Image: $(MAKE) generate install: - sudo rm -rf $(RISCV)/$(BUILDROOT) - sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) + rm -rf $(RISCV)/$(BUILDROOT) + mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) # Temp rule for debugging test: From efb68e7eebe04bb4bc1ae79bf028a3da96e1c969 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 26 Mar 2024 10:28:50 -0700 Subject: [PATCH 03/11] Added dumptvs function to Linux makefile to create linux-testvectors in /opt/riscv directory --- linux/Makefile | 5 +++++ sim/regression-wally | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/linux/Makefile b/linux/Makefile index 46a193090..e2ba5e9f3 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -40,6 +40,11 @@ install: sudo rm -rf $(RISCV)/$(BUILDROOT) sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) +dumptvs: + export RISCV=$(RISCV) + mkdir -p ../linux-testvectors + cd testvector-generation; ./genInitMem.sh + # Temp rule for debugging test: echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") diff --git a/sim/regression-wally b/sim/regression-wally index df4ac86e2..ec420113c 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -61,7 +61,7 @@ else: def getBuildrootTC(boot): INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM - MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. + MAX_EXPECTED = 591000000 # *** TODO: replace this with a search for the login prompt. if boot: name="buildrootboot" BRcmd="vsim > {} -c < Date: Tue, 26 Mar 2024 10:32:28 -0700 Subject: [PATCH 04/11] Added generated directory linux-testvectors to gitignore --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 8e52bfbd2..e837f1fe0 100644 --- a/.gitignore +++ b/.gitignore @@ -7,7 +7,8 @@ __pycache__/ .vscode/ #buildrootignore -/buildroot/ +buildroot/ +linux-testvectors/* #External repos addins/riscv-arch-test/Makefile.include From 5378b61eb22af92e61e2b480576701faa506b111 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 17:18:03 -0700 Subject: [PATCH 05/11] Added UART output file buildroot_uart.out for Linux test 'buildroot'. --- sim/run-imperas-linux.sh | 2 +- testbench/testbench.sv | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 86e6d1f64..65e4826fb 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100" #export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" #export OTHERFLAGS="" -vsim -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" +vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" diff --git a/testbench/testbench.sv b/testbench/testbench.sv index fb12eb082..05d15e63d 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -236,7 +236,7 @@ module testbench; logic ResetCntRst; logic CopyRAM; - string signame, memfilename, bootmemfilename, pathname; + string signame, memfilename, bootmemfilename, uartoutfilename, pathname; integer begin_signature_addr, end_signature_addr, signature_size; assign ResetThreshold = 3'd5; @@ -299,6 +299,7 @@ module testbench; // Find the test vector files and populate the PC to function label converter //////////////////////////////////////////////////////////////////////////////// logic [P.XLEN-1:0] testadr; + integer memFile; assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; assign signature_size = end_signature_addr - begin_signature_addr; @@ -308,6 +309,10 @@ module testbench; else if(TEST == "buildroot") begin memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; + uartoutfilename = {"logs/",TEST,"_uart.out"}; + // Initialize uart output file + memFile = $fopen(uartoutfilename, "w"); // Clear existing values in uartFile + $fclose(memFile); end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -389,7 +394,6 @@ module testbench; integer StartIndex; integer EndIndex; integer BaseIndex; - integer memFile; integer readResult; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin @@ -547,6 +551,16 @@ module testbench; .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end + // Write UART output to file for tests + always @(posedge clk) begin + if (TEST == "buildroot") begin + if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin + memFile = $fopen(uartoutfilename, "ab"); + $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); + $fclose(memFile); + end + end + end // Termination condition // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed From d89a187ce8a69af94ee35b80fba7b40a77ea8e2c Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 20:44:11 -0700 Subject: [PATCH 06/11] Fixed commit where Linux Makefile always built Linux into repo instead of into shared directory. --- linux/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 169721c24..37b0cd2df 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -1,4 +1,4 @@ -RISCV := $(WALLY)# Changed to test linux build +RISCV := $(RISCV) #BUILDROOT := ${RISCV}/buildroot-test BUILDROOT := buildroot IMAGES := ${BUILDROOT}/output/images @@ -42,7 +42,7 @@ install: dumptvs: export RISCV=$(RISCV) - mkdir -p ../linux-testvectors + mkdir -p $(RISCV)/linux-testvectors cd testvector-generation; ./genInitMem.sh # Temp rule for debugging From 37716f1b563a0d07fd38a5e84bfeecad8d99315d Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 20:53:52 -0700 Subject: [PATCH 07/11] Removed redundant lines from linux Makefile; gitignore --- .gitignore | 3 --- linux/Makefile | 1 - 2 files changed, 4 deletions(-) diff --git a/.gitignore b/.gitignore index e837f1fe0..d073ef20f 100644 --- a/.gitignore +++ b/.gitignore @@ -6,9 +6,6 @@ __pycache__/ .vscode/ -#buildrootignore -buildroot/ -linux-testvectors/* #External repos addins/riscv-arch-test/Makefile.include diff --git a/linux/Makefile b/linux/Makefile index 37b0cd2df..9904806ee 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -41,7 +41,6 @@ install: mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) dumptvs: - export RISCV=$(RISCV) mkdir -p $(RISCV)/linux-testvectors cd testvector-generation; ./genInitMem.sh From 2fcae601a96003d9afff26bdba12864fe098125a Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 20:59:08 -0700 Subject: [PATCH 08/11] Replaced funky rewrite call with file removal --- testbench/testbench.sv | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 7f7a5f510..3fd367eb6 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -299,7 +299,6 @@ module testbench; // Find the test vector files and populate the PC to function label converter //////////////////////////////////////////////////////////////////////////////// logic [P.XLEN-1:0] testadr; - integer memFile; always_comb begin begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; @@ -331,8 +330,7 @@ module testbench; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; uartoutfilename = {"logs/",TEST,"_uart.out"}; // Initialize uart output file - memFile = $fopen(uartoutfilename, "w"); // Clear existing values in uartFile - $fclose(memFile); + $system("rm ",uartoutfilename); // Clear existing values in uartFile end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -415,6 +413,7 @@ module testbench; integer StartIndex; integer EndIndex; integer BaseIndex; + integer memFile; integer readResult; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin From 45cf997154f0b58f80ff62579044938f9340cf65 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 21:05:10 -0700 Subject: [PATCH 09/11] Removed extraneous whitespace --- .gitignore | 1 - 1 file changed, 1 deletion(-) diff --git a/.gitignore b/.gitignore index d073ef20f..2acbd1f2a 100644 --- a/.gitignore +++ b/.gitignore @@ -6,7 +6,6 @@ __pycache__/ .vscode/ - #External repos addins/riscv-arch-test/Makefile.include addins/riscv-tests/target From e631ae8c2d0fe8c4e96817ea7198afb707668961 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 21:38:30 -0700 Subject: [PATCH 10/11] Fixed sudo permissions in Linux Makefile, added nosudo versions of sudo commands --- linux/Makefile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/linux/Makefile b/linux/Makefile index 9904806ee..6f7b6c7fb 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -1,4 +1,3 @@ -RISCV := $(RISCV) #BUILDROOT := ${RISCV}/buildroot-test BUILDROOT := buildroot IMAGES := ${BUILDROOT}/output/images @@ -32,15 +31,25 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) all: clean download Image disassemble install +all_nosudo: clean download Image disassemble install_nosudo + Image: bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;" $(MAKE) generate install: + sudo rm -rf $(RISCV)/$(BUILDROOT) + sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) + +install_nosudo: rm -rf $(RISCV)/$(BUILDROOT) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) dumptvs: + sudo mkdir -p $(RISCV)/linux-testvectors + cd testvector-generation; sudo ./genInitMem.sh + +dumptvs_nosudo: mkdir -p $(RISCV)/linux-testvectors cd testvector-generation; ./genInitMem.sh From d107a42e8c19e7dec9f3cacfed04a5d14c1db1c2 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 21:39:41 -0700 Subject: [PATCH 11/11] Replaced rewrite command with system rm command for uart file. Fixed comment on line 573 --- testbench/testbench.sv | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3fd367eb6..d3f3ee36a 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -329,8 +329,7 @@ module testbench; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; uartoutfilename = {"logs/",TEST,"_uart.out"}; - // Initialize uart output file - $system("rm ",uartoutfilename); // Clear existing values in uartFile + $system("rm ",uartoutfilename); // Delete existing UARToutfile end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -571,7 +570,7 @@ module testbench; .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end - // Write UART output to file for tests + // Append UART output to file for tests always @(posedge clk) begin if (TEST == "buildroot") begin if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin