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cacheway cleanup

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This commit is contained in:
David Harris 2022-02-03 16:52:22 +00:00
parent eef04eed84
commit 65f3bf4e0a
2 changed files with 29 additions and 37 deletions
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8
pipelined/src/cache/cache.sv vendored
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@ -74,7 +74,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
logic [LINELEN-1:0] SRAMWriteData;
logic SetValid, ClearValid;
logic SetDirty, ClearDirty;
logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
logic [NUMWAYS-1:0] WayHit;
logic CacheHit;
logic [LINELEN-1:0] ReadDataLine;
@ -126,7 +126,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
.TagWriteEnable(SRAMLineWayWriteEnable),
.WriteData(SRAMWriteData),
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay), .SelFlush,
.ReadDataLineWayMasked, .WayHit, .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
.SelectedReadDataLine(ReadDataLineWay), .WayHit, .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
.InvalidateAll(InvalidateCacheM));
if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
@ -134,10 +134,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
end else assign VictimWay = 1'b1; // one hot.
assign CacheHit = | WayHit;
assign VictimDirty = | VictimDirtyWay;
// ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways.
// ReadDataLineWay is a 2d array of cache line len by number of ways.
// Need to OR together each way in a bitwise manner.
// Final part of the AO Mux. First is the AND in the cacheway.
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLine));
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine));
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));

56
pipelined/src/cache/cacheway.sv vendored
View File

@ -52,20 +52,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
input logic SelFlush,
input logic Flush,
output logic [LINELEN-1:0] ReadDataLineWayMasked,
output logic [LINELEN-1:0] SelectedReadDataLine,
output logic WayHit,
output logic VictimDirty,
output logic [TAGLEN-1:0] VictimTag);
logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits;
logic [LINELEN-1:0] ReadDataLineWay;
logic [LINELEN-1:0] ReadDataLine;
logic [TAGLEN-1:0] ReadTag;
logic Valid;
logic Dirty;
logic SelectedWay;
// logic [TAGLEN-1:0] VicDirtyWay;
// logic [TAGLEN-1:0] FlushThisWay;
logic SelData;
logic SelTag;
logic [$clog2(NUMLINES)-1:0] RAdrD;
@ -74,41 +72,35 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
logic WriteEnableD, VDWriteEnableD;
/////////////////////////////////////////////////////////////////////////////////////////////
// Data and Tag Arrays
// Tag Array
/////////////////////////////////////////////////////////////////////////////////////////////
// Potential optimization: if byte write enables are available, could remove subwordwrites
/* sram1rw #(.DEPTH(NUMLINES), .WIDTH(LINELEN)) CacheDataMem(
.clk(clk), .Addr(RAdr),
.ReadData(ReadDataLineWay), .WriteData(WriteData),
.WriteEnable(WriteEnable & WriteWordEnable[words])); // *** */
genvar words;
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN))
CacheDataMem(.clk(clk), .Addr(RAdr),
.ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
end
sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk),
.Addr(RAdr), .ReadData(ReadTag),
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable));
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
assign SelectedWay = SelFlush ? Flush : (SelEvict ? Victim : WayHit);
assign ReadDataLineWayMasked = SelectedWay ? ReadDataLineWay : '0; // AND part of AO mux.
assign VictimDirty = SelFlush ? Flush & Dirty & Valid :
Victim & Dirty & Valid;
/*
assign VicDirtyWay = Victim ? ReadTag : '0;
assign FlushThisWay = Flush ? ReadTag : '0;
assign VictimTag = SelFlush ? FlushThisWay : VicDirtyWay;
*/
// AND portion of distributed tag multiplexer
assign SelTag = SelFlush ? Flush : Victim;
assign VictimTag = SelTag ? ReadTag : '0; // AND part of AOMux
assign VictimDirty = SelTag & Dirty & Valid;
/////////////////////////////////////////////////////////////////////////////////////////////
// Data Array
/////////////////////////////////////////////////////////////////////////////////////////////
// *** Potential optimization: if byte write enables are available, could remove subwordwrites
genvar words;
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Addr(RAdr),
.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
end
// AND portion of distributed read multiplexers
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
assign SelData = SelFlush ? Flush : (SelEvict ? Victim : WayHit);
assign SelectedReadDataLine = SelData ? ReadDataLine : '0; // AND part of AO mux.
/////////////////////////////////////////////////////////////////////////////////////////////
// Valid Bits