diff --git a/examples/verilog/fulladder/fulladder-batch.do b/examples/verilog/fulladder/fulladder-batch.do
new file mode 100644
index 000000000..5b4b3f828
--- /dev/null
+++ b/examples/verilog/fulladder/fulladder-batch.do
@@ -0,0 +1,7 @@
+# fulladder-batch.do 
+# David_Harris@hmc.edu 10 January 2021
+vlog fulladder.sv 
+vopt +acc work.testbench -o workopt 
+vsim workopt
+run -all
+quit
\ No newline at end of file
diff --git a/examples/verilog/fulladder/fulladder.do b/examples/verilog/fulladder/fulladder.do
new file mode 100644
index 000000000..d88b0fd03
--- /dev/null
+++ b/examples/verilog/fulladder/fulladder.do
@@ -0,0 +1,12 @@
+# fulladder.do 
+# David_Harris@hmc.edu 10 January 2021
+
+# compile, optimize, and start the simulation
+vlog fulladder.sv 
+vopt +acc work.testbench -o workopt 
+vsim workopt
+
+# Add waveforms and run the simulation
+add wave *
+run -all
+view wave
diff --git a/examples/verilog/fulladder/sim-fulladder-batch b/examples/verilog/fulladder/sim-fulladder-batch
new file mode 100755
index 000000000..ff89dac36
--- /dev/null
+++ b/examples/verilog/fulladder/sim-fulladder-batch
@@ -0,0 +1 @@
+vsim -c -do fulladder-batch.do