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structural muxes.

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This commit is contained in:
Ross Thompson 2022-02-09 19:36:21 -06:00
parent 21364dae32
commit 65803ebe98
1 changed files with 1 additions and 3 deletions
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4
pipelined/src/cache/cacheway.sv vendored
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@ -112,7 +112,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
// AND portion of distributed read multiplexers // AND portion of distributed read multiplexers
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
assign SelData = SelFlush ? Flush : (SelEvict ? Victim : WayHit); mux3 #(1) selecteddatamux(WayHit, Victim, Flush, {SelFlush, SelEvict}, SelData);
assign SelectedReadDataLine = SelData ? ReadDataLine : '0; // AND part of AO mux. assign SelectedReadDataLine = SelData ? ReadDataLine : '0; // AND part of AO mux.
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
@ -124,9 +124,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
else if (SetValid) ValidBits[RAdr] <= #1 1'b1; else if (SetValid) ValidBits[RAdr] <= #1 1'b1;
else if (ClearValid) ValidBits[RAdr] <= #1 1'b0; else if (ClearValid) ValidBits[RAdr] <= #1 1'b0;
end end
// *** consider revisiting whether these delays are the best option?
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
//flop #(2) ValidCtrlDelayReg(clk, {SetValid, ClearValid}, {SetValidD, ClearValidD});
assign Valid = ValidBits[RAdrD]; assign Valid = ValidBits[RAdrD];
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////