From 654cafb7f714076b093e529920cc8e5a401ebe0a Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 30 Jul 2023 01:54:41 -0700 Subject: [PATCH] Fixed Questa warnings in plic_apb about part select out of bounds --- src/uncore/plic_apb.sv | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index ea564ec63..9889d25d2 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -73,6 +73,14 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( logic [`C-1:0][7:1] threshMask; logic [P.PLIC_NUM_SRC-1:0] One; + // hacks to handle gracefully PLIC_NUM_SRC being smaller than 32 + // Otherwise Questa and other simulators produce part-select out of bounds even + // though sources >=32 are never used + + localparam PLIC_SRC_TOP = (P.PLIC_NUM_SRC >= 32) ? P.PLIC_NUM_SRC : 1; + localparam PLIC_SRC_BOT = (P.PLIC_NUM_SRC >= 32) ? 32 : 1; + localparam PLIC_SRC_DINTOP = (P.PLIC_NUM_SRC >= 32) ? P.PLIC_NUM_SRC -32 : 0; + // ======= // AHB I/O // ======= @@ -107,7 +115,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( intInProgress <= #1 '0; // writing end else begin - if (memwrite) + if (memwrite) casez(entry) 24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0]; 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1]; @@ -116,8 +124,8 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // verilator lint_off SELRANGE // *** RT: Long term we want to factor out these variable number of registers as a generate loop // I think this won't work as a case statement. - 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; - 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; + 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT] <= #1 Din[PLIC_SRC_DINTOP:0]; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT] <= #1 Din[PLIC_SRC_DINTOP:0]; // verilator lint_on SELRANGE 24'h200000: intThreshold[0] <= #1 Din[2:0]; 24'h200004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion @@ -134,15 +142,15 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // verilator lint_off SELRANGE // verilator lint_off WIDTHTRUNC - 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; - 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; + 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]}; + 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]}; // verilator lint_on SELRANGE // verilator lint_on WIDTHTRUNC 24'h002080: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0}; // verilator lint_off SELRANGE // verilator lint_off WIDTHTRUNC - 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]}; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]}; // verilator lint_on SELRANGE // verilator lint_on WIDTHTRUNC 24'h200000: Dout <= #1 {29'b0,intThreshold[0]};