From 654a33bf92887a78c7a7ef08eb48f5fb1c8302b3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 12 Jan 2022 17:41:39 -0600 Subject: [PATCH] Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu. --- pipelined/src/lsu/lsu.sv | 5 ++++- pipelined/src/uncore/uncore.sv | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index d716377f4..9ac887fe7 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -374,7 +374,10 @@ module lsu assign LocalLSUBusAdr = SelUncachedAdr ? LSUPAdrM : DCacheBusAdr ; assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount]; - assign LSUBusHWDATA = SelUncachedAdr ? WriteDataM : PreLSUBusHWDATA; // *** why is this not FinalWriteDataM? which does not work. + // exclude the subword write for uncached. We don't read the data first so we cannot + // select the subword by masking. Subword write also exists inside the uncore to + // suport subword masking for i/o. I'm not sure if this is necessary. + assign LSUBusHWDATA = SelUncachedAdr ? FinalAMOWriteDataM : PreLSUBusHWDATA; if (`XLEN == 32) assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b010; else assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b011; diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 351fbb4cb..f9190f2d3 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -191,7 +191,7 @@ module uncore ( // mux could also include external memory // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | - ({`XLEN{HSELEXTD}} & HRDATAEXT) | + ({`XLEN{HSELEXTD}} & HRDATAEXT) | ({`XLEN{HSELCLINTD}} & HREADCLINT) | ({`XLEN{HSELPLICD}} & HREADPLIC) | ({`XLEN{HSELGPIOD}} & HREADGPIO) |